mthca_srq.c 16 KB

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  1. /*
  2. * Copyright (c) 2005 Cisco Systems. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. * $Id: mthca_srq.c 3047 2005-08-10 03:59:35Z roland $
  33. */
  34. #include <linux/slab.h>
  35. #include <linux/string.h>
  36. #include "mthca_dev.h"
  37. #include "mthca_cmd.h"
  38. #include "mthca_memfree.h"
  39. #include "mthca_wqe.h"
  40. enum {
  41. MTHCA_MAX_DIRECT_SRQ_SIZE = 4 * PAGE_SIZE
  42. };
  43. struct mthca_tavor_srq_context {
  44. __be64 wqe_base_ds; /* low 6 bits is descriptor size */
  45. __be32 state_pd;
  46. __be32 lkey;
  47. __be32 uar;
  48. __be32 wqe_cnt;
  49. u32 reserved[2];
  50. };
  51. struct mthca_arbel_srq_context {
  52. __be32 state_logsize_srqn;
  53. __be32 lkey;
  54. __be32 db_index;
  55. __be32 logstride_usrpage;
  56. __be64 wqe_base;
  57. __be32 eq_pd;
  58. __be16 limit_watermark;
  59. __be16 wqe_cnt;
  60. u16 reserved1;
  61. __be16 wqe_counter;
  62. u32 reserved2[3];
  63. };
  64. static void *get_wqe(struct mthca_srq *srq, int n)
  65. {
  66. if (srq->is_direct)
  67. return srq->queue.direct.buf + (n << srq->wqe_shift);
  68. else
  69. return srq->queue.page_list[(n << srq->wqe_shift) >> PAGE_SHIFT].buf +
  70. ((n << srq->wqe_shift) & (PAGE_SIZE - 1));
  71. }
  72. /*
  73. * Return a pointer to the location within a WQE that we're using as a
  74. * link when the WQE is in the free list. We use the imm field
  75. * because in the Tavor case, posting a WQE may overwrite the next
  76. * segment of the previous WQE, but a receive WQE will never touch the
  77. * imm field. This avoids corrupting our free list if the previous
  78. * WQE has already completed and been put on the free list when we
  79. * post the next WQE.
  80. */
  81. static inline int *wqe_to_link(void *wqe)
  82. {
  83. return (int *) (wqe + offsetof(struct mthca_next_seg, imm));
  84. }
  85. static void mthca_tavor_init_srq_context(struct mthca_dev *dev,
  86. struct mthca_pd *pd,
  87. struct mthca_srq *srq,
  88. struct mthca_tavor_srq_context *context)
  89. {
  90. memset(context, 0, sizeof *context);
  91. context->wqe_base_ds = cpu_to_be64(1 << (srq->wqe_shift - 4));
  92. context->state_pd = cpu_to_be32(pd->pd_num);
  93. context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
  94. if (pd->ibpd.uobject)
  95. context->uar =
  96. cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index);
  97. else
  98. context->uar = cpu_to_be32(dev->driver_uar.index);
  99. }
  100. static void mthca_arbel_init_srq_context(struct mthca_dev *dev,
  101. struct mthca_pd *pd,
  102. struct mthca_srq *srq,
  103. struct mthca_arbel_srq_context *context)
  104. {
  105. int logsize;
  106. memset(context, 0, sizeof *context);
  107. logsize = long_log2(srq->max) + srq->wqe_shift;
  108. context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn);
  109. context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
  110. context->db_index = cpu_to_be32(srq->db_index);
  111. context->logstride_usrpage = cpu_to_be32((srq->wqe_shift - 4) << 29);
  112. if (pd->ibpd.uobject)
  113. context->logstride_usrpage |=
  114. cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index);
  115. else
  116. context->logstride_usrpage |= cpu_to_be32(dev->driver_uar.index);
  117. context->eq_pd = cpu_to_be32(MTHCA_EQ_ASYNC << 24 | pd->pd_num);
  118. }
  119. static void mthca_free_srq_buf(struct mthca_dev *dev, struct mthca_srq *srq)
  120. {
  121. mthca_buf_free(dev, srq->max << srq->wqe_shift, &srq->queue,
  122. srq->is_direct, &srq->mr);
  123. kfree(srq->wrid);
  124. }
  125. static int mthca_alloc_srq_buf(struct mthca_dev *dev, struct mthca_pd *pd,
  126. struct mthca_srq *srq)
  127. {
  128. struct mthca_data_seg *scatter;
  129. void *wqe;
  130. int err;
  131. int i;
  132. if (pd->ibpd.uobject)
  133. return 0;
  134. srq->wrid = kmalloc(srq->max * sizeof (u64), GFP_KERNEL);
  135. if (!srq->wrid)
  136. return -ENOMEM;
  137. err = mthca_buf_alloc(dev, srq->max << srq->wqe_shift,
  138. MTHCA_MAX_DIRECT_SRQ_SIZE,
  139. &srq->queue, &srq->is_direct, pd, 1, &srq->mr);
  140. if (err) {
  141. kfree(srq->wrid);
  142. return err;
  143. }
  144. /*
  145. * Now initialize the SRQ buffer so that all of the WQEs are
  146. * linked into the list of free WQEs. In addition, set the
  147. * scatter list L_Keys to the sentry value of 0x100.
  148. */
  149. for (i = 0; i < srq->max; ++i) {
  150. wqe = get_wqe(srq, i);
  151. *wqe_to_link(wqe) = i < srq->max - 1 ? i + 1 : -1;
  152. for (scatter = wqe + sizeof (struct mthca_next_seg);
  153. (void *) scatter < wqe + (1 << srq->wqe_shift);
  154. ++scatter)
  155. scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  156. }
  157. srq->last = get_wqe(srq, srq->max - 1);
  158. return 0;
  159. }
  160. int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
  161. struct ib_srq_attr *attr, struct mthca_srq *srq)
  162. {
  163. struct mthca_mailbox *mailbox;
  164. u8 status;
  165. int ds;
  166. int err;
  167. /* Sanity check SRQ size before proceeding */
  168. if (attr->max_wr > dev->limits.max_srq_wqes ||
  169. attr->max_sge > dev->limits.max_sg)
  170. return -EINVAL;
  171. srq->max = attr->max_wr;
  172. srq->max_gs = attr->max_sge;
  173. srq->counter = 0;
  174. if (mthca_is_memfree(dev))
  175. srq->max = roundup_pow_of_two(srq->max + 1);
  176. ds = max(64UL,
  177. roundup_pow_of_two(sizeof (struct mthca_next_seg) +
  178. srq->max_gs * sizeof (struct mthca_data_seg)));
  179. srq->wqe_shift = long_log2(ds);
  180. srq->srqn = mthca_alloc(&dev->srq_table.alloc);
  181. if (srq->srqn == -1)
  182. return -ENOMEM;
  183. if (mthca_is_memfree(dev)) {
  184. err = mthca_table_get(dev, dev->srq_table.table, srq->srqn);
  185. if (err)
  186. goto err_out;
  187. if (!pd->ibpd.uobject) {
  188. srq->db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SRQ,
  189. srq->srqn, &srq->db);
  190. if (srq->db_index < 0) {
  191. err = -ENOMEM;
  192. goto err_out_icm;
  193. }
  194. }
  195. }
  196. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  197. if (IS_ERR(mailbox)) {
  198. err = PTR_ERR(mailbox);
  199. goto err_out_db;
  200. }
  201. err = mthca_alloc_srq_buf(dev, pd, srq);
  202. if (err)
  203. goto err_out_mailbox;
  204. spin_lock_init(&srq->lock);
  205. atomic_set(&srq->refcount, 1);
  206. init_waitqueue_head(&srq->wait);
  207. if (mthca_is_memfree(dev))
  208. mthca_arbel_init_srq_context(dev, pd, srq, mailbox->buf);
  209. else
  210. mthca_tavor_init_srq_context(dev, pd, srq, mailbox->buf);
  211. err = mthca_SW2HW_SRQ(dev, mailbox, srq->srqn, &status);
  212. if (err) {
  213. mthca_warn(dev, "SW2HW_SRQ failed (%d)\n", err);
  214. goto err_out_free_buf;
  215. }
  216. if (status) {
  217. mthca_warn(dev, "SW2HW_SRQ returned status 0x%02x\n",
  218. status);
  219. err = -EINVAL;
  220. goto err_out_free_buf;
  221. }
  222. spin_lock_irq(&dev->srq_table.lock);
  223. if (mthca_array_set(&dev->srq_table.srq,
  224. srq->srqn & (dev->limits.num_srqs - 1),
  225. srq)) {
  226. spin_unlock_irq(&dev->srq_table.lock);
  227. goto err_out_free_srq;
  228. }
  229. spin_unlock_irq(&dev->srq_table.lock);
  230. mthca_free_mailbox(dev, mailbox);
  231. srq->first_free = 0;
  232. srq->last_free = srq->max - 1;
  233. return 0;
  234. err_out_free_srq:
  235. err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status);
  236. if (err)
  237. mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err);
  238. else if (status)
  239. mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status);
  240. err_out_free_buf:
  241. if (!pd->ibpd.uobject)
  242. mthca_free_srq_buf(dev, srq);
  243. err_out_mailbox:
  244. mthca_free_mailbox(dev, mailbox);
  245. err_out_db:
  246. if (!pd->ibpd.uobject && mthca_is_memfree(dev))
  247. mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index);
  248. err_out_icm:
  249. mthca_table_put(dev, dev->srq_table.table, srq->srqn);
  250. err_out:
  251. mthca_free(&dev->srq_table.alloc, srq->srqn);
  252. return err;
  253. }
  254. void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq)
  255. {
  256. struct mthca_mailbox *mailbox;
  257. int err;
  258. u8 status;
  259. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  260. if (IS_ERR(mailbox)) {
  261. mthca_warn(dev, "No memory for mailbox to free SRQ.\n");
  262. return;
  263. }
  264. err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status);
  265. if (err)
  266. mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err);
  267. else if (status)
  268. mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status);
  269. spin_lock_irq(&dev->srq_table.lock);
  270. mthca_array_clear(&dev->srq_table.srq,
  271. srq->srqn & (dev->limits.num_srqs - 1));
  272. spin_unlock_irq(&dev->srq_table.lock);
  273. atomic_dec(&srq->refcount);
  274. wait_event(srq->wait, !atomic_read(&srq->refcount));
  275. if (!srq->ibsrq.uobject) {
  276. mthca_free_srq_buf(dev, srq);
  277. if (mthca_is_memfree(dev))
  278. mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index);
  279. }
  280. mthca_table_put(dev, dev->srq_table.table, srq->srqn);
  281. mthca_free(&dev->srq_table.alloc, srq->srqn);
  282. mthca_free_mailbox(dev, mailbox);
  283. }
  284. int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
  285. enum ib_srq_attr_mask attr_mask)
  286. {
  287. struct mthca_dev *dev = to_mdev(ibsrq->device);
  288. struct mthca_srq *srq = to_msrq(ibsrq);
  289. int ret;
  290. u8 status;
  291. /* We don't support resizing SRQs (yet?) */
  292. if (attr_mask & IB_SRQ_MAX_WR)
  293. return -EINVAL;
  294. if (attr_mask & IB_SRQ_LIMIT) {
  295. ret = mthca_ARM_SRQ(dev, srq->srqn, attr->srq_limit, &status);
  296. if (ret)
  297. return ret;
  298. if (status)
  299. return -EINVAL;
  300. }
  301. return 0;
  302. }
  303. void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
  304. enum ib_event_type event_type)
  305. {
  306. struct mthca_srq *srq;
  307. struct ib_event event;
  308. spin_lock(&dev->srq_table.lock);
  309. srq = mthca_array_get(&dev->srq_table.srq, srqn & (dev->limits.num_srqs - 1));
  310. if (srq)
  311. atomic_inc(&srq->refcount);
  312. spin_unlock(&dev->srq_table.lock);
  313. if (!srq) {
  314. mthca_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
  315. return;
  316. }
  317. if (!srq->ibsrq.event_handler)
  318. goto out;
  319. event.device = &dev->ib_dev;
  320. event.event = event_type;
  321. event.element.srq = &srq->ibsrq;
  322. srq->ibsrq.event_handler(&event, srq->ibsrq.srq_context);
  323. out:
  324. if (atomic_dec_and_test(&srq->refcount))
  325. wake_up(&srq->wait);
  326. }
  327. /*
  328. * This function must be called with IRQs disabled.
  329. */
  330. void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr)
  331. {
  332. int ind;
  333. ind = wqe_addr >> srq->wqe_shift;
  334. spin_lock(&srq->lock);
  335. if (likely(srq->first_free >= 0))
  336. *wqe_to_link(get_wqe(srq, srq->last_free)) = ind;
  337. else
  338. srq->first_free = ind;
  339. *wqe_to_link(get_wqe(srq, ind)) = -1;
  340. srq->last_free = ind;
  341. spin_unlock(&srq->lock);
  342. }
  343. int mthca_tavor_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  344. struct ib_recv_wr **bad_wr)
  345. {
  346. struct mthca_dev *dev = to_mdev(ibsrq->device);
  347. struct mthca_srq *srq = to_msrq(ibsrq);
  348. __be32 doorbell[2];
  349. unsigned long flags;
  350. int err = 0;
  351. int first_ind;
  352. int ind;
  353. int next_ind;
  354. int nreq;
  355. int i;
  356. void *wqe;
  357. void *prev_wqe;
  358. spin_lock_irqsave(&srq->lock, flags);
  359. first_ind = srq->first_free;
  360. for (nreq = 0; wr; ++nreq, wr = wr->next) {
  361. if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
  362. nreq = 0;
  363. doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift);
  364. doorbell[1] = cpu_to_be32(srq->srqn << 8);
  365. /*
  366. * Make sure that descriptors are written
  367. * before doorbell is rung.
  368. */
  369. wmb();
  370. mthca_write64(doorbell,
  371. dev->kar + MTHCA_RECEIVE_DOORBELL,
  372. MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
  373. first_ind = srq->first_free;
  374. }
  375. ind = srq->first_free;
  376. if (ind < 0) {
  377. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  378. err = -ENOMEM;
  379. *bad_wr = wr;
  380. break;
  381. }
  382. wqe = get_wqe(srq, ind);
  383. next_ind = *wqe_to_link(wqe);
  384. if (next_ind < 0) {
  385. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  386. err = -ENOMEM;
  387. *bad_wr = wr;
  388. break;
  389. }
  390. prev_wqe = srq->last;
  391. srq->last = wqe;
  392. ((struct mthca_next_seg *) wqe)->nda_op = 0;
  393. ((struct mthca_next_seg *) wqe)->ee_nds = 0;
  394. /* flags field will always remain 0 */
  395. wqe += sizeof (struct mthca_next_seg);
  396. if (unlikely(wr->num_sge > srq->max_gs)) {
  397. err = -EINVAL;
  398. *bad_wr = wr;
  399. srq->last = prev_wqe;
  400. break;
  401. }
  402. for (i = 0; i < wr->num_sge; ++i) {
  403. ((struct mthca_data_seg *) wqe)->byte_count =
  404. cpu_to_be32(wr->sg_list[i].length);
  405. ((struct mthca_data_seg *) wqe)->lkey =
  406. cpu_to_be32(wr->sg_list[i].lkey);
  407. ((struct mthca_data_seg *) wqe)->addr =
  408. cpu_to_be64(wr->sg_list[i].addr);
  409. wqe += sizeof (struct mthca_data_seg);
  410. }
  411. if (i < srq->max_gs) {
  412. ((struct mthca_data_seg *) wqe)->byte_count = 0;
  413. ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  414. ((struct mthca_data_seg *) wqe)->addr = 0;
  415. }
  416. ((struct mthca_next_seg *) prev_wqe)->nda_op =
  417. cpu_to_be32((ind << srq->wqe_shift) | 1);
  418. wmb();
  419. ((struct mthca_next_seg *) prev_wqe)->ee_nds =
  420. cpu_to_be32(MTHCA_NEXT_DBD);
  421. srq->wrid[ind] = wr->wr_id;
  422. srq->first_free = next_ind;
  423. }
  424. if (likely(nreq)) {
  425. doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift);
  426. doorbell[1] = cpu_to_be32((srq->srqn << 8) | nreq);
  427. /*
  428. * Make sure that descriptors are written before
  429. * doorbell is rung.
  430. */
  431. wmb();
  432. mthca_write64(doorbell,
  433. dev->kar + MTHCA_RECEIVE_DOORBELL,
  434. MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
  435. }
  436. spin_unlock_irqrestore(&srq->lock, flags);
  437. return err;
  438. }
  439. int mthca_arbel_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  440. struct ib_recv_wr **bad_wr)
  441. {
  442. struct mthca_dev *dev = to_mdev(ibsrq->device);
  443. struct mthca_srq *srq = to_msrq(ibsrq);
  444. unsigned long flags;
  445. int err = 0;
  446. int ind;
  447. int next_ind;
  448. int nreq;
  449. int i;
  450. void *wqe;
  451. spin_lock_irqsave(&srq->lock, flags);
  452. for (nreq = 0; wr; ++nreq, wr = wr->next) {
  453. ind = srq->first_free;
  454. if (ind < 0) {
  455. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  456. err = -ENOMEM;
  457. *bad_wr = wr;
  458. break;
  459. }
  460. wqe = get_wqe(srq, ind);
  461. next_ind = *wqe_to_link(wqe);
  462. if (next_ind < 0) {
  463. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  464. err = -ENOMEM;
  465. *bad_wr = wr;
  466. break;
  467. }
  468. ((struct mthca_next_seg *) wqe)->nda_op =
  469. cpu_to_be32((next_ind << srq->wqe_shift) | 1);
  470. ((struct mthca_next_seg *) wqe)->ee_nds = 0;
  471. /* flags field will always remain 0 */
  472. wqe += sizeof (struct mthca_next_seg);
  473. if (unlikely(wr->num_sge > srq->max_gs)) {
  474. err = -EINVAL;
  475. *bad_wr = wr;
  476. break;
  477. }
  478. for (i = 0; i < wr->num_sge; ++i) {
  479. ((struct mthca_data_seg *) wqe)->byte_count =
  480. cpu_to_be32(wr->sg_list[i].length);
  481. ((struct mthca_data_seg *) wqe)->lkey =
  482. cpu_to_be32(wr->sg_list[i].lkey);
  483. ((struct mthca_data_seg *) wqe)->addr =
  484. cpu_to_be64(wr->sg_list[i].addr);
  485. wqe += sizeof (struct mthca_data_seg);
  486. }
  487. if (i < srq->max_gs) {
  488. ((struct mthca_data_seg *) wqe)->byte_count = 0;
  489. ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  490. ((struct mthca_data_seg *) wqe)->addr = 0;
  491. }
  492. srq->wrid[ind] = wr->wr_id;
  493. srq->first_free = next_ind;
  494. }
  495. if (likely(nreq)) {
  496. srq->counter += nreq;
  497. /*
  498. * Make sure that descriptors are written before
  499. * we write doorbell record.
  500. */
  501. wmb();
  502. *srq->db = cpu_to_be32(srq->counter);
  503. }
  504. spin_unlock_irqrestore(&srq->lock, flags);
  505. return err;
  506. }
  507. int __devinit mthca_init_srq_table(struct mthca_dev *dev)
  508. {
  509. int err;
  510. if (!(dev->mthca_flags & MTHCA_FLAG_SRQ))
  511. return 0;
  512. spin_lock_init(&dev->srq_table.lock);
  513. err = mthca_alloc_init(&dev->srq_table.alloc,
  514. dev->limits.num_srqs,
  515. dev->limits.num_srqs - 1,
  516. dev->limits.reserved_srqs);
  517. if (err)
  518. return err;
  519. err = mthca_array_init(&dev->srq_table.srq,
  520. dev->limits.num_srqs);
  521. if (err)
  522. mthca_alloc_cleanup(&dev->srq_table.alloc);
  523. return err;
  524. }
  525. void __devexit mthca_cleanup_srq_table(struct mthca_dev *dev)
  526. {
  527. if (!(dev->mthca_flags & MTHCA_FLAG_SRQ))
  528. return;
  529. mthca_array_cleanup(&dev->srq_table.srq, dev->limits.num_srqs);
  530. mthca_alloc_cleanup(&dev->srq_table.alloc);
  531. }