mthca_main.c 32 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_PCI_MSI
  52. static int msi_x = 0;
  53. module_param(msi_x, int, 0444);
  54. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  55. static int msi = 0;
  56. module_param(msi, int, 0444);
  57. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #define msi (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static const char mthca_version[] __devinitdata =
  63. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  64. DRV_VERSION " (" DRV_RELDATE ")\n";
  65. static struct mthca_profile default_profile = {
  66. .num_qp = 1 << 16,
  67. .rdb_per_qp = 4,
  68. .num_cq = 1 << 16,
  69. .num_mcg = 1 << 13,
  70. .num_mpt = 1 << 17,
  71. .num_mtt = 1 << 20,
  72. .num_udav = 1 << 15, /* Tavor only */
  73. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  74. .uarc_size = 1 << 18, /* Arbel only */
  75. };
  76. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  77. {
  78. int cap;
  79. u16 val;
  80. /* First try to max out Read Byte Count */
  81. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  82. if (cap) {
  83. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  84. mthca_err(mdev, "Couldn't read PCI-X command register, "
  85. "aborting.\n");
  86. return -ENODEV;
  87. }
  88. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  89. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  90. mthca_err(mdev, "Couldn't write PCI-X command register, "
  91. "aborting.\n");
  92. return -ENODEV;
  93. }
  94. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  95. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  96. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  97. if (cap) {
  98. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  99. mthca_err(mdev, "Couldn't read PCI Express device control "
  100. "register, aborting.\n");
  101. return -ENODEV;
  102. }
  103. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  104. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  105. mthca_err(mdev, "Couldn't write PCI Express device control "
  106. "register, aborting.\n");
  107. return -ENODEV;
  108. }
  109. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  110. mthca_info(mdev, "No PCI Express capability, "
  111. "not setting Max Read Request Size.\n");
  112. return 0;
  113. }
  114. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  115. {
  116. int err;
  117. u8 status;
  118. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  119. if (err) {
  120. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  121. return err;
  122. }
  123. if (status) {
  124. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  125. "aborting.\n", status);
  126. return -EINVAL;
  127. }
  128. if (dev_lim->min_page_sz > PAGE_SIZE) {
  129. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  130. "kernel PAGE_SIZE of %ld, aborting.\n",
  131. dev_lim->min_page_sz, PAGE_SIZE);
  132. return -ENODEV;
  133. }
  134. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  135. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  136. "aborting.\n",
  137. dev_lim->num_ports, MTHCA_MAX_PORTS);
  138. return -ENODEV;
  139. }
  140. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  141. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  142. "PCI resource 2 size of 0x%lx, aborting.\n",
  143. dev_lim->uar_size, pci_resource_len(mdev->pdev, 2));
  144. return -ENODEV;
  145. }
  146. mdev->limits.num_ports = dev_lim->num_ports;
  147. mdev->limits.vl_cap = dev_lim->max_vl;
  148. mdev->limits.mtu_cap = dev_lim->max_mtu;
  149. mdev->limits.gid_table_len = dev_lim->max_gids;
  150. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  151. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  152. mdev->limits.max_sg = dev_lim->max_sg;
  153. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  154. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  155. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  156. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  157. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  158. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  159. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  160. /*
  161. * Subtract 1 from the limit because we need to allocate a
  162. * spare CQE so the HCA HW can tell the difference between an
  163. * empty CQ and a full CQ.
  164. */
  165. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  166. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  167. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  168. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  169. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  170. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  171. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  172. mdev->limits.port_width_cap = dev_lim->max_port_width;
  173. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  174. mdev->limits.flags = dev_lim->flags;
  175. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  176. May be doable since hardware supports it for SRQ.
  177. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  178. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  179. supported by driver. */
  180. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  181. IB_DEVICE_PORT_ACTIVE_EVENT |
  182. IB_DEVICE_SYS_IMAGE_GUID |
  183. IB_DEVICE_RC_RNR_NAK_GEN;
  184. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  185. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  186. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  187. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  188. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  189. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  190. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  191. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  192. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  193. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  194. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  195. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  196. return 0;
  197. }
  198. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  199. {
  200. u8 status;
  201. int err;
  202. struct mthca_dev_lim dev_lim;
  203. struct mthca_profile profile;
  204. struct mthca_init_hca_param init_hca;
  205. err = mthca_SYS_EN(mdev, &status);
  206. if (err) {
  207. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  208. return err;
  209. }
  210. if (status) {
  211. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  212. "aborting.\n", status);
  213. return -EINVAL;
  214. }
  215. err = mthca_QUERY_FW(mdev, &status);
  216. if (err) {
  217. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  218. goto err_disable;
  219. }
  220. if (status) {
  221. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  222. "aborting.\n", status);
  223. err = -EINVAL;
  224. goto err_disable;
  225. }
  226. err = mthca_QUERY_DDR(mdev, &status);
  227. if (err) {
  228. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  229. goto err_disable;
  230. }
  231. if (status) {
  232. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  233. "aborting.\n", status);
  234. err = -EINVAL;
  235. goto err_disable;
  236. }
  237. err = mthca_dev_lim(mdev, &dev_lim);
  238. if (err) {
  239. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  240. goto err_disable;
  241. }
  242. profile = default_profile;
  243. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  244. profile.uarc_size = 0;
  245. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  246. profile.num_srq = dev_lim.max_srqs;
  247. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  248. if (err < 0)
  249. goto err_disable;
  250. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  251. if (err) {
  252. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  253. goto err_disable;
  254. }
  255. if (status) {
  256. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  257. "aborting.\n", status);
  258. err = -EINVAL;
  259. goto err_disable;
  260. }
  261. return 0;
  262. err_disable:
  263. mthca_SYS_DIS(mdev, &status);
  264. return err;
  265. }
  266. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  267. {
  268. u8 status;
  269. int err;
  270. /* FIXME: use HCA-attached memory for FW if present */
  271. mdev->fw.arbel.fw_icm =
  272. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  273. GFP_HIGHUSER | __GFP_NOWARN);
  274. if (!mdev->fw.arbel.fw_icm) {
  275. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  276. return -ENOMEM;
  277. }
  278. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  279. if (err) {
  280. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  281. goto err_free;
  282. }
  283. if (status) {
  284. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  285. err = -EINVAL;
  286. goto err_free;
  287. }
  288. err = mthca_RUN_FW(mdev, &status);
  289. if (err) {
  290. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  291. goto err_unmap_fa;
  292. }
  293. if (status) {
  294. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  295. err = -EINVAL;
  296. goto err_unmap_fa;
  297. }
  298. return 0;
  299. err_unmap_fa:
  300. mthca_UNMAP_FA(mdev, &status);
  301. err_free:
  302. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  303. return err;
  304. }
  305. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  306. struct mthca_dev_lim *dev_lim,
  307. struct mthca_init_hca_param *init_hca,
  308. u64 icm_size)
  309. {
  310. u64 aux_pages;
  311. u8 status;
  312. int err;
  313. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  314. if (err) {
  315. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  316. return err;
  317. }
  318. if (status) {
  319. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  320. "aborting.\n", status);
  321. return -EINVAL;
  322. }
  323. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  324. (unsigned long long) icm_size >> 10,
  325. (unsigned long long) aux_pages << 2);
  326. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  327. GFP_HIGHUSER | __GFP_NOWARN);
  328. if (!mdev->fw.arbel.aux_icm) {
  329. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  330. return -ENOMEM;
  331. }
  332. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  333. if (err) {
  334. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  335. goto err_free_aux;
  336. }
  337. if (status) {
  338. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  339. err = -EINVAL;
  340. goto err_free_aux;
  341. }
  342. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  343. if (err) {
  344. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  345. goto err_unmap_aux;
  346. }
  347. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  348. MTHCA_MTT_SEG_SIZE,
  349. mdev->limits.num_mtt_segs,
  350. mdev->limits.reserved_mtts, 1);
  351. if (!mdev->mr_table.mtt_table) {
  352. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  353. err = -ENOMEM;
  354. goto err_unmap_eq;
  355. }
  356. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  357. dev_lim->mpt_entry_sz,
  358. mdev->limits.num_mpts,
  359. mdev->limits.reserved_mrws, 1);
  360. if (!mdev->mr_table.mpt_table) {
  361. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  362. err = -ENOMEM;
  363. goto err_unmap_mtt;
  364. }
  365. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  366. dev_lim->qpc_entry_sz,
  367. mdev->limits.num_qps,
  368. mdev->limits.reserved_qps, 0);
  369. if (!mdev->qp_table.qp_table) {
  370. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  371. err = -ENOMEM;
  372. goto err_unmap_mpt;
  373. }
  374. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  375. dev_lim->eqpc_entry_sz,
  376. mdev->limits.num_qps,
  377. mdev->limits.reserved_qps, 0);
  378. if (!mdev->qp_table.eqp_table) {
  379. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  380. err = -ENOMEM;
  381. goto err_unmap_qp;
  382. }
  383. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  384. MTHCA_RDB_ENTRY_SIZE,
  385. mdev->limits.num_qps <<
  386. mdev->qp_table.rdb_shift,
  387. 0, 0);
  388. if (!mdev->qp_table.rdb_table) {
  389. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  390. err = -ENOMEM;
  391. goto err_unmap_eqp;
  392. }
  393. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  394. dev_lim->cqc_entry_sz,
  395. mdev->limits.num_cqs,
  396. mdev->limits.reserved_cqs, 0);
  397. if (!mdev->cq_table.table) {
  398. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  399. err = -ENOMEM;
  400. goto err_unmap_rdb;
  401. }
  402. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  403. mdev->srq_table.table =
  404. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  405. dev_lim->srq_entry_sz,
  406. mdev->limits.num_srqs,
  407. mdev->limits.reserved_srqs, 0);
  408. if (!mdev->srq_table.table) {
  409. mthca_err(mdev, "Failed to map SRQ context memory, "
  410. "aborting.\n");
  411. err = -ENOMEM;
  412. goto err_unmap_cq;
  413. }
  414. }
  415. /*
  416. * It's not strictly required, but for simplicity just map the
  417. * whole multicast group table now. The table isn't very big
  418. * and it's a lot easier than trying to track ref counts.
  419. */
  420. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  421. MTHCA_MGM_ENTRY_SIZE,
  422. mdev->limits.num_mgms +
  423. mdev->limits.num_amgms,
  424. mdev->limits.num_mgms +
  425. mdev->limits.num_amgms,
  426. 0);
  427. if (!mdev->mcg_table.table) {
  428. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  429. err = -ENOMEM;
  430. goto err_unmap_srq;
  431. }
  432. return 0;
  433. err_unmap_srq:
  434. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  435. mthca_free_icm_table(mdev, mdev->srq_table.table);
  436. err_unmap_cq:
  437. mthca_free_icm_table(mdev, mdev->cq_table.table);
  438. err_unmap_rdb:
  439. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  440. err_unmap_eqp:
  441. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  442. err_unmap_qp:
  443. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  444. err_unmap_mpt:
  445. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  446. err_unmap_mtt:
  447. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  448. err_unmap_eq:
  449. mthca_unmap_eq_icm(mdev);
  450. err_unmap_aux:
  451. mthca_UNMAP_ICM_AUX(mdev, &status);
  452. err_free_aux:
  453. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  454. return err;
  455. }
  456. static void mthca_free_icms(struct mthca_dev *mdev)
  457. {
  458. u8 status;
  459. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  460. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  461. mthca_free_icm_table(mdev, mdev->srq_table.table);
  462. mthca_free_icm_table(mdev, mdev->cq_table.table);
  463. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  464. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  465. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  466. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  467. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  468. mthca_unmap_eq_icm(mdev);
  469. mthca_UNMAP_ICM_AUX(mdev, &status);
  470. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  471. }
  472. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  473. {
  474. struct mthca_dev_lim dev_lim;
  475. struct mthca_profile profile;
  476. struct mthca_init_hca_param init_hca;
  477. u64 icm_size;
  478. u8 status;
  479. int err;
  480. err = mthca_QUERY_FW(mdev, &status);
  481. if (err) {
  482. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  483. return err;
  484. }
  485. if (status) {
  486. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  487. "aborting.\n", status);
  488. return -EINVAL;
  489. }
  490. err = mthca_ENABLE_LAM(mdev, &status);
  491. if (err) {
  492. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  493. return err;
  494. }
  495. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  496. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  497. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  498. } else if (status) {
  499. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  500. "aborting.\n", status);
  501. return -EINVAL;
  502. }
  503. err = mthca_load_fw(mdev);
  504. if (err) {
  505. mthca_err(mdev, "Failed to start FW, aborting.\n");
  506. goto err_disable;
  507. }
  508. err = mthca_dev_lim(mdev, &dev_lim);
  509. if (err) {
  510. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  511. goto err_stop_fw;
  512. }
  513. profile = default_profile;
  514. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  515. profile.num_udav = 0;
  516. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  517. profile.num_srq = dev_lim.max_srqs;
  518. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  519. if ((int) icm_size < 0) {
  520. err = icm_size;
  521. goto err_stop_fw;
  522. }
  523. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  524. if (err)
  525. goto err_stop_fw;
  526. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  527. if (err) {
  528. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  529. goto err_free_icm;
  530. }
  531. if (status) {
  532. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  533. "aborting.\n", status);
  534. err = -EINVAL;
  535. goto err_free_icm;
  536. }
  537. return 0;
  538. err_free_icm:
  539. mthca_free_icms(mdev);
  540. err_stop_fw:
  541. mthca_UNMAP_FA(mdev, &status);
  542. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  543. err_disable:
  544. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  545. mthca_DISABLE_LAM(mdev, &status);
  546. return err;
  547. }
  548. static void mthca_close_hca(struct mthca_dev *mdev)
  549. {
  550. u8 status;
  551. mthca_CLOSE_HCA(mdev, 0, &status);
  552. if (mthca_is_memfree(mdev)) {
  553. mthca_free_icms(mdev);
  554. mthca_UNMAP_FA(mdev, &status);
  555. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  556. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  557. mthca_DISABLE_LAM(mdev, &status);
  558. } else
  559. mthca_SYS_DIS(mdev, &status);
  560. }
  561. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  562. {
  563. u8 status;
  564. int err;
  565. struct mthca_adapter adapter;
  566. if (mthca_is_memfree(mdev))
  567. err = mthca_init_arbel(mdev);
  568. else
  569. err = mthca_init_tavor(mdev);
  570. if (err)
  571. return err;
  572. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  573. if (err) {
  574. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  575. goto err_close;
  576. }
  577. if (status) {
  578. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  579. "aborting.\n", status);
  580. err = -EINVAL;
  581. goto err_close;
  582. }
  583. mdev->eq_table.inta_pin = adapter.inta_pin;
  584. mdev->rev_id = adapter.revision_id;
  585. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  586. return 0;
  587. err_close:
  588. mthca_close_hca(mdev);
  589. return err;
  590. }
  591. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  592. {
  593. int err;
  594. u8 status;
  595. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  596. err = mthca_init_uar_table(dev);
  597. if (err) {
  598. mthca_err(dev, "Failed to initialize "
  599. "user access region table, aborting.\n");
  600. return err;
  601. }
  602. err = mthca_uar_alloc(dev, &dev->driver_uar);
  603. if (err) {
  604. mthca_err(dev, "Failed to allocate driver access region, "
  605. "aborting.\n");
  606. goto err_uar_table_free;
  607. }
  608. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  609. if (!dev->kar) {
  610. mthca_err(dev, "Couldn't map kernel access region, "
  611. "aborting.\n");
  612. err = -ENOMEM;
  613. goto err_uar_free;
  614. }
  615. err = mthca_init_pd_table(dev);
  616. if (err) {
  617. mthca_err(dev, "Failed to initialize "
  618. "protection domain table, aborting.\n");
  619. goto err_kar_unmap;
  620. }
  621. err = mthca_init_mr_table(dev);
  622. if (err) {
  623. mthca_err(dev, "Failed to initialize "
  624. "memory region table, aborting.\n");
  625. goto err_pd_table_free;
  626. }
  627. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  628. if (err) {
  629. mthca_err(dev, "Failed to create driver PD, "
  630. "aborting.\n");
  631. goto err_mr_table_free;
  632. }
  633. err = mthca_init_eq_table(dev);
  634. if (err) {
  635. mthca_err(dev, "Failed to initialize "
  636. "event queue table, aborting.\n");
  637. goto err_pd_free;
  638. }
  639. err = mthca_cmd_use_events(dev);
  640. if (err) {
  641. mthca_err(dev, "Failed to switch to event-driven "
  642. "firmware commands, aborting.\n");
  643. goto err_eq_table_free;
  644. }
  645. err = mthca_NOP(dev, &status);
  646. if (err || status) {
  647. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  648. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  649. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  650. dev->pdev->irq);
  651. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  652. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  653. else
  654. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  655. goto err_cmd_poll;
  656. }
  657. mthca_dbg(dev, "NOP command IRQ test passed\n");
  658. err = mthca_init_cq_table(dev);
  659. if (err) {
  660. mthca_err(dev, "Failed to initialize "
  661. "completion queue table, aborting.\n");
  662. goto err_cmd_poll;
  663. }
  664. err = mthca_init_srq_table(dev);
  665. if (err) {
  666. mthca_err(dev, "Failed to initialize "
  667. "shared receive queue table, aborting.\n");
  668. goto err_cq_table_free;
  669. }
  670. err = mthca_init_qp_table(dev);
  671. if (err) {
  672. mthca_err(dev, "Failed to initialize "
  673. "queue pair table, aborting.\n");
  674. goto err_srq_table_free;
  675. }
  676. err = mthca_init_av_table(dev);
  677. if (err) {
  678. mthca_err(dev, "Failed to initialize "
  679. "address vector table, aborting.\n");
  680. goto err_qp_table_free;
  681. }
  682. err = mthca_init_mcg_table(dev);
  683. if (err) {
  684. mthca_err(dev, "Failed to initialize "
  685. "multicast group table, aborting.\n");
  686. goto err_av_table_free;
  687. }
  688. return 0;
  689. err_av_table_free:
  690. mthca_cleanup_av_table(dev);
  691. err_qp_table_free:
  692. mthca_cleanup_qp_table(dev);
  693. err_srq_table_free:
  694. mthca_cleanup_srq_table(dev);
  695. err_cq_table_free:
  696. mthca_cleanup_cq_table(dev);
  697. err_cmd_poll:
  698. mthca_cmd_use_polling(dev);
  699. err_eq_table_free:
  700. mthca_cleanup_eq_table(dev);
  701. err_pd_free:
  702. mthca_pd_free(dev, &dev->driver_pd);
  703. err_mr_table_free:
  704. mthca_cleanup_mr_table(dev);
  705. err_pd_table_free:
  706. mthca_cleanup_pd_table(dev);
  707. err_kar_unmap:
  708. iounmap(dev->kar);
  709. err_uar_free:
  710. mthca_uar_free(dev, &dev->driver_uar);
  711. err_uar_table_free:
  712. mthca_cleanup_uar_table(dev);
  713. return err;
  714. }
  715. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  716. int ddr_hidden)
  717. {
  718. int err;
  719. /*
  720. * We can't just use pci_request_regions() because the MSI-X
  721. * table is right in the middle of the first BAR. If we did
  722. * pci_request_region and grab all of the first BAR, then
  723. * setting up MSI-X would fail, since the PCI core wants to do
  724. * request_mem_region on the MSI-X vector table.
  725. *
  726. * So just request what we need right now, and request any
  727. * other regions we need when setting up EQs.
  728. */
  729. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  730. MTHCA_HCR_SIZE, DRV_NAME))
  731. return -EBUSY;
  732. err = pci_request_region(pdev, 2, DRV_NAME);
  733. if (err)
  734. goto err_bar2_failed;
  735. if (!ddr_hidden) {
  736. err = pci_request_region(pdev, 4, DRV_NAME);
  737. if (err)
  738. goto err_bar4_failed;
  739. }
  740. return 0;
  741. err_bar4_failed:
  742. pci_release_region(pdev, 2);
  743. err_bar2_failed:
  744. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  745. MTHCA_HCR_SIZE);
  746. return err;
  747. }
  748. static void mthca_release_regions(struct pci_dev *pdev,
  749. int ddr_hidden)
  750. {
  751. if (!ddr_hidden)
  752. pci_release_region(pdev, 4);
  753. pci_release_region(pdev, 2);
  754. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  755. MTHCA_HCR_SIZE);
  756. }
  757. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  758. {
  759. struct msix_entry entries[3];
  760. int err;
  761. entries[0].entry = 0;
  762. entries[1].entry = 1;
  763. entries[2].entry = 2;
  764. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  765. if (err) {
  766. if (err > 0)
  767. mthca_info(mdev, "Only %d MSI-X vectors available, "
  768. "not using MSI-X\n", err);
  769. return err;
  770. }
  771. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  772. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  773. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  774. return 0;
  775. }
  776. /* Types of supported HCA */
  777. enum {
  778. TAVOR, /* MT23108 */
  779. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  780. ARBEL_NATIVE, /* MT25208 with extended features */
  781. SINAI /* MT25204 */
  782. };
  783. #define MTHCA_FW_VER(major, minor, subminor) \
  784. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  785. static struct {
  786. u64 latest_fw;
  787. int is_memfree;
  788. int is_pcie;
  789. } mthca_hca_table[] = {
  790. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3), .is_memfree = 0, .is_pcie = 0 },
  791. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0), .is_memfree = 0, .is_pcie = 1 },
  792. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0), .is_memfree = 1, .is_pcie = 1 },
  793. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1), .is_memfree = 1, .is_pcie = 1 }
  794. };
  795. static int __devinit mthca_init_one(struct pci_dev *pdev,
  796. const struct pci_device_id *id)
  797. {
  798. static int mthca_version_printed = 0;
  799. int ddr_hidden = 0;
  800. int err;
  801. struct mthca_dev *mdev;
  802. if (!mthca_version_printed) {
  803. printk(KERN_INFO "%s", mthca_version);
  804. ++mthca_version_printed;
  805. }
  806. printk(KERN_INFO PFX "Initializing %s\n",
  807. pci_name(pdev));
  808. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  809. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  810. pci_name(pdev), id->driver_data);
  811. return -ENODEV;
  812. }
  813. err = pci_enable_device(pdev);
  814. if (err) {
  815. dev_err(&pdev->dev, "Cannot enable PCI device, "
  816. "aborting.\n");
  817. return err;
  818. }
  819. /*
  820. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  821. * be present)
  822. */
  823. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  824. pci_resource_len(pdev, 0) != 1 << 20) {
  825. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  826. err = -ENODEV;
  827. goto err_disable_pdev;
  828. }
  829. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  830. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  831. err = -ENODEV;
  832. goto err_disable_pdev;
  833. }
  834. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  835. ddr_hidden = 1;
  836. err = mthca_request_regions(pdev, ddr_hidden);
  837. if (err) {
  838. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  839. "aborting.\n");
  840. goto err_disable_pdev;
  841. }
  842. pci_set_master(pdev);
  843. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  844. if (err) {
  845. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  846. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  847. if (err) {
  848. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  849. goto err_free_res;
  850. }
  851. }
  852. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  853. if (err) {
  854. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  855. "consistent PCI DMA mask.\n");
  856. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  857. if (err) {
  858. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  859. "aborting.\n");
  860. goto err_free_res;
  861. }
  862. }
  863. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  864. if (!mdev) {
  865. dev_err(&pdev->dev, "Device struct alloc failed, "
  866. "aborting.\n");
  867. err = -ENOMEM;
  868. goto err_free_res;
  869. }
  870. mdev->pdev = pdev;
  871. if (ddr_hidden)
  872. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  873. if (mthca_hca_table[id->driver_data].is_memfree)
  874. mdev->mthca_flags |= MTHCA_FLAG_MEMFREE;
  875. if (mthca_hca_table[id->driver_data].is_pcie)
  876. mdev->mthca_flags |= MTHCA_FLAG_PCIE;
  877. /*
  878. * Now reset the HCA before we touch the PCI capabilities or
  879. * attempt a firmware command, since a boot ROM may have left
  880. * the HCA in an undefined state.
  881. */
  882. err = mthca_reset(mdev);
  883. if (err) {
  884. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  885. goto err_free_dev;
  886. }
  887. if (msi_x && !mthca_enable_msi_x(mdev))
  888. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  889. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  890. !pci_enable_msi(pdev))
  891. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  892. if (mthca_cmd_init(mdev)) {
  893. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  894. goto err_free_dev;
  895. }
  896. err = mthca_tune_pci(mdev);
  897. if (err)
  898. goto err_cmd;
  899. err = mthca_init_hca(mdev);
  900. if (err)
  901. goto err_cmd;
  902. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  903. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  904. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  905. (int) (mdev->fw_ver & 0xffff),
  906. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  907. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  908. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  909. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  910. }
  911. err = mthca_setup_hca(mdev);
  912. if (err)
  913. goto err_close;
  914. err = mthca_register_device(mdev);
  915. if (err)
  916. goto err_cleanup;
  917. err = mthca_create_agents(mdev);
  918. if (err)
  919. goto err_unregister;
  920. pci_set_drvdata(pdev, mdev);
  921. return 0;
  922. err_unregister:
  923. mthca_unregister_device(mdev);
  924. err_cleanup:
  925. mthca_cleanup_mcg_table(mdev);
  926. mthca_cleanup_av_table(mdev);
  927. mthca_cleanup_qp_table(mdev);
  928. mthca_cleanup_srq_table(mdev);
  929. mthca_cleanup_cq_table(mdev);
  930. mthca_cmd_use_polling(mdev);
  931. mthca_cleanup_eq_table(mdev);
  932. mthca_pd_free(mdev, &mdev->driver_pd);
  933. mthca_cleanup_mr_table(mdev);
  934. mthca_cleanup_pd_table(mdev);
  935. mthca_cleanup_uar_table(mdev);
  936. err_close:
  937. mthca_close_hca(mdev);
  938. err_cmd:
  939. mthca_cmd_cleanup(mdev);
  940. err_free_dev:
  941. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  942. pci_disable_msix(pdev);
  943. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  944. pci_disable_msi(pdev);
  945. ib_dealloc_device(&mdev->ib_dev);
  946. err_free_res:
  947. mthca_release_regions(pdev, ddr_hidden);
  948. err_disable_pdev:
  949. pci_disable_device(pdev);
  950. pci_set_drvdata(pdev, NULL);
  951. return err;
  952. }
  953. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  954. {
  955. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  956. u8 status;
  957. int p;
  958. if (mdev) {
  959. mthca_free_agents(mdev);
  960. mthca_unregister_device(mdev);
  961. for (p = 1; p <= mdev->limits.num_ports; ++p)
  962. mthca_CLOSE_IB(mdev, p, &status);
  963. mthca_cleanup_mcg_table(mdev);
  964. mthca_cleanup_av_table(mdev);
  965. mthca_cleanup_qp_table(mdev);
  966. mthca_cleanup_srq_table(mdev);
  967. mthca_cleanup_cq_table(mdev);
  968. mthca_cmd_use_polling(mdev);
  969. mthca_cleanup_eq_table(mdev);
  970. mthca_pd_free(mdev, &mdev->driver_pd);
  971. mthca_cleanup_mr_table(mdev);
  972. mthca_cleanup_pd_table(mdev);
  973. iounmap(mdev->kar);
  974. mthca_uar_free(mdev, &mdev->driver_uar);
  975. mthca_cleanup_uar_table(mdev);
  976. mthca_close_hca(mdev);
  977. mthca_cmd_cleanup(mdev);
  978. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  979. pci_disable_msix(pdev);
  980. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  981. pci_disable_msi(pdev);
  982. ib_dealloc_device(&mdev->ib_dev);
  983. mthca_release_regions(pdev, mdev->mthca_flags &
  984. MTHCA_FLAG_DDR_HIDDEN);
  985. pci_disable_device(pdev);
  986. pci_set_drvdata(pdev, NULL);
  987. }
  988. }
  989. static struct pci_device_id mthca_pci_table[] = {
  990. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  991. .driver_data = TAVOR },
  992. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  993. .driver_data = TAVOR },
  994. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  995. .driver_data = ARBEL_COMPAT },
  996. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  997. .driver_data = ARBEL_COMPAT },
  998. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  999. .driver_data = ARBEL_NATIVE },
  1000. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1001. .driver_data = ARBEL_NATIVE },
  1002. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1003. .driver_data = SINAI },
  1004. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1005. .driver_data = SINAI },
  1006. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1007. .driver_data = SINAI },
  1008. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1009. .driver_data = SINAI },
  1010. { 0, }
  1011. };
  1012. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1013. static struct pci_driver mthca_driver = {
  1014. .name = DRV_NAME,
  1015. .id_table = mthca_pci_table,
  1016. .probe = mthca_init_one,
  1017. .remove = __devexit_p(mthca_remove_one)
  1018. };
  1019. static int __init mthca_init(void)
  1020. {
  1021. int ret;
  1022. ret = pci_register_driver(&mthca_driver);
  1023. return ret < 0 ? ret : 0;
  1024. }
  1025. static void __exit mthca_cleanup(void)
  1026. {
  1027. pci_unregister_driver(&mthca_driver);
  1028. }
  1029. module_init(mthca_init);
  1030. module_exit(mthca_cleanup);