video1394.c 42 KB

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  1. /*
  2. * video1394.c - video driver for OHCI 1394 boards
  3. * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
  4. * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. * NOTES:
  21. *
  22. * ioctl return codes:
  23. * EFAULT is only for invalid address for the argp
  24. * EINVAL for out of range values
  25. * EBUSY when trying to use an already used resource
  26. * ESRCH when trying to free/stop a not used resource
  27. * EAGAIN for resource allocation failure that could perhaps succeed later
  28. * ENOTTY for unsupported ioctl request
  29. *
  30. */
  31. #include <linux/config.h>
  32. #include <linux/kernel.h>
  33. #include <linux/list.h>
  34. #include <linux/slab.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/wait.h>
  37. #include <linux/errno.h>
  38. #include <linux/module.h>
  39. #include <linux/init.h>
  40. #include <linux/pci.h>
  41. #include <linux/fs.h>
  42. #include <linux/poll.h>
  43. #include <linux/smp_lock.h>
  44. #include <linux/delay.h>
  45. #include <linux/devfs_fs_kernel.h>
  46. #include <linux/bitops.h>
  47. #include <linux/types.h>
  48. #include <linux/vmalloc.h>
  49. #include <linux/timex.h>
  50. #include <linux/mm.h>
  51. #include <linux/compat.h>
  52. #include <linux/cdev.h>
  53. #include "ieee1394.h"
  54. #include "ieee1394_types.h"
  55. #include "hosts.h"
  56. #include "ieee1394_core.h"
  57. #include "highlevel.h"
  58. #include "video1394.h"
  59. #include "nodemgr.h"
  60. #include "dma.h"
  61. #include "ohci1394.h"
  62. #define ISO_CHANNELS 64
  63. struct it_dma_prg {
  64. struct dma_cmd begin;
  65. quadlet_t data[4];
  66. struct dma_cmd end;
  67. quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  68. };
  69. struct dma_iso_ctx {
  70. struct ti_ohci *ohci;
  71. int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
  72. struct ohci1394_iso_tasklet iso_tasklet;
  73. int channel;
  74. int ctx;
  75. int last_buffer;
  76. int * next_buffer; /* For ISO Transmit of video packets
  77. to write the correct SYT field
  78. into the next block */
  79. unsigned int num_desc;
  80. unsigned int buf_size;
  81. unsigned int frame_size;
  82. unsigned int packet_size;
  83. unsigned int left_size;
  84. unsigned int nb_cmd;
  85. struct dma_region dma;
  86. struct dma_prog_region *prg_reg;
  87. struct dma_cmd **ir_prg;
  88. struct it_dma_prg **it_prg;
  89. unsigned int *buffer_status;
  90. unsigned int *buffer_prg_assignment;
  91. struct timeval *buffer_time; /* time when the buffer was received */
  92. unsigned int *last_used_cmd; /* For ISO Transmit with
  93. variable sized packets only ! */
  94. int ctrlClear;
  95. int ctrlSet;
  96. int cmdPtr;
  97. int ctxMatch;
  98. wait_queue_head_t waitq;
  99. spinlock_t lock;
  100. unsigned int syt_offset;
  101. int flags;
  102. struct list_head link;
  103. };
  104. struct file_ctx {
  105. struct ti_ohci *ohci;
  106. struct list_head context_list;
  107. struct dma_iso_ctx *current_ctx;
  108. };
  109. #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  110. #define VIDEO1394_DEBUG
  111. #endif
  112. #ifdef DBGMSG
  113. #undef DBGMSG
  114. #endif
  115. #ifdef VIDEO1394_DEBUG
  116. #define DBGMSG(card, fmt, args...) \
  117. printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
  118. #else
  119. #define DBGMSG(card, fmt, args...)
  120. #endif
  121. /* print general (card independent) information */
  122. #define PRINT_G(level, fmt, args...) \
  123. printk(level "video1394: " fmt "\n" , ## args)
  124. /* print card specific information */
  125. #define PRINT(level, card, fmt, args...) \
  126. printk(level "video1394_%d: " fmt "\n" , card , ## args)
  127. static void wakeup_dma_ir_ctx(unsigned long l);
  128. static void wakeup_dma_it_ctx(unsigned long l);
  129. static struct hpsb_highlevel video1394_highlevel;
  130. static int free_dma_iso_ctx(struct dma_iso_ctx *d)
  131. {
  132. int i;
  133. DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
  134. ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
  135. if (d->iso_tasklet.link.next != NULL)
  136. ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
  137. dma_region_free(&d->dma);
  138. if (d->prg_reg) {
  139. for (i = 0; i < d->num_desc; i++)
  140. dma_prog_region_free(&d->prg_reg[i]);
  141. kfree(d->prg_reg);
  142. }
  143. kfree(d->ir_prg);
  144. kfree(d->it_prg);
  145. kfree(d->buffer_status);
  146. kfree(d->buffer_prg_assignment);
  147. kfree(d->buffer_time);
  148. kfree(d->last_used_cmd);
  149. kfree(d->next_buffer);
  150. list_del(&d->link);
  151. kfree(d);
  152. return 0;
  153. }
  154. static struct dma_iso_ctx *
  155. alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
  156. int buf_size, int channel, unsigned int packet_size)
  157. {
  158. struct dma_iso_ctx *d;
  159. int i;
  160. d = kzalloc(sizeof(*d), GFP_KERNEL);
  161. if (!d) {
  162. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
  163. return NULL;
  164. }
  165. d->ohci = ohci;
  166. d->type = type;
  167. d->channel = channel;
  168. d->num_desc = num_desc;
  169. d->frame_size = buf_size;
  170. d->buf_size = PAGE_ALIGN(buf_size);
  171. d->last_buffer = -1;
  172. INIT_LIST_HEAD(&d->link);
  173. init_waitqueue_head(&d->waitq);
  174. /* Init the regions for easy cleanup */
  175. dma_region_init(&d->dma);
  176. if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev,
  177. PCI_DMA_BIDIRECTIONAL)) {
  178. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
  179. free_dma_iso_ctx(d);
  180. return NULL;
  181. }
  182. if (type == OHCI_ISO_RECEIVE)
  183. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  184. wakeup_dma_ir_ctx,
  185. (unsigned long) d);
  186. else
  187. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  188. wakeup_dma_it_ctx,
  189. (unsigned long) d);
  190. if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
  191. PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
  192. type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
  193. free_dma_iso_ctx(d);
  194. return NULL;
  195. }
  196. d->ctx = d->iso_tasklet.context;
  197. d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL);
  198. if (!d->prg_reg) {
  199. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
  200. free_dma_iso_ctx(d);
  201. return NULL;
  202. }
  203. /* Makes for easier cleanup */
  204. for (i = 0; i < d->num_desc; i++)
  205. dma_prog_region_init(&d->prg_reg[i]);
  206. if (type == OHCI_ISO_RECEIVE) {
  207. d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
  208. d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
  209. d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
  210. d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
  211. d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg),
  212. GFP_KERNEL);
  213. if (!d->ir_prg) {
  214. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  215. free_dma_iso_ctx(d);
  216. return NULL;
  217. }
  218. d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
  219. d->left_size = (d->frame_size % PAGE_SIZE) ?
  220. d->frame_size % PAGE_SIZE : PAGE_SIZE;
  221. for (i = 0;i < d->num_desc; i++) {
  222. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  223. sizeof(struct dma_cmd), ohci->dev)) {
  224. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  225. free_dma_iso_ctx(d);
  226. return NULL;
  227. }
  228. d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
  229. }
  230. } else { /* OHCI_ISO_TRANSMIT */
  231. d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
  232. d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
  233. d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
  234. d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg),
  235. GFP_KERNEL);
  236. if (!d->it_prg) {
  237. PRINT(KERN_ERR, ohci->host->id,
  238. "Failed to allocate dma it prg");
  239. free_dma_iso_ctx(d);
  240. return NULL;
  241. }
  242. d->packet_size = packet_size;
  243. if (PAGE_SIZE % packet_size || packet_size>4096) {
  244. PRINT(KERN_ERR, ohci->host->id,
  245. "Packet size %d (page_size: %ld) "
  246. "not yet supported\n",
  247. packet_size, PAGE_SIZE);
  248. free_dma_iso_ctx(d);
  249. return NULL;
  250. }
  251. d->nb_cmd = d->frame_size / d->packet_size;
  252. if (d->frame_size % d->packet_size) {
  253. d->nb_cmd++;
  254. d->left_size = d->frame_size % d->packet_size;
  255. } else
  256. d->left_size = d->packet_size;
  257. for (i = 0; i < d->num_desc; i++) {
  258. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  259. sizeof(struct it_dma_prg), ohci->dev)) {
  260. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
  261. free_dma_iso_ctx(d);
  262. return NULL;
  263. }
  264. d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
  265. }
  266. }
  267. d->buffer_status =
  268. kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL);
  269. d->buffer_prg_assignment =
  270. kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL);
  271. d->buffer_time =
  272. kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL);
  273. d->last_used_cmd =
  274. kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL);
  275. d->next_buffer =
  276. kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL);
  277. if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time ||
  278. !d->last_used_cmd || !d->next_buffer) {
  279. PRINT(KERN_ERR, ohci->host->id,
  280. "Failed to allocate dma_iso_ctx member");
  281. free_dma_iso_ctx(d);
  282. return NULL;
  283. }
  284. spin_lock_init(&d->lock);
  285. PRINT(KERN_INFO, ohci->host->id, "Iso %s DMA: %d buffers "
  286. "of size %d allocated for a frame size %d, each with %d prgs",
  287. (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
  288. d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd);
  289. return d;
  290. }
  291. static void reset_ir_status(struct dma_iso_ctx *d, int n)
  292. {
  293. int i;
  294. d->ir_prg[n][0].status = cpu_to_le32(4);
  295. d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
  296. for (i = 2; i < d->nb_cmd - 1; i++)
  297. d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
  298. d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
  299. }
  300. static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags)
  301. {
  302. struct dma_cmd *ir_prg = d->ir_prg[n];
  303. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  304. int i;
  305. d->buffer_prg_assignment[n] = buffer;
  306. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  307. (unsigned long)d->dma.kvirt));
  308. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  309. (buf + 4) - (unsigned long)d->dma.kvirt));
  310. for (i=2;i<d->nb_cmd-1;i++) {
  311. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  312. (buf+(i-1)*PAGE_SIZE) -
  313. (unsigned long)d->dma.kvirt));
  314. }
  315. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  316. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  317. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  318. (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt));
  319. }
  320. static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
  321. {
  322. struct dma_cmd *ir_prg = d->ir_prg[n];
  323. struct dma_prog_region *ir_reg = &d->prg_reg[n];
  324. unsigned long buf = (unsigned long)d->dma.kvirt;
  325. int i;
  326. /* the first descriptor will read only 4 bytes */
  327. ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  328. DMA_CTL_BRANCH | 4);
  329. /* set the sync flag */
  330. if (flags & VIDEO1394_SYNC_FRAMES)
  331. ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
  332. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  333. (unsigned long)d->dma.kvirt));
  334. ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  335. 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  336. /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
  337. if (d->nb_cmd > 2) {
  338. /* The second descriptor will read PAGE_SIZE-4 bytes */
  339. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  340. DMA_CTL_BRANCH | (PAGE_SIZE-4));
  341. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
  342. (unsigned long)d->dma.kvirt));
  343. ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  344. 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  345. for (i = 2; i < d->nb_cmd - 1; i++) {
  346. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  347. DMA_CTL_BRANCH | PAGE_SIZE);
  348. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  349. (buf+(i-1)*PAGE_SIZE) -
  350. (unsigned long)d->dma.kvirt));
  351. ir_prg[i].branchAddress =
  352. cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  353. (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  354. }
  355. /* The last descriptor will generate an interrupt */
  356. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  357. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  358. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  359. (buf+(i-1)*PAGE_SIZE) -
  360. (unsigned long)d->dma.kvirt));
  361. } else {
  362. /* Only one DMA page is used. Read d->left_size immediately and */
  363. /* generate an interrupt as this is also the last page. */
  364. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  365. DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
  366. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  367. (buf + 4) - (unsigned long)d->dma.kvirt));
  368. }
  369. }
  370. static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
  371. {
  372. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  373. int i;
  374. d->flags = flags;
  375. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  376. for (i=0;i<d->num_desc;i++) {
  377. initialize_dma_ir_prg(d, i, flags);
  378. reset_ir_status(d, i);
  379. }
  380. /* reset the ctrl register */
  381. reg_write(ohci, d->ctrlClear, 0xf0000000);
  382. /* Set bufferFill */
  383. reg_write(ohci, d->ctrlSet, 0x80000000);
  384. /* Set isoch header */
  385. if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
  386. reg_write(ohci, d->ctrlSet, 0x40000000);
  387. /* Set the context match register to match on all tags,
  388. sync for sync tag, and listen to d->channel */
  389. reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
  390. /* Set up isoRecvIntMask to generate interrupts */
  391. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
  392. }
  393. /* find which context is listening to this channel */
  394. static struct dma_iso_ctx *
  395. find_ctx(struct list_head *list, int type, int channel)
  396. {
  397. struct dma_iso_ctx *ctx;
  398. list_for_each_entry(ctx, list, link) {
  399. if (ctx->type == type && ctx->channel == channel)
  400. return ctx;
  401. }
  402. return NULL;
  403. }
  404. static void wakeup_dma_ir_ctx(unsigned long l)
  405. {
  406. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  407. int i;
  408. spin_lock(&d->lock);
  409. for (i = 0; i < d->num_desc; i++) {
  410. if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
  411. reset_ir_status(d, i);
  412. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  413. do_gettimeofday(&d->buffer_time[d->buffer_prg_assignment[i]]);
  414. }
  415. }
  416. spin_unlock(&d->lock);
  417. if (waitqueue_active(&d->waitq))
  418. wake_up_interruptible(&d->waitq);
  419. }
  420. static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
  421. int n)
  422. {
  423. unsigned char* buf = d->dma.kvirt + n * d->buf_size;
  424. u32 cycleTimer;
  425. u32 timeStamp;
  426. if (n == -1) {
  427. return;
  428. }
  429. cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  430. timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
  431. timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
  432. + (cycleTimer & 0xf000)) & 0xffff;
  433. buf[6] = timeStamp >> 8;
  434. buf[7] = timeStamp & 0xff;
  435. /* if first packet is empty packet, then put timestamp into the next full one too */
  436. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  437. buf += d->packet_size;
  438. buf[6] = timeStamp >> 8;
  439. buf[7] = timeStamp & 0xff;
  440. }
  441. /* do the next buffer frame too in case of irq latency */
  442. n = d->next_buffer[n];
  443. if (n == -1) {
  444. return;
  445. }
  446. buf = d->dma.kvirt + n * d->buf_size;
  447. timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
  448. buf[6] = timeStamp >> 8;
  449. buf[7] = timeStamp & 0xff;
  450. /* if first packet is empty packet, then put timestamp into the next full one too */
  451. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  452. buf += d->packet_size;
  453. buf[6] = timeStamp >> 8;
  454. buf[7] = timeStamp & 0xff;
  455. }
  456. #if 0
  457. printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
  458. curr, n, cycleTimer, timeStamp);
  459. #endif
  460. }
  461. static void wakeup_dma_it_ctx(unsigned long l)
  462. {
  463. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  464. struct ti_ohci *ohci = d->ohci;
  465. int i;
  466. spin_lock(&d->lock);
  467. for (i = 0; i < d->num_desc; i++) {
  468. if (d->it_prg[i][d->last_used_cmd[i]].end.status &
  469. cpu_to_le32(0xFFFF0000)) {
  470. int next = d->next_buffer[i];
  471. put_timestamp(ohci, d, next);
  472. d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
  473. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  474. }
  475. }
  476. spin_unlock(&d->lock);
  477. if (waitqueue_active(&d->waitq))
  478. wake_up_interruptible(&d->waitq);
  479. }
  480. static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer)
  481. {
  482. struct it_dma_prg *it_prg = d->it_prg[n];
  483. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  484. int i;
  485. d->buffer_prg_assignment[n] = buffer;
  486. for (i=0;i<d->nb_cmd;i++) {
  487. it_prg[i].end.address =
  488. cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  489. (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt));
  490. }
  491. }
  492. static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
  493. {
  494. struct it_dma_prg *it_prg = d->it_prg[n];
  495. struct dma_prog_region *it_reg = &d->prg_reg[n];
  496. unsigned long buf = (unsigned long)d->dma.kvirt;
  497. int i;
  498. d->last_used_cmd[n] = d->nb_cmd - 1;
  499. for (i=0;i<d->nb_cmd;i++) {
  500. it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
  501. DMA_CTL_IMMEDIATE | 8) ;
  502. it_prg[i].begin.address = 0;
  503. it_prg[i].begin.status = 0;
  504. it_prg[i].data[0] = cpu_to_le32(
  505. (IEEE1394_SPEED_100 << 16)
  506. | (/* tag */ 1 << 14)
  507. | (d->channel << 8)
  508. | (TCODE_ISO_DATA << 4));
  509. if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
  510. it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
  511. it_prg[i].data[2] = 0;
  512. it_prg[i].data[3] = 0;
  513. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
  514. DMA_CTL_BRANCH);
  515. it_prg[i].end.address =
  516. cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
  517. (unsigned long)d->dma.kvirt));
  518. if (i<d->nb_cmd-1) {
  519. it_prg[i].end.control |= cpu_to_le32(d->packet_size);
  520. it_prg[i].begin.branchAddress =
  521. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  522. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  523. it_prg[i].end.branchAddress =
  524. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  525. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  526. } else {
  527. /* the last prg generates an interrupt */
  528. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  529. DMA_CTL_IRQ | d->left_size);
  530. /* the last prg doesn't branch */
  531. it_prg[i].begin.branchAddress = 0;
  532. it_prg[i].end.branchAddress = 0;
  533. }
  534. it_prg[i].end.status = 0;
  535. }
  536. }
  537. static void initialize_dma_it_prg_var_packet_queue(
  538. struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
  539. struct ti_ohci *ohci)
  540. {
  541. struct it_dma_prg *it_prg = d->it_prg[n];
  542. struct dma_prog_region *it_reg = &d->prg_reg[n];
  543. int i;
  544. #if 0
  545. if (n != -1) {
  546. put_timestamp(ohci, d, n);
  547. }
  548. #endif
  549. d->last_used_cmd[n] = d->nb_cmd - 1;
  550. for (i = 0; i < d->nb_cmd; i++) {
  551. unsigned int size;
  552. if (packet_sizes[i] > d->packet_size) {
  553. size = d->packet_size;
  554. } else {
  555. size = packet_sizes[i];
  556. }
  557. it_prg[i].data[1] = cpu_to_le32(size << 16);
  558. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
  559. if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
  560. it_prg[i].end.control |= cpu_to_le32(size);
  561. it_prg[i].begin.branchAddress =
  562. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  563. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  564. it_prg[i].end.branchAddress =
  565. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  566. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  567. } else {
  568. /* the last prg generates an interrupt */
  569. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  570. DMA_CTL_IRQ | size);
  571. /* the last prg doesn't branch */
  572. it_prg[i].begin.branchAddress = 0;
  573. it_prg[i].end.branchAddress = 0;
  574. d->last_used_cmd[n] = i;
  575. break;
  576. }
  577. }
  578. }
  579. static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
  580. unsigned int syt_offset, int flags)
  581. {
  582. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  583. int i;
  584. d->flags = flags;
  585. d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
  586. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  587. for (i=0;i<d->num_desc;i++)
  588. initialize_dma_it_prg(d, i, sync_tag);
  589. /* Set up isoRecvIntMask to generate interrupts */
  590. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
  591. }
  592. static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
  593. unsigned int buffer)
  594. {
  595. unsigned long flags;
  596. unsigned int ret;
  597. spin_lock_irqsave(&d->lock, flags);
  598. ret = d->buffer_status[buffer];
  599. spin_unlock_irqrestore(&d->lock, flags);
  600. return ret;
  601. }
  602. static int __video1394_ioctl(struct file *file,
  603. unsigned int cmd, unsigned long arg)
  604. {
  605. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  606. struct ti_ohci *ohci = ctx->ohci;
  607. unsigned long flags;
  608. void __user *argp = (void __user *)arg;
  609. switch(cmd)
  610. {
  611. case VIDEO1394_IOC_LISTEN_CHANNEL:
  612. case VIDEO1394_IOC_TALK_CHANNEL:
  613. {
  614. struct video1394_mmap v;
  615. u64 mask;
  616. struct dma_iso_ctx *d;
  617. int i;
  618. if (copy_from_user(&v, argp, sizeof(v)))
  619. return -EFAULT;
  620. /* if channel < 0, find lowest available one */
  621. if (v.channel < 0) {
  622. mask = (u64)0x1;
  623. for (i=0; ; i++) {
  624. if (i == ISO_CHANNELS) {
  625. PRINT(KERN_ERR, ohci->host->id,
  626. "No free channel found");
  627. return EAGAIN;
  628. }
  629. if (!(ohci->ISO_channel_usage & mask)) {
  630. v.channel = i;
  631. PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
  632. break;
  633. }
  634. mask = mask << 1;
  635. }
  636. } else if (v.channel >= ISO_CHANNELS) {
  637. PRINT(KERN_ERR, ohci->host->id,
  638. "Iso channel %d out of bounds", v.channel);
  639. return -EINVAL;
  640. } else {
  641. mask = (u64)0x1<<v.channel;
  642. }
  643. PRINT(KERN_INFO, ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
  644. (u32)(mask>>32),(u32)(mask&0xffffffff),
  645. (u32)(ohci->ISO_channel_usage>>32),
  646. (u32)(ohci->ISO_channel_usage&0xffffffff));
  647. if (ohci->ISO_channel_usage & mask) {
  648. PRINT(KERN_ERR, ohci->host->id,
  649. "Channel %d is already taken", v.channel);
  650. return -EBUSY;
  651. }
  652. if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
  653. PRINT(KERN_ERR, ohci->host->id,
  654. "Invalid %d length buffer requested",v.buf_size);
  655. return -EINVAL;
  656. }
  657. if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
  658. PRINT(KERN_ERR, ohci->host->id,
  659. "Invalid %d buffers requested",v.nb_buffers);
  660. return -EINVAL;
  661. }
  662. if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
  663. PRINT(KERN_ERR, ohci->host->id,
  664. "%d buffers of size %d bytes is too big",
  665. v.nb_buffers, v.buf_size);
  666. return -EINVAL;
  667. }
  668. if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
  669. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
  670. v.nb_buffers + 1, v.buf_size,
  671. v.channel, 0);
  672. if (d == NULL) {
  673. PRINT(KERN_ERR, ohci->host->id,
  674. "Couldn't allocate ir context");
  675. return -EAGAIN;
  676. }
  677. initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
  678. ctx->current_ctx = d;
  679. v.buf_size = d->buf_size;
  680. list_add_tail(&d->link, &ctx->context_list);
  681. PRINT(KERN_INFO, ohci->host->id,
  682. "iso context %d listen on channel %d",
  683. d->ctx, v.channel);
  684. }
  685. else {
  686. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
  687. v.nb_buffers + 1, v.buf_size,
  688. v.channel, v.packet_size);
  689. if (d == NULL) {
  690. PRINT(KERN_ERR, ohci->host->id,
  691. "Couldn't allocate it context");
  692. return -EAGAIN;
  693. }
  694. initialize_dma_it_ctx(d, v.sync_tag,
  695. v.syt_offset, v.flags);
  696. ctx->current_ctx = d;
  697. v.buf_size = d->buf_size;
  698. list_add_tail(&d->link, &ctx->context_list);
  699. PRINT(KERN_INFO, ohci->host->id,
  700. "Iso context %d talk on channel %d", d->ctx,
  701. v.channel);
  702. }
  703. if (copy_to_user(argp, &v, sizeof(v))) {
  704. /* FIXME : free allocated dma resources */
  705. return -EFAULT;
  706. }
  707. ohci->ISO_channel_usage |= mask;
  708. return 0;
  709. }
  710. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  711. case VIDEO1394_IOC_UNTALK_CHANNEL:
  712. {
  713. int channel;
  714. u64 mask;
  715. struct dma_iso_ctx *d;
  716. if (copy_from_user(&channel, argp, sizeof(int)))
  717. return -EFAULT;
  718. if (channel < 0 || channel >= ISO_CHANNELS) {
  719. PRINT(KERN_ERR, ohci->host->id,
  720. "Iso channel %d out of bound", channel);
  721. return -EINVAL;
  722. }
  723. mask = (u64)0x1<<channel;
  724. if (!(ohci->ISO_channel_usage & mask)) {
  725. PRINT(KERN_ERR, ohci->host->id,
  726. "Channel %d is not being used", channel);
  727. return -ESRCH;
  728. }
  729. /* Mark this channel as unused */
  730. ohci->ISO_channel_usage &= ~mask;
  731. if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
  732. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
  733. else
  734. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
  735. if (d == NULL) return -ESRCH;
  736. PRINT(KERN_INFO, ohci->host->id, "Iso context %d "
  737. "stop talking on channel %d", d->ctx, channel);
  738. free_dma_iso_ctx(d);
  739. return 0;
  740. }
  741. case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
  742. {
  743. struct video1394_wait v;
  744. struct dma_iso_ctx *d;
  745. int next_prg;
  746. if (copy_from_user(&v, argp, sizeof(v)))
  747. return -EFAULT;
  748. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  749. if (d == NULL) return -EFAULT;
  750. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  751. PRINT(KERN_ERR, ohci->host->id,
  752. "Buffer %d out of range",v.buffer);
  753. return -EINVAL;
  754. }
  755. spin_lock_irqsave(&d->lock,flags);
  756. if (d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED) {
  757. PRINT(KERN_ERR, ohci->host->id,
  758. "Buffer %d is already used",v.buffer);
  759. spin_unlock_irqrestore(&d->lock,flags);
  760. return -EBUSY;
  761. }
  762. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  763. next_prg = (d->last_buffer + 1) % d->num_desc;
  764. if (d->last_buffer>=0)
  765. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
  766. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0)
  767. & 0xfffffff0) | 0x1);
  768. d->last_buffer = next_prg;
  769. reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags);
  770. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
  771. spin_unlock_irqrestore(&d->lock,flags);
  772. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  773. {
  774. DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
  775. /* Tell the controller where the first program is */
  776. reg_write(ohci, d->cmdPtr,
  777. dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1);
  778. /* Run IR context */
  779. reg_write(ohci, d->ctrlSet, 0x8000);
  780. }
  781. else {
  782. /* Wake up dma context if necessary */
  783. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  784. PRINT(KERN_INFO, ohci->host->id,
  785. "Waking up iso dma ctx=%d", d->ctx);
  786. reg_write(ohci, d->ctrlSet, 0x1000);
  787. }
  788. }
  789. return 0;
  790. }
  791. case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
  792. case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
  793. {
  794. struct video1394_wait v;
  795. struct dma_iso_ctx *d;
  796. int i = 0;
  797. if (copy_from_user(&v, argp, sizeof(v)))
  798. return -EFAULT;
  799. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  800. if (d == NULL) return -EFAULT;
  801. if ((v.buffer<0) || (v.buffer>d->num_desc - 1)) {
  802. PRINT(KERN_ERR, ohci->host->id,
  803. "Buffer %d out of range",v.buffer);
  804. return -EINVAL;
  805. }
  806. /*
  807. * I change the way it works so that it returns
  808. * the last received frame.
  809. */
  810. spin_lock_irqsave(&d->lock, flags);
  811. switch(d->buffer_status[v.buffer]) {
  812. case VIDEO1394_BUFFER_READY:
  813. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  814. break;
  815. case VIDEO1394_BUFFER_QUEUED:
  816. if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
  817. /* for polling, return error code EINTR */
  818. spin_unlock_irqrestore(&d->lock, flags);
  819. return -EINTR;
  820. }
  821. spin_unlock_irqrestore(&d->lock, flags);
  822. wait_event_interruptible(d->waitq,
  823. video1394_buffer_state(d, v.buffer) ==
  824. VIDEO1394_BUFFER_READY);
  825. if (signal_pending(current))
  826. return -EINTR;
  827. spin_lock_irqsave(&d->lock, flags);
  828. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  829. break;
  830. default:
  831. PRINT(KERN_ERR, ohci->host->id,
  832. "Buffer %d is not queued",v.buffer);
  833. spin_unlock_irqrestore(&d->lock, flags);
  834. return -ESRCH;
  835. }
  836. /* set time of buffer */
  837. v.filltime = d->buffer_time[v.buffer];
  838. /*
  839. * Look ahead to see how many more buffers have been received
  840. */
  841. i=0;
  842. while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]==
  843. VIDEO1394_BUFFER_READY) {
  844. v.buffer=(v.buffer+1)%(d->num_desc - 1);
  845. i++;
  846. }
  847. spin_unlock_irqrestore(&d->lock, flags);
  848. v.buffer=i;
  849. if (copy_to_user(argp, &v, sizeof(v)))
  850. return -EFAULT;
  851. return 0;
  852. }
  853. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  854. {
  855. struct video1394_wait v;
  856. unsigned int *psizes = NULL;
  857. struct dma_iso_ctx *d;
  858. int next_prg;
  859. if (copy_from_user(&v, argp, sizeof(v)))
  860. return -EFAULT;
  861. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  862. if (d == NULL) return -EFAULT;
  863. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  864. PRINT(KERN_ERR, ohci->host->id,
  865. "Buffer %d out of range",v.buffer);
  866. return -EINVAL;
  867. }
  868. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  869. int buf_size = d->nb_cmd * sizeof(*psizes);
  870. struct video1394_queue_variable __user *p = argp;
  871. unsigned int __user *qv;
  872. if (get_user(qv, &p->packet_sizes))
  873. return -EFAULT;
  874. psizes = kmalloc(buf_size, GFP_KERNEL);
  875. if (!psizes)
  876. return -ENOMEM;
  877. if (copy_from_user(psizes, qv, buf_size)) {
  878. kfree(psizes);
  879. return -EFAULT;
  880. }
  881. }
  882. spin_lock_irqsave(&d->lock,flags);
  883. /* last_buffer is last_prg */
  884. next_prg = (d->last_buffer + 1) % d->num_desc;
  885. if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
  886. PRINT(KERN_ERR, ohci->host->id,
  887. "Buffer %d is already used",v.buffer);
  888. spin_unlock_irqrestore(&d->lock,flags);
  889. kfree(psizes);
  890. return -EBUSY;
  891. }
  892. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  893. initialize_dma_it_prg_var_packet_queue(
  894. d, next_prg, psizes, ohci);
  895. }
  896. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  897. if (d->last_buffer >= 0) {
  898. d->it_prg[d->last_buffer]
  899. [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
  900. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  901. 0) & 0xfffffff0) | 0x3);
  902. d->it_prg[d->last_buffer]
  903. [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
  904. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  905. 0) & 0xfffffff0) | 0x3);
  906. d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1);
  907. }
  908. d->last_buffer = next_prg;
  909. reprogram_dma_it_prg(d, d->last_buffer, v.buffer);
  910. d->next_buffer[d->last_buffer] = -1;
  911. d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
  912. spin_unlock_irqrestore(&d->lock,flags);
  913. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  914. {
  915. DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
  916. d->ctx);
  917. put_timestamp(ohci, d, d->last_buffer);
  918. /* Tell the controller where the first program is */
  919. reg_write(ohci, d->cmdPtr,
  920. dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3);
  921. /* Run IT context */
  922. reg_write(ohci, d->ctrlSet, 0x8000);
  923. }
  924. else {
  925. /* Wake up dma context if necessary */
  926. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  927. PRINT(KERN_INFO, ohci->host->id,
  928. "Waking up iso transmit dma ctx=%d",
  929. d->ctx);
  930. put_timestamp(ohci, d, d->last_buffer);
  931. reg_write(ohci, d->ctrlSet, 0x1000);
  932. }
  933. }
  934. kfree(psizes);
  935. return 0;
  936. }
  937. case VIDEO1394_IOC_TALK_WAIT_BUFFER:
  938. {
  939. struct video1394_wait v;
  940. struct dma_iso_ctx *d;
  941. if (copy_from_user(&v, argp, sizeof(v)))
  942. return -EFAULT;
  943. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  944. if (d == NULL) return -EFAULT;
  945. if ((v.buffer<0) || (v.buffer>=d->num_desc-1)) {
  946. PRINT(KERN_ERR, ohci->host->id,
  947. "Buffer %d out of range",v.buffer);
  948. return -EINVAL;
  949. }
  950. switch(d->buffer_status[v.buffer]) {
  951. case VIDEO1394_BUFFER_READY:
  952. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  953. return 0;
  954. case VIDEO1394_BUFFER_QUEUED:
  955. wait_event_interruptible(d->waitq,
  956. (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
  957. if (signal_pending(current))
  958. return -EINTR;
  959. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  960. return 0;
  961. default:
  962. PRINT(KERN_ERR, ohci->host->id,
  963. "Buffer %d is not queued",v.buffer);
  964. return -ESRCH;
  965. }
  966. }
  967. default:
  968. return -ENOTTY;
  969. }
  970. }
  971. static long video1394_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  972. {
  973. int err;
  974. lock_kernel();
  975. err = __video1394_ioctl(file, cmd, arg);
  976. unlock_kernel();
  977. return err;
  978. }
  979. /*
  980. * This maps the vmalloced and reserved buffer to user space.
  981. *
  982. * FIXME:
  983. * - PAGE_READONLY should suffice!?
  984. * - remap_pfn_range is kind of inefficient for page by page remapping.
  985. * But e.g. pte_alloc() does not work in modules ... :-(
  986. */
  987. static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
  988. {
  989. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  990. int res = -EINVAL;
  991. lock_kernel();
  992. if (ctx->current_ctx == NULL) {
  993. PRINT(KERN_ERR, ctx->ohci->host->id, "Current iso context not set");
  994. } else
  995. res = dma_region_mmap(&ctx->current_ctx->dma, file, vma);
  996. unlock_kernel();
  997. return res;
  998. }
  999. static int video1394_open(struct inode *inode, struct file *file)
  1000. {
  1001. int i = ieee1394_file_to_instance(file);
  1002. struct ti_ohci *ohci;
  1003. struct file_ctx *ctx;
  1004. ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
  1005. if (ohci == NULL)
  1006. return -EIO;
  1007. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  1008. if (!ctx) {
  1009. PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
  1010. return -ENOMEM;
  1011. }
  1012. ctx->ohci = ohci;
  1013. INIT_LIST_HEAD(&ctx->context_list);
  1014. ctx->current_ctx = NULL;
  1015. file->private_data = ctx;
  1016. return 0;
  1017. }
  1018. static int video1394_release(struct inode *inode, struct file *file)
  1019. {
  1020. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1021. struct ti_ohci *ohci = ctx->ohci;
  1022. struct list_head *lh, *next;
  1023. u64 mask;
  1024. lock_kernel();
  1025. list_for_each_safe(lh, next, &ctx->context_list) {
  1026. struct dma_iso_ctx *d;
  1027. d = list_entry(lh, struct dma_iso_ctx, link);
  1028. mask = (u64) 1 << d->channel;
  1029. if (!(ohci->ISO_channel_usage & mask))
  1030. PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
  1031. "is not being used", d->channel);
  1032. else
  1033. ohci->ISO_channel_usage &= ~mask;
  1034. PRINT(KERN_INFO, ohci->host->id, "On release: Iso %s context "
  1035. "%d stop listening on channel %d",
  1036. d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
  1037. d->ctx, d->channel);
  1038. free_dma_iso_ctx(d);
  1039. }
  1040. kfree(ctx);
  1041. file->private_data = NULL;
  1042. unlock_kernel();
  1043. return 0;
  1044. }
  1045. #ifdef CONFIG_COMPAT
  1046. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
  1047. #endif
  1048. static struct cdev video1394_cdev;
  1049. static struct file_operations video1394_fops=
  1050. {
  1051. .owner = THIS_MODULE,
  1052. .unlocked_ioctl = video1394_ioctl,
  1053. #ifdef CONFIG_COMPAT
  1054. .compat_ioctl = video1394_compat_ioctl,
  1055. #endif
  1056. .mmap = video1394_mmap,
  1057. .open = video1394_open,
  1058. .release = video1394_release
  1059. };
  1060. /*** HOTPLUG STUFF **********************************************************/
  1061. /*
  1062. * Export information about protocols/devices supported by this driver.
  1063. */
  1064. static struct ieee1394_device_id video1394_id_table[] = {
  1065. {
  1066. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1067. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1068. .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
  1069. },
  1070. {
  1071. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1072. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1073. .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
  1074. },
  1075. {
  1076. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1077. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1078. .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
  1079. },
  1080. { }
  1081. };
  1082. MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
  1083. static struct hpsb_protocol_driver video1394_driver = {
  1084. .name = "1394 Digital Camera Driver",
  1085. .id_table = video1394_id_table,
  1086. .driver = {
  1087. .name = VIDEO1394_DRIVER_NAME,
  1088. .bus = &ieee1394_bus_type,
  1089. },
  1090. };
  1091. static void video1394_add_host (struct hpsb_host *host)
  1092. {
  1093. struct ti_ohci *ohci;
  1094. int minor;
  1095. /* We only work with the OHCI-1394 driver */
  1096. if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
  1097. return;
  1098. ohci = (struct ti_ohci *)host->hostdata;
  1099. if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
  1100. PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
  1101. return;
  1102. }
  1103. hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
  1104. hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
  1105. minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
  1106. class_device_create(hpsb_protocol_class, NULL, MKDEV(
  1107. IEEE1394_MAJOR, minor),
  1108. NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1109. devfs_mk_cdev(MKDEV(IEEE1394_MAJOR, minor),
  1110. S_IFCHR | S_IRUSR | S_IWUSR,
  1111. "%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1112. }
  1113. static void video1394_remove_host (struct hpsb_host *host)
  1114. {
  1115. struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
  1116. if (ohci) {
  1117. class_device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
  1118. IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
  1119. devfs_remove("%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1120. }
  1121. return;
  1122. }
  1123. static struct hpsb_highlevel video1394_highlevel = {
  1124. .name = VIDEO1394_DRIVER_NAME,
  1125. .add_host = video1394_add_host,
  1126. .remove_host = video1394_remove_host,
  1127. };
  1128. MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
  1129. MODULE_DESCRIPTION("driver for digital video on OHCI board");
  1130. MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
  1131. MODULE_LICENSE("GPL");
  1132. #ifdef CONFIG_COMPAT
  1133. #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
  1134. _IOW ('#', 0x12, struct video1394_wait32)
  1135. #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
  1136. _IOWR('#', 0x13, struct video1394_wait32)
  1137. #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
  1138. _IOW ('#', 0x17, struct video1394_wait32)
  1139. #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
  1140. _IOWR('#', 0x18, struct video1394_wait32)
  1141. struct video1394_wait32 {
  1142. u32 channel;
  1143. u32 buffer;
  1144. struct compat_timeval filltime;
  1145. };
  1146. static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1147. {
  1148. struct video1394_wait32 __user *argp = (void __user *)arg;
  1149. struct video1394_wait32 wait32;
  1150. struct video1394_wait wait;
  1151. mm_segment_t old_fs;
  1152. int ret;
  1153. if (copy_from_user(&wait32, argp, sizeof(wait32)))
  1154. return -EFAULT;
  1155. wait.channel = wait32.channel;
  1156. wait.buffer = wait32.buffer;
  1157. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1158. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1159. old_fs = get_fs();
  1160. set_fs(KERNEL_DS);
  1161. if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
  1162. ret = video1394_ioctl(file,
  1163. VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
  1164. (unsigned long) &wait);
  1165. else
  1166. ret = video1394_ioctl(file,
  1167. VIDEO1394_IOC_LISTEN_POLL_BUFFER,
  1168. (unsigned long) &wait);
  1169. set_fs(old_fs);
  1170. if (!ret) {
  1171. wait32.channel = wait.channel;
  1172. wait32.buffer = wait.buffer;
  1173. wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
  1174. wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
  1175. if (copy_to_user(argp, &wait32, sizeof(wait32)))
  1176. ret = -EFAULT;
  1177. }
  1178. return ret;
  1179. }
  1180. static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1181. {
  1182. struct video1394_wait32 wait32;
  1183. struct video1394_wait wait;
  1184. mm_segment_t old_fs;
  1185. int ret;
  1186. if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
  1187. return -EFAULT;
  1188. wait.channel = wait32.channel;
  1189. wait.buffer = wait32.buffer;
  1190. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1191. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1192. old_fs = get_fs();
  1193. set_fs(KERNEL_DS);
  1194. if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
  1195. ret = video1394_ioctl(file,
  1196. VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
  1197. (unsigned long) &wait);
  1198. else
  1199. ret = video1394_ioctl(file,
  1200. VIDEO1394_IOC_TALK_WAIT_BUFFER,
  1201. (unsigned long) &wait);
  1202. set_fs(old_fs);
  1203. return ret;
  1204. }
  1205. static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
  1206. {
  1207. return -EFAULT; /* ??? was there before. */
  1208. return video1394_ioctl(file,
  1209. VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
  1210. }
  1211. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
  1212. {
  1213. switch (cmd) {
  1214. case VIDEO1394_IOC_LISTEN_CHANNEL:
  1215. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  1216. case VIDEO1394_IOC_TALK_CHANNEL:
  1217. case VIDEO1394_IOC_UNTALK_CHANNEL:
  1218. return video1394_ioctl(f, cmd, arg);
  1219. case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
  1220. return video1394_w_wait32(f, cmd, arg);
  1221. case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
  1222. return video1394_wr_wait32(f, cmd, arg);
  1223. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  1224. return video1394_queue_buf32(f, cmd, arg);
  1225. case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
  1226. return video1394_w_wait32(f, cmd, arg);
  1227. case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
  1228. return video1394_wr_wait32(f, cmd, arg);
  1229. default:
  1230. return -ENOIOCTLCMD;
  1231. }
  1232. }
  1233. #endif /* CONFIG_COMPAT */
  1234. static void __exit video1394_exit_module (void)
  1235. {
  1236. hpsb_unregister_protocol(&video1394_driver);
  1237. hpsb_unregister_highlevel(&video1394_highlevel);
  1238. devfs_remove(VIDEO1394_DRIVER_NAME);
  1239. cdev_del(&video1394_cdev);
  1240. PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
  1241. }
  1242. static int __init video1394_init_module (void)
  1243. {
  1244. int ret;
  1245. cdev_init(&video1394_cdev, &video1394_fops);
  1246. video1394_cdev.owner = THIS_MODULE;
  1247. kobject_set_name(&video1394_cdev.kobj, VIDEO1394_DRIVER_NAME);
  1248. ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
  1249. if (ret) {
  1250. PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
  1251. return ret;
  1252. }
  1253. devfs_mk_dir(VIDEO1394_DRIVER_NAME);
  1254. hpsb_register_highlevel(&video1394_highlevel);
  1255. ret = hpsb_register_protocol(&video1394_driver);
  1256. if (ret) {
  1257. PRINT_G(KERN_ERR, "video1394: failed to register protocol");
  1258. hpsb_unregister_highlevel(&video1394_highlevel);
  1259. devfs_remove(VIDEO1394_DRIVER_NAME);
  1260. cdev_del(&video1394_cdev);
  1261. return ret;
  1262. }
  1263. PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
  1264. return 0;
  1265. }
  1266. module_init(video1394_init_module);
  1267. module_exit(video1394_exit_module);