i2c-s3c2410.c 20 KB

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  1. /* linux/drivers/i2c/busses/i2c-s3c2410.c
  2. *
  3. * Copyright (C) 2004,2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 I2C Controller
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/config.h>
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/i2c.h>
  26. #include <linux/i2c-id.h>
  27. #include <linux/init.h>
  28. #include <linux/time.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/sched.h>
  31. #include <linux/delay.h>
  32. #include <linux/errno.h>
  33. #include <linux/err.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/clk.h>
  36. #include <asm/hardware.h>
  37. #include <asm/irq.h>
  38. #include <asm/io.h>
  39. #include <asm/arch/regs-gpio.h>
  40. #include <asm/arch/regs-iic.h>
  41. #include <asm/arch/iic.h>
  42. /* i2c controller state */
  43. enum s3c24xx_i2c_state {
  44. STATE_IDLE,
  45. STATE_START,
  46. STATE_READ,
  47. STATE_WRITE,
  48. STATE_STOP
  49. };
  50. struct s3c24xx_i2c {
  51. spinlock_t lock;
  52. wait_queue_head_t wait;
  53. struct i2c_msg *msg;
  54. unsigned int msg_num;
  55. unsigned int msg_idx;
  56. unsigned int msg_ptr;
  57. enum s3c24xx_i2c_state state;
  58. void __iomem *regs;
  59. struct clk *clk;
  60. struct device *dev;
  61. struct resource *irq;
  62. struct resource *ioarea;
  63. struct i2c_adapter adap;
  64. };
  65. /* default platform data to use if not supplied in the platform_device
  66. */
  67. static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
  68. .flags = 0,
  69. .slave_addr = 0x10,
  70. .bus_freq = 100*1000,
  71. .max_freq = 400*1000,
  72. .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
  73. };
  74. /* s3c24xx_i2c_is2440()
  75. *
  76. * return true is this is an s3c2440
  77. */
  78. static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
  79. {
  80. struct platform_device *pdev = to_platform_device(i2c->dev);
  81. return !strcmp(pdev->name, "s3c2440-i2c");
  82. }
  83. /* s3c24xx_i2c_get_platformdata
  84. *
  85. * get the platform data associated with the given device, or return
  86. * the default if there is none
  87. */
  88. static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
  89. {
  90. if (dev->platform_data != NULL)
  91. return (struct s3c2410_platform_i2c *)dev->platform_data;
  92. return &s3c24xx_i2c_default_platform;
  93. }
  94. /* s3c24xx_i2c_master_complete
  95. *
  96. * complete the message and wake up the caller, using the given return code,
  97. * or zero to mean ok.
  98. */
  99. static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
  100. {
  101. dev_dbg(i2c->dev, "master_complete %d\n", ret);
  102. i2c->msg_ptr = 0;
  103. i2c->msg = NULL;
  104. i2c->msg_idx ++;
  105. i2c->msg_num = 0;
  106. if (ret)
  107. i2c->msg_idx = ret;
  108. wake_up(&i2c->wait);
  109. }
  110. static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
  111. {
  112. unsigned long tmp;
  113. tmp = readl(i2c->regs + S3C2410_IICCON);
  114. writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
  115. }
  116. static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
  117. {
  118. unsigned long tmp;
  119. tmp = readl(i2c->regs + S3C2410_IICCON);
  120. writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
  121. }
  122. /* irq enable/disable functions */
  123. static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
  124. {
  125. unsigned long tmp;
  126. tmp = readl(i2c->regs + S3C2410_IICCON);
  127. writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
  128. }
  129. static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
  130. {
  131. unsigned long tmp;
  132. tmp = readl(i2c->regs + S3C2410_IICCON);
  133. writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
  134. }
  135. /* s3c24xx_i2c_message_start
  136. *
  137. * put the start of a message onto the bus
  138. */
  139. static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
  140. struct i2c_msg *msg)
  141. {
  142. unsigned int addr = (msg->addr & 0x7f) << 1;
  143. unsigned long stat;
  144. unsigned long iiccon;
  145. stat = 0;
  146. stat |= S3C2410_IICSTAT_TXRXEN;
  147. if (msg->flags & I2C_M_RD) {
  148. stat |= S3C2410_IICSTAT_MASTER_RX;
  149. addr |= 1;
  150. } else
  151. stat |= S3C2410_IICSTAT_MASTER_TX;
  152. if (msg->flags & I2C_M_REV_DIR_ADDR)
  153. addr ^= 1;
  154. // todo - check for wether ack wanted or not
  155. s3c24xx_i2c_enable_ack(i2c);
  156. iiccon = readl(i2c->regs + S3C2410_IICCON);
  157. writel(stat, i2c->regs + S3C2410_IICSTAT);
  158. dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
  159. writeb(addr, i2c->regs + S3C2410_IICDS);
  160. // delay a bit and reset iiccon before setting start (per samsung)
  161. udelay(1);
  162. dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
  163. writel(iiccon, i2c->regs + S3C2410_IICCON);
  164. stat |= S3C2410_IICSTAT_START;
  165. writel(stat, i2c->regs + S3C2410_IICSTAT);
  166. }
  167. static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
  168. {
  169. unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
  170. dev_dbg(i2c->dev, "STOP\n");
  171. /* stop the transfer */
  172. iicstat &= ~ S3C2410_IICSTAT_START;
  173. writel(iicstat, i2c->regs + S3C2410_IICSTAT);
  174. i2c->state = STATE_STOP;
  175. s3c24xx_i2c_master_complete(i2c, ret);
  176. s3c24xx_i2c_disable_irq(i2c);
  177. }
  178. /* helper functions to determine the current state in the set of
  179. * messages we are sending */
  180. /* is_lastmsg()
  181. *
  182. * returns TRUE if the current message is the last in the set
  183. */
  184. static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
  185. {
  186. return i2c->msg_idx >= (i2c->msg_num - 1);
  187. }
  188. /* is_msglast
  189. *
  190. * returns TRUE if we this is the last byte in the current message
  191. */
  192. static inline int is_msglast(struct s3c24xx_i2c *i2c)
  193. {
  194. return i2c->msg_ptr == i2c->msg->len-1;
  195. }
  196. /* is_msgend
  197. *
  198. * returns TRUE if we reached the end of the current message
  199. */
  200. static inline int is_msgend(struct s3c24xx_i2c *i2c)
  201. {
  202. return i2c->msg_ptr >= i2c->msg->len;
  203. }
  204. /* i2s_s3c_irq_nextbyte
  205. *
  206. * process an interrupt and work out what to do
  207. */
  208. static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
  209. {
  210. unsigned long tmp;
  211. unsigned char byte;
  212. int ret = 0;
  213. switch (i2c->state) {
  214. case STATE_IDLE:
  215. dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __FUNCTION__);
  216. goto out;
  217. break;
  218. case STATE_STOP:
  219. dev_err(i2c->dev, "%s: called in STATE_STOP\n", __FUNCTION__);
  220. s3c24xx_i2c_disable_irq(i2c);
  221. goto out_ack;
  222. case STATE_START:
  223. /* last thing we did was send a start condition on the
  224. * bus, or started a new i2c message
  225. */
  226. if (iicstat & S3C2410_IICSTAT_LASTBIT &&
  227. !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
  228. /* ack was not received... */
  229. dev_dbg(i2c->dev, "ack was not received\n");
  230. s3c24xx_i2c_stop(i2c, -EREMOTEIO);
  231. goto out_ack;
  232. }
  233. if (i2c->msg->flags & I2C_M_RD)
  234. i2c->state = STATE_READ;
  235. else
  236. i2c->state = STATE_WRITE;
  237. /* terminate the transfer if there is nothing to do
  238. * (used by the i2c probe to find devices */
  239. if (is_lastmsg(i2c) && i2c->msg->len == 0) {
  240. s3c24xx_i2c_stop(i2c, 0);
  241. goto out_ack;
  242. }
  243. if (i2c->state == STATE_READ)
  244. goto prepare_read;
  245. /* fall through to the write state, as we will need to
  246. * send a byte as well */
  247. case STATE_WRITE:
  248. /* we are writing data to the device... check for the
  249. * end of the message, and if so, work out what to do
  250. */
  251. retry_write:
  252. if (!is_msgend(i2c)) {
  253. byte = i2c->msg->buf[i2c->msg_ptr++];
  254. writeb(byte, i2c->regs + S3C2410_IICDS);
  255. } else if (!is_lastmsg(i2c)) {
  256. /* we need to go to the next i2c message */
  257. dev_dbg(i2c->dev, "WRITE: Next Message\n");
  258. i2c->msg_ptr = 0;
  259. i2c->msg_idx ++;
  260. i2c->msg++;
  261. /* check to see if we need to do another message */
  262. if (i2c->msg->flags & I2C_M_NOSTART) {
  263. if (i2c->msg->flags & I2C_M_RD) {
  264. /* cannot do this, the controller
  265. * forces us to send a new START
  266. * when we change direction */
  267. s3c24xx_i2c_stop(i2c, -EINVAL);
  268. }
  269. goto retry_write;
  270. } else {
  271. /* send the new start */
  272. s3c24xx_i2c_message_start(i2c, i2c->msg);
  273. i2c->state = STATE_START;
  274. }
  275. } else {
  276. /* send stop */
  277. s3c24xx_i2c_stop(i2c, 0);
  278. }
  279. break;
  280. case STATE_READ:
  281. /* we have a byte of data in the data register, do
  282. * something with it, and then work out wether we are
  283. * going to do any more read/write
  284. */
  285. if (!(i2c->msg->flags & I2C_M_IGNORE_NAK) &&
  286. !(is_msglast(i2c) && is_lastmsg(i2c))) {
  287. if (iicstat & S3C2410_IICSTAT_LASTBIT) {
  288. dev_dbg(i2c->dev, "READ: No Ack\n");
  289. s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
  290. goto out_ack;
  291. }
  292. }
  293. byte = readb(i2c->regs + S3C2410_IICDS);
  294. i2c->msg->buf[i2c->msg_ptr++] = byte;
  295. prepare_read:
  296. if (is_msglast(i2c)) {
  297. /* last byte of buffer */
  298. if (is_lastmsg(i2c))
  299. s3c24xx_i2c_disable_ack(i2c);
  300. } else if (is_msgend(i2c)) {
  301. /* ok, we've read the entire buffer, see if there
  302. * is anything else we need to do */
  303. if (is_lastmsg(i2c)) {
  304. /* last message, send stop and complete */
  305. dev_dbg(i2c->dev, "READ: Send Stop\n");
  306. s3c24xx_i2c_stop(i2c, 0);
  307. } else {
  308. /* go to the next transfer */
  309. dev_dbg(i2c->dev, "READ: Next Transfer\n");
  310. i2c->msg_ptr = 0;
  311. i2c->msg_idx++;
  312. i2c->msg++;
  313. }
  314. }
  315. break;
  316. }
  317. /* acknowlegde the IRQ and get back on with the work */
  318. out_ack:
  319. tmp = readl(i2c->regs + S3C2410_IICCON);
  320. tmp &= ~S3C2410_IICCON_IRQPEND;
  321. writel(tmp, i2c->regs + S3C2410_IICCON);
  322. out:
  323. return ret;
  324. }
  325. /* s3c24xx_i2c_irq
  326. *
  327. * top level IRQ servicing routine
  328. */
  329. static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id,
  330. struct pt_regs *regs)
  331. {
  332. struct s3c24xx_i2c *i2c = dev_id;
  333. unsigned long status;
  334. unsigned long tmp;
  335. status = readl(i2c->regs + S3C2410_IICSTAT);
  336. if (status & S3C2410_IICSTAT_ARBITR) {
  337. // deal with arbitration loss
  338. dev_err(i2c->dev, "deal with arbitration loss\n");
  339. }
  340. if (i2c->state == STATE_IDLE) {
  341. dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
  342. tmp = readl(i2c->regs + S3C2410_IICCON);
  343. tmp &= ~S3C2410_IICCON_IRQPEND;
  344. writel(tmp, i2c->regs + S3C2410_IICCON);
  345. goto out;
  346. }
  347. /* pretty much this leaves us with the fact that we've
  348. * transmitted or received whatever byte we last sent */
  349. i2s_s3c_irq_nextbyte(i2c, status);
  350. out:
  351. return IRQ_HANDLED;
  352. }
  353. /* s3c24xx_i2c_set_master
  354. *
  355. * get the i2c bus for a master transaction
  356. */
  357. static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
  358. {
  359. unsigned long iicstat;
  360. int timeout = 400;
  361. while (timeout-- > 0) {
  362. iicstat = readl(i2c->regs + S3C2410_IICSTAT);
  363. if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
  364. return 0;
  365. msleep(1);
  366. }
  367. dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
  368. __raw_readl(S3C2410_GPEDAT));
  369. return -ETIMEDOUT;
  370. }
  371. /* s3c24xx_i2c_doxfer
  372. *
  373. * this starts an i2c transfer
  374. */
  375. static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
  376. {
  377. unsigned long timeout;
  378. int ret;
  379. ret = s3c24xx_i2c_set_master(i2c);
  380. if (ret != 0) {
  381. dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
  382. ret = -EAGAIN;
  383. goto out;
  384. }
  385. spin_lock_irq(&i2c->lock);
  386. i2c->msg = msgs;
  387. i2c->msg_num = num;
  388. i2c->msg_ptr = 0;
  389. i2c->msg_idx = 0;
  390. i2c->state = STATE_START;
  391. s3c24xx_i2c_enable_irq(i2c);
  392. s3c24xx_i2c_message_start(i2c, msgs);
  393. spin_unlock_irq(&i2c->lock);
  394. timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
  395. ret = i2c->msg_idx;
  396. /* having these next two as dev_err() makes life very
  397. * noisy when doing an i2cdetect */
  398. if (timeout == 0)
  399. dev_dbg(i2c->dev, "timeout\n");
  400. else if (ret != num)
  401. dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
  402. /* ensure the stop has been through the bus */
  403. msleep(1);
  404. out:
  405. return ret;
  406. }
  407. /* s3c24xx_i2c_xfer
  408. *
  409. * first port of call from the i2c bus code when an message needs
  410. * transferring across the i2c bus.
  411. */
  412. static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
  413. struct i2c_msg *msgs, int num)
  414. {
  415. struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
  416. int retry;
  417. int ret;
  418. for (retry = 0; retry < adap->retries; retry++) {
  419. ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
  420. if (ret != -EAGAIN)
  421. return ret;
  422. dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
  423. udelay(100);
  424. }
  425. return -EREMOTEIO;
  426. }
  427. /* declare our i2c functionality */
  428. static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
  429. {
  430. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
  431. }
  432. /* i2c bus registration info */
  433. static struct i2c_algorithm s3c24xx_i2c_algorithm = {
  434. .master_xfer = s3c24xx_i2c_xfer,
  435. .functionality = s3c24xx_i2c_func,
  436. };
  437. static struct s3c24xx_i2c s3c24xx_i2c = {
  438. .lock = SPIN_LOCK_UNLOCKED,
  439. .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
  440. .adap = {
  441. .name = "s3c2410-i2c",
  442. .owner = THIS_MODULE,
  443. .algo = &s3c24xx_i2c_algorithm,
  444. .retries = 2,
  445. .class = I2C_CLASS_HWMON,
  446. },
  447. };
  448. /* s3c24xx_i2c_calcdivisor
  449. *
  450. * return the divisor settings for a given frequency
  451. */
  452. static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
  453. unsigned int *div1, unsigned int *divs)
  454. {
  455. unsigned int calc_divs = clkin / wanted;
  456. unsigned int calc_div1;
  457. if (calc_divs > (16*16))
  458. calc_div1 = 512;
  459. else
  460. calc_div1 = 16;
  461. calc_divs += calc_div1-1;
  462. calc_divs /= calc_div1;
  463. if (calc_divs == 0)
  464. calc_divs = 1;
  465. if (calc_divs > 17)
  466. calc_divs = 17;
  467. *divs = calc_divs;
  468. *div1 = calc_div1;
  469. return clkin / (calc_divs * calc_div1);
  470. }
  471. /* freq_acceptable
  472. *
  473. * test wether a frequency is within the acceptable range of error
  474. */
  475. static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
  476. {
  477. int diff = freq - wanted;
  478. return (diff >= -2 && diff <= 2);
  479. }
  480. /* s3c24xx_i2c_getdivisor
  481. *
  482. * work out a divisor for the user requested frequency setting,
  483. * either by the requested frequency, or scanning the acceptable
  484. * range of frequencies until something is found
  485. */
  486. static int s3c24xx_i2c_getdivisor(struct s3c24xx_i2c *i2c,
  487. struct s3c2410_platform_i2c *pdata,
  488. unsigned long *iicon,
  489. unsigned int *got)
  490. {
  491. unsigned long clkin = clk_get_rate(i2c->clk);
  492. unsigned int divs, div1;
  493. int freq;
  494. int start, end;
  495. clkin /= 1000; /* clkin now in KHz */
  496. dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
  497. pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
  498. if (pdata->bus_freq != 0) {
  499. freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
  500. &div1, &divs);
  501. if (freq_acceptable(freq, pdata->bus_freq/1000))
  502. goto found;
  503. }
  504. /* ok, we may have to search for something suitable... */
  505. start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
  506. end = pdata->min_freq;
  507. start /= 1000;
  508. end /= 1000;
  509. /* search loop... */
  510. for (; start > end; start--) {
  511. freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
  512. if (freq_acceptable(freq, start))
  513. goto found;
  514. }
  515. /* cannot find frequency spec */
  516. return -EINVAL;
  517. found:
  518. *got = freq;
  519. *iicon |= (divs-1);
  520. *iicon |= (div1 == 512) ? S3C2410_IICCON_TXDIV_512 : 0;
  521. return 0;
  522. }
  523. /* s3c24xx_i2c_init
  524. *
  525. * initialise the controller, set the IO lines and frequency
  526. */
  527. static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
  528. {
  529. unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
  530. struct s3c2410_platform_i2c *pdata;
  531. unsigned int freq;
  532. /* get the plafrom data */
  533. pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
  534. /* inititalise the gpio */
  535. s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
  536. s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
  537. /* write slave address */
  538. writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
  539. dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
  540. /* we need to work out the divisors for the clock... */
  541. if (s3c24xx_i2c_getdivisor(i2c, pdata, &iicon, &freq) != 0) {
  542. dev_err(i2c->dev, "cannot meet bus frequency required\n");
  543. return -EINVAL;
  544. }
  545. /* todo - check that the i2c lines aren't being dragged anywhere */
  546. dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
  547. dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
  548. writel(iicon, i2c->regs + S3C2410_IICCON);
  549. /* check for s3c2440 i2c controller */
  550. if (s3c24xx_i2c_is2440(i2c)) {
  551. dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
  552. writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
  553. }
  554. return 0;
  555. }
  556. static void s3c24xx_i2c_free(struct s3c24xx_i2c *i2c)
  557. {
  558. if (i2c->clk != NULL && !IS_ERR(i2c->clk)) {
  559. clk_disable(i2c->clk);
  560. clk_put(i2c->clk);
  561. i2c->clk = NULL;
  562. }
  563. if (i2c->regs != NULL) {
  564. iounmap(i2c->regs);
  565. i2c->regs = NULL;
  566. }
  567. if (i2c->ioarea != NULL) {
  568. release_resource(i2c->ioarea);
  569. kfree(i2c->ioarea);
  570. i2c->ioarea = NULL;
  571. }
  572. }
  573. /* s3c24xx_i2c_probe
  574. *
  575. * called by the bus driver when a suitable device is found
  576. */
  577. static int s3c24xx_i2c_probe(struct platform_device *pdev)
  578. {
  579. struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
  580. struct resource *res;
  581. int ret;
  582. /* find the clock and enable it */
  583. i2c->dev = &pdev->dev;
  584. i2c->clk = clk_get(&pdev->dev, "i2c");
  585. if (IS_ERR(i2c->clk)) {
  586. dev_err(&pdev->dev, "cannot get clock\n");
  587. ret = -ENOENT;
  588. goto out;
  589. }
  590. dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
  591. clk_enable(i2c->clk);
  592. /* map the registers */
  593. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  594. if (res == NULL) {
  595. dev_err(&pdev->dev, "cannot find IO resource\n");
  596. ret = -ENOENT;
  597. goto out;
  598. }
  599. i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
  600. pdev->name);
  601. if (i2c->ioarea == NULL) {
  602. dev_err(&pdev->dev, "cannot request IO\n");
  603. ret = -ENXIO;
  604. goto out;
  605. }
  606. i2c->regs = ioremap(res->start, (res->end-res->start)+1);
  607. if (i2c->regs == NULL) {
  608. dev_err(&pdev->dev, "cannot map IO\n");
  609. ret = -ENXIO;
  610. goto out;
  611. }
  612. dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
  613. /* setup info block for the i2c core */
  614. i2c->adap.algo_data = i2c;
  615. i2c->adap.dev.parent = &pdev->dev;
  616. /* initialise the i2c controller */
  617. ret = s3c24xx_i2c_init(i2c);
  618. if (ret != 0)
  619. goto out;
  620. /* find the IRQ for this unit (note, this relies on the init call to
  621. * ensure no current IRQs pending
  622. */
  623. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  624. if (res == NULL) {
  625. dev_err(&pdev->dev, "cannot find IRQ\n");
  626. ret = -ENOENT;
  627. goto out;
  628. }
  629. ret = request_irq(res->start, s3c24xx_i2c_irq, SA_INTERRUPT,
  630. pdev->name, i2c);
  631. if (ret != 0) {
  632. dev_err(&pdev->dev, "cannot claim IRQ\n");
  633. goto out;
  634. }
  635. i2c->irq = res;
  636. dev_dbg(&pdev->dev, "irq resource %p (%ld)\n", res, res->start);
  637. ret = i2c_add_adapter(&i2c->adap);
  638. if (ret < 0) {
  639. dev_err(&pdev->dev, "failed to add bus to i2c core\n");
  640. goto out;
  641. }
  642. platform_set_drvdata(pdev, i2c);
  643. dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
  644. out:
  645. if (ret < 0)
  646. s3c24xx_i2c_free(i2c);
  647. return ret;
  648. }
  649. /* s3c24xx_i2c_remove
  650. *
  651. * called when device is removed from the bus
  652. */
  653. static int s3c24xx_i2c_remove(struct platform_device *pdev)
  654. {
  655. struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
  656. if (i2c != NULL) {
  657. s3c24xx_i2c_free(i2c);
  658. platform_set_drvdata(pdev, NULL);
  659. }
  660. return 0;
  661. }
  662. #ifdef CONFIG_PM
  663. static int s3c24xx_i2c_resume(struct platform_device *dev)
  664. {
  665. struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
  666. if (i2c != NULL)
  667. s3c24xx_i2c_init(i2c);
  668. return 0;
  669. }
  670. #else
  671. #define s3c24xx_i2c_resume NULL
  672. #endif
  673. /* device driver for platform bus bits */
  674. static struct platform_driver s3c2410_i2c_driver = {
  675. .probe = s3c24xx_i2c_probe,
  676. .remove = s3c24xx_i2c_remove,
  677. .resume = s3c24xx_i2c_resume,
  678. .driver = {
  679. .owner = THIS_MODULE,
  680. .name = "s3c2410-i2c",
  681. },
  682. };
  683. static struct platform_driver s3c2440_i2c_driver = {
  684. .probe = s3c24xx_i2c_probe,
  685. .remove = s3c24xx_i2c_remove,
  686. .resume = s3c24xx_i2c_resume,
  687. .driver = {
  688. .owner = THIS_MODULE,
  689. .name = "s3c2440-i2c",
  690. },
  691. };
  692. static int __init i2c_adap_s3c_init(void)
  693. {
  694. int ret;
  695. ret = platform_driver_register(&s3c2410_i2c_driver);
  696. if (ret == 0) {
  697. ret = platform_driver_register(&s3c2440_i2c_driver);
  698. if (ret)
  699. platform_driver_unregister(&s3c2410_i2c_driver);
  700. }
  701. return ret;
  702. }
  703. static void __exit i2c_adap_s3c_exit(void)
  704. {
  705. platform_driver_unregister(&s3c2410_i2c_driver);
  706. platform_driver_unregister(&s3c2440_i2c_driver);
  707. }
  708. module_init(i2c_adap_s3c_init);
  709. module_exit(i2c_adap_s3c_exit);
  710. MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
  711. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  712. MODULE_LICENSE("GPL");