i810_dma.c 36 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/pagemap.h>
  39. #define I810_BUF_FREE 2
  40. #define I810_BUF_CLIENT 1
  41. #define I810_BUF_HARDWARE 0
  42. #define I810_BUF_UNMAPPED 0
  43. #define I810_BUF_MAPPED 1
  44. static drm_buf_t *i810_freelist_get(drm_device_t * dev)
  45. {
  46. drm_device_dma_t *dma = dev->dma;
  47. int i;
  48. int used;
  49. /* Linear search might not be the best solution */
  50. for (i = 0; i < dma->buf_count; i++) {
  51. drm_buf_t *buf = dma->buflist[i];
  52. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  53. /* In use is already a pointer */
  54. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  55. I810_BUF_CLIENT);
  56. if (used == I810_BUF_FREE) {
  57. return buf;
  58. }
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(drm_device_t * dev, drm_buf_t * buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. drm_file_t *priv = filp->private_data;
  80. drm_device_t *dev;
  81. drm_i810_private_t *dev_priv;
  82. drm_buf_t *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. lock_kernel();
  85. dev = priv->head->dev;
  86. dev_priv = dev->dev_private;
  87. buf = dev_priv->mmap_buffer;
  88. buf_priv = buf->dev_private;
  89. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  90. vma->vm_file = filp;
  91. buf_priv->currently_mapped = I810_BUF_MAPPED;
  92. unlock_kernel();
  93. if (io_remap_pfn_range(vma, vma->vm_start,
  94. VM_OFFSET(vma) >> PAGE_SHIFT,
  95. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  96. return -EAGAIN;
  97. return 0;
  98. }
  99. static struct file_operations i810_buffer_fops = {
  100. .open = drm_open,
  101. .release = drm_release,
  102. .ioctl = drm_ioctl,
  103. .mmap = i810_mmap_buffers,
  104. .fasync = drm_fasync,
  105. };
  106. static int i810_map_buffer(drm_buf_t * buf, struct file *filp)
  107. {
  108. drm_file_t *priv = filp->private_data;
  109. drm_device_t *dev = priv->head->dev;
  110. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  111. drm_i810_private_t *dev_priv = dev->dev_private;
  112. struct file_operations *old_fops;
  113. int retcode = 0;
  114. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  115. return -EINVAL;
  116. down_write(&current->mm->mmap_sem);
  117. old_fops = filp->f_op;
  118. filp->f_op = &i810_buffer_fops;
  119. dev_priv->mmap_buffer = buf;
  120. buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total,
  121. PROT_READ | PROT_WRITE,
  122. MAP_SHARED, buf->bus_address);
  123. dev_priv->mmap_buffer = NULL;
  124. filp->f_op = old_fops;
  125. if ((unsigned long)buf_priv->virtual > -1024UL) {
  126. /* Real error */
  127. DRM_ERROR("mmap error\n");
  128. retcode = (signed int)buf_priv->virtual;
  129. buf_priv->virtual = NULL;
  130. }
  131. up_write(&current->mm->mmap_sem);
  132. return retcode;
  133. }
  134. static int i810_unmap_buffer(drm_buf_t * buf)
  135. {
  136. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  137. int retcode = 0;
  138. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  139. return -EINVAL;
  140. down_write(&current->mm->mmap_sem);
  141. retcode = do_munmap(current->mm,
  142. (unsigned long)buf_priv->virtual,
  143. (size_t) buf->total);
  144. up_write(&current->mm->mmap_sem);
  145. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  146. buf_priv->virtual = NULL;
  147. return retcode;
  148. }
  149. static int i810_dma_get_buffer(drm_device_t * dev, drm_i810_dma_t * d,
  150. struct file *filp)
  151. {
  152. drm_buf_t *buf;
  153. drm_i810_buf_priv_t *buf_priv;
  154. int retcode = 0;
  155. buf = i810_freelist_get(dev);
  156. if (!buf) {
  157. retcode = -ENOMEM;
  158. DRM_DEBUG("retcode=%d\n", retcode);
  159. return retcode;
  160. }
  161. retcode = i810_map_buffer(buf, filp);
  162. if (retcode) {
  163. i810_freelist_put(dev, buf);
  164. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  165. return retcode;
  166. }
  167. buf->filp = filp;
  168. buf_priv = buf->dev_private;
  169. d->granted = 1;
  170. d->request_idx = buf->idx;
  171. d->request_size = buf->total;
  172. d->virtual = buf_priv->virtual;
  173. return retcode;
  174. }
  175. static int i810_dma_cleanup(drm_device_t * dev)
  176. {
  177. drm_device_dma_t *dma = dev->dma;
  178. /* Make sure interrupts are disabled here because the uninstall ioctl
  179. * may not have been called from userspace and after dev_private
  180. * is freed, it's too late.
  181. */
  182. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  183. drm_irq_uninstall(dev);
  184. if (dev->dev_private) {
  185. int i;
  186. drm_i810_private_t *dev_priv =
  187. (drm_i810_private_t *) dev->dev_private;
  188. if (dev_priv->ring.virtual_start) {
  189. drm_ioremapfree((void *)dev_priv->ring.virtual_start,
  190. dev_priv->ring.Size, dev);
  191. }
  192. if (dev_priv->hw_status_page) {
  193. pci_free_consistent(dev->pdev, PAGE_SIZE,
  194. dev_priv->hw_status_page,
  195. dev_priv->dma_status_page);
  196. /* Need to rewrite hardware status page */
  197. I810_WRITE(0x02080, 0x1ffff000);
  198. }
  199. drm_free(dev->dev_private, sizeof(drm_i810_private_t),
  200. DRM_MEM_DRIVER);
  201. dev->dev_private = NULL;
  202. for (i = 0; i < dma->buf_count; i++) {
  203. drm_buf_t *buf = dma->buflist[i];
  204. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  205. if (buf_priv->kernel_virtual && buf->total)
  206. drm_ioremapfree(buf_priv->kernel_virtual,
  207. buf->total, dev);
  208. }
  209. }
  210. return 0;
  211. }
  212. static int i810_wait_ring(drm_device_t * dev, int n)
  213. {
  214. drm_i810_private_t *dev_priv = dev->dev_private;
  215. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  216. int iters = 0;
  217. unsigned long end;
  218. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  219. end = jiffies + (HZ * 3);
  220. while (ring->space < n) {
  221. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  222. ring->space = ring->head - (ring->tail + 8);
  223. if (ring->space < 0)
  224. ring->space += ring->Size;
  225. if (ring->head != last_head) {
  226. end = jiffies + (HZ * 3);
  227. last_head = ring->head;
  228. }
  229. iters++;
  230. if (time_before(end, jiffies)) {
  231. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  232. DRM_ERROR("lockup\n");
  233. goto out_wait_ring;
  234. }
  235. udelay(1);
  236. }
  237. out_wait_ring:
  238. return iters;
  239. }
  240. static void i810_kernel_lost_context(drm_device_t * dev)
  241. {
  242. drm_i810_private_t *dev_priv = dev->dev_private;
  243. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  244. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  245. ring->tail = I810_READ(LP_RING + RING_TAIL);
  246. ring->space = ring->head - (ring->tail + 8);
  247. if (ring->space < 0)
  248. ring->space += ring->Size;
  249. }
  250. static int i810_freelist_init(drm_device_t * dev, drm_i810_private_t * dev_priv)
  251. {
  252. drm_device_dma_t *dma = dev->dma;
  253. int my_idx = 24;
  254. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  255. int i;
  256. if (dma->buf_count > 1019) {
  257. /* Not enough space in the status page for the freelist */
  258. return -EINVAL;
  259. }
  260. for (i = 0; i < dma->buf_count; i++) {
  261. drm_buf_t *buf = dma->buflist[i];
  262. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  263. buf_priv->in_use = hw_status++;
  264. buf_priv->my_use_idx = my_idx;
  265. my_idx += 4;
  266. *buf_priv->in_use = I810_BUF_FREE;
  267. buf_priv->kernel_virtual = drm_ioremap(buf->bus_address,
  268. buf->total, dev);
  269. }
  270. return 0;
  271. }
  272. static int i810_dma_initialize(drm_device_t * dev,
  273. drm_i810_private_t * dev_priv,
  274. drm_i810_init_t * init)
  275. {
  276. struct list_head *list;
  277. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  278. list_for_each(list, &dev->maplist->head) {
  279. drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
  280. if (r_list->map &&
  281. r_list->map->type == _DRM_SHM &&
  282. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  283. dev_priv->sarea_map = r_list->map;
  284. break;
  285. }
  286. }
  287. if (!dev_priv->sarea_map) {
  288. dev->dev_private = (void *)dev_priv;
  289. i810_dma_cleanup(dev);
  290. DRM_ERROR("can not find sarea!\n");
  291. return -EINVAL;
  292. }
  293. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  294. if (!dev_priv->mmio_map) {
  295. dev->dev_private = (void *)dev_priv;
  296. i810_dma_cleanup(dev);
  297. DRM_ERROR("can not find mmio map!\n");
  298. return -EINVAL;
  299. }
  300. dev->agp_buffer_token = init->buffers_offset;
  301. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  302. if (!dev->agp_buffer_map) {
  303. dev->dev_private = (void *)dev_priv;
  304. i810_dma_cleanup(dev);
  305. DRM_ERROR("can not find dma buffer map!\n");
  306. return -EINVAL;
  307. }
  308. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  309. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  310. dev_priv->ring.Start = init->ring_start;
  311. dev_priv->ring.End = init->ring_end;
  312. dev_priv->ring.Size = init->ring_size;
  313. dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base +
  314. init->ring_start,
  315. init->ring_size, dev);
  316. if (dev_priv->ring.virtual_start == NULL) {
  317. dev->dev_private = (void *)dev_priv;
  318. i810_dma_cleanup(dev);
  319. DRM_ERROR("can not ioremap virtual address for"
  320. " ring buffer\n");
  321. return -ENOMEM;
  322. }
  323. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  324. dev_priv->w = init->w;
  325. dev_priv->h = init->h;
  326. dev_priv->pitch = init->pitch;
  327. dev_priv->back_offset = init->back_offset;
  328. dev_priv->depth_offset = init->depth_offset;
  329. dev_priv->front_offset = init->front_offset;
  330. dev_priv->overlay_offset = init->overlay_offset;
  331. dev_priv->overlay_physical = init->overlay_physical;
  332. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  333. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  334. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  335. /* Program Hardware Status Page */
  336. dev_priv->hw_status_page =
  337. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  338. &dev_priv->dma_status_page);
  339. if (!dev_priv->hw_status_page) {
  340. dev->dev_private = (void *)dev_priv;
  341. i810_dma_cleanup(dev);
  342. DRM_ERROR("Can not allocate hardware status page\n");
  343. return -ENOMEM;
  344. }
  345. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  346. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  347. I810_WRITE(0x02080, dev_priv->dma_status_page);
  348. DRM_DEBUG("Enabled hardware status page\n");
  349. /* Now we need to init our freelist */
  350. if (i810_freelist_init(dev, dev_priv) != 0) {
  351. dev->dev_private = (void *)dev_priv;
  352. i810_dma_cleanup(dev);
  353. DRM_ERROR("Not enough space in the status page for"
  354. " the freelist\n");
  355. return -ENOMEM;
  356. }
  357. dev->dev_private = (void *)dev_priv;
  358. return 0;
  359. }
  360. /* i810 DRM version 1.1 used a smaller init structure with different
  361. * ordering of values than is currently used (drm >= 1.2). There is
  362. * no defined way to detect the XFree version to correct this problem,
  363. * however by checking using this procedure we can detect the correct
  364. * thing to do.
  365. *
  366. * #1 Read the Smaller init structure from user-space
  367. * #2 Verify the overlay_physical is a valid physical address, or NULL
  368. * If it isn't then we have a v1.1 client. Fix up params.
  369. * If it is, then we have a 1.2 client... get the rest of the data.
  370. */
  371. static int i810_dma_init_compat(drm_i810_init_t * init, unsigned long arg)
  372. {
  373. /* Get v1.1 init data */
  374. if (copy_from_user(init, (drm_i810_pre12_init_t __user *) arg,
  375. sizeof(drm_i810_pre12_init_t))) {
  376. return -EFAULT;
  377. }
  378. if ((!init->overlay_physical) || (init->overlay_physical > 4096)) {
  379. /* This is a v1.2 client, just get the v1.2 init data */
  380. DRM_INFO("Using POST v1.2 init.\n");
  381. if (copy_from_user(init, (drm_i810_init_t __user *) arg,
  382. sizeof(drm_i810_init_t))) {
  383. return -EFAULT;
  384. }
  385. } else {
  386. /* This is a v1.1 client, fix the params */
  387. DRM_INFO("Using PRE v1.2 init.\n");
  388. init->pitch_bits = init->h;
  389. init->pitch = init->w;
  390. init->h = init->overlay_physical;
  391. init->w = init->overlay_offset;
  392. init->overlay_physical = 0;
  393. init->overlay_offset = 0;
  394. }
  395. return 0;
  396. }
  397. static int i810_dma_init(struct inode *inode, struct file *filp,
  398. unsigned int cmd, unsigned long arg)
  399. {
  400. drm_file_t *priv = filp->private_data;
  401. drm_device_t *dev = priv->head->dev;
  402. drm_i810_private_t *dev_priv;
  403. drm_i810_init_t init;
  404. int retcode = 0;
  405. /* Get only the init func */
  406. if (copy_from_user
  407. (&init, (void __user *)arg, sizeof(drm_i810_init_func_t)))
  408. return -EFAULT;
  409. switch (init.func) {
  410. case I810_INIT_DMA:
  411. /* This case is for backward compatibility. It
  412. * handles XFree 4.1.0 and 4.2.0, and has to
  413. * do some parameter checking as described below.
  414. * It will someday go away.
  415. */
  416. retcode = i810_dma_init_compat(&init, arg);
  417. if (retcode)
  418. return retcode;
  419. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  420. DRM_MEM_DRIVER);
  421. if (dev_priv == NULL)
  422. return -ENOMEM;
  423. retcode = i810_dma_initialize(dev, dev_priv, &init);
  424. break;
  425. default:
  426. case I810_INIT_DMA_1_4:
  427. DRM_INFO("Using v1.4 init.\n");
  428. if (copy_from_user(&init, (drm_i810_init_t __user *) arg,
  429. sizeof(drm_i810_init_t))) {
  430. return -EFAULT;
  431. }
  432. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  433. DRM_MEM_DRIVER);
  434. if (dev_priv == NULL)
  435. return -ENOMEM;
  436. retcode = i810_dma_initialize(dev, dev_priv, &init);
  437. break;
  438. case I810_CLEANUP_DMA:
  439. DRM_INFO("DMA Cleanup\n");
  440. retcode = i810_dma_cleanup(dev);
  441. break;
  442. }
  443. return retcode;
  444. }
  445. /* Most efficient way to verify state for the i810 is as it is
  446. * emitted. Non-conformant state is silently dropped.
  447. *
  448. * Use 'volatile' & local var tmp to force the emitted values to be
  449. * identical to the verified ones.
  450. */
  451. static void i810EmitContextVerified(drm_device_t * dev,
  452. volatile unsigned int *code)
  453. {
  454. drm_i810_private_t *dev_priv = dev->dev_private;
  455. int i, j = 0;
  456. unsigned int tmp;
  457. RING_LOCALS;
  458. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  459. OUT_RING(GFX_OP_COLOR_FACTOR);
  460. OUT_RING(code[I810_CTXREG_CF1]);
  461. OUT_RING(GFX_OP_STIPPLE);
  462. OUT_RING(code[I810_CTXREG_ST1]);
  463. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  464. tmp = code[i];
  465. if ((tmp & (7 << 29)) == (3 << 29) &&
  466. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  467. OUT_RING(tmp);
  468. j++;
  469. } else
  470. printk("constext state dropped!!!\n");
  471. }
  472. if (j & 1)
  473. OUT_RING(0);
  474. ADVANCE_LP_RING();
  475. }
  476. static void i810EmitTexVerified(drm_device_t * dev, volatile unsigned int *code)
  477. {
  478. drm_i810_private_t *dev_priv = dev->dev_private;
  479. int i, j = 0;
  480. unsigned int tmp;
  481. RING_LOCALS;
  482. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  483. OUT_RING(GFX_OP_MAP_INFO);
  484. OUT_RING(code[I810_TEXREG_MI1]);
  485. OUT_RING(code[I810_TEXREG_MI2]);
  486. OUT_RING(code[I810_TEXREG_MI3]);
  487. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  488. tmp = code[i];
  489. if ((tmp & (7 << 29)) == (3 << 29) &&
  490. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  491. OUT_RING(tmp);
  492. j++;
  493. } else
  494. printk("texture state dropped!!!\n");
  495. }
  496. if (j & 1)
  497. OUT_RING(0);
  498. ADVANCE_LP_RING();
  499. }
  500. /* Need to do some additional checking when setting the dest buffer.
  501. */
  502. static void i810EmitDestVerified(drm_device_t * dev,
  503. volatile unsigned int *code)
  504. {
  505. drm_i810_private_t *dev_priv = dev->dev_private;
  506. unsigned int tmp;
  507. RING_LOCALS;
  508. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  509. tmp = code[I810_DESTREG_DI1];
  510. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  511. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  512. OUT_RING(tmp);
  513. } else
  514. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  515. tmp, dev_priv->front_di1, dev_priv->back_di1);
  516. /* invarient:
  517. */
  518. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  519. OUT_RING(dev_priv->zi1);
  520. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  521. OUT_RING(code[I810_DESTREG_DV1]);
  522. OUT_RING(GFX_OP_DRAWRECT_INFO);
  523. OUT_RING(code[I810_DESTREG_DR1]);
  524. OUT_RING(code[I810_DESTREG_DR2]);
  525. OUT_RING(code[I810_DESTREG_DR3]);
  526. OUT_RING(code[I810_DESTREG_DR4]);
  527. OUT_RING(0);
  528. ADVANCE_LP_RING();
  529. }
  530. static void i810EmitState(drm_device_t * dev)
  531. {
  532. drm_i810_private_t *dev_priv = dev->dev_private;
  533. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  534. unsigned int dirty = sarea_priv->dirty;
  535. DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
  536. if (dirty & I810_UPLOAD_BUFFERS) {
  537. i810EmitDestVerified(dev, sarea_priv->BufferState);
  538. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  539. }
  540. if (dirty & I810_UPLOAD_CTX) {
  541. i810EmitContextVerified(dev, sarea_priv->ContextState);
  542. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  543. }
  544. if (dirty & I810_UPLOAD_TEX0) {
  545. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  546. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  547. }
  548. if (dirty & I810_UPLOAD_TEX1) {
  549. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  550. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  551. }
  552. }
  553. /* need to verify
  554. */
  555. static void i810_dma_dispatch_clear(drm_device_t * dev, int flags,
  556. unsigned int clear_color,
  557. unsigned int clear_zval)
  558. {
  559. drm_i810_private_t *dev_priv = dev->dev_private;
  560. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  561. int nbox = sarea_priv->nbox;
  562. drm_clip_rect_t *pbox = sarea_priv->boxes;
  563. int pitch = dev_priv->pitch;
  564. int cpp = 2;
  565. int i;
  566. RING_LOCALS;
  567. if (dev_priv->current_page == 1) {
  568. unsigned int tmp = flags;
  569. flags &= ~(I810_FRONT | I810_BACK);
  570. if (tmp & I810_FRONT)
  571. flags |= I810_BACK;
  572. if (tmp & I810_BACK)
  573. flags |= I810_FRONT;
  574. }
  575. i810_kernel_lost_context(dev);
  576. if (nbox > I810_NR_SAREA_CLIPRECTS)
  577. nbox = I810_NR_SAREA_CLIPRECTS;
  578. for (i = 0; i < nbox; i++, pbox++) {
  579. unsigned int x = pbox->x1;
  580. unsigned int y = pbox->y1;
  581. unsigned int width = (pbox->x2 - x) * cpp;
  582. unsigned int height = pbox->y2 - y;
  583. unsigned int start = y * pitch + x * cpp;
  584. if (pbox->x1 > pbox->x2 ||
  585. pbox->y1 > pbox->y2 ||
  586. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  587. continue;
  588. if (flags & I810_FRONT) {
  589. BEGIN_LP_RING(6);
  590. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  591. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  592. OUT_RING((height << 16) | width);
  593. OUT_RING(start);
  594. OUT_RING(clear_color);
  595. OUT_RING(0);
  596. ADVANCE_LP_RING();
  597. }
  598. if (flags & I810_BACK) {
  599. BEGIN_LP_RING(6);
  600. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  601. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  602. OUT_RING((height << 16) | width);
  603. OUT_RING(dev_priv->back_offset + start);
  604. OUT_RING(clear_color);
  605. OUT_RING(0);
  606. ADVANCE_LP_RING();
  607. }
  608. if (flags & I810_DEPTH) {
  609. BEGIN_LP_RING(6);
  610. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  611. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  612. OUT_RING((height << 16) | width);
  613. OUT_RING(dev_priv->depth_offset + start);
  614. OUT_RING(clear_zval);
  615. OUT_RING(0);
  616. ADVANCE_LP_RING();
  617. }
  618. }
  619. }
  620. static void i810_dma_dispatch_swap(drm_device_t * dev)
  621. {
  622. drm_i810_private_t *dev_priv = dev->dev_private;
  623. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  624. int nbox = sarea_priv->nbox;
  625. drm_clip_rect_t *pbox = sarea_priv->boxes;
  626. int pitch = dev_priv->pitch;
  627. int cpp = 2;
  628. int i;
  629. RING_LOCALS;
  630. DRM_DEBUG("swapbuffers\n");
  631. i810_kernel_lost_context(dev);
  632. if (nbox > I810_NR_SAREA_CLIPRECTS)
  633. nbox = I810_NR_SAREA_CLIPRECTS;
  634. for (i = 0; i < nbox; i++, pbox++) {
  635. unsigned int w = pbox->x2 - pbox->x1;
  636. unsigned int h = pbox->y2 - pbox->y1;
  637. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  638. unsigned int start = dst;
  639. if (pbox->x1 > pbox->x2 ||
  640. pbox->y1 > pbox->y2 ||
  641. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  642. continue;
  643. BEGIN_LP_RING(6);
  644. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  645. OUT_RING(pitch | (0xCC << 16));
  646. OUT_RING((h << 16) | (w * cpp));
  647. if (dev_priv->current_page == 0)
  648. OUT_RING(dev_priv->front_offset + start);
  649. else
  650. OUT_RING(dev_priv->back_offset + start);
  651. OUT_RING(pitch);
  652. if (dev_priv->current_page == 0)
  653. OUT_RING(dev_priv->back_offset + start);
  654. else
  655. OUT_RING(dev_priv->front_offset + start);
  656. ADVANCE_LP_RING();
  657. }
  658. }
  659. static void i810_dma_dispatch_vertex(drm_device_t * dev,
  660. drm_buf_t * buf, int discard, int used)
  661. {
  662. drm_i810_private_t *dev_priv = dev->dev_private;
  663. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  664. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  665. drm_clip_rect_t *box = sarea_priv->boxes;
  666. int nbox = sarea_priv->nbox;
  667. unsigned long address = (unsigned long)buf->bus_address;
  668. unsigned long start = address - dev->agp->base;
  669. int i = 0;
  670. RING_LOCALS;
  671. i810_kernel_lost_context(dev);
  672. if (nbox > I810_NR_SAREA_CLIPRECTS)
  673. nbox = I810_NR_SAREA_CLIPRECTS;
  674. if (used > 4 * 1024)
  675. used = 0;
  676. if (sarea_priv->dirty)
  677. i810EmitState(dev);
  678. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  679. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  680. *(u32 *) buf_priv->kernel_virtual =
  681. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  682. if (used & 4) {
  683. *(u32 *) ((u32) buf_priv->kernel_virtual + used) = 0;
  684. used += 4;
  685. }
  686. i810_unmap_buffer(buf);
  687. }
  688. if (used) {
  689. do {
  690. if (i < nbox) {
  691. BEGIN_LP_RING(4);
  692. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  693. SC_ENABLE);
  694. OUT_RING(GFX_OP_SCISSOR_INFO);
  695. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  696. OUT_RING((box[i].x2 -
  697. 1) | ((box[i].y2 - 1) << 16));
  698. ADVANCE_LP_RING();
  699. }
  700. BEGIN_LP_RING(4);
  701. OUT_RING(CMD_OP_BATCH_BUFFER);
  702. OUT_RING(start | BB1_PROTECTED);
  703. OUT_RING(start + used - 4);
  704. OUT_RING(0);
  705. ADVANCE_LP_RING();
  706. } while (++i < nbox);
  707. }
  708. if (discard) {
  709. dev_priv->counter++;
  710. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  711. I810_BUF_HARDWARE);
  712. BEGIN_LP_RING(8);
  713. OUT_RING(CMD_STORE_DWORD_IDX);
  714. OUT_RING(20);
  715. OUT_RING(dev_priv->counter);
  716. OUT_RING(CMD_STORE_DWORD_IDX);
  717. OUT_RING(buf_priv->my_use_idx);
  718. OUT_RING(I810_BUF_FREE);
  719. OUT_RING(CMD_REPORT_HEAD);
  720. OUT_RING(0);
  721. ADVANCE_LP_RING();
  722. }
  723. }
  724. static void i810_dma_dispatch_flip(drm_device_t * dev)
  725. {
  726. drm_i810_private_t *dev_priv = dev->dev_private;
  727. int pitch = dev_priv->pitch;
  728. RING_LOCALS;
  729. DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
  730. __FUNCTION__,
  731. dev_priv->current_page,
  732. dev_priv->sarea_priv->pf_current_page);
  733. i810_kernel_lost_context(dev);
  734. BEGIN_LP_RING(2);
  735. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  736. OUT_RING(0);
  737. ADVANCE_LP_RING();
  738. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  739. /* On i815 at least ASYNC is buggy */
  740. /* pitch<<5 is from 11.2.8 p158,
  741. its the pitch / 8 then left shifted 8,
  742. so (pitch >> 3) << 8 */
  743. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  744. if (dev_priv->current_page == 0) {
  745. OUT_RING(dev_priv->back_offset);
  746. dev_priv->current_page = 1;
  747. } else {
  748. OUT_RING(dev_priv->front_offset);
  749. dev_priv->current_page = 0;
  750. }
  751. OUT_RING(0);
  752. ADVANCE_LP_RING();
  753. BEGIN_LP_RING(2);
  754. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  755. OUT_RING(0);
  756. ADVANCE_LP_RING();
  757. /* Increment the frame counter. The client-side 3D driver must
  758. * throttle the framerate by waiting for this value before
  759. * performing the swapbuffer ioctl.
  760. */
  761. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  762. }
  763. static void i810_dma_quiescent(drm_device_t * dev)
  764. {
  765. drm_i810_private_t *dev_priv = dev->dev_private;
  766. RING_LOCALS;
  767. /* printk("%s\n", __FUNCTION__); */
  768. i810_kernel_lost_context(dev);
  769. BEGIN_LP_RING(4);
  770. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  771. OUT_RING(CMD_REPORT_HEAD);
  772. OUT_RING(0);
  773. OUT_RING(0);
  774. ADVANCE_LP_RING();
  775. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  776. }
  777. static int i810_flush_queue(drm_device_t * dev)
  778. {
  779. drm_i810_private_t *dev_priv = dev->dev_private;
  780. drm_device_dma_t *dma = dev->dma;
  781. int i, ret = 0;
  782. RING_LOCALS;
  783. /* printk("%s\n", __FUNCTION__); */
  784. i810_kernel_lost_context(dev);
  785. BEGIN_LP_RING(2);
  786. OUT_RING(CMD_REPORT_HEAD);
  787. OUT_RING(0);
  788. ADVANCE_LP_RING();
  789. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  790. for (i = 0; i < dma->buf_count; i++) {
  791. drm_buf_t *buf = dma->buflist[i];
  792. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  793. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  794. I810_BUF_FREE);
  795. if (used == I810_BUF_HARDWARE)
  796. DRM_DEBUG("reclaimed from HARDWARE\n");
  797. if (used == I810_BUF_CLIENT)
  798. DRM_DEBUG("still on client\n");
  799. }
  800. return ret;
  801. }
  802. /* Must be called with the lock held */
  803. static void i810_reclaim_buffers(drm_device_t * dev, struct file *filp)
  804. {
  805. drm_device_dma_t *dma = dev->dma;
  806. int i;
  807. if (!dma)
  808. return;
  809. if (!dev->dev_private)
  810. return;
  811. if (!dma->buflist)
  812. return;
  813. i810_flush_queue(dev);
  814. for (i = 0; i < dma->buf_count; i++) {
  815. drm_buf_t *buf = dma->buflist[i];
  816. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  817. if (buf->filp == filp && buf_priv) {
  818. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  819. I810_BUF_FREE);
  820. if (used == I810_BUF_CLIENT)
  821. DRM_DEBUG("reclaimed from client\n");
  822. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  823. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  824. }
  825. }
  826. }
  827. static int i810_flush_ioctl(struct inode *inode, struct file *filp,
  828. unsigned int cmd, unsigned long arg)
  829. {
  830. drm_file_t *priv = filp->private_data;
  831. drm_device_t *dev = priv->head->dev;
  832. LOCK_TEST_WITH_RETURN(dev, filp);
  833. i810_flush_queue(dev);
  834. return 0;
  835. }
  836. static int i810_dma_vertex(struct inode *inode, struct file *filp,
  837. unsigned int cmd, unsigned long arg)
  838. {
  839. drm_file_t *priv = filp->private_data;
  840. drm_device_t *dev = priv->head->dev;
  841. drm_device_dma_t *dma = dev->dma;
  842. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  843. u32 *hw_status = dev_priv->hw_status_page;
  844. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  845. dev_priv->sarea_priv;
  846. drm_i810_vertex_t vertex;
  847. if (copy_from_user
  848. (&vertex, (drm_i810_vertex_t __user *) arg, sizeof(vertex)))
  849. return -EFAULT;
  850. LOCK_TEST_WITH_RETURN(dev, filp);
  851. DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
  852. vertex.idx, vertex.used, vertex.discard);
  853. if (vertex.idx < 0 || vertex.idx > dma->buf_count)
  854. return -EINVAL;
  855. i810_dma_dispatch_vertex(dev,
  856. dma->buflist[vertex.idx],
  857. vertex.discard, vertex.used);
  858. atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
  859. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  860. sarea_priv->last_enqueue = dev_priv->counter - 1;
  861. sarea_priv->last_dispatch = (int)hw_status[5];
  862. return 0;
  863. }
  864. static int i810_clear_bufs(struct inode *inode, struct file *filp,
  865. unsigned int cmd, unsigned long arg)
  866. {
  867. drm_file_t *priv = filp->private_data;
  868. drm_device_t *dev = priv->head->dev;
  869. drm_i810_clear_t clear;
  870. if (copy_from_user
  871. (&clear, (drm_i810_clear_t __user *) arg, sizeof(clear)))
  872. return -EFAULT;
  873. LOCK_TEST_WITH_RETURN(dev, filp);
  874. /* GH: Someone's doing nasty things... */
  875. if (!dev->dev_private) {
  876. return -EINVAL;
  877. }
  878. i810_dma_dispatch_clear(dev, clear.flags,
  879. clear.clear_color, clear.clear_depth);
  880. return 0;
  881. }
  882. static int i810_swap_bufs(struct inode *inode, struct file *filp,
  883. unsigned int cmd, unsigned long arg)
  884. {
  885. drm_file_t *priv = filp->private_data;
  886. drm_device_t *dev = priv->head->dev;
  887. DRM_DEBUG("i810_swap_bufs\n");
  888. LOCK_TEST_WITH_RETURN(dev, filp);
  889. i810_dma_dispatch_swap(dev);
  890. return 0;
  891. }
  892. static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
  893. unsigned long arg)
  894. {
  895. drm_file_t *priv = filp->private_data;
  896. drm_device_t *dev = priv->head->dev;
  897. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  898. u32 *hw_status = dev_priv->hw_status_page;
  899. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  900. dev_priv->sarea_priv;
  901. sarea_priv->last_dispatch = (int)hw_status[5];
  902. return 0;
  903. }
  904. static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
  905. unsigned long arg)
  906. {
  907. drm_file_t *priv = filp->private_data;
  908. drm_device_t *dev = priv->head->dev;
  909. int retcode = 0;
  910. drm_i810_dma_t d;
  911. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  912. u32 *hw_status = dev_priv->hw_status_page;
  913. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  914. dev_priv->sarea_priv;
  915. if (copy_from_user(&d, (drm_i810_dma_t __user *) arg, sizeof(d)))
  916. return -EFAULT;
  917. LOCK_TEST_WITH_RETURN(dev, filp);
  918. d.granted = 0;
  919. retcode = i810_dma_get_buffer(dev, &d, filp);
  920. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  921. current->pid, retcode, d.granted);
  922. if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d)))
  923. return -EFAULT;
  924. sarea_priv->last_dispatch = (int)hw_status[5];
  925. return retcode;
  926. }
  927. static int i810_copybuf(struct inode *inode,
  928. struct file *filp, unsigned int cmd, unsigned long arg)
  929. {
  930. /* Never copy - 2.4.x doesn't need it */
  931. return 0;
  932. }
  933. static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
  934. unsigned long arg)
  935. {
  936. /* Never copy - 2.4.x doesn't need it */
  937. return 0;
  938. }
  939. static void i810_dma_dispatch_mc(drm_device_t * dev, drm_buf_t * buf, int used,
  940. unsigned int last_render)
  941. {
  942. drm_i810_private_t *dev_priv = dev->dev_private;
  943. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  944. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  945. unsigned long address = (unsigned long)buf->bus_address;
  946. unsigned long start = address - dev->agp->base;
  947. int u;
  948. RING_LOCALS;
  949. i810_kernel_lost_context(dev);
  950. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  951. if (u != I810_BUF_CLIENT) {
  952. DRM_DEBUG("MC found buffer that isn't mine!\n");
  953. }
  954. if (used > 4 * 1024)
  955. used = 0;
  956. sarea_priv->dirty = 0x7f;
  957. DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used);
  958. dev_priv->counter++;
  959. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  960. DRM_DEBUG("i810_dma_dispatch_mc\n");
  961. DRM_DEBUG("start : %lx\n", start);
  962. DRM_DEBUG("used : %d\n", used);
  963. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  964. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  965. if (used & 4) {
  966. *(u32 *) ((u32) buf_priv->virtual + used) = 0;
  967. used += 4;
  968. }
  969. i810_unmap_buffer(buf);
  970. }
  971. BEGIN_LP_RING(4);
  972. OUT_RING(CMD_OP_BATCH_BUFFER);
  973. OUT_RING(start | BB1_PROTECTED);
  974. OUT_RING(start + used - 4);
  975. OUT_RING(0);
  976. ADVANCE_LP_RING();
  977. BEGIN_LP_RING(8);
  978. OUT_RING(CMD_STORE_DWORD_IDX);
  979. OUT_RING(buf_priv->my_use_idx);
  980. OUT_RING(I810_BUF_FREE);
  981. OUT_RING(0);
  982. OUT_RING(CMD_STORE_DWORD_IDX);
  983. OUT_RING(16);
  984. OUT_RING(last_render);
  985. OUT_RING(0);
  986. ADVANCE_LP_RING();
  987. }
  988. static int i810_dma_mc(struct inode *inode, struct file *filp,
  989. unsigned int cmd, unsigned long arg)
  990. {
  991. drm_file_t *priv = filp->private_data;
  992. drm_device_t *dev = priv->head->dev;
  993. drm_device_dma_t *dma = dev->dma;
  994. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  995. u32 *hw_status = dev_priv->hw_status_page;
  996. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  997. dev_priv->sarea_priv;
  998. drm_i810_mc_t mc;
  999. if (copy_from_user(&mc, (drm_i810_mc_t __user *) arg, sizeof(mc)))
  1000. return -EFAULT;
  1001. LOCK_TEST_WITH_RETURN(dev, filp);
  1002. if (mc.idx >= dma->buf_count || mc.idx < 0)
  1003. return -EINVAL;
  1004. i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used,
  1005. mc.last_render);
  1006. atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]);
  1007. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  1008. sarea_priv->last_enqueue = dev_priv->counter - 1;
  1009. sarea_priv->last_dispatch = (int)hw_status[5];
  1010. return 0;
  1011. }
  1012. static int i810_rstatus(struct inode *inode, struct file *filp,
  1013. unsigned int cmd, unsigned long arg)
  1014. {
  1015. drm_file_t *priv = filp->private_data;
  1016. drm_device_t *dev = priv->head->dev;
  1017. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1018. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  1019. }
  1020. static int i810_ov0_info(struct inode *inode, struct file *filp,
  1021. unsigned int cmd, unsigned long arg)
  1022. {
  1023. drm_file_t *priv = filp->private_data;
  1024. drm_device_t *dev = priv->head->dev;
  1025. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1026. drm_i810_overlay_t data;
  1027. data.offset = dev_priv->overlay_offset;
  1028. data.physical = dev_priv->overlay_physical;
  1029. if (copy_to_user
  1030. ((drm_i810_overlay_t __user *) arg, &data, sizeof(data)))
  1031. return -EFAULT;
  1032. return 0;
  1033. }
  1034. static int i810_fstatus(struct inode *inode, struct file *filp,
  1035. unsigned int cmd, unsigned long arg)
  1036. {
  1037. drm_file_t *priv = filp->private_data;
  1038. drm_device_t *dev = priv->head->dev;
  1039. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1040. LOCK_TEST_WITH_RETURN(dev, filp);
  1041. return I810_READ(0x30008);
  1042. }
  1043. static int i810_ov0_flip(struct inode *inode, struct file *filp,
  1044. unsigned int cmd, unsigned long arg)
  1045. {
  1046. drm_file_t *priv = filp->private_data;
  1047. drm_device_t *dev = priv->head->dev;
  1048. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1049. LOCK_TEST_WITH_RETURN(dev, filp);
  1050. //Tell the overlay to update
  1051. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  1052. return 0;
  1053. }
  1054. /* Not sure why this isn't set all the time:
  1055. */
  1056. static void i810_do_init_pageflip(drm_device_t * dev)
  1057. {
  1058. drm_i810_private_t *dev_priv = dev->dev_private;
  1059. DRM_DEBUG("%s\n", __FUNCTION__);
  1060. dev_priv->page_flipping = 1;
  1061. dev_priv->current_page = 0;
  1062. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  1063. }
  1064. static int i810_do_cleanup_pageflip(drm_device_t * dev)
  1065. {
  1066. drm_i810_private_t *dev_priv = dev->dev_private;
  1067. DRM_DEBUG("%s\n", __FUNCTION__);
  1068. if (dev_priv->current_page != 0)
  1069. i810_dma_dispatch_flip(dev);
  1070. dev_priv->page_flipping = 0;
  1071. return 0;
  1072. }
  1073. static int i810_flip_bufs(struct inode *inode, struct file *filp,
  1074. unsigned int cmd, unsigned long arg)
  1075. {
  1076. drm_file_t *priv = filp->private_data;
  1077. drm_device_t *dev = priv->head->dev;
  1078. drm_i810_private_t *dev_priv = dev->dev_private;
  1079. DRM_DEBUG("%s\n", __FUNCTION__);
  1080. LOCK_TEST_WITH_RETURN(dev, filp);
  1081. if (!dev_priv->page_flipping)
  1082. i810_do_init_pageflip(dev);
  1083. i810_dma_dispatch_flip(dev);
  1084. return 0;
  1085. }
  1086. int i810_driver_load(drm_device_t *dev, unsigned long flags)
  1087. {
  1088. /* i810 has 4 more counters */
  1089. dev->counters += 4;
  1090. dev->types[6] = _DRM_STAT_IRQ;
  1091. dev->types[7] = _DRM_STAT_PRIMARY;
  1092. dev->types[8] = _DRM_STAT_SECONDARY;
  1093. dev->types[9] = _DRM_STAT_DMA;
  1094. return 0;
  1095. }
  1096. void i810_driver_lastclose(drm_device_t * dev)
  1097. {
  1098. i810_dma_cleanup(dev);
  1099. }
  1100. void i810_driver_preclose(drm_device_t * dev, DRMFILE filp)
  1101. {
  1102. if (dev->dev_private) {
  1103. drm_i810_private_t *dev_priv = dev->dev_private;
  1104. if (dev_priv->page_flipping) {
  1105. i810_do_cleanup_pageflip(dev);
  1106. }
  1107. }
  1108. }
  1109. void i810_driver_reclaim_buffers_locked(drm_device_t * dev, struct file *filp)
  1110. {
  1111. i810_reclaim_buffers(dev, filp);
  1112. }
  1113. int i810_driver_dma_quiescent(drm_device_t * dev)
  1114. {
  1115. i810_dma_quiescent(dev);
  1116. return 0;
  1117. }
  1118. drm_ioctl_desc_t i810_ioctls[] = {
  1119. [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
  1120. [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, DRM_AUTH},
  1121. [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, DRM_AUTH},
  1122. [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, DRM_AUTH},
  1123. [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, DRM_AUTH},
  1124. [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, DRM_AUTH},
  1125. [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, DRM_AUTH},
  1126. [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, DRM_AUTH},
  1127. [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, DRM_AUTH},
  1128. [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, DRM_AUTH},
  1129. [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, DRM_AUTH},
  1130. [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, DRM_AUTH},
  1131. [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
  1132. [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, DRM_AUTH},
  1133. [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, DRM_AUTH}
  1134. };
  1135. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1136. /**
  1137. * Determine if the device really is AGP or not.
  1138. *
  1139. * All Intel graphics chipsets are treated as AGP, even if they are really
  1140. * PCI-e.
  1141. *
  1142. * \param dev The device to be tested.
  1143. *
  1144. * \returns
  1145. * A value of 1 is always retured to indictate every i810 is AGP.
  1146. */
  1147. int i810_driver_device_is_agp(drm_device_t * dev)
  1148. {
  1149. return 1;
  1150. }