ibm44x_common.c 6.0 KB

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  1. /*
  2. * arch/ppc/syslib/ibm44x_common.c
  3. *
  4. * PPC44x system library
  5. *
  6. * Matt Porter <mporter@kernel.crashing.org>
  7. * Copyright 2002-2005 MontaVista Software Inc.
  8. *
  9. * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  10. * Copyright (c) 2003, 2004 Zultys Technologies
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. */
  18. #include <linux/config.h>
  19. #include <linux/time.h>
  20. #include <linux/types.h>
  21. #include <linux/serial.h>
  22. #include <linux/module.h>
  23. #include <linux/initrd.h>
  24. #include <asm/ibm44x.h>
  25. #include <asm/mmu.h>
  26. #include <asm/machdep.h>
  27. #include <asm/time.h>
  28. #include <asm/ppc4xx_pic.h>
  29. #include <asm/param.h>
  30. #include <asm/bootinfo.h>
  31. #include <asm/ppcboot.h>
  32. #include <syslib/gen550.h>
  33. /* Global Variables */
  34. bd_t __res;
  35. phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
  36. {
  37. phys_addr_t page_4gb = 0;
  38. /*
  39. * Trap the least significant 32-bit portions of an
  40. * address in the 440's 36-bit address space. Fix
  41. * them up with the appropriate ERPN
  42. */
  43. if ((addr >= PPC44x_IO_LO) && (addr <= PPC44x_IO_HI))
  44. page_4gb = PPC44x_IO_PAGE;
  45. else if ((addr >= PPC44x_PCI0CFG_LO) && (addr <= PPC44x_PCI0CFG_HI))
  46. page_4gb = PPC44x_PCICFG_PAGE;
  47. #ifdef CONFIG_440SP
  48. else if ((addr >= PPC44x_PCI1CFG_LO) && (addr <= PPC44x_PCI1CFG_HI))
  49. page_4gb = PPC44x_PCICFG_PAGE;
  50. else if ((addr >= PPC44x_PCI2CFG_LO) && (addr <= PPC44x_PCI2CFG_HI))
  51. page_4gb = PPC44x_PCICFG_PAGE;
  52. #endif
  53. else if ((addr >= PPC44x_PCIMEM_LO) && (addr <= PPC44x_PCIMEM_HI))
  54. page_4gb = PPC44x_PCIMEM_PAGE;
  55. return (page_4gb | addr);
  56. };
  57. EXPORT_SYMBOL(fixup_bigphys_addr);
  58. void __init ibm44x_calibrate_decr(unsigned int freq)
  59. {
  60. tb_ticks_per_jiffy = freq / HZ;
  61. tb_to_us = mulhwu_scale_factor(freq, 1000000);
  62. /* Set the time base to zero */
  63. mtspr(SPRN_TBWL, 0);
  64. mtspr(SPRN_TBWU, 0);
  65. /* Clear any pending timer interrupts */
  66. mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
  67. /* Enable decrementer interrupt */
  68. mtspr(SPRN_TCR, TCR_DIE);
  69. }
  70. extern void abort(void);
  71. static void ibm44x_restart(char *cmd)
  72. {
  73. local_irq_disable();
  74. abort();
  75. }
  76. static void ibm44x_power_off(void)
  77. {
  78. local_irq_disable();
  79. for(;;);
  80. }
  81. static void ibm44x_halt(void)
  82. {
  83. local_irq_disable();
  84. for(;;);
  85. }
  86. /*
  87. * Read the 44x memory controller to get size of system memory.
  88. */
  89. static unsigned long __init ibm44x_find_end_of_memory(void)
  90. {
  91. u32 i, bank_config;
  92. u32 mem_size = 0;
  93. for (i=0; i<4; i++)
  94. {
  95. switch (i)
  96. {
  97. case 0:
  98. mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
  99. break;
  100. case 1:
  101. mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
  102. break;
  103. case 2:
  104. mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
  105. break;
  106. case 3:
  107. mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
  108. break;
  109. }
  110. bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
  111. if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
  112. continue;
  113. switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
  114. {
  115. case SDRAM_CONFIG_SIZE_8M:
  116. mem_size += PPC44x_MEM_SIZE_8M;
  117. break;
  118. case SDRAM_CONFIG_SIZE_16M:
  119. mem_size += PPC44x_MEM_SIZE_16M;
  120. break;
  121. case SDRAM_CONFIG_SIZE_32M:
  122. mem_size += PPC44x_MEM_SIZE_32M;
  123. break;
  124. case SDRAM_CONFIG_SIZE_64M:
  125. mem_size += PPC44x_MEM_SIZE_64M;
  126. break;
  127. case SDRAM_CONFIG_SIZE_128M:
  128. mem_size += PPC44x_MEM_SIZE_128M;
  129. break;
  130. case SDRAM_CONFIG_SIZE_256M:
  131. mem_size += PPC44x_MEM_SIZE_256M;
  132. break;
  133. case SDRAM_CONFIG_SIZE_512M:
  134. mem_size += PPC44x_MEM_SIZE_512M;
  135. break;
  136. }
  137. }
  138. return mem_size;
  139. }
  140. void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
  141. unsigned long r6, unsigned long r7)
  142. {
  143. parse_bootinfo(find_bootinfo());
  144. /*
  145. * If we were passed in a board information, copy it into the
  146. * residual data area.
  147. */
  148. if (r3)
  149. __res = *(bd_t *)(r3 + KERNELBASE);
  150. #if defined(CONFIG_BLK_DEV_INITRD)
  151. /*
  152. * If the init RAM disk has been configured in, and there's a valid
  153. * starting address for it, set it up.
  154. */
  155. if (r4) {
  156. initrd_start = r4 + KERNELBASE;
  157. initrd_end = r5 + KERNELBASE;
  158. }
  159. #endif /* CONFIG_BLK_DEV_INITRD */
  160. /* Copy the kernel command line arguments to a safe place. */
  161. if (r6) {
  162. *(char *) (r7 + KERNELBASE) = 0;
  163. strcpy(cmd_line, (char *) (r6 + KERNELBASE));
  164. }
  165. ppc_md.init_IRQ = ppc4xx_pic_init;
  166. ppc_md.find_end_of_memory = ibm44x_find_end_of_memory;
  167. ppc_md.restart = ibm44x_restart;
  168. ppc_md.power_off = ibm44x_power_off;
  169. ppc_md.halt = ibm44x_halt;
  170. #ifdef CONFIG_SERIAL_TEXT_DEBUG
  171. ppc_md.progress = gen550_progress;
  172. #endif /* CONFIG_SERIAL_TEXT_DEBUG */
  173. #ifdef CONFIG_KGDB
  174. ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
  175. #endif
  176. /*
  177. * The Abatron BDI JTAG debugger does not tolerate others
  178. * mucking with the debug registers.
  179. */
  180. #if !defined(CONFIG_BDI_SWITCH)
  181. /* Enable internal debug mode */
  182. mtspr(SPRN_DBCR0, (DBCR0_IDM));
  183. /* Clear any residual debug events */
  184. mtspr(SPRN_DBSR, 0xffffffff);
  185. #endif
  186. }
  187. /* Called from machine_check_exception */
  188. void platform_machine_check(struct pt_regs *regs)
  189. {
  190. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  191. printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
  192. mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
  193. mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
  194. mfdcr(DCRN_PLB0_BESRL));
  195. printk("PLB1: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
  196. mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
  197. mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
  198. mfdcr(DCRN_PLB1_BESRL));
  199. #else
  200. printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n",
  201. mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
  202. mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR));
  203. #endif
  204. printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
  205. mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
  206. mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
  207. printk("OPB0: BEAR=0x%08x%08x BSTAT=0x%08x\n",
  208. mfdcr(DCRN_OPB0_BEARH), mfdcr(DCRN_OPB0_BEARL),
  209. mfdcr(DCRN_OPB0_BSTAT));
  210. }