gt64260_pic.c 9.4 KB

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  1. /*
  2. * arch/ppc/syslib/gt64260_pic.c
  3. *
  4. * Interrupt controller support for Galileo's GT64260.
  5. *
  6. * Author: Chris Zankel <source@mvista.com>
  7. * Modified by: Mark A. Greer <mgreer@mvista.com>
  8. *
  9. * Based on sources from Rabeeh Khoury / Galileo Technology
  10. *
  11. * 2001 (c) MontaVista, Software, Inc. This file is licensed under
  12. * the terms of the GNU General Public License version 2. This program
  13. * is licensed "as is" without any warranty of any kind, whether express
  14. * or implied.
  15. */
  16. /*
  17. * This file contains the specific functions to support the GT64260
  18. * interrupt controller.
  19. *
  20. * The GT64260 has two main interrupt registers (high and low) that
  21. * summarizes the interrupts generated by the units of the GT64260.
  22. * Each bit is assigned to an interrupt number, where the low register
  23. * are assigned from IRQ0 to IRQ31 and the high cause register
  24. * from IRQ32 to IRQ63
  25. * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0)
  26. * to IRQ95 (GPP31).
  27. * get_irq() returns the lowest interrupt number that is currently asserted.
  28. *
  29. * Note:
  30. * - This driver does not initialize the GPP when used as an interrupt
  31. * input.
  32. */
  33. #include <linux/stddef.h>
  34. #include <linux/init.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/sched.h>
  37. #include <linux/signal.h>
  38. #include <linux/stddef.h>
  39. #include <linux/delay.h>
  40. #include <linux/irq.h>
  41. #include <asm/io.h>
  42. #include <asm/system.h>
  43. #include <asm/irq.h>
  44. #include <asm/mv64x60.h>
  45. #include <asm/machdep.h>
  46. #define CPU_INTR_STR "gt64260 cpu interface error"
  47. #define PCI0_INTR_STR "gt64260 pci 0 error"
  48. #define PCI1_INTR_STR "gt64260 pci 1 error"
  49. /* ========================== forward declaration ========================== */
  50. static void gt64260_unmask_irq(unsigned int);
  51. static void gt64260_mask_irq(unsigned int);
  52. /* ========================== local declarations =========================== */
  53. struct hw_interrupt_type gt64260_pic = {
  54. .typename = " gt64260_pic ",
  55. .enable = gt64260_unmask_irq,
  56. .disable = gt64260_mask_irq,
  57. .ack = gt64260_mask_irq,
  58. .end = gt64260_unmask_irq,
  59. };
  60. u32 gt64260_irq_base = 0; /* GT64260 handles the next 96 IRQs from here */
  61. static struct mv64x60_handle bh;
  62. /* gt64260_init_irq()
  63. *
  64. * This function initializes the interrupt controller. It assigns
  65. * all interrupts from IRQ0 to IRQ95 to the gt64260 interrupt controller.
  66. *
  67. * Note:
  68. * We register all GPP inputs as interrupt source, but disable them.
  69. */
  70. void __init
  71. gt64260_init_irq(void)
  72. {
  73. int i;
  74. if (ppc_md.progress)
  75. ppc_md.progress("gt64260_init_irq: enter", 0x0);
  76. bh.v_base = mv64x60_get_bridge_vbase();
  77. ppc_cached_irq_mask[0] = 0;
  78. ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */
  79. ppc_cached_irq_mask[2] = 0;
  80. /* disable all interrupts and clear current interrupts */
  81. mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
  82. mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0);
  83. mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]);
  84. mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]);
  85. /* use the gt64260 for all (possible) interrupt sources */
  86. for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++)
  87. irq_desc[i].handler = &gt64260_pic;
  88. if (ppc_md.progress)
  89. ppc_md.progress("gt64260_init_irq: exit", 0x0);
  90. }
  91. /*
  92. * gt64260_get_irq()
  93. *
  94. * This function returns the lowest interrupt number of all interrupts that
  95. * are currently asserted.
  96. *
  97. * Input Variable(s):
  98. * struct pt_regs* not used
  99. *
  100. * Output Variable(s):
  101. * None.
  102. *
  103. * Returns:
  104. * int <interrupt number> or -2 (bogus interrupt)
  105. */
  106. int
  107. gt64260_get_irq(struct pt_regs *regs)
  108. {
  109. int irq;
  110. int irq_gpp;
  111. irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_LO);
  112. irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
  113. if (irq == -1) {
  114. irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_HI);
  115. irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]);
  116. if (irq == -1)
  117. irq = -2; /* bogus interrupt, should never happen */
  118. else {
  119. if (irq >= 24) {
  120. irq_gpp = mv64x60_read(&bh,
  121. MV64x60_GPP_INTR_CAUSE);
  122. irq_gpp = __ilog2(irq_gpp &
  123. ppc_cached_irq_mask[2]);
  124. if (irq_gpp == -1)
  125. irq = -2;
  126. else {
  127. irq = irq_gpp + 64;
  128. mv64x60_write(&bh,
  129. MV64x60_GPP_INTR_CAUSE,
  130. ~(1 << (irq - 64)));
  131. }
  132. } else
  133. irq += 32;
  134. }
  135. }
  136. (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
  137. if (irq < 0)
  138. return (irq);
  139. else
  140. return (gt64260_irq_base + irq);
  141. }
  142. /* gt64260_unmask_irq()
  143. *
  144. * This function enables an interrupt.
  145. *
  146. * Input Variable(s):
  147. * unsigned int interrupt number (IRQ0...IRQ95).
  148. *
  149. * Output Variable(s):
  150. * None.
  151. *
  152. * Returns:
  153. * void
  154. */
  155. static void
  156. gt64260_unmask_irq(unsigned int irq)
  157. {
  158. irq -= gt64260_irq_base;
  159. if (irq > 31)
  160. if (irq > 63) /* unmask GPP irq */
  161. mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
  162. ppc_cached_irq_mask[2] |= (1 << (irq - 64)));
  163. else /* mask high interrupt register */
  164. mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
  165. ppc_cached_irq_mask[1] |= (1 << (irq - 32)));
  166. else /* mask low interrupt register */
  167. mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
  168. ppc_cached_irq_mask[0] |= (1 << irq));
  169. (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
  170. return;
  171. }
  172. /* gt64260_mask_irq()
  173. *
  174. * This function disables the requested interrupt.
  175. *
  176. * Input Variable(s):
  177. * unsigned int interrupt number (IRQ0...IRQ95).
  178. *
  179. * Output Variable(s):
  180. * None.
  181. *
  182. * Returns:
  183. * void
  184. */
  185. static void
  186. gt64260_mask_irq(unsigned int irq)
  187. {
  188. irq -= gt64260_irq_base;
  189. if (irq > 31)
  190. if (irq > 63) /* mask GPP irq */
  191. mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
  192. ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
  193. else /* mask high interrupt register */
  194. mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
  195. ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
  196. else /* mask low interrupt register */
  197. mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
  198. ppc_cached_irq_mask[0] &= ~(1 << irq));
  199. (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
  200. return;
  201. }
  202. static irqreturn_t
  203. gt64260_cpu_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
  204. {
  205. printk(KERN_ERR "gt64260_cpu_error_int_handler: %s 0x%08x\n",
  206. "Error on CPU interface - Cause regiser",
  207. mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE));
  208. printk(KERN_ERR "\tCPU error register dump:\n");
  209. printk(KERN_ERR "\tAddress low 0x%08x\n",
  210. mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO));
  211. printk(KERN_ERR "\tAddress high 0x%08x\n",
  212. mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI));
  213. printk(KERN_ERR "\tData low 0x%08x\n",
  214. mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO));
  215. printk(KERN_ERR "\tData high 0x%08x\n",
  216. mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI));
  217. printk(KERN_ERR "\tParity 0x%08x\n",
  218. mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY));
  219. mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
  220. return IRQ_HANDLED;
  221. }
  222. static irqreturn_t
  223. gt64260_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
  224. {
  225. u32 val;
  226. unsigned int pci_bus = (unsigned int)dev_id;
  227. if (pci_bus == 0) { /* Error on PCI 0 */
  228. val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE);
  229. printk(KERN_ERR "%s: Error in PCI %d Interface\n",
  230. "gt64260_pci_error_int_handler", pci_bus);
  231. printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
  232. printk(KERN_ERR "\tCause register 0x%08x\n", val);
  233. printk(KERN_ERR "\tAddress Low 0x%08x\n",
  234. mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO));
  235. printk(KERN_ERR "\tAddress High 0x%08x\n",
  236. mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI));
  237. printk(KERN_ERR "\tAttribute 0x%08x\n",
  238. mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO));
  239. printk(KERN_ERR "\tCommand 0x%08x\n",
  240. mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD));
  241. mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val);
  242. }
  243. if (pci_bus == 1) { /* Error on PCI 1 */
  244. val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE);
  245. printk(KERN_ERR "%s: Error in PCI %d Interface\n",
  246. "gt64260_pci_error_int_handler", pci_bus);
  247. printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
  248. printk(KERN_ERR "\tCause register 0x%08x\n", val);
  249. printk(KERN_ERR "\tAddress Low 0x%08x\n",
  250. mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO));
  251. printk(KERN_ERR "\tAddress High 0x%08x\n",
  252. mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI));
  253. printk(KERN_ERR "\tAttribute 0x%08x\n",
  254. mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO));
  255. printk(KERN_ERR "\tCommand 0x%08x\n",
  256. mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD));
  257. mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val);
  258. }
  259. return IRQ_HANDLED;
  260. }
  261. static int __init
  262. gt64260_register_hdlrs(void)
  263. {
  264. int rc;
  265. /* Register CPU interface error interrupt handler */
  266. if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
  267. gt64260_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0)))
  268. printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
  269. mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
  270. mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe);
  271. /* Register PCI 0 error interrupt handler */
  272. if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler,
  273. SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
  274. printk(KERN_WARNING "Can't register pci 0 error handler: %d",
  275. rc);
  276. mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
  277. mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24);
  278. /* Register PCI 1 error interrupt handler */
  279. if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler,
  280. SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
  281. printk(KERN_WARNING "Can't register pci 1 error handler: %d",
  282. rc);
  283. mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
  284. mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24);
  285. return 0;
  286. }
  287. arch_initcall(gt64260_register_hdlrs);