chrp_pegasos_eth.c 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213
  1. /*
  2. * arch/ppc/platforms/chrp_pegasos_eth.c
  3. *
  4. * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
  5. * Thanks to :
  6. * Dale Farnsworth <dale@farnsworth.org>
  7. * Mark A. Greer <mgreer@mvista.com>
  8. * Nicolas DET <nd@bplan-gmbh.de>
  9. * Benjamin Herrenschmidt <benh@kernel.crashing.org>
  10. * And anyone else who helped me on this.
  11. */
  12. #include <linux/types.h>
  13. #include <linux/init.h>
  14. #include <linux/ioport.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mv643xx.h>
  17. #include <linux/pci.h>
  18. #define PEGASOS2_MARVELL_REGBASE (0xf1000000)
  19. #define PEGASOS2_MARVELL_REGSIZE (0x00004000)
  20. #define PEGASOS2_SRAM_BASE (0xf2000000)
  21. #define PEGASOS2_SRAM_SIZE (256*1024)
  22. #define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
  23. #define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
  24. #define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
  25. #define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
  26. #undef BE_VERBOSE
  27. static struct resource mv643xx_eth_shared_resources[] = {
  28. [0] = {
  29. .name = "ethernet shared base",
  30. .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
  31. .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
  32. MV643XX_ETH_SHARED_REGS_SIZE - 1,
  33. .flags = IORESOURCE_MEM,
  34. },
  35. };
  36. static struct platform_device mv643xx_eth_shared_device = {
  37. .name = MV643XX_ETH_SHARED_NAME,
  38. .id = 0,
  39. .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
  40. .resource = mv643xx_eth_shared_resources,
  41. };
  42. static struct resource mv643xx_eth0_resources[] = {
  43. [0] = {
  44. .name = "eth0 irq",
  45. .start = 9,
  46. .end = 9,
  47. .flags = IORESOURCE_IRQ,
  48. },
  49. };
  50. static struct mv643xx_eth_platform_data eth0_pd = {
  51. .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
  52. .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
  53. .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
  54. .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE,
  55. .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
  56. .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
  57. };
  58. static struct platform_device eth0_device = {
  59. .name = MV643XX_ETH_NAME,
  60. .id = 0,
  61. .num_resources = ARRAY_SIZE(mv643xx_eth0_resources),
  62. .resource = mv643xx_eth0_resources,
  63. .dev = {
  64. .platform_data = &eth0_pd,
  65. },
  66. };
  67. static struct resource mv643xx_eth1_resources[] = {
  68. [0] = {
  69. .name = "eth1 irq",
  70. .start = 9,
  71. .end = 9,
  72. .flags = IORESOURCE_IRQ,
  73. },
  74. };
  75. static struct mv643xx_eth_platform_data eth1_pd = {
  76. .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
  77. .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
  78. .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
  79. .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
  80. .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
  81. .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
  82. };
  83. static struct platform_device eth1_device = {
  84. .name = MV643XX_ETH_NAME,
  85. .id = 1,
  86. .num_resources = ARRAY_SIZE(mv643xx_eth1_resources),
  87. .resource = mv643xx_eth1_resources,
  88. .dev = {
  89. .platform_data = &eth1_pd,
  90. },
  91. };
  92. static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
  93. &mv643xx_eth_shared_device,
  94. &eth0_device,
  95. &eth1_device,
  96. };
  97. /***********/
  98. /***********/
  99. #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
  100. #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
  101. static void __iomem *mv643xx_reg_base;
  102. static int Enable_SRAM(void)
  103. {
  104. u32 ALong;
  105. if (mv643xx_reg_base == NULL)
  106. mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
  107. PEGASOS2_MARVELL_REGSIZE);
  108. if (mv643xx_reg_base == NULL)
  109. return -ENOMEM;
  110. #ifdef BE_VERBOSE
  111. printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
  112. (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
  113. #endif
  114. MV_WRITE(MV64340_SRAM_CONFIG, 0);
  115. MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
  116. MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
  117. ALong &= ~(1 << 19);
  118. MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
  119. ALong = 0x02;
  120. ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
  121. MV_WRITE(MV643XX_ETH_BAR_4, ALong);
  122. MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
  123. MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
  124. ALong &= ~(1 << 4);
  125. MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
  126. #ifdef BE_VERBOSE
  127. printk("Pegasos II/Marvell MV64361: register unmapped\n");
  128. printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
  129. #endif
  130. iounmap(mv643xx_reg_base);
  131. mv643xx_reg_base = NULL;
  132. return 1;
  133. }
  134. /***********/
  135. /***********/
  136. int mv643xx_eth_add_pds(void)
  137. {
  138. int ret = 0;
  139. static struct pci_device_id pci_marvell_mv64360[] = {
  140. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
  141. { }
  142. };
  143. #ifdef BE_VERBOSE
  144. printk("Pegasos II/Marvell MV64361: init\n");
  145. #endif
  146. if (pci_dev_present(pci_marvell_mv64360)) {
  147. ret = platform_add_devices(mv643xx_eth_pd_devs,
  148. ARRAY_SIZE(mv643xx_eth_pd_devs));
  149. if ( Enable_SRAM() < 0)
  150. {
  151. eth0_pd.tx_sram_addr = 0;
  152. eth0_pd.tx_sram_size = 0;
  153. eth0_pd.rx_sram_addr = 0;
  154. eth0_pd.rx_sram_size = 0;
  155. eth1_pd.tx_sram_addr = 0;
  156. eth1_pd.tx_sram_size = 0;
  157. eth1_pd.rx_sram_addr = 0;
  158. eth1_pd.rx_sram_size = 0;
  159. #ifdef BE_VERBOSE
  160. printk("Pegasos II/Marvell MV64361: Can't enable the "
  161. "SRAM\n");
  162. #endif
  163. }
  164. }
  165. #ifdef BE_VERBOSE
  166. printk("Pegasos II/Marvell MV64361: init is over\n");
  167. #endif
  168. return ret;
  169. }
  170. device_initcall(mv643xx_eth_add_pds);