pci.c 2.5 KB

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  1. /*
  2. * FSL SoC setup code
  3. *
  4. * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/config.h>
  12. #include <linux/stddef.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/errno.h>
  16. #include <linux/pci.h>
  17. #include <linux/delay.h>
  18. #include <linux/irq.h>
  19. #include <linux/module.h>
  20. #include <asm/system.h>
  21. #include <asm/atomic.h>
  22. #include <asm/io.h>
  23. #include <asm/pci-bridge.h>
  24. #include <asm/prom.h>
  25. #include <sysdev/fsl_soc.h>
  26. #undef DEBUG
  27. #ifdef DEBUG
  28. #define DBG(x...) printk(x)
  29. #else
  30. #define DBG(x...)
  31. #endif
  32. int mpc83xx_pci2_busno;
  33. #ifdef CONFIG_PCI
  34. int __init add_bridge(struct device_node *dev)
  35. {
  36. int len;
  37. struct pci_controller *hose;
  38. struct resource rsrc;
  39. int *bus_range;
  40. int primary = 1, has_address = 0;
  41. phys_addr_t immr = get_immrbase();
  42. DBG("Adding PCI host bridge %s\n", dev->full_name);
  43. /* Fetch host bridge registers address */
  44. has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
  45. /* Get bus range if any */
  46. bus_range = (int *) get_property(dev, "bus-range", &len);
  47. if (bus_range == NULL || len < 2 * sizeof(int)) {
  48. printk(KERN_WARNING "Can't get bus-range for %s, assume"
  49. " bus 0\n", dev->full_name);
  50. }
  51. hose = pcibios_alloc_controller();
  52. if (!hose)
  53. return -ENOMEM;
  54. hose->arch_data = dev;
  55. hose->set_cfg_type = 1;
  56. hose->first_busno = bus_range ? bus_range[0] : 0;
  57. hose->last_busno = bus_range ? bus_range[1] : 0xff;
  58. /* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
  59. * the other at 0x8600, we consider the 0x8500 the primary controller
  60. */
  61. /* PCI 1 */
  62. if ((rsrc.start & 0xfffff) == 0x8500) {
  63. setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304);
  64. }
  65. /* PCI 2*/
  66. if ((rsrc.start & 0xfffff) == 0x8600) {
  67. setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384);
  68. primary = 0;
  69. hose->bus_offset = hose->first_busno;
  70. mpc83xx_pci2_busno = hose->first_busno;
  71. }
  72. printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%08lx. "
  73. "Firmware bus number: %d->%d\n",
  74. rsrc.start, hose->first_busno, hose->last_busno);
  75. DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
  76. hose, hose->cfg_addr, hose->cfg_data);
  77. /* Interpret the "ranges" property */
  78. /* This also maps the I/O region and sets isa_io/mem_base */
  79. pci_process_bridge_OF_ranges(hose, dev, primary);
  80. return 0;
  81. }
  82. #endif