ip22-eisa.c 6.5 KB

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  1. /*
  2. * Basic EISA bus support for the SGI Indigo-2.
  3. *
  4. * (C) 2002 Pascal Dameme <netinet@freesurf.fr>
  5. * and Marc Zyngier <mzyngier@freesurf.fr>
  6. *
  7. * This code is released under both the GPL version 2 and BSD
  8. * licenses. Either license may be used.
  9. *
  10. * This code offers a very basic support for this EISA bus present in
  11. * the SGI Indigo-2. It currently only supports PIO (forget about DMA
  12. * for the time being). This is enough for a low-end ethernet card,
  13. * but forget about your favorite SCSI card...
  14. *
  15. * TODO :
  16. * - Fix bugs...
  17. * - Add ISA support
  18. * - Add DMA (yeah, right...).
  19. * - Fix more bugs.
  20. */
  21. #include <linux/config.h>
  22. #include <linux/eisa.h>
  23. #include <linux/types.h>
  24. #include <linux/init.h>
  25. #include <linux/irq.h>
  26. #include <linux/kernel_stat.h>
  27. #include <linux/signal.h>
  28. #include <linux/sched.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/delay.h>
  31. #include <asm/io.h>
  32. #include <asm/irq.h>
  33. #include <asm/mipsregs.h>
  34. #include <asm/addrspace.h>
  35. #include <asm/processor.h>
  36. #include <asm/sgi/ioc.h>
  37. #include <asm/sgi/mc.h>
  38. #include <asm/sgi/ip22.h>
  39. /* I2 has four EISA slots. */
  40. #define IP22_EISA_MAX_SLOTS 4
  41. #define EISA_MAX_IRQ 16
  42. #define EIU_MODE_REG 0x0001ffc0
  43. #define EIU_STAT_REG 0x0001ffc4
  44. #define EIU_PREMPT_REG 0x0001ffc8
  45. #define EIU_QUIET_REG 0x0001ffcc
  46. #define EIU_INTRPT_ACK 0x00010004
  47. static char __init *decode_eisa_sig(unsigned long addr)
  48. {
  49. static char sig_str[EISA_SIG_LEN];
  50. u8 sig[4];
  51. u16 rev;
  52. int i;
  53. for (i = 0; i < 4; i++) {
  54. sig[i] = inb (addr + i);
  55. if (!i && (sig[0] & 0x80))
  56. return NULL;
  57. }
  58. sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1);
  59. sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1);
  60. sig_str[2] = (sig[1] & 0x1f) + ('A' - 1);
  61. rev = (sig[2] << 8) | sig[3];
  62. sprintf(sig_str + 3, "%04X", rev);
  63. return sig_str;
  64. }
  65. static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs)
  66. {
  67. u8 eisa_irq;
  68. u8 dma1, dma2;
  69. eisa_irq = inb(EIU_INTRPT_ACK);
  70. dma1 = inb(EISA_DMA1_STATUS);
  71. dma2 = inb(EISA_DMA2_STATUS);
  72. if (eisa_irq < EISA_MAX_IRQ) {
  73. do_IRQ(eisa_irq, regs);
  74. return IRQ_HANDLED;
  75. }
  76. /* Oops, Bad Stuff Happened... */
  77. printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);
  78. outb(0x20, EISA_INT2_CTRL);
  79. outb(0x20, EISA_INT1_CTRL);
  80. return IRQ_NONE;
  81. }
  82. static void enable_eisa1_irq(unsigned int irq)
  83. {
  84. unsigned long flags;
  85. u8 mask;
  86. local_irq_save(flags);
  87. mask = inb(EISA_INT1_MASK);
  88. mask &= ~((u8) (1 << irq));
  89. outb(mask, EISA_INT1_MASK);
  90. local_irq_restore(flags);
  91. }
  92. static unsigned int startup_eisa1_irq(unsigned int irq)
  93. {
  94. u8 edge;
  95. /* Only use edge interrupts for EISA */
  96. edge = inb(EISA_INT1_EDGE_LEVEL);
  97. edge &= ~((u8) (1 << irq));
  98. outb(edge, EISA_INT1_EDGE_LEVEL);
  99. enable_eisa1_irq(irq);
  100. return 0;
  101. }
  102. static void disable_eisa1_irq(unsigned int irq)
  103. {
  104. u8 mask;
  105. mask = inb(EISA_INT1_MASK);
  106. mask |= ((u8) (1 << irq));
  107. outb(mask, EISA_INT1_MASK);
  108. }
  109. #define shutdown_eisa1_irq disable_eisa1_irq
  110. static void mask_and_ack_eisa1_irq(unsigned int irq)
  111. {
  112. disable_eisa1_irq(irq);
  113. outb(0x20, EISA_INT1_CTRL);
  114. }
  115. static void end_eisa1_irq(unsigned int irq)
  116. {
  117. if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  118. enable_eisa1_irq(irq);
  119. }
  120. static struct hw_interrupt_type ip22_eisa1_irq_type = {
  121. .typename = "IP22 EISA",
  122. .startup = startup_eisa1_irq,
  123. .shutdown = shutdown_eisa1_irq,
  124. .enable = enable_eisa1_irq,
  125. .disable = disable_eisa1_irq,
  126. .ack = mask_and_ack_eisa1_irq,
  127. .end = end_eisa1_irq,
  128. };
  129. static void enable_eisa2_irq(unsigned int irq)
  130. {
  131. unsigned long flags;
  132. u8 mask;
  133. local_irq_save(flags);
  134. mask = inb(EISA_INT2_MASK);
  135. mask &= ~((u8) (1 << (irq - 8)));
  136. outb(mask, EISA_INT2_MASK);
  137. local_irq_restore(flags);
  138. }
  139. static unsigned int startup_eisa2_irq(unsigned int irq)
  140. {
  141. u8 edge;
  142. /* Only use edge interrupts for EISA */
  143. edge = inb(EISA_INT2_EDGE_LEVEL);
  144. edge &= ~((u8) (1 << (irq - 8)));
  145. outb(edge, EISA_INT2_EDGE_LEVEL);
  146. enable_eisa2_irq(irq);
  147. return 0;
  148. }
  149. static void disable_eisa2_irq(unsigned int irq)
  150. {
  151. u8 mask;
  152. mask = inb(EISA_INT2_MASK);
  153. mask |= ((u8) (1 << (irq - 8)));
  154. outb(mask, EISA_INT2_MASK);
  155. }
  156. #define shutdown_eisa2_irq disable_eisa2_irq
  157. static void mask_and_ack_eisa2_irq(unsigned int irq)
  158. {
  159. disable_eisa2_irq(irq);
  160. outb(0x20, EISA_INT2_CTRL);
  161. }
  162. static void end_eisa2_irq(unsigned int irq)
  163. {
  164. if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  165. enable_eisa2_irq(irq);
  166. }
  167. static struct hw_interrupt_type ip22_eisa2_irq_type = {
  168. .typename = "IP22 EISA",
  169. .startup = startup_eisa2_irq,
  170. .shutdown = shutdown_eisa2_irq,
  171. .enable = enable_eisa2_irq,
  172. .disable = disable_eisa2_irq,
  173. .ack = mask_and_ack_eisa2_irq,
  174. .end = end_eisa2_irq,
  175. };
  176. static struct irqaction eisa_action = {
  177. .handler = ip22_eisa_intr,
  178. .name = "EISA",
  179. };
  180. static struct irqaction cascade_action = {
  181. .handler = no_action,
  182. .name = "EISA cascade",
  183. };
  184. int __init ip22_eisa_init(void)
  185. {
  186. int i, c;
  187. char *str;
  188. if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
  189. printk(KERN_INFO "EISA: bus not present.\n");
  190. return 1;
  191. }
  192. printk(KERN_INFO "EISA: Probing bus...\n");
  193. for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) {
  194. if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) {
  195. printk(KERN_INFO "EISA: slot %d : %s detected.\n",
  196. i, str);
  197. c++;
  198. }
  199. }
  200. printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s");
  201. #ifdef CONFIG_ISA
  202. printk(KERN_INFO "ISA support compiled in.\n");
  203. #endif
  204. /* Warning : BlackMagicAhead(tm).
  205. Please wave your favorite dead chicken over the busses */
  206. /* First say hello to the EIU */
  207. outl(0x0000FFFF, EIU_PREMPT_REG);
  208. outl(1, EIU_QUIET_REG);
  209. outl(0x40f3c07F, EIU_MODE_REG);
  210. /* Now be nice to the EISA chipset */
  211. outb(1, EISA_EXT_NMI_RESET_CTRL);
  212. udelay(50); /* Wait long enough for the dust to settle */
  213. outb(0, EISA_EXT_NMI_RESET_CTRL);
  214. outb(0x11, EISA_INT1_CTRL);
  215. outb(0x11, EISA_INT2_CTRL);
  216. outb(0, EISA_INT1_MASK);
  217. outb(8, EISA_INT2_MASK);
  218. outb(4, EISA_INT1_MASK);
  219. outb(2, EISA_INT2_MASK);
  220. outb(1, EISA_INT1_MASK);
  221. outb(1, EISA_INT2_MASK);
  222. outb(0xfb, EISA_INT1_MASK);
  223. outb(0xff, EISA_INT2_MASK);
  224. outb(0, EISA_DMA2_WRITE_SINGLE);
  225. for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
  226. irq_desc[i].status = IRQ_DISABLED;
  227. irq_desc[i].action = 0;
  228. irq_desc[i].depth = 1;
  229. if (i < (SGINT_EISA + 8))
  230. irq_desc[i].handler = &ip22_eisa1_irq_type;
  231. else
  232. irq_desc[i].handler = &ip22_eisa2_irq_type;
  233. }
  234. /* Cannot use request_irq because of kmalloc not being ready at such
  235. * an early stage. Yes, I've been bitten... */
  236. setup_irq(SGI_EISA_IRQ, &eisa_action);
  237. setup_irq(SGINT_EISA + 2, &cascade_action);
  238. EISA_bus = 1;
  239. return 0;
  240. }