bios32.c 11 KB

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  1. /*
  2. * bios32.c - PCI BIOS functions for m68k systems.
  3. *
  4. * Written by Wout Klaren.
  5. *
  6. * Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger.
  7. */
  8. #include <linux/config.h>
  9. #include <linux/init.h>
  10. #include <linux/kernel.h>
  11. #if 0
  12. # define DBG_DEVS(args) printk args
  13. #else
  14. # define DBG_DEVS(args)
  15. #endif
  16. #ifdef CONFIG_PCI
  17. /*
  18. * PCI support for Linux/m68k. Currently only the Hades is supported.
  19. *
  20. * The support for PCI bridges in the DEC Alpha version has
  21. * been removed in this version.
  22. */
  23. #include <linux/pci.h>
  24. #include <linux/slab.h>
  25. #include <linux/mm.h>
  26. #include <asm/io.h>
  27. #include <asm/pci.h>
  28. #include <asm/uaccess.h>
  29. #define KB 1024
  30. #define MB (1024*KB)
  31. #define GB (1024*MB)
  32. #define MAJOR_REV 0
  33. #define MINOR_REV 5
  34. /*
  35. * Align VAL to ALIGN, which must be a power of two.
  36. */
  37. #define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
  38. /*
  39. * Offsets relative to the I/O and memory base addresses from where resources
  40. * are allocated.
  41. */
  42. #define IO_ALLOC_OFFSET 0x00004000
  43. #define MEM_ALLOC_OFFSET 0x04000000
  44. /*
  45. * Declarations of hardware specific initialisation functions.
  46. */
  47. extern struct pci_bus_info *init_hades_pci(void);
  48. /*
  49. * Bus info structure of the PCI bus. A pointer to this structure is
  50. * put in the sysdata member of the pci_bus structure.
  51. */
  52. static struct pci_bus_info *bus_info;
  53. static int pci_modify = 1; /* If set, layout the PCI bus ourself. */
  54. static int skip_vga; /* If set do not modify base addresses
  55. of vga cards.*/
  56. static int disable_pci_burst; /* If set do not allow PCI bursts. */
  57. static unsigned int io_base;
  58. static unsigned int mem_base;
  59. /*
  60. * static void disable_dev(struct pci_dev *dev)
  61. *
  62. * Disable PCI device DEV so that it does not respond to I/O or memory
  63. * accesses.
  64. *
  65. * Parameters:
  66. *
  67. * dev - device to disable.
  68. */
  69. static void __init disable_dev(struct pci_dev *dev)
  70. {
  71. unsigned short cmd;
  72. if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
  73. (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
  74. (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
  75. return;
  76. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  77. cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
  78. pci_write_config_word(dev, PCI_COMMAND, cmd);
  79. }
  80. /*
  81. * static void layout_dev(struct pci_dev *dev)
  82. *
  83. * Layout memory and I/O for a device.
  84. *
  85. * Parameters:
  86. *
  87. * device - device to layout memory and I/O for.
  88. */
  89. static void __init layout_dev(struct pci_dev *dev)
  90. {
  91. unsigned short cmd;
  92. unsigned int base, mask, size, reg;
  93. unsigned int alignto;
  94. int i;
  95. /*
  96. * Skip video cards if requested.
  97. */
  98. if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
  99. (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
  100. (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
  101. return;
  102. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  103. for (reg = PCI_BASE_ADDRESS_0, i = 0; reg <= PCI_BASE_ADDRESS_5; reg += 4, i++)
  104. {
  105. /*
  106. * Figure out how much space and of what type this
  107. * device wants.
  108. */
  109. pci_write_config_dword(dev, reg, 0xffffffff);
  110. pci_read_config_dword(dev, reg, &base);
  111. if (!base)
  112. {
  113. /* this base-address register is unused */
  114. dev->resource[i].start = 0;
  115. dev->resource[i].end = 0;
  116. dev->resource[i].flags = 0;
  117. continue;
  118. }
  119. /*
  120. * We've read the base address register back after
  121. * writing all ones and so now we must decode it.
  122. */
  123. if (base & PCI_BASE_ADDRESS_SPACE_IO)
  124. {
  125. /*
  126. * I/O space base address register.
  127. */
  128. cmd |= PCI_COMMAND_IO;
  129. base &= PCI_BASE_ADDRESS_IO_MASK;
  130. mask = (~base << 1) | 0x1;
  131. size = (mask & base) & 0xffffffff;
  132. /*
  133. * Align to multiple of size of minimum base.
  134. */
  135. alignto = max_t(unsigned int, 0x040, size);
  136. base = ALIGN(io_base, alignto);
  137. io_base = base + size;
  138. pci_write_config_dword(dev, reg, base | PCI_BASE_ADDRESS_SPACE_IO);
  139. dev->resource[i].start = base;
  140. dev->resource[i].end = dev->resource[i].start + size - 1;
  141. dev->resource[i].flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
  142. DBG_DEVS(("layout_dev: IO address: %lX\n", base));
  143. }
  144. else
  145. {
  146. unsigned int type;
  147. /*
  148. * Memory space base address register.
  149. */
  150. cmd |= PCI_COMMAND_MEMORY;
  151. type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  152. base &= PCI_BASE_ADDRESS_MEM_MASK;
  153. mask = (~base << 1) | 0x1;
  154. size = (mask & base) & 0xffffffff;
  155. switch (type)
  156. {
  157. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  158. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  159. break;
  160. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  161. printk("bios32 WARNING: slot %d, function %d "
  162. "requests memory below 1MB---don't "
  163. "know how to do that.\n",
  164. PCI_SLOT(dev->devfn),
  165. PCI_FUNC(dev->devfn));
  166. continue;
  167. }
  168. /*
  169. * Align to multiple of size of minimum base.
  170. */
  171. alignto = max_t(unsigned int, 0x1000, size);
  172. base = ALIGN(mem_base, alignto);
  173. mem_base = base + size;
  174. pci_write_config_dword(dev, reg, base);
  175. dev->resource[i].start = base;
  176. dev->resource[i].end = dev->resource[i].start + size - 1;
  177. dev->resource[i].flags = IORESOURCE_MEM;
  178. if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
  179. {
  180. /*
  181. * 64-bit address, set the highest 32 bits
  182. * to zero.
  183. */
  184. reg += 4;
  185. pci_write_config_dword(dev, reg, 0);
  186. i++;
  187. dev->resource[i].start = 0;
  188. dev->resource[i].end = 0;
  189. dev->resource[i].flags = 0;
  190. }
  191. }
  192. }
  193. /*
  194. * Enable device:
  195. */
  196. if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
  197. dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
  198. dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
  199. dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
  200. {
  201. /*
  202. * All of these (may) have I/O scattered all around
  203. * and may not use i/o-base address registers at all.
  204. * So we just have to always enable I/O to these
  205. * devices.
  206. */
  207. cmd |= PCI_COMMAND_IO;
  208. }
  209. pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
  210. pci_write_config_byte(dev, PCI_LATENCY_TIMER, (disable_pci_burst) ? 0 : 32);
  211. if (bus_info != NULL)
  212. bus_info->conf_device(dev); /* Machine dependent configuration. */
  213. DBG_DEVS(("layout_dev: bus %d slot 0x%x VID 0x%x DID 0x%x class 0x%x\n",
  214. dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device, dev->class));
  215. }
  216. /*
  217. * static void layout_bus(struct pci_bus *bus)
  218. *
  219. * Layout memory and I/O for all devices on the given bus.
  220. *
  221. * Parameters:
  222. *
  223. * bus - bus.
  224. */
  225. static void __init layout_bus(struct pci_bus *bus)
  226. {
  227. unsigned int bio, bmem;
  228. struct pci_dev *dev;
  229. DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
  230. if (!bus->devices && !bus->children)
  231. return;
  232. /*
  233. * Align the current bases on appropriate boundaries (4K for
  234. * IO and 1MB for memory).
  235. */
  236. bio = io_base = ALIGN(io_base, 4*KB);
  237. bmem = mem_base = ALIGN(mem_base, 1*MB);
  238. /*
  239. * PCI devices might have been setup by a PCI BIOS emulation
  240. * running under TOS. In these cases there is a
  241. * window during which two devices may have an overlapping
  242. * address range. To avoid this causing trouble, we first
  243. * turn off the I/O and memory address decoders for all PCI
  244. * devices. They'll be re-enabled only once all address
  245. * decoders are programmed consistently.
  246. */
  247. DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number));
  248. for (dev = bus->devices; dev; dev = dev->sibling)
  249. {
  250. if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
  251. (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
  252. disable_dev(dev);
  253. }
  254. /*
  255. * Allocate space to each device:
  256. */
  257. DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
  258. for (dev = bus->devices; dev; dev = dev->sibling)
  259. {
  260. if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
  261. (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
  262. layout_dev(dev);
  263. }
  264. DBG_DEVS(("layout_bus: bus %d finished\n", bus->number));
  265. }
  266. /*
  267. * static void pcibios_fixup(void)
  268. *
  269. * Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is
  270. * true. This might be necessary because not every m68k machine with a PCI
  271. * bus has a PCI BIOS. This function should be called right after
  272. * pci_scan_bus() in pcibios_init().
  273. */
  274. static void __init pcibios_fixup(void)
  275. {
  276. if (pci_modify)
  277. {
  278. /*
  279. * Set base addresses for allocation of I/O and memory space.
  280. */
  281. io_base = bus_info->io_space.start + IO_ALLOC_OFFSET;
  282. mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET;
  283. /*
  284. * Scan the tree, allocating PCI memory and I/O space.
  285. */
  286. layout_bus(pci_bus_b(pci_root.next));
  287. }
  288. /*
  289. * Fix interrupt assignments, etc.
  290. */
  291. bus_info->fixup(pci_modify);
  292. }
  293. /*
  294. * static void pcibios_claim_resources(struct pci_bus *bus)
  295. *
  296. * Claim all resources that are assigned to devices on the given bus.
  297. *
  298. * Parameters:
  299. *
  300. * bus - bus.
  301. */
  302. static void __init pcibios_claim_resources(struct pci_bus *bus)
  303. {
  304. struct pci_dev *dev;
  305. int i;
  306. while (bus)
  307. {
  308. for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
  309. {
  310. for (i = 0; i < PCI_NUM_RESOURCES; i++)
  311. {
  312. struct resource *r = &dev->resource[i];
  313. struct resource *pr;
  314. struct pci_bus_info *bus_info = (struct pci_bus_info *) dev->sysdata;
  315. if ((r->start == 0) || (r->parent != NULL))
  316. continue;
  317. #if 1
  318. if (r->flags & IORESOURCE_IO)
  319. pr = &bus_info->io_space;
  320. else
  321. pr = &bus_info->mem_space;
  322. #else
  323. if (r->flags & IORESOURCE_IO)
  324. pr = &ioport_resource;
  325. else
  326. pr = &iomem_resource;
  327. #endif
  328. if (request_resource(pr, r) < 0)
  329. {
  330. printk(KERN_ERR "PCI: Address space collision on region %d of device %s\n", i, dev->name);
  331. }
  332. }
  333. }
  334. if (bus->children)
  335. pcibios_claim_resources(bus->children);
  336. bus = bus->next;
  337. }
  338. }
  339. /*
  340. * int pcibios_assign_resource(struct pci_dev *dev, int i)
  341. *
  342. * Assign a new address to a PCI resource.
  343. *
  344. * Parameters:
  345. *
  346. * dev - device.
  347. * i - resource.
  348. *
  349. * Result: 0 if successful.
  350. */
  351. int __init pcibios_assign_resource(struct pci_dev *dev, int i)
  352. {
  353. struct resource *r = &dev->resource[i];
  354. struct resource *pr = pci_find_parent_resource(dev, r);
  355. unsigned long size = r->end + 1;
  356. if (!pr)
  357. return -EINVAL;
  358. if (r->flags & IORESOURCE_IO)
  359. {
  360. if (size > 0x100)
  361. return -EFBIG;
  362. if (allocate_resource(pr, r, size, bus_info->io_space.start +
  363. IO_ALLOC_OFFSET, bus_info->io_space.end, 1024))
  364. return -EBUSY;
  365. }
  366. else
  367. {
  368. if (allocate_resource(pr, r, size, bus_info->mem_space.start +
  369. MEM_ALLOC_OFFSET, bus_info->mem_space.end, size))
  370. return -EBUSY;
  371. }
  372. if (i < 6)
  373. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, r->start);
  374. return 0;
  375. }
  376. void __init pcibios_fixup_bus(struct pci_bus *bus)
  377. {
  378. struct pci_dev *dev;
  379. void *sysdata;
  380. sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata;
  381. for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
  382. dev->sysdata = sysdata;
  383. }
  384. void __init pcibios_init(void)
  385. {
  386. printk("Linux/m68k PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
  387. bus_info = NULL;
  388. #ifdef CONFIG_HADES
  389. if (MACH_IS_HADES)
  390. bus_info = init_hades_pci();
  391. #endif
  392. if (bus_info != NULL)
  393. {
  394. printk("PCI: Probing PCI hardware\n");
  395. pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info);
  396. pcibios_fixup();
  397. pcibios_claim_resources(pci_root);
  398. }
  399. else
  400. printk("PCI: No PCI bus detected\n");
  401. }
  402. char * __init pcibios_setup(char *str)
  403. {
  404. if (!strcmp(str, "nomodify"))
  405. {
  406. pci_modify = 0;
  407. return NULL;
  408. }
  409. else if (!strcmp(str, "skipvga"))
  410. {
  411. skip_vga = 1;
  412. return NULL;
  413. }
  414. else if (!strcmp(str, "noburst"))
  415. {
  416. disable_pci_burst = 1;
  417. return NULL;
  418. }
  419. return str;
  420. }
  421. #endif /* CONFIG_PCI */