bte.c 13 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved.
  7. */
  8. #include <linux/config.h>
  9. #include <linux/module.h>
  10. #include <asm/sn/nodepda.h>
  11. #include <asm/sn/addrs.h>
  12. #include <asm/sn/arch.h>
  13. #include <asm/sn/sn_cpuid.h>
  14. #include <asm/sn/pda.h>
  15. #include <asm/sn/shubio.h>
  16. #include <asm/nodedata.h>
  17. #include <asm/delay.h>
  18. #include <linux/bootmem.h>
  19. #include <linux/string.h>
  20. #include <linux/sched.h>
  21. #include <asm/sn/bte.h>
  22. #ifndef L1_CACHE_MASK
  23. #define L1_CACHE_MASK (L1_CACHE_BYTES - 1)
  24. #endif
  25. /* two interfaces on two btes */
  26. #define MAX_INTERFACES_TO_TRY 4
  27. #define MAX_NODES_TO_TRY 2
  28. static struct bteinfo_s *bte_if_on_node(nasid_t nasid, int interface)
  29. {
  30. nodepda_t *tmp_nodepda;
  31. if (nasid_to_cnodeid(nasid) == -1)
  32. return (struct bteinfo_s *)NULL;;
  33. tmp_nodepda = NODEPDA(nasid_to_cnodeid(nasid));
  34. return &tmp_nodepda->bte_if[interface];
  35. }
  36. static inline void bte_start_transfer(struct bteinfo_s *bte, u64 len, u64 mode)
  37. {
  38. if (is_shub2()) {
  39. BTE_CTRL_STORE(bte, (IBLS_BUSY | ((len) | (mode) << 24)));
  40. } else {
  41. BTE_LNSTAT_STORE(bte, len);
  42. BTE_CTRL_STORE(bte, mode);
  43. }
  44. }
  45. /************************************************************************
  46. * Block Transfer Engine copy related functions.
  47. *
  48. ***********************************************************************/
  49. /*
  50. * bte_copy(src, dest, len, mode, notification)
  51. *
  52. * Use the block transfer engine to move kernel memory from src to dest
  53. * using the assigned mode.
  54. *
  55. * Paramaters:
  56. * src - physical address of the transfer source.
  57. * dest - physical address of the transfer destination.
  58. * len - number of bytes to transfer from source to dest.
  59. * mode - hardware defined. See reference information
  60. * for IBCT0/1 in the SHUB Programmers Reference
  61. * notification - kernel virtual address of the notification cache
  62. * line. If NULL, the default is used and
  63. * the bte_copy is synchronous.
  64. *
  65. * NOTE: This function requires src, dest, and len to
  66. * be cacheline aligned.
  67. */
  68. bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
  69. {
  70. u64 transfer_size;
  71. u64 transfer_stat;
  72. u64 notif_phys_addr;
  73. struct bteinfo_s *bte;
  74. bte_result_t bte_status;
  75. unsigned long irq_flags;
  76. unsigned long itc_end = 0;
  77. int nasid_to_try[MAX_NODES_TO_TRY];
  78. int my_nasid = cpuid_to_nasid(raw_smp_processor_id());
  79. int bte_if_index, nasid_index;
  80. int bte_first, btes_per_node = BTES_PER_NODE;
  81. BTE_PRINTK(("bte_copy(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%p)\n",
  82. src, dest, len, mode, notification));
  83. if (len == 0) {
  84. return BTE_SUCCESS;
  85. }
  86. BUG_ON((len & L1_CACHE_MASK) ||
  87. (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK));
  88. BUG_ON(!(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT)));
  89. /*
  90. * Start with interface corresponding to cpu number
  91. */
  92. bte_first = raw_smp_processor_id() % btes_per_node;
  93. if (mode & BTE_USE_DEST) {
  94. /* try remote then local */
  95. nasid_to_try[0] = NASID_GET(dest);
  96. if (mode & BTE_USE_ANY) {
  97. nasid_to_try[1] = my_nasid;
  98. } else {
  99. nasid_to_try[1] = (int)NULL;
  100. }
  101. } else {
  102. /* try local then remote */
  103. nasid_to_try[0] = my_nasid;
  104. if (mode & BTE_USE_ANY) {
  105. nasid_to_try[1] = NASID_GET(dest);
  106. } else {
  107. nasid_to_try[1] = (int)NULL;
  108. }
  109. }
  110. retry_bteop:
  111. do {
  112. local_irq_save(irq_flags);
  113. bte_if_index = bte_first;
  114. nasid_index = 0;
  115. /* Attempt to lock one of the BTE interfaces. */
  116. while (nasid_index < MAX_NODES_TO_TRY) {
  117. bte = bte_if_on_node(nasid_to_try[nasid_index],bte_if_index);
  118. if (bte == NULL) {
  119. nasid_index++;
  120. continue;
  121. }
  122. if (spin_trylock(&bte->spinlock)) {
  123. if (!(*bte->most_rcnt_na & BTE_WORD_AVAILABLE) ||
  124. (BTE_LNSTAT_LOAD(bte) & BTE_ACTIVE)) {
  125. /* Got the lock but BTE still busy */
  126. spin_unlock(&bte->spinlock);
  127. } else {
  128. /* we got the lock and it's not busy */
  129. break;
  130. }
  131. }
  132. bte_if_index = (bte_if_index + 1) % btes_per_node; /* Next interface */
  133. if (bte_if_index == bte_first) {
  134. /*
  135. * We've tried all interfaces on this node
  136. */
  137. nasid_index++;
  138. }
  139. bte = NULL;
  140. }
  141. if (bte != NULL) {
  142. break;
  143. }
  144. local_irq_restore(irq_flags);
  145. if (!(mode & BTE_WACQUIRE)) {
  146. return BTEFAIL_NOTAVAIL;
  147. }
  148. } while (1);
  149. if (notification == NULL) {
  150. /* User does not want to be notified. */
  151. bte->most_rcnt_na = &bte->notify;
  152. } else {
  153. bte->most_rcnt_na = notification;
  154. }
  155. /* Calculate the number of cache lines to transfer. */
  156. transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK);
  157. /* Initialize the notification to a known value. */
  158. *bte->most_rcnt_na = BTE_WORD_BUSY;
  159. notif_phys_addr = TO_PHYS(ia64_tpa((unsigned long)bte->most_rcnt_na));
  160. if (is_shub2()) {
  161. src = SH2_TIO_PHYS_TO_DMA(src);
  162. dest = SH2_TIO_PHYS_TO_DMA(dest);
  163. notif_phys_addr = SH2_TIO_PHYS_TO_DMA(notif_phys_addr);
  164. }
  165. /* Set the source and destination registers */
  166. BTE_PRINTKV(("IBSA = 0x%lx)\n", (TO_PHYS(src))));
  167. BTE_SRC_STORE(bte, TO_PHYS(src));
  168. BTE_PRINTKV(("IBDA = 0x%lx)\n", (TO_PHYS(dest))));
  169. BTE_DEST_STORE(bte, TO_PHYS(dest));
  170. /* Set the notification register */
  171. BTE_PRINTKV(("IBNA = 0x%lx)\n", notif_phys_addr));
  172. BTE_NOTIF_STORE(bte, notif_phys_addr);
  173. /* Initiate the transfer */
  174. BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode)));
  175. bte_start_transfer(bte, transfer_size, BTE_VALID_MODE(mode));
  176. itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec);
  177. spin_unlock_irqrestore(&bte->spinlock, irq_flags);
  178. if (notification != NULL) {
  179. return BTE_SUCCESS;
  180. }
  181. while ((transfer_stat = *bte->most_rcnt_na) == BTE_WORD_BUSY) {
  182. cpu_relax();
  183. if (ia64_get_itc() > itc_end) {
  184. BTE_PRINTK(("BTE timeout nasid 0x%x bte%d IBLS = 0x%lx na 0x%lx\n",
  185. NASID_GET(bte->bte_base_addr), bte->bte_num,
  186. BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na) );
  187. bte->bte_error_count++;
  188. bte->bh_error = IBLS_ERROR;
  189. bte_error_handler((unsigned long)NODEPDA(bte->bte_cnode));
  190. *bte->most_rcnt_na = BTE_WORD_AVAILABLE;
  191. goto retry_bteop;
  192. }
  193. }
  194. BTE_PRINTKV((" Delay Done. IBLS = 0x%lx, most_rcnt_na = 0x%lx\n",
  195. BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
  196. if (transfer_stat & IBLS_ERROR) {
  197. bte_status = transfer_stat & ~IBLS_ERROR;
  198. } else {
  199. bte_status = BTE_SUCCESS;
  200. }
  201. *bte->most_rcnt_na = BTE_WORD_AVAILABLE;
  202. BTE_PRINTK(("Returning status is 0x%lx and most_rcnt_na is 0x%lx\n",
  203. BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
  204. return bte_status;
  205. }
  206. EXPORT_SYMBOL(bte_copy);
  207. /*
  208. * bte_unaligned_copy(src, dest, len, mode)
  209. *
  210. * use the block transfer engine to move kernel
  211. * memory from src to dest using the assigned mode.
  212. *
  213. * Paramaters:
  214. * src - physical address of the transfer source.
  215. * dest - physical address of the transfer destination.
  216. * len - number of bytes to transfer from source to dest.
  217. * mode - hardware defined. See reference information
  218. * for IBCT0/1 in the SGI documentation.
  219. *
  220. * NOTE: If the source, dest, and len are all cache line aligned,
  221. * then it would be _FAR_ preferrable to use bte_copy instead.
  222. */
  223. bte_result_t bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode)
  224. {
  225. int destFirstCacheOffset;
  226. u64 headBteSource;
  227. u64 headBteLen;
  228. u64 headBcopySrcOffset;
  229. u64 headBcopyDest;
  230. u64 headBcopyLen;
  231. u64 footBteSource;
  232. u64 footBteLen;
  233. u64 footBcopyDest;
  234. u64 footBcopyLen;
  235. bte_result_t rv;
  236. char *bteBlock, *bteBlock_unaligned;
  237. if (len == 0) {
  238. return BTE_SUCCESS;
  239. }
  240. /* temporary buffer used during unaligned transfers */
  241. bteBlock_unaligned = kmalloc(len + 3 * L1_CACHE_BYTES,
  242. GFP_KERNEL | GFP_DMA);
  243. if (bteBlock_unaligned == NULL) {
  244. return BTEFAIL_NOTAVAIL;
  245. }
  246. bteBlock = (char *)L1_CACHE_ALIGN((u64) bteBlock_unaligned);
  247. headBcopySrcOffset = src & L1_CACHE_MASK;
  248. destFirstCacheOffset = dest & L1_CACHE_MASK;
  249. /*
  250. * At this point, the transfer is broken into
  251. * (up to) three sections. The first section is
  252. * from the start address to the first physical
  253. * cache line, the second is from the first physical
  254. * cache line to the last complete cache line,
  255. * and the third is from the last cache line to the
  256. * end of the buffer. The first and third sections
  257. * are handled by bte copying into a temporary buffer
  258. * and then bcopy'ing the necessary section into the
  259. * final location. The middle section is handled with
  260. * a standard bte copy.
  261. *
  262. * One nasty exception to the above rule is when the
  263. * source and destination are not symetrically
  264. * mis-aligned. If the source offset from the first
  265. * cache line is different from the destination offset,
  266. * we make the first section be the entire transfer
  267. * and the bcopy the entire block into place.
  268. */
  269. if (headBcopySrcOffset == destFirstCacheOffset) {
  270. /*
  271. * Both the source and destination are the same
  272. * distance from a cache line boundary so we can
  273. * use the bte to transfer the bulk of the
  274. * data.
  275. */
  276. headBteSource = src & ~L1_CACHE_MASK;
  277. headBcopyDest = dest;
  278. if (headBcopySrcOffset) {
  279. headBcopyLen =
  280. (len >
  281. (L1_CACHE_BYTES -
  282. headBcopySrcOffset) ? L1_CACHE_BYTES
  283. - headBcopySrcOffset : len);
  284. headBteLen = L1_CACHE_BYTES;
  285. } else {
  286. headBcopyLen = 0;
  287. headBteLen = 0;
  288. }
  289. if (len > headBcopyLen) {
  290. footBcopyLen = (len - headBcopyLen) & L1_CACHE_MASK;
  291. footBteLen = L1_CACHE_BYTES;
  292. footBteSource = src + len - footBcopyLen;
  293. footBcopyDest = dest + len - footBcopyLen;
  294. if (footBcopyDest == (headBcopyDest + headBcopyLen)) {
  295. /*
  296. * We have two contigous bcopy
  297. * blocks. Merge them.
  298. */
  299. headBcopyLen += footBcopyLen;
  300. headBteLen += footBteLen;
  301. } else if (footBcopyLen > 0) {
  302. rv = bte_copy(footBteSource,
  303. ia64_tpa((unsigned long)bteBlock),
  304. footBteLen, mode, NULL);
  305. if (rv != BTE_SUCCESS) {
  306. kfree(bteBlock_unaligned);
  307. return rv;
  308. }
  309. memcpy(__va(footBcopyDest),
  310. (char *)bteBlock, footBcopyLen);
  311. }
  312. } else {
  313. footBcopyLen = 0;
  314. footBteLen = 0;
  315. }
  316. if (len > (headBcopyLen + footBcopyLen)) {
  317. /* now transfer the middle. */
  318. rv = bte_copy((src + headBcopyLen),
  319. (dest +
  320. headBcopyLen),
  321. (len - headBcopyLen -
  322. footBcopyLen), mode, NULL);
  323. if (rv != BTE_SUCCESS) {
  324. kfree(bteBlock_unaligned);
  325. return rv;
  326. }
  327. }
  328. } else {
  329. /*
  330. * The transfer is not symetric, we will
  331. * allocate a buffer large enough for all the
  332. * data, bte_copy into that buffer and then
  333. * bcopy to the destination.
  334. */
  335. /* Add the leader from source */
  336. headBteLen = len + (src & L1_CACHE_MASK);
  337. /* Add the trailing bytes from footer. */
  338. headBteLen += L1_CACHE_BYTES - (headBteLen & L1_CACHE_MASK);
  339. headBteSource = src & ~L1_CACHE_MASK;
  340. headBcopySrcOffset = src & L1_CACHE_MASK;
  341. headBcopyDest = dest;
  342. headBcopyLen = len;
  343. }
  344. if (headBcopyLen > 0) {
  345. rv = bte_copy(headBteSource,
  346. ia64_tpa((unsigned long)bteBlock), headBteLen,
  347. mode, NULL);
  348. if (rv != BTE_SUCCESS) {
  349. kfree(bteBlock_unaligned);
  350. return rv;
  351. }
  352. memcpy(__va(headBcopyDest), ((char *)bteBlock +
  353. headBcopySrcOffset), headBcopyLen);
  354. }
  355. kfree(bteBlock_unaligned);
  356. return BTE_SUCCESS;
  357. }
  358. EXPORT_SYMBOL(bte_unaligned_copy);
  359. /************************************************************************
  360. * Block Transfer Engine initialization functions.
  361. *
  362. ***********************************************************************/
  363. /*
  364. * bte_init_node(nodepda, cnode)
  365. *
  366. * Initialize the nodepda structure with BTE base addresses and
  367. * spinlocks.
  368. */
  369. void bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode)
  370. {
  371. int i;
  372. /*
  373. * Indicate that all the block transfer engines on this node
  374. * are available.
  375. */
  376. /*
  377. * Allocate one bte_recover_t structure per node. It holds
  378. * the recovery lock for node. All the bte interface structures
  379. * will point at this one bte_recover structure to get the lock.
  380. */
  381. spin_lock_init(&mynodepda->bte_recovery_lock);
  382. init_timer(&mynodepda->bte_recovery_timer);
  383. mynodepda->bte_recovery_timer.function = bte_error_handler;
  384. mynodepda->bte_recovery_timer.data = (unsigned long)mynodepda;
  385. for (i = 0; i < BTES_PER_NODE; i++) {
  386. u64 *base_addr;
  387. /* Which link status register should we use? */
  388. base_addr = (u64 *)
  389. REMOTE_HUB_ADDR(cnodeid_to_nasid(cnode), BTE_BASE_ADDR(i));
  390. mynodepda->bte_if[i].bte_base_addr = base_addr;
  391. mynodepda->bte_if[i].bte_source_addr = BTE_SOURCE_ADDR(base_addr);
  392. mynodepda->bte_if[i].bte_destination_addr = BTE_DEST_ADDR(base_addr);
  393. mynodepda->bte_if[i].bte_control_addr = BTE_CTRL_ADDR(base_addr);
  394. mynodepda->bte_if[i].bte_notify_addr = BTE_NOTIF_ADDR(base_addr);
  395. /*
  396. * Initialize the notification and spinlock
  397. * so the first transfer can occur.
  398. */
  399. mynodepda->bte_if[i].most_rcnt_na =
  400. &(mynodepda->bte_if[i].notify);
  401. mynodepda->bte_if[i].notify = BTE_WORD_AVAILABLE;
  402. spin_lock_init(&mynodepda->bte_if[i].spinlock);
  403. mynodepda->bte_if[i].bte_cnode = cnode;
  404. mynodepda->bte_if[i].bte_error_count = 0;
  405. mynodepda->bte_if[i].bte_num = i;
  406. mynodepda->bte_if[i].cleanup_active = 0;
  407. mynodepda->bte_if[i].bh_error = 0;
  408. }
  409. }