radeon_mode.h 18 KB

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  1. /*
  2. * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  3. * VA Linux Systems Inc., Fremont, California.
  4. * Copyright 2008 Red Hat Inc.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Original Authors:
  25. * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26. *
  27. * Kernel port Author: Dave Airlie
  28. */
  29. #ifndef RADEON_MODE_H
  30. #define RADEON_MODE_H
  31. #include <drm_crtc.h>
  32. #include <drm_mode.h>
  33. #include <drm_edid.h>
  34. #include <drm_dp_helper.h>
  35. #include <linux/i2c.h>
  36. #include <linux/i2c-id.h>
  37. #include <linux/i2c-algo-bit.h>
  38. #include "radeon_fixed.h"
  39. struct radeon_bo;
  40. struct radeon_device;
  41. #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
  42. #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
  43. #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
  44. #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
  45. enum radeon_rmx_type {
  46. RMX_OFF,
  47. RMX_FULL,
  48. RMX_CENTER,
  49. RMX_ASPECT
  50. };
  51. enum radeon_tv_std {
  52. TV_STD_NTSC,
  53. TV_STD_PAL,
  54. TV_STD_PAL_M,
  55. TV_STD_PAL_60,
  56. TV_STD_NTSC_J,
  57. TV_STD_SCART_PAL,
  58. TV_STD_SECAM,
  59. TV_STD_PAL_CN,
  60. TV_STD_PAL_N,
  61. };
  62. /* radeon gpio-based i2c
  63. * 1. "mask" reg and bits
  64. * grabs the gpio pins for software use
  65. * 0=not held 1=held
  66. * 2. "a" reg and bits
  67. * output pin value
  68. * 0=low 1=high
  69. * 3. "en" reg and bits
  70. * sets the pin direction
  71. * 0=input 1=output
  72. * 4. "y" reg and bits
  73. * input pin value
  74. * 0=low 1=high
  75. */
  76. struct radeon_i2c_bus_rec {
  77. bool valid;
  78. /* id used by atom */
  79. uint8_t i2c_id;
  80. /* id used by atom */
  81. uint8_t hpd_id;
  82. /* can be used with hw i2c engine */
  83. bool hw_capable;
  84. /* uses multi-media i2c engine */
  85. bool mm_i2c;
  86. /* regs and bits */
  87. uint32_t mask_clk_reg;
  88. uint32_t mask_data_reg;
  89. uint32_t a_clk_reg;
  90. uint32_t a_data_reg;
  91. uint32_t en_clk_reg;
  92. uint32_t en_data_reg;
  93. uint32_t y_clk_reg;
  94. uint32_t y_data_reg;
  95. uint32_t mask_clk_mask;
  96. uint32_t mask_data_mask;
  97. uint32_t a_clk_mask;
  98. uint32_t a_data_mask;
  99. uint32_t en_clk_mask;
  100. uint32_t en_data_mask;
  101. uint32_t y_clk_mask;
  102. uint32_t y_data_mask;
  103. };
  104. struct radeon_tmds_pll {
  105. uint32_t freq;
  106. uint32_t value;
  107. };
  108. #define RADEON_MAX_BIOS_CONNECTOR 16
  109. /* pll flags */
  110. #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
  111. #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
  112. #define RADEON_PLL_USE_REF_DIV (1 << 2)
  113. #define RADEON_PLL_LEGACY (1 << 3)
  114. #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
  115. #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
  116. #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
  117. #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
  118. #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
  119. #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
  120. #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
  121. #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
  122. #define RADEON_PLL_USE_POST_DIV (1 << 12)
  123. #define RADEON_PLL_IS_LCD (1 << 13)
  124. /* pll algo */
  125. enum radeon_pll_algo {
  126. PLL_ALGO_LEGACY,
  127. PLL_ALGO_NEW
  128. };
  129. struct radeon_pll {
  130. /* reference frequency */
  131. uint32_t reference_freq;
  132. /* fixed dividers */
  133. uint32_t reference_div;
  134. uint32_t post_div;
  135. /* pll in/out limits */
  136. uint32_t pll_in_min;
  137. uint32_t pll_in_max;
  138. uint32_t pll_out_min;
  139. uint32_t pll_out_max;
  140. uint32_t lcd_pll_out_min;
  141. uint32_t lcd_pll_out_max;
  142. uint32_t best_vco;
  143. /* divider limits */
  144. uint32_t min_ref_div;
  145. uint32_t max_ref_div;
  146. uint32_t min_post_div;
  147. uint32_t max_post_div;
  148. uint32_t min_feedback_div;
  149. uint32_t max_feedback_div;
  150. uint32_t min_frac_feedback_div;
  151. uint32_t max_frac_feedback_div;
  152. /* flags for the current clock */
  153. uint32_t flags;
  154. /* pll id */
  155. uint32_t id;
  156. /* pll algo */
  157. enum radeon_pll_algo algo;
  158. };
  159. struct radeon_i2c_chan {
  160. struct i2c_adapter adapter;
  161. struct drm_device *dev;
  162. union {
  163. struct i2c_algo_bit_data bit;
  164. struct i2c_algo_dp_aux_data dp;
  165. } algo;
  166. struct radeon_i2c_bus_rec rec;
  167. };
  168. /* mostly for macs, but really any system without connector tables */
  169. enum radeon_connector_table {
  170. CT_NONE,
  171. CT_GENERIC,
  172. CT_IBOOK,
  173. CT_POWERBOOK_EXTERNAL,
  174. CT_POWERBOOK_INTERNAL,
  175. CT_POWERBOOK_VGA,
  176. CT_MINI_EXTERNAL,
  177. CT_MINI_INTERNAL,
  178. CT_IMAC_G5_ISIGHT,
  179. CT_EMAC,
  180. };
  181. enum radeon_dvo_chip {
  182. DVO_SIL164,
  183. DVO_SIL1178,
  184. };
  185. struct radeon_fbdev;
  186. struct radeon_mode_info {
  187. struct atom_context *atom_context;
  188. struct card_info *atom_card_info;
  189. enum radeon_connector_table connector_table;
  190. bool mode_config_initialized;
  191. struct radeon_crtc *crtcs[6];
  192. /* DVI-I properties */
  193. struct drm_property *coherent_mode_property;
  194. /* DAC enable load detect */
  195. struct drm_property *load_detect_property;
  196. /* TV standard load detect */
  197. struct drm_property *tv_std_property;
  198. /* legacy TMDS PLL detect */
  199. struct drm_property *tmds_pll_property;
  200. /* hardcoded DFP edid from BIOS */
  201. struct edid *bios_hardcoded_edid;
  202. /* pointer to fbdev info structure */
  203. struct radeon_fbdev *rfbdev;
  204. };
  205. #define MAX_H_CODE_TIMING_LEN 32
  206. #define MAX_V_CODE_TIMING_LEN 32
  207. /* need to store these as reading
  208. back code tables is excessive */
  209. struct radeon_tv_regs {
  210. uint32_t tv_uv_adr;
  211. uint32_t timing_cntl;
  212. uint32_t hrestart;
  213. uint32_t vrestart;
  214. uint32_t frestart;
  215. uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
  216. uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
  217. };
  218. struct radeon_crtc {
  219. struct drm_crtc base;
  220. int crtc_id;
  221. u16 lut_r[256], lut_g[256], lut_b[256];
  222. bool enabled;
  223. bool can_tile;
  224. uint32_t crtc_offset;
  225. struct drm_gem_object *cursor_bo;
  226. uint64_t cursor_addr;
  227. int cursor_width;
  228. int cursor_height;
  229. uint32_t legacy_display_base_addr;
  230. uint32_t legacy_cursor_offset;
  231. enum radeon_rmx_type rmx_type;
  232. fixed20_12 vsc;
  233. fixed20_12 hsc;
  234. struct drm_display_mode native_mode;
  235. int pll_id;
  236. };
  237. struct radeon_encoder_primary_dac {
  238. /* legacy primary dac */
  239. uint32_t ps2_pdac_adj;
  240. };
  241. struct radeon_encoder_lvds {
  242. /* legacy lvds */
  243. uint16_t panel_vcc_delay;
  244. uint8_t panel_pwr_delay;
  245. uint8_t panel_digon_delay;
  246. uint8_t panel_blon_delay;
  247. uint16_t panel_ref_divider;
  248. uint8_t panel_post_divider;
  249. uint16_t panel_fb_divider;
  250. bool use_bios_dividers;
  251. uint32_t lvds_gen_cntl;
  252. /* panel mode */
  253. struct drm_display_mode native_mode;
  254. };
  255. struct radeon_encoder_tv_dac {
  256. /* legacy tv dac */
  257. uint32_t ps2_tvdac_adj;
  258. uint32_t ntsc_tvdac_adj;
  259. uint32_t pal_tvdac_adj;
  260. int h_pos;
  261. int v_pos;
  262. int h_size;
  263. int supported_tv_stds;
  264. bool tv_on;
  265. enum radeon_tv_std tv_std;
  266. struct radeon_tv_regs tv;
  267. };
  268. struct radeon_encoder_int_tmds {
  269. /* legacy int tmds */
  270. struct radeon_tmds_pll tmds_pll[4];
  271. };
  272. struct radeon_encoder_ext_tmds {
  273. /* tmds over dvo */
  274. struct radeon_i2c_chan *i2c_bus;
  275. uint8_t slave_addr;
  276. enum radeon_dvo_chip dvo_chip;
  277. };
  278. /* spread spectrum */
  279. struct radeon_atom_ss {
  280. uint16_t percentage;
  281. uint8_t type;
  282. uint8_t step;
  283. uint8_t delay;
  284. uint8_t range;
  285. uint8_t refdiv;
  286. };
  287. struct radeon_encoder_atom_dig {
  288. /* atom dig */
  289. bool coherent_mode;
  290. int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
  291. /* atom lvds */
  292. uint32_t lvds_misc;
  293. uint16_t panel_pwr_delay;
  294. enum radeon_pll_algo pll_algo;
  295. struct radeon_atom_ss *ss;
  296. /* panel mode */
  297. struct drm_display_mode native_mode;
  298. };
  299. struct radeon_encoder_atom_dac {
  300. enum radeon_tv_std tv_std;
  301. };
  302. struct radeon_encoder {
  303. struct drm_encoder base;
  304. uint32_t encoder_id;
  305. uint32_t devices;
  306. uint32_t active_device;
  307. uint32_t flags;
  308. uint32_t pixel_clock;
  309. enum radeon_rmx_type rmx_type;
  310. struct drm_display_mode native_mode;
  311. void *enc_priv;
  312. int hdmi_offset;
  313. int hdmi_config_offset;
  314. int hdmi_audio_workaround;
  315. int hdmi_buffer_status;
  316. };
  317. struct radeon_connector_atom_dig {
  318. uint32_t igp_lane_info;
  319. bool linkb;
  320. /* displayport */
  321. struct radeon_i2c_chan *dp_i2c_bus;
  322. u8 dpcd[8];
  323. u8 dp_sink_type;
  324. int dp_clock;
  325. int dp_lane_count;
  326. };
  327. struct radeon_gpio_rec {
  328. bool valid;
  329. u8 id;
  330. u32 reg;
  331. u32 mask;
  332. };
  333. enum radeon_hpd_id {
  334. RADEON_HPD_NONE = 0,
  335. RADEON_HPD_1,
  336. RADEON_HPD_2,
  337. RADEON_HPD_3,
  338. RADEON_HPD_4,
  339. RADEON_HPD_5,
  340. RADEON_HPD_6,
  341. };
  342. struct radeon_hpd {
  343. enum radeon_hpd_id hpd;
  344. u8 plugged_state;
  345. struct radeon_gpio_rec gpio;
  346. };
  347. struct radeon_connector {
  348. struct drm_connector base;
  349. uint32_t connector_id;
  350. uint32_t devices;
  351. struct radeon_i2c_chan *ddc_bus;
  352. /* some systems have a an hdmi and vga port with a shared ddc line */
  353. bool shared_ddc;
  354. bool use_digital;
  355. /* we need to mind the EDID between detect
  356. and get modes due to analog/digital/tvencoder */
  357. struct edid *edid;
  358. void *con_priv;
  359. bool dac_load_detect;
  360. uint16_t connector_object_id;
  361. struct radeon_hpd hpd;
  362. };
  363. struct radeon_framebuffer {
  364. struct drm_framebuffer base;
  365. struct drm_gem_object *obj;
  366. };
  367. extern enum radeon_tv_std
  368. radeon_combios_get_tv_info(struct radeon_device *rdev);
  369. extern enum radeon_tv_std
  370. radeon_atombios_get_tv_info(struct radeon_device *rdev);
  371. extern void radeon_connector_hotplug(struct drm_connector *connector);
  372. extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
  373. extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
  374. struct drm_display_mode *mode);
  375. extern void radeon_dp_set_link_config(struct drm_connector *connector,
  376. struct drm_display_mode *mode);
  377. extern void dp_link_train(struct drm_encoder *encoder,
  378. struct drm_connector *connector);
  379. extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
  380. extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
  381. extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
  382. extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
  383. int action, uint8_t lane_num,
  384. uint8_t lane_set);
  385. extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  386. uint8_t write_byte, uint8_t *read_byte);
  387. extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
  388. struct radeon_i2c_bus_rec *rec,
  389. const char *name);
  390. extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
  391. struct radeon_i2c_bus_rec *rec,
  392. const char *name);
  393. extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
  394. extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
  395. u8 slave_addr,
  396. u8 addr,
  397. u8 *val);
  398. extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
  399. u8 slave_addr,
  400. u8 addr,
  401. u8 val);
  402. extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
  403. extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
  404. extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
  405. extern void radeon_compute_pll(struct radeon_pll *pll,
  406. uint64_t freq,
  407. uint32_t *dot_clock_p,
  408. uint32_t *fb_div_p,
  409. uint32_t *frac_fb_div_p,
  410. uint32_t *ref_div_p,
  411. uint32_t *post_div_p);
  412. extern void radeon_setup_encoder_clones(struct drm_device *dev);
  413. struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
  414. struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
  415. struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
  416. struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
  417. struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
  418. extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
  419. extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
  420. extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
  421. extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
  422. extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
  423. extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  424. struct drm_framebuffer *old_fb);
  425. extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
  426. struct drm_display_mode *mode,
  427. struct drm_display_mode *adjusted_mode,
  428. int x, int y,
  429. struct drm_framebuffer *old_fb);
  430. extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
  431. extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  432. struct drm_framebuffer *old_fb);
  433. extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
  434. struct drm_file *file_priv,
  435. uint32_t handle,
  436. uint32_t width,
  437. uint32_t height);
  438. extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
  439. int x, int y);
  440. extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
  441. extern struct edid *
  442. radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
  443. extern bool radeon_atom_get_clock_info(struct drm_device *dev);
  444. extern bool radeon_combios_get_clock_info(struct drm_device *dev);
  445. extern struct radeon_encoder_atom_dig *
  446. radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
  447. extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
  448. struct radeon_encoder_int_tmds *tmds);
  449. extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
  450. struct radeon_encoder_int_tmds *tmds);
  451. extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
  452. struct radeon_encoder_int_tmds *tmds);
  453. extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
  454. struct radeon_encoder_ext_tmds *tmds);
  455. extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
  456. struct radeon_encoder_ext_tmds *tmds);
  457. extern struct radeon_encoder_primary_dac *
  458. radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
  459. extern struct radeon_encoder_tv_dac *
  460. radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
  461. extern struct radeon_encoder_lvds *
  462. radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
  463. extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
  464. extern struct radeon_encoder_tv_dac *
  465. radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
  466. extern struct radeon_encoder_primary_dac *
  467. radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
  468. extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
  469. extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
  470. extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
  471. extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
  472. extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
  473. extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
  474. extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
  475. extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
  476. extern void
  477. radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
  478. extern void
  479. radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
  480. extern void
  481. radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
  482. extern void
  483. radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
  484. extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  485. u16 blue, int regno);
  486. extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  487. u16 *blue, int regno);
  488. void radeon_framebuffer_init(struct drm_device *dev,
  489. struct radeon_framebuffer *rfb,
  490. struct drm_mode_fb_cmd *mode_cmd,
  491. struct drm_gem_object *obj);
  492. int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
  493. bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
  494. bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
  495. void radeon_atombios_init_crtc(struct drm_device *dev,
  496. struct radeon_crtc *radeon_crtc);
  497. void radeon_legacy_init_crtc(struct drm_device *dev,
  498. struct radeon_crtc *radeon_crtc);
  499. void radeon_get_clock_info(struct drm_device *dev);
  500. extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
  501. extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
  502. void radeon_enc_destroy(struct drm_encoder *encoder);
  503. void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
  504. void radeon_combios_asic_init(struct drm_device *dev);
  505. extern int radeon_static_clocks_init(struct drm_device *dev);
  506. bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
  507. struct drm_display_mode *mode,
  508. struct drm_display_mode *adjusted_mode);
  509. void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
  510. /* legacy tv */
  511. void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
  512. uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
  513. uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
  514. void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
  515. uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
  516. uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
  517. void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
  518. uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
  519. uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
  520. void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
  521. struct drm_display_mode *mode,
  522. struct drm_display_mode *adjusted_mode);
  523. /* fbdev layer */
  524. int radeon_fbdev_init(struct radeon_device *rdev);
  525. void radeon_fbdev_fini(struct radeon_device *rdev);
  526. void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
  527. int radeon_fbdev_total_size(struct radeon_device *rdev);
  528. bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
  529. void radeonfb_hotplug(struct drm_device *dev);
  530. #endif