sx8.c 40 KB

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  1. /*
  2. * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware
  3. *
  4. * Copyright 2004 Red Hat, Inc.
  5. *
  6. * Author/maintainer: Jeff Garzik <jgarzik@pobox.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/slab.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/blkdev.h>
  19. #include <linux/sched.h>
  20. #include <linux/devfs_fs_kernel.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/compiler.h>
  23. #include <linux/workqueue.h>
  24. #include <linux/bitops.h>
  25. #include <linux/delay.h>
  26. #include <linux/time.h>
  27. #include <linux/hdreg.h>
  28. #include <asm/io.h>
  29. #include <asm/semaphore.h>
  30. #include <asm/uaccess.h>
  31. MODULE_AUTHOR("Jeff Garzik");
  32. MODULE_LICENSE("GPL");
  33. MODULE_DESCRIPTION("Promise SATA SX8 block driver");
  34. #if 0
  35. #define CARM_DEBUG
  36. #define CARM_VERBOSE_DEBUG
  37. #else
  38. #undef CARM_DEBUG
  39. #undef CARM_VERBOSE_DEBUG
  40. #endif
  41. #undef CARM_NDEBUG
  42. #define DRV_NAME "sx8"
  43. #define DRV_VERSION "0.8"
  44. #define PFX DRV_NAME ": "
  45. #define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN)
  46. /* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */
  47. #define TAG_ENCODE(tag) (((tag) << 16) | 0xf)
  48. #define TAG_DECODE(tag) (((tag) >> 16) & 0x1f)
  49. #define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32))
  50. /* note: prints function name for you */
  51. #ifdef CARM_DEBUG
  52. #define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
  53. #ifdef CARM_VERBOSE_DEBUG
  54. #define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
  55. #else
  56. #define VPRINTK(fmt, args...)
  57. #endif /* CARM_VERBOSE_DEBUG */
  58. #else
  59. #define DPRINTK(fmt, args...)
  60. #define VPRINTK(fmt, args...)
  61. #endif /* CARM_DEBUG */
  62. #ifdef CARM_NDEBUG
  63. #define assert(expr)
  64. #else
  65. #define assert(expr) \
  66. if(unlikely(!(expr))) { \
  67. printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
  68. #expr,__FILE__,__FUNCTION__,__LINE__); \
  69. }
  70. #endif
  71. /* defines only for the constants which don't work well as enums */
  72. struct carm_host;
  73. enum {
  74. /* adapter-wide limits */
  75. CARM_MAX_PORTS = 8,
  76. CARM_SHM_SIZE = (4096 << 7),
  77. CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS,
  78. CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1,
  79. /* command message queue limits */
  80. CARM_MAX_REQ = 64, /* max command msgs per host */
  81. CARM_MAX_Q = 1, /* one command at a time */
  82. CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */
  83. /* S/G limits, host-wide and per-request */
  84. CARM_MAX_REQ_SG = 32, /* max s/g entries per request */
  85. CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */
  86. CARM_MAX_HOST_SG = 600, /* max s/g entries per host */
  87. CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */
  88. /* hardware registers */
  89. CARM_IHQP = 0x1c,
  90. CARM_INT_STAT = 0x10, /* interrupt status */
  91. CARM_INT_MASK = 0x14, /* interrupt mask */
  92. CARM_HMUC = 0x18, /* host message unit control */
  93. RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */
  94. RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */
  95. RBUF_BYTE_SZ = 0x28,
  96. CARM_RESP_IDX = 0x2c,
  97. CARM_CMS0 = 0x30, /* command message size reg 0 */
  98. CARM_LMUC = 0x48,
  99. CARM_HMPHA = 0x6c,
  100. CARM_INITC = 0xb5,
  101. /* bits in CARM_INT_{STAT,MASK} */
  102. INT_RESERVED = 0xfffffff0,
  103. INT_WATCHDOG = (1 << 3), /* watchdog timer */
  104. INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */
  105. INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */
  106. INT_RESPONSE = (1 << 0), /* response msg available */
  107. INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW,
  108. INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW |
  109. INT_RESPONSE,
  110. /* command messages, and related register bits */
  111. CARM_HAVE_RESP = 0x01,
  112. CARM_MSG_READ = 1,
  113. CARM_MSG_WRITE = 2,
  114. CARM_MSG_VERIFY = 3,
  115. CARM_MSG_GET_CAPACITY = 4,
  116. CARM_MSG_FLUSH = 5,
  117. CARM_MSG_IOCTL = 6,
  118. CARM_MSG_ARRAY = 8,
  119. CARM_MSG_MISC = 9,
  120. CARM_CME = (1 << 2),
  121. CARM_RME = (1 << 1),
  122. CARM_WZBC = (1 << 0),
  123. CARM_RMI = (1 << 0),
  124. CARM_Q_FULL = (1 << 3),
  125. CARM_MSG_SIZE = 288,
  126. CARM_Q_LEN = 48,
  127. /* CARM_MSG_IOCTL messages */
  128. CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */
  129. CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */
  130. CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */
  131. IOC_SCAN_CHAN_NODEV = 0x1f,
  132. IOC_SCAN_CHAN_OFFSET = 0x40,
  133. /* CARM_MSG_ARRAY messages */
  134. CARM_ARRAY_INFO = 0,
  135. ARRAY_NO_EXIST = (1 << 31),
  136. /* response messages */
  137. RMSG_SZ = 8, /* sizeof(struct carm_response) */
  138. RMSG_Q_LEN = 48, /* resp. msg list length */
  139. RMSG_OK = 1, /* bit indicating msg was successful */
  140. /* length of entire resp. msg buffer */
  141. RBUF_LEN = RMSG_SZ * RMSG_Q_LEN,
  142. PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */
  143. /* CARM_MSG_MISC messages */
  144. MISC_GET_FW_VER = 2,
  145. MISC_ALLOC_MEM = 3,
  146. MISC_SET_TIME = 5,
  147. /* MISC_GET_FW_VER feature bits */
  148. FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */
  149. FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */
  150. FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */
  151. /* carm_host flags */
  152. FL_NON_RAID = FW_VER_NON_RAID,
  153. FL_4PORT = FW_VER_4PORT,
  154. FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT),
  155. FL_DAC = (1 << 16),
  156. FL_DYN_MAJOR = (1 << 17),
  157. };
  158. enum scatter_gather_types {
  159. SGT_32BIT = 0,
  160. SGT_64BIT = 1,
  161. };
  162. enum host_states {
  163. HST_INVALID, /* invalid state; never used */
  164. HST_ALLOC_BUF, /* setting up master SHM area */
  165. HST_ERROR, /* we never leave here */
  166. HST_PORT_SCAN, /* start dev scan */
  167. HST_DEV_SCAN_START, /* start per-device probe */
  168. HST_DEV_SCAN, /* continue per-device probe */
  169. HST_DEV_ACTIVATE, /* activate devices we found */
  170. HST_PROBE_FINISHED, /* probe is complete */
  171. HST_PROBE_START, /* initiate probe */
  172. HST_SYNC_TIME, /* tell firmware what time it is */
  173. HST_GET_FW_VER, /* get firmware version, adapter port cnt */
  174. };
  175. #ifdef CARM_DEBUG
  176. static const char *state_name[] = {
  177. "HST_INVALID",
  178. "HST_ALLOC_BUF",
  179. "HST_ERROR",
  180. "HST_PORT_SCAN",
  181. "HST_DEV_SCAN_START",
  182. "HST_DEV_SCAN",
  183. "HST_DEV_ACTIVATE",
  184. "HST_PROBE_FINISHED",
  185. "HST_PROBE_START",
  186. "HST_SYNC_TIME",
  187. "HST_GET_FW_VER",
  188. };
  189. #endif
  190. struct carm_port {
  191. unsigned int port_no;
  192. unsigned int n_queued;
  193. struct gendisk *disk;
  194. struct carm_host *host;
  195. /* attached device characteristics */
  196. u64 capacity;
  197. char name[41];
  198. u16 dev_geom_head;
  199. u16 dev_geom_sect;
  200. u16 dev_geom_cyl;
  201. };
  202. struct carm_request {
  203. unsigned int tag;
  204. int n_elem;
  205. unsigned int msg_type;
  206. unsigned int msg_subtype;
  207. unsigned int msg_bucket;
  208. struct request *rq;
  209. struct carm_port *port;
  210. struct scatterlist sg[CARM_MAX_REQ_SG];
  211. };
  212. struct carm_host {
  213. unsigned long flags;
  214. void __iomem *mmio;
  215. void *shm;
  216. dma_addr_t shm_dma;
  217. int major;
  218. int id;
  219. char name[32];
  220. spinlock_t lock;
  221. struct pci_dev *pdev;
  222. unsigned int state;
  223. u32 fw_ver;
  224. request_queue_t *oob_q;
  225. unsigned int n_oob;
  226. unsigned int hw_sg_used;
  227. unsigned int resp_idx;
  228. unsigned int wait_q_prod;
  229. unsigned int wait_q_cons;
  230. request_queue_t *wait_q[CARM_MAX_WAIT_Q];
  231. unsigned int n_msgs;
  232. u64 msg_alloc;
  233. struct carm_request req[CARM_MAX_REQ];
  234. void *msg_base;
  235. dma_addr_t msg_dma;
  236. int cur_scan_dev;
  237. unsigned long dev_active;
  238. unsigned long dev_present;
  239. struct carm_port port[CARM_MAX_PORTS];
  240. struct work_struct fsm_task;
  241. struct semaphore probe_sem;
  242. };
  243. struct carm_response {
  244. __le32 ret_handle;
  245. __le32 status;
  246. } __attribute__((packed));
  247. struct carm_msg_sg {
  248. __le32 start;
  249. __le32 len;
  250. } __attribute__((packed));
  251. struct carm_msg_rw {
  252. u8 type;
  253. u8 id;
  254. u8 sg_count;
  255. u8 sg_type;
  256. __le32 handle;
  257. __le32 lba;
  258. __le16 lba_count;
  259. __le16 lba_high;
  260. struct carm_msg_sg sg[32];
  261. } __attribute__((packed));
  262. struct carm_msg_allocbuf {
  263. u8 type;
  264. u8 subtype;
  265. u8 n_sg;
  266. u8 sg_type;
  267. __le32 handle;
  268. __le32 addr;
  269. __le32 len;
  270. __le32 evt_pool;
  271. __le32 n_evt;
  272. __le32 rbuf_pool;
  273. __le32 n_rbuf;
  274. __le32 msg_pool;
  275. __le32 n_msg;
  276. struct carm_msg_sg sg[8];
  277. } __attribute__((packed));
  278. struct carm_msg_ioctl {
  279. u8 type;
  280. u8 subtype;
  281. u8 array_id;
  282. u8 reserved1;
  283. __le32 handle;
  284. __le32 data_addr;
  285. u32 reserved2;
  286. } __attribute__((packed));
  287. struct carm_msg_sync_time {
  288. u8 type;
  289. u8 subtype;
  290. u16 reserved1;
  291. __le32 handle;
  292. u32 reserved2;
  293. __le32 timestamp;
  294. } __attribute__((packed));
  295. struct carm_msg_get_fw_ver {
  296. u8 type;
  297. u8 subtype;
  298. u16 reserved1;
  299. __le32 handle;
  300. __le32 data_addr;
  301. u32 reserved2;
  302. } __attribute__((packed));
  303. struct carm_fw_ver {
  304. __le32 version;
  305. u8 features;
  306. u8 reserved1;
  307. u16 reserved2;
  308. } __attribute__((packed));
  309. struct carm_array_info {
  310. __le32 size;
  311. __le16 size_hi;
  312. __le16 stripe_size;
  313. __le32 mode;
  314. __le16 stripe_blk_sz;
  315. __le16 reserved1;
  316. __le16 cyl;
  317. __le16 head;
  318. __le16 sect;
  319. u8 array_id;
  320. u8 reserved2;
  321. char name[40];
  322. __le32 array_status;
  323. /* device list continues beyond this point? */
  324. } __attribute__((packed));
  325. static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  326. static void carm_remove_one (struct pci_dev *pdev);
  327. static int carm_bdev_ioctl(struct inode *ino, struct file *fil,
  328. unsigned int cmd, unsigned long arg);
  329. static struct pci_device_id carm_pci_tbl[] = {
  330. { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  331. { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  332. { } /* terminate list */
  333. };
  334. MODULE_DEVICE_TABLE(pci, carm_pci_tbl);
  335. static struct pci_driver carm_driver = {
  336. .name = DRV_NAME,
  337. .id_table = carm_pci_tbl,
  338. .probe = carm_init_one,
  339. .remove = carm_remove_one,
  340. };
  341. static struct block_device_operations carm_bd_ops = {
  342. .owner = THIS_MODULE,
  343. .ioctl = carm_bdev_ioctl,
  344. };
  345. static unsigned int carm_host_id;
  346. static unsigned long carm_major_alloc;
  347. static int carm_bdev_ioctl(struct inode *ino, struct file *fil,
  348. unsigned int cmd, unsigned long arg)
  349. {
  350. void __user *usermem = (void __user *) arg;
  351. struct carm_port *port = ino->i_bdev->bd_disk->private_data;
  352. struct hd_geometry geom;
  353. switch (cmd) {
  354. case HDIO_GETGEO:
  355. if (!usermem)
  356. return -EINVAL;
  357. geom.heads = (u8) port->dev_geom_head;
  358. geom.sectors = (u8) port->dev_geom_sect;
  359. geom.cylinders = port->dev_geom_cyl;
  360. geom.start = get_start_sect(ino->i_bdev);
  361. if (copy_to_user(usermem, &geom, sizeof(geom)))
  362. return -EFAULT;
  363. return 0;
  364. default:
  365. break;
  366. }
  367. return -EOPNOTSUPP;
  368. }
  369. static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE };
  370. static inline int carm_lookup_bucket(u32 msg_size)
  371. {
  372. int i;
  373. for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
  374. if (msg_size <= msg_sizes[i])
  375. return i;
  376. return -ENOENT;
  377. }
  378. static void carm_init_buckets(void __iomem *mmio)
  379. {
  380. unsigned int i;
  381. for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
  382. writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i));
  383. }
  384. static inline void *carm_ref_msg(struct carm_host *host,
  385. unsigned int msg_idx)
  386. {
  387. return host->msg_base + (msg_idx * CARM_MSG_SIZE);
  388. }
  389. static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host,
  390. unsigned int msg_idx)
  391. {
  392. return host->msg_dma + (msg_idx * CARM_MSG_SIZE);
  393. }
  394. static int carm_send_msg(struct carm_host *host,
  395. struct carm_request *crq)
  396. {
  397. void __iomem *mmio = host->mmio;
  398. u32 msg = (u32) carm_ref_msg_dma(host, crq->tag);
  399. u32 cm_bucket = crq->msg_bucket;
  400. u32 tmp;
  401. int rc = 0;
  402. VPRINTK("ENTER\n");
  403. tmp = readl(mmio + CARM_HMUC);
  404. if (tmp & CARM_Q_FULL) {
  405. #if 0
  406. tmp = readl(mmio + CARM_INT_MASK);
  407. tmp |= INT_Q_AVAILABLE;
  408. writel(tmp, mmio + CARM_INT_MASK);
  409. readl(mmio + CARM_INT_MASK); /* flush */
  410. #endif
  411. DPRINTK("host msg queue full\n");
  412. rc = -EBUSY;
  413. } else {
  414. writel(msg | (cm_bucket << 1), mmio + CARM_IHQP);
  415. readl(mmio + CARM_IHQP); /* flush */
  416. }
  417. return rc;
  418. }
  419. static struct carm_request *carm_get_request(struct carm_host *host)
  420. {
  421. unsigned int i;
  422. /* obey global hardware limit on S/G entries */
  423. if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG))
  424. return NULL;
  425. for (i = 0; i < CARM_MAX_Q; i++)
  426. if ((host->msg_alloc & (1ULL << i)) == 0) {
  427. struct carm_request *crq = &host->req[i];
  428. crq->port = NULL;
  429. crq->n_elem = 0;
  430. host->msg_alloc |= (1ULL << i);
  431. host->n_msgs++;
  432. assert(host->n_msgs <= CARM_MAX_REQ);
  433. return crq;
  434. }
  435. DPRINTK("no request available, returning NULL\n");
  436. return NULL;
  437. }
  438. static int carm_put_request(struct carm_host *host, struct carm_request *crq)
  439. {
  440. assert(crq->tag < CARM_MAX_Q);
  441. if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0))
  442. return -EINVAL; /* tried to clear a tag that was not active */
  443. assert(host->hw_sg_used >= crq->n_elem);
  444. host->msg_alloc &= ~(1ULL << crq->tag);
  445. host->hw_sg_used -= crq->n_elem;
  446. host->n_msgs--;
  447. return 0;
  448. }
  449. static struct carm_request *carm_get_special(struct carm_host *host)
  450. {
  451. unsigned long flags;
  452. struct carm_request *crq = NULL;
  453. struct request *rq;
  454. int tries = 5000;
  455. while (tries-- > 0) {
  456. spin_lock_irqsave(&host->lock, flags);
  457. crq = carm_get_request(host);
  458. spin_unlock_irqrestore(&host->lock, flags);
  459. if (crq)
  460. break;
  461. msleep(10);
  462. }
  463. if (!crq)
  464. return NULL;
  465. rq = blk_get_request(host->oob_q, WRITE /* bogus */, GFP_KERNEL);
  466. if (!rq) {
  467. spin_lock_irqsave(&host->lock, flags);
  468. carm_put_request(host, crq);
  469. spin_unlock_irqrestore(&host->lock, flags);
  470. return NULL;
  471. }
  472. crq->rq = rq;
  473. return crq;
  474. }
  475. static int carm_array_info (struct carm_host *host, unsigned int array_idx)
  476. {
  477. struct carm_msg_ioctl *ioc;
  478. unsigned int idx;
  479. u32 msg_data;
  480. dma_addr_t msg_dma;
  481. struct carm_request *crq;
  482. int rc;
  483. crq = carm_get_special(host);
  484. if (!crq) {
  485. rc = -ENOMEM;
  486. goto err_out;
  487. }
  488. idx = crq->tag;
  489. ioc = carm_ref_msg(host, idx);
  490. msg_dma = carm_ref_msg_dma(host, idx);
  491. msg_data = (u32) (msg_dma + sizeof(struct carm_array_info));
  492. crq->msg_type = CARM_MSG_ARRAY;
  493. crq->msg_subtype = CARM_ARRAY_INFO;
  494. rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) +
  495. sizeof(struct carm_array_info));
  496. BUG_ON(rc < 0);
  497. crq->msg_bucket = (u32) rc;
  498. memset(ioc, 0, sizeof(*ioc));
  499. ioc->type = CARM_MSG_ARRAY;
  500. ioc->subtype = CARM_ARRAY_INFO;
  501. ioc->array_id = (u8) array_idx;
  502. ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
  503. ioc->data_addr = cpu_to_le32(msg_data);
  504. spin_lock_irq(&host->lock);
  505. assert(host->state == HST_DEV_SCAN_START ||
  506. host->state == HST_DEV_SCAN);
  507. spin_unlock_irq(&host->lock);
  508. DPRINTK("blk_insert_request, tag == %u\n", idx);
  509. blk_insert_request(host->oob_q, crq->rq, 1, crq);
  510. return 0;
  511. err_out:
  512. spin_lock_irq(&host->lock);
  513. host->state = HST_ERROR;
  514. spin_unlock_irq(&host->lock);
  515. return rc;
  516. }
  517. typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *);
  518. static int carm_send_special (struct carm_host *host, carm_sspc_t func)
  519. {
  520. struct carm_request *crq;
  521. struct carm_msg_ioctl *ioc;
  522. void *mem;
  523. unsigned int idx, msg_size;
  524. int rc;
  525. crq = carm_get_special(host);
  526. if (!crq)
  527. return -ENOMEM;
  528. idx = crq->tag;
  529. mem = carm_ref_msg(host, idx);
  530. msg_size = func(host, idx, mem);
  531. ioc = mem;
  532. crq->msg_type = ioc->type;
  533. crq->msg_subtype = ioc->subtype;
  534. rc = carm_lookup_bucket(msg_size);
  535. BUG_ON(rc < 0);
  536. crq->msg_bucket = (u32) rc;
  537. DPRINTK("blk_insert_request, tag == %u\n", idx);
  538. blk_insert_request(host->oob_q, crq->rq, 1, crq);
  539. return 0;
  540. }
  541. static unsigned int carm_fill_sync_time(struct carm_host *host,
  542. unsigned int idx, void *mem)
  543. {
  544. struct timeval tv;
  545. struct carm_msg_sync_time *st = mem;
  546. do_gettimeofday(&tv);
  547. memset(st, 0, sizeof(*st));
  548. st->type = CARM_MSG_MISC;
  549. st->subtype = MISC_SET_TIME;
  550. st->handle = cpu_to_le32(TAG_ENCODE(idx));
  551. st->timestamp = cpu_to_le32(tv.tv_sec);
  552. return sizeof(struct carm_msg_sync_time);
  553. }
  554. static unsigned int carm_fill_alloc_buf(struct carm_host *host,
  555. unsigned int idx, void *mem)
  556. {
  557. struct carm_msg_allocbuf *ab = mem;
  558. memset(ab, 0, sizeof(*ab));
  559. ab->type = CARM_MSG_MISC;
  560. ab->subtype = MISC_ALLOC_MEM;
  561. ab->handle = cpu_to_le32(TAG_ENCODE(idx));
  562. ab->n_sg = 1;
  563. ab->sg_type = SGT_32BIT;
  564. ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
  565. ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1);
  566. ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024));
  567. ab->n_evt = cpu_to_le32(1024);
  568. ab->rbuf_pool = cpu_to_le32(host->shm_dma);
  569. ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN);
  570. ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN);
  571. ab->n_msg = cpu_to_le32(CARM_Q_LEN);
  572. ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
  573. ab->sg[0].len = cpu_to_le32(65536);
  574. return sizeof(struct carm_msg_allocbuf);
  575. }
  576. static unsigned int carm_fill_scan_channels(struct carm_host *host,
  577. unsigned int idx, void *mem)
  578. {
  579. struct carm_msg_ioctl *ioc = mem;
  580. u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) +
  581. IOC_SCAN_CHAN_OFFSET);
  582. memset(ioc, 0, sizeof(*ioc));
  583. ioc->type = CARM_MSG_IOCTL;
  584. ioc->subtype = CARM_IOC_SCAN_CHAN;
  585. ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
  586. ioc->data_addr = cpu_to_le32(msg_data);
  587. /* fill output data area with "no device" default values */
  588. mem += IOC_SCAN_CHAN_OFFSET;
  589. memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS);
  590. return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS;
  591. }
  592. static unsigned int carm_fill_get_fw_ver(struct carm_host *host,
  593. unsigned int idx, void *mem)
  594. {
  595. struct carm_msg_get_fw_ver *ioc = mem;
  596. u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc));
  597. memset(ioc, 0, sizeof(*ioc));
  598. ioc->type = CARM_MSG_MISC;
  599. ioc->subtype = MISC_GET_FW_VER;
  600. ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
  601. ioc->data_addr = cpu_to_le32(msg_data);
  602. return sizeof(struct carm_msg_get_fw_ver) +
  603. sizeof(struct carm_fw_ver);
  604. }
  605. static inline void carm_end_request_queued(struct carm_host *host,
  606. struct carm_request *crq,
  607. int uptodate)
  608. {
  609. struct request *req = crq->rq;
  610. int rc;
  611. rc = end_that_request_first(req, uptodate, req->hard_nr_sectors);
  612. assert(rc == 0);
  613. end_that_request_last(req);
  614. rc = carm_put_request(host, crq);
  615. assert(rc == 0);
  616. }
  617. static inline void carm_push_q (struct carm_host *host, request_queue_t *q)
  618. {
  619. unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q;
  620. blk_stop_queue(q);
  621. VPRINTK("STOPPED QUEUE %p\n", q);
  622. host->wait_q[idx] = q;
  623. host->wait_q_prod++;
  624. BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */
  625. }
  626. static inline request_queue_t *carm_pop_q(struct carm_host *host)
  627. {
  628. unsigned int idx;
  629. if (host->wait_q_prod == host->wait_q_cons)
  630. return NULL;
  631. idx = host->wait_q_cons % CARM_MAX_WAIT_Q;
  632. host->wait_q_cons++;
  633. return host->wait_q[idx];
  634. }
  635. static inline void carm_round_robin(struct carm_host *host)
  636. {
  637. request_queue_t *q = carm_pop_q(host);
  638. if (q) {
  639. blk_start_queue(q);
  640. VPRINTK("STARTED QUEUE %p\n", q);
  641. }
  642. }
  643. static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq,
  644. int is_ok)
  645. {
  646. carm_end_request_queued(host, crq, is_ok);
  647. if (CARM_MAX_Q == 1)
  648. carm_round_robin(host);
  649. else if ((host->n_msgs <= CARM_MSG_LOW_WATER) &&
  650. (host->hw_sg_used <= CARM_SG_LOW_WATER)) {
  651. carm_round_robin(host);
  652. }
  653. }
  654. static void carm_oob_rq_fn(request_queue_t *q)
  655. {
  656. struct carm_host *host = q->queuedata;
  657. struct carm_request *crq;
  658. struct request *rq;
  659. int rc;
  660. while (1) {
  661. DPRINTK("get req\n");
  662. rq = elv_next_request(q);
  663. if (!rq)
  664. break;
  665. blkdev_dequeue_request(rq);
  666. crq = rq->special;
  667. assert(crq != NULL);
  668. assert(crq->rq == rq);
  669. crq->n_elem = 0;
  670. DPRINTK("send req\n");
  671. rc = carm_send_msg(host, crq);
  672. if (rc) {
  673. blk_requeue_request(q, rq);
  674. carm_push_q(host, q);
  675. return; /* call us again later, eventually */
  676. }
  677. }
  678. }
  679. static void carm_rq_fn(request_queue_t *q)
  680. {
  681. struct carm_port *port = q->queuedata;
  682. struct carm_host *host = port->host;
  683. struct carm_msg_rw *msg;
  684. struct carm_request *crq;
  685. struct request *rq;
  686. struct scatterlist *sg;
  687. int writing = 0, pci_dir, i, n_elem, rc;
  688. u32 tmp;
  689. unsigned int msg_size;
  690. queue_one_request:
  691. VPRINTK("get req\n");
  692. rq = elv_next_request(q);
  693. if (!rq)
  694. return;
  695. crq = carm_get_request(host);
  696. if (!crq) {
  697. carm_push_q(host, q);
  698. return; /* call us again later, eventually */
  699. }
  700. crq->rq = rq;
  701. blkdev_dequeue_request(rq);
  702. if (rq_data_dir(rq) == WRITE) {
  703. writing = 1;
  704. pci_dir = PCI_DMA_TODEVICE;
  705. } else {
  706. pci_dir = PCI_DMA_FROMDEVICE;
  707. }
  708. /* get scatterlist from block layer */
  709. sg = &crq->sg[0];
  710. n_elem = blk_rq_map_sg(q, rq, sg);
  711. if (n_elem <= 0) {
  712. carm_end_rq(host, crq, 0);
  713. return; /* request with no s/g entries? */
  714. }
  715. /* map scatterlist to PCI bus addresses */
  716. n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir);
  717. if (n_elem <= 0) {
  718. carm_end_rq(host, crq, 0);
  719. return; /* request with no s/g entries? */
  720. }
  721. crq->n_elem = n_elem;
  722. crq->port = port;
  723. host->hw_sg_used += n_elem;
  724. /*
  725. * build read/write message
  726. */
  727. VPRINTK("build msg\n");
  728. msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag);
  729. if (writing) {
  730. msg->type = CARM_MSG_WRITE;
  731. crq->msg_type = CARM_MSG_WRITE;
  732. } else {
  733. msg->type = CARM_MSG_READ;
  734. crq->msg_type = CARM_MSG_READ;
  735. }
  736. msg->id = port->port_no;
  737. msg->sg_count = n_elem;
  738. msg->sg_type = SGT_32BIT;
  739. msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag));
  740. msg->lba = cpu_to_le32(rq->sector & 0xffffffff);
  741. tmp = (rq->sector >> 16) >> 16;
  742. msg->lba_high = cpu_to_le16( (u16) tmp );
  743. msg->lba_count = cpu_to_le16(rq->nr_sectors);
  744. msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg);
  745. for (i = 0; i < n_elem; i++) {
  746. struct carm_msg_sg *carm_sg = &msg->sg[i];
  747. carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i]));
  748. carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i]));
  749. msg_size += sizeof(struct carm_msg_sg);
  750. }
  751. rc = carm_lookup_bucket(msg_size);
  752. BUG_ON(rc < 0);
  753. crq->msg_bucket = (u32) rc;
  754. /*
  755. * queue read/write message to hardware
  756. */
  757. VPRINTK("send msg, tag == %u\n", crq->tag);
  758. rc = carm_send_msg(host, crq);
  759. if (rc) {
  760. carm_put_request(host, crq);
  761. blk_requeue_request(q, rq);
  762. carm_push_q(host, q);
  763. return; /* call us again later, eventually */
  764. }
  765. goto queue_one_request;
  766. }
  767. static void carm_handle_array_info(struct carm_host *host,
  768. struct carm_request *crq, u8 *mem,
  769. int is_ok)
  770. {
  771. struct carm_port *port;
  772. u8 *msg_data = mem + sizeof(struct carm_array_info);
  773. struct carm_array_info *desc = (struct carm_array_info *) msg_data;
  774. u64 lo, hi;
  775. int cur_port;
  776. size_t slen;
  777. DPRINTK("ENTER\n");
  778. carm_end_rq(host, crq, is_ok);
  779. if (!is_ok)
  780. goto out;
  781. if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST)
  782. goto out;
  783. cur_port = host->cur_scan_dev;
  784. /* should never occur */
  785. if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) {
  786. printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n",
  787. cur_port, (int) desc->array_id);
  788. goto out;
  789. }
  790. port = &host->port[cur_port];
  791. lo = (u64) le32_to_cpu(desc->size);
  792. hi = (u64) le16_to_cpu(desc->size_hi);
  793. port->capacity = lo | (hi << 32);
  794. port->dev_geom_head = le16_to_cpu(desc->head);
  795. port->dev_geom_sect = le16_to_cpu(desc->sect);
  796. port->dev_geom_cyl = le16_to_cpu(desc->cyl);
  797. host->dev_active |= (1 << cur_port);
  798. strncpy(port->name, desc->name, sizeof(port->name));
  799. port->name[sizeof(port->name) - 1] = 0;
  800. slen = strlen(port->name);
  801. while (slen && (port->name[slen - 1] == ' ')) {
  802. port->name[slen - 1] = 0;
  803. slen--;
  804. }
  805. printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n",
  806. pci_name(host->pdev), port->port_no,
  807. (unsigned long long) port->capacity);
  808. printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n",
  809. pci_name(host->pdev), port->port_no, port->name);
  810. out:
  811. assert(host->state == HST_DEV_SCAN);
  812. schedule_work(&host->fsm_task);
  813. }
  814. static void carm_handle_scan_chan(struct carm_host *host,
  815. struct carm_request *crq, u8 *mem,
  816. int is_ok)
  817. {
  818. u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET;
  819. unsigned int i, dev_count = 0;
  820. int new_state = HST_DEV_SCAN_START;
  821. DPRINTK("ENTER\n");
  822. carm_end_rq(host, crq, is_ok);
  823. if (!is_ok) {
  824. new_state = HST_ERROR;
  825. goto out;
  826. }
  827. /* TODO: scan and support non-disk devices */
  828. for (i = 0; i < 8; i++)
  829. if (msg_data[i] == 0) { /* direct-access device (disk) */
  830. host->dev_present |= (1 << i);
  831. dev_count++;
  832. }
  833. printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n",
  834. pci_name(host->pdev), dev_count);
  835. out:
  836. assert(host->state == HST_PORT_SCAN);
  837. host->state = new_state;
  838. schedule_work(&host->fsm_task);
  839. }
  840. static void carm_handle_generic(struct carm_host *host,
  841. struct carm_request *crq, int is_ok,
  842. int cur_state, int next_state)
  843. {
  844. DPRINTK("ENTER\n");
  845. carm_end_rq(host, crq, is_ok);
  846. assert(host->state == cur_state);
  847. if (is_ok)
  848. host->state = next_state;
  849. else
  850. host->state = HST_ERROR;
  851. schedule_work(&host->fsm_task);
  852. }
  853. static inline void carm_handle_rw(struct carm_host *host,
  854. struct carm_request *crq, int is_ok)
  855. {
  856. int pci_dir;
  857. VPRINTK("ENTER\n");
  858. if (rq_data_dir(crq->rq) == WRITE)
  859. pci_dir = PCI_DMA_TODEVICE;
  860. else
  861. pci_dir = PCI_DMA_FROMDEVICE;
  862. pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir);
  863. carm_end_rq(host, crq, is_ok);
  864. }
  865. static inline void carm_handle_resp(struct carm_host *host,
  866. __le32 ret_handle_le, u32 status)
  867. {
  868. u32 handle = le32_to_cpu(ret_handle_le);
  869. unsigned int msg_idx;
  870. struct carm_request *crq;
  871. int is_ok = (status == RMSG_OK);
  872. u8 *mem;
  873. VPRINTK("ENTER, handle == 0x%x\n", handle);
  874. if (unlikely(!TAG_VALID(handle))) {
  875. printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n",
  876. pci_name(host->pdev), handle);
  877. return;
  878. }
  879. msg_idx = TAG_DECODE(handle);
  880. VPRINTK("tag == %u\n", msg_idx);
  881. crq = &host->req[msg_idx];
  882. /* fast path */
  883. if (likely(crq->msg_type == CARM_MSG_READ ||
  884. crq->msg_type == CARM_MSG_WRITE)) {
  885. carm_handle_rw(host, crq, is_ok);
  886. return;
  887. }
  888. mem = carm_ref_msg(host, msg_idx);
  889. switch (crq->msg_type) {
  890. case CARM_MSG_IOCTL: {
  891. switch (crq->msg_subtype) {
  892. case CARM_IOC_SCAN_CHAN:
  893. carm_handle_scan_chan(host, crq, mem, is_ok);
  894. break;
  895. default:
  896. /* unknown / invalid response */
  897. goto err_out;
  898. }
  899. break;
  900. }
  901. case CARM_MSG_MISC: {
  902. switch (crq->msg_subtype) {
  903. case MISC_ALLOC_MEM:
  904. carm_handle_generic(host, crq, is_ok,
  905. HST_ALLOC_BUF, HST_SYNC_TIME);
  906. break;
  907. case MISC_SET_TIME:
  908. carm_handle_generic(host, crq, is_ok,
  909. HST_SYNC_TIME, HST_GET_FW_VER);
  910. break;
  911. case MISC_GET_FW_VER: {
  912. struct carm_fw_ver *ver = (struct carm_fw_ver *)
  913. mem + sizeof(struct carm_msg_get_fw_ver);
  914. if (is_ok) {
  915. host->fw_ver = le32_to_cpu(ver->version);
  916. host->flags |= (ver->features & FL_FW_VER_MASK);
  917. }
  918. carm_handle_generic(host, crq, is_ok,
  919. HST_GET_FW_VER, HST_PORT_SCAN);
  920. break;
  921. }
  922. default:
  923. /* unknown / invalid response */
  924. goto err_out;
  925. }
  926. break;
  927. }
  928. case CARM_MSG_ARRAY: {
  929. switch (crq->msg_subtype) {
  930. case CARM_ARRAY_INFO:
  931. carm_handle_array_info(host, crq, mem, is_ok);
  932. break;
  933. default:
  934. /* unknown / invalid response */
  935. goto err_out;
  936. }
  937. break;
  938. }
  939. default:
  940. /* unknown / invalid response */
  941. goto err_out;
  942. }
  943. return;
  944. err_out:
  945. printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n",
  946. pci_name(host->pdev), crq->msg_type, crq->msg_subtype);
  947. carm_end_rq(host, crq, 0);
  948. }
  949. static inline void carm_handle_responses(struct carm_host *host)
  950. {
  951. void __iomem *mmio = host->mmio;
  952. struct carm_response *resp = (struct carm_response *) host->shm;
  953. unsigned int work = 0;
  954. unsigned int idx = host->resp_idx % RMSG_Q_LEN;
  955. while (1) {
  956. u32 status = le32_to_cpu(resp[idx].status);
  957. if (status == 0xffffffff) {
  958. VPRINTK("ending response on index %u\n", idx);
  959. writel(idx << 3, mmio + CARM_RESP_IDX);
  960. break;
  961. }
  962. /* response to a message we sent */
  963. else if ((status & (1 << 31)) == 0) {
  964. VPRINTK("handling msg response on index %u\n", idx);
  965. carm_handle_resp(host, resp[idx].ret_handle, status);
  966. resp[idx].status = cpu_to_le32(0xffffffff);
  967. }
  968. /* asynchronous events the hardware throws our way */
  969. else if ((status & 0xff000000) == (1 << 31)) {
  970. u8 *evt_type_ptr = (u8 *) &resp[idx];
  971. u8 evt_type = *evt_type_ptr;
  972. printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n",
  973. pci_name(host->pdev), (int) evt_type);
  974. resp[idx].status = cpu_to_le32(0xffffffff);
  975. }
  976. idx = NEXT_RESP(idx);
  977. work++;
  978. }
  979. VPRINTK("EXIT, work==%u\n", work);
  980. host->resp_idx += work;
  981. }
  982. static irqreturn_t carm_interrupt(int irq, void *__host, struct pt_regs *regs)
  983. {
  984. struct carm_host *host = __host;
  985. void __iomem *mmio;
  986. u32 mask;
  987. int handled = 0;
  988. unsigned long flags;
  989. if (!host) {
  990. VPRINTK("no host\n");
  991. return IRQ_NONE;
  992. }
  993. spin_lock_irqsave(&host->lock, flags);
  994. mmio = host->mmio;
  995. /* reading should also clear interrupts */
  996. mask = readl(mmio + CARM_INT_STAT);
  997. if (mask == 0 || mask == 0xffffffff) {
  998. VPRINTK("no work, mask == 0x%x\n", mask);
  999. goto out;
  1000. }
  1001. if (mask & INT_ACK_MASK)
  1002. writel(mask, mmio + CARM_INT_STAT);
  1003. if (unlikely(host->state == HST_INVALID)) {
  1004. VPRINTK("not initialized yet, mask = 0x%x\n", mask);
  1005. goto out;
  1006. }
  1007. if (mask & CARM_HAVE_RESP) {
  1008. handled = 1;
  1009. carm_handle_responses(host);
  1010. }
  1011. out:
  1012. spin_unlock_irqrestore(&host->lock, flags);
  1013. VPRINTK("EXIT\n");
  1014. return IRQ_RETVAL(handled);
  1015. }
  1016. static void carm_fsm_task (void *_data)
  1017. {
  1018. struct carm_host *host = _data;
  1019. unsigned long flags;
  1020. unsigned int state;
  1021. int rc, i, next_dev;
  1022. int reschedule = 0;
  1023. int new_state = HST_INVALID;
  1024. spin_lock_irqsave(&host->lock, flags);
  1025. state = host->state;
  1026. spin_unlock_irqrestore(&host->lock, flags);
  1027. DPRINTK("ENTER, state == %s\n", state_name[state]);
  1028. switch (state) {
  1029. case HST_PROBE_START:
  1030. new_state = HST_ALLOC_BUF;
  1031. reschedule = 1;
  1032. break;
  1033. case HST_ALLOC_BUF:
  1034. rc = carm_send_special(host, carm_fill_alloc_buf);
  1035. if (rc) {
  1036. new_state = HST_ERROR;
  1037. reschedule = 1;
  1038. }
  1039. break;
  1040. case HST_SYNC_TIME:
  1041. rc = carm_send_special(host, carm_fill_sync_time);
  1042. if (rc) {
  1043. new_state = HST_ERROR;
  1044. reschedule = 1;
  1045. }
  1046. break;
  1047. case HST_GET_FW_VER:
  1048. rc = carm_send_special(host, carm_fill_get_fw_ver);
  1049. if (rc) {
  1050. new_state = HST_ERROR;
  1051. reschedule = 1;
  1052. }
  1053. break;
  1054. case HST_PORT_SCAN:
  1055. rc = carm_send_special(host, carm_fill_scan_channels);
  1056. if (rc) {
  1057. new_state = HST_ERROR;
  1058. reschedule = 1;
  1059. }
  1060. break;
  1061. case HST_DEV_SCAN_START:
  1062. host->cur_scan_dev = -1;
  1063. new_state = HST_DEV_SCAN;
  1064. reschedule = 1;
  1065. break;
  1066. case HST_DEV_SCAN:
  1067. next_dev = -1;
  1068. for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++)
  1069. if (host->dev_present & (1 << i)) {
  1070. next_dev = i;
  1071. break;
  1072. }
  1073. if (next_dev >= 0) {
  1074. host->cur_scan_dev = next_dev;
  1075. rc = carm_array_info(host, next_dev);
  1076. if (rc) {
  1077. new_state = HST_ERROR;
  1078. reschedule = 1;
  1079. }
  1080. } else {
  1081. new_state = HST_DEV_ACTIVATE;
  1082. reschedule = 1;
  1083. }
  1084. break;
  1085. case HST_DEV_ACTIVATE: {
  1086. int activated = 0;
  1087. for (i = 0; i < CARM_MAX_PORTS; i++)
  1088. if (host->dev_active & (1 << i)) {
  1089. struct carm_port *port = &host->port[i];
  1090. struct gendisk *disk = port->disk;
  1091. set_capacity(disk, port->capacity);
  1092. add_disk(disk);
  1093. activated++;
  1094. }
  1095. printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n",
  1096. pci_name(host->pdev), activated);
  1097. new_state = HST_PROBE_FINISHED;
  1098. reschedule = 1;
  1099. break;
  1100. }
  1101. case HST_PROBE_FINISHED:
  1102. up(&host->probe_sem);
  1103. break;
  1104. case HST_ERROR:
  1105. /* FIXME: TODO */
  1106. break;
  1107. default:
  1108. /* should never occur */
  1109. printk(KERN_ERR PFX "BUG: unknown state %d\n", state);
  1110. assert(0);
  1111. break;
  1112. }
  1113. if (new_state != HST_INVALID) {
  1114. spin_lock_irqsave(&host->lock, flags);
  1115. host->state = new_state;
  1116. spin_unlock_irqrestore(&host->lock, flags);
  1117. }
  1118. if (reschedule)
  1119. schedule_work(&host->fsm_task);
  1120. }
  1121. static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit)
  1122. {
  1123. unsigned int i;
  1124. for (i = 0; i < 50000; i++) {
  1125. u32 tmp = readl(mmio + CARM_LMUC);
  1126. udelay(100);
  1127. if (test_bit) {
  1128. if ((tmp & bits) == bits)
  1129. return 0;
  1130. } else {
  1131. if ((tmp & bits) == 0)
  1132. return 0;
  1133. }
  1134. cond_resched();
  1135. }
  1136. printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n",
  1137. bits, test_bit ? "yes" : "no");
  1138. return -EBUSY;
  1139. }
  1140. static void carm_init_responses(struct carm_host *host)
  1141. {
  1142. void __iomem *mmio = host->mmio;
  1143. unsigned int i;
  1144. struct carm_response *resp = (struct carm_response *) host->shm;
  1145. for (i = 0; i < RMSG_Q_LEN; i++)
  1146. resp[i].status = cpu_to_le32(0xffffffff);
  1147. writel(0, mmio + CARM_RESP_IDX);
  1148. }
  1149. static int carm_init_host(struct carm_host *host)
  1150. {
  1151. void __iomem *mmio = host->mmio;
  1152. u32 tmp;
  1153. u8 tmp8;
  1154. int rc;
  1155. DPRINTK("ENTER\n");
  1156. writel(0, mmio + CARM_INT_MASK);
  1157. tmp8 = readb(mmio + CARM_INITC);
  1158. if (tmp8 & 0x01) {
  1159. tmp8 &= ~0x01;
  1160. writeb(tmp8, mmio + CARM_INITC);
  1161. readb(mmio + CARM_INITC); /* flush */
  1162. DPRINTK("snooze...\n");
  1163. msleep(5000);
  1164. }
  1165. tmp = readl(mmio + CARM_HMUC);
  1166. if (tmp & CARM_CME) {
  1167. DPRINTK("CME bit present, waiting\n");
  1168. rc = carm_init_wait(mmio, CARM_CME, 1);
  1169. if (rc) {
  1170. DPRINTK("EXIT, carm_init_wait 1 failed\n");
  1171. return rc;
  1172. }
  1173. }
  1174. if (tmp & CARM_RME) {
  1175. DPRINTK("RME bit present, waiting\n");
  1176. rc = carm_init_wait(mmio, CARM_RME, 1);
  1177. if (rc) {
  1178. DPRINTK("EXIT, carm_init_wait 2 failed\n");
  1179. return rc;
  1180. }
  1181. }
  1182. tmp &= ~(CARM_RME | CARM_CME);
  1183. writel(tmp, mmio + CARM_HMUC);
  1184. readl(mmio + CARM_HMUC); /* flush */
  1185. rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0);
  1186. if (rc) {
  1187. DPRINTK("EXIT, carm_init_wait 3 failed\n");
  1188. return rc;
  1189. }
  1190. carm_init_buckets(mmio);
  1191. writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO);
  1192. writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI);
  1193. writel(RBUF_LEN, mmio + RBUF_BYTE_SZ);
  1194. tmp = readl(mmio + CARM_HMUC);
  1195. tmp |= (CARM_RME | CARM_CME | CARM_WZBC);
  1196. writel(tmp, mmio + CARM_HMUC);
  1197. readl(mmio + CARM_HMUC); /* flush */
  1198. rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1);
  1199. if (rc) {
  1200. DPRINTK("EXIT, carm_init_wait 4 failed\n");
  1201. return rc;
  1202. }
  1203. writel(0, mmio + CARM_HMPHA);
  1204. writel(INT_DEF_MASK, mmio + CARM_INT_MASK);
  1205. carm_init_responses(host);
  1206. /* start initialization, probing state machine */
  1207. spin_lock_irq(&host->lock);
  1208. assert(host->state == HST_INVALID);
  1209. host->state = HST_PROBE_START;
  1210. spin_unlock_irq(&host->lock);
  1211. schedule_work(&host->fsm_task);
  1212. DPRINTK("EXIT\n");
  1213. return 0;
  1214. }
  1215. static int carm_init_disks(struct carm_host *host)
  1216. {
  1217. unsigned int i;
  1218. int rc = 0;
  1219. for (i = 0; i < CARM_MAX_PORTS; i++) {
  1220. struct gendisk *disk;
  1221. request_queue_t *q;
  1222. struct carm_port *port;
  1223. port = &host->port[i];
  1224. port->host = host;
  1225. port->port_no = i;
  1226. disk = alloc_disk(CARM_MINORS_PER_MAJOR);
  1227. if (!disk) {
  1228. rc = -ENOMEM;
  1229. break;
  1230. }
  1231. port->disk = disk;
  1232. sprintf(disk->disk_name, DRV_NAME "/%u",
  1233. (unsigned int) (host->id * CARM_MAX_PORTS) + i);
  1234. sprintf(disk->devfs_name, DRV_NAME "/%u_%u", host->id, i);
  1235. disk->major = host->major;
  1236. disk->first_minor = i * CARM_MINORS_PER_MAJOR;
  1237. disk->fops = &carm_bd_ops;
  1238. disk->private_data = port;
  1239. q = blk_init_queue(carm_rq_fn, &host->lock);
  1240. if (!q) {
  1241. rc = -ENOMEM;
  1242. break;
  1243. }
  1244. disk->queue = q;
  1245. blk_queue_max_hw_segments(q, CARM_MAX_REQ_SG);
  1246. blk_queue_max_phys_segments(q, CARM_MAX_REQ_SG);
  1247. blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
  1248. q->queuedata = port;
  1249. }
  1250. return rc;
  1251. }
  1252. static void carm_free_disks(struct carm_host *host)
  1253. {
  1254. unsigned int i;
  1255. for (i = 0; i < CARM_MAX_PORTS; i++) {
  1256. struct gendisk *disk = host->port[i].disk;
  1257. if (disk) {
  1258. request_queue_t *q = disk->queue;
  1259. if (disk->flags & GENHD_FL_UP)
  1260. del_gendisk(disk);
  1261. if (q)
  1262. blk_cleanup_queue(q);
  1263. put_disk(disk);
  1264. }
  1265. }
  1266. }
  1267. static int carm_init_shm(struct carm_host *host)
  1268. {
  1269. host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE,
  1270. &host->shm_dma);
  1271. if (!host->shm)
  1272. return -ENOMEM;
  1273. host->msg_base = host->shm + RBUF_LEN;
  1274. host->msg_dma = host->shm_dma + RBUF_LEN;
  1275. memset(host->shm, 0xff, RBUF_LEN);
  1276. memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN);
  1277. return 0;
  1278. }
  1279. static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  1280. {
  1281. static unsigned int printed_version;
  1282. struct carm_host *host;
  1283. unsigned int pci_dac;
  1284. int rc;
  1285. request_queue_t *q;
  1286. unsigned int i;
  1287. if (!printed_version++)
  1288. printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
  1289. rc = pci_enable_device(pdev);
  1290. if (rc)
  1291. return rc;
  1292. rc = pci_request_regions(pdev, DRV_NAME);
  1293. if (rc)
  1294. goto err_out;
  1295. #if IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
  1296. rc = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
  1297. if (!rc) {
  1298. rc = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
  1299. if (rc) {
  1300. printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n",
  1301. pci_name(pdev));
  1302. goto err_out_regions;
  1303. }
  1304. pci_dac = 1;
  1305. } else {
  1306. #endif
  1307. rc = pci_set_dma_mask(pdev, 0xffffffffULL);
  1308. if (rc) {
  1309. printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n",
  1310. pci_name(pdev));
  1311. goto err_out_regions;
  1312. }
  1313. pci_dac = 0;
  1314. #if IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
  1315. }
  1316. #endif
  1317. host = kmalloc(sizeof(*host), GFP_KERNEL);
  1318. if (!host) {
  1319. printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n",
  1320. pci_name(pdev));
  1321. rc = -ENOMEM;
  1322. goto err_out_regions;
  1323. }
  1324. memset(host, 0, sizeof(*host));
  1325. host->pdev = pdev;
  1326. host->flags = pci_dac ? FL_DAC : 0;
  1327. spin_lock_init(&host->lock);
  1328. INIT_WORK(&host->fsm_task, carm_fsm_task, host);
  1329. init_MUTEX_LOCKED(&host->probe_sem);
  1330. for (i = 0; i < ARRAY_SIZE(host->req); i++)
  1331. host->req[i].tag = i;
  1332. host->mmio = ioremap(pci_resource_start(pdev, 0),
  1333. pci_resource_len(pdev, 0));
  1334. if (!host->mmio) {
  1335. printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n",
  1336. pci_name(pdev));
  1337. rc = -ENOMEM;
  1338. goto err_out_kfree;
  1339. }
  1340. rc = carm_init_shm(host);
  1341. if (rc) {
  1342. printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n",
  1343. pci_name(pdev));
  1344. goto err_out_iounmap;
  1345. }
  1346. q = blk_init_queue(carm_oob_rq_fn, &host->lock);
  1347. if (!q) {
  1348. printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n",
  1349. pci_name(pdev));
  1350. rc = -ENOMEM;
  1351. goto err_out_pci_free;
  1352. }
  1353. host->oob_q = q;
  1354. q->queuedata = host;
  1355. /*
  1356. * Figure out which major to use: 160, 161, or dynamic
  1357. */
  1358. if (!test_and_set_bit(0, &carm_major_alloc))
  1359. host->major = 160;
  1360. else if (!test_and_set_bit(1, &carm_major_alloc))
  1361. host->major = 161;
  1362. else
  1363. host->flags |= FL_DYN_MAJOR;
  1364. host->id = carm_host_id;
  1365. sprintf(host->name, DRV_NAME "%d", carm_host_id);
  1366. rc = register_blkdev(host->major, host->name);
  1367. if (rc < 0)
  1368. goto err_out_free_majors;
  1369. if (host->flags & FL_DYN_MAJOR)
  1370. host->major = rc;
  1371. devfs_mk_dir(DRV_NAME);
  1372. rc = carm_init_disks(host);
  1373. if (rc)
  1374. goto err_out_blkdev_disks;
  1375. pci_set_master(pdev);
  1376. rc = request_irq(pdev->irq, carm_interrupt, SA_SHIRQ, DRV_NAME, host);
  1377. if (rc) {
  1378. printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n",
  1379. pci_name(pdev));
  1380. goto err_out_blkdev_disks;
  1381. }
  1382. rc = carm_init_host(host);
  1383. if (rc)
  1384. goto err_out_free_irq;
  1385. DPRINTK("waiting for probe_sem\n");
  1386. down(&host->probe_sem);
  1387. printk(KERN_INFO "%s: pci %s, ports %d, io %lx, irq %u, major %d\n",
  1388. host->name, pci_name(pdev), (int) CARM_MAX_PORTS,
  1389. pci_resource_start(pdev, 0), pdev->irq, host->major);
  1390. carm_host_id++;
  1391. pci_set_drvdata(pdev, host);
  1392. return 0;
  1393. err_out_free_irq:
  1394. free_irq(pdev->irq, host);
  1395. err_out_blkdev_disks:
  1396. carm_free_disks(host);
  1397. unregister_blkdev(host->major, host->name);
  1398. err_out_free_majors:
  1399. if (host->major == 160)
  1400. clear_bit(0, &carm_major_alloc);
  1401. else if (host->major == 161)
  1402. clear_bit(1, &carm_major_alloc);
  1403. blk_cleanup_queue(host->oob_q);
  1404. err_out_pci_free:
  1405. pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
  1406. err_out_iounmap:
  1407. iounmap(host->mmio);
  1408. err_out_kfree:
  1409. kfree(host);
  1410. err_out_regions:
  1411. pci_release_regions(pdev);
  1412. err_out:
  1413. pci_disable_device(pdev);
  1414. return rc;
  1415. }
  1416. static void carm_remove_one (struct pci_dev *pdev)
  1417. {
  1418. struct carm_host *host = pci_get_drvdata(pdev);
  1419. if (!host) {
  1420. printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n",
  1421. pci_name(pdev));
  1422. return;
  1423. }
  1424. free_irq(pdev->irq, host);
  1425. carm_free_disks(host);
  1426. devfs_remove(DRV_NAME);
  1427. unregister_blkdev(host->major, host->name);
  1428. if (host->major == 160)
  1429. clear_bit(0, &carm_major_alloc);
  1430. else if (host->major == 161)
  1431. clear_bit(1, &carm_major_alloc);
  1432. blk_cleanup_queue(host->oob_q);
  1433. pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
  1434. iounmap(host->mmio);
  1435. kfree(host);
  1436. pci_release_regions(pdev);
  1437. pci_disable_device(pdev);
  1438. pci_set_drvdata(pdev, NULL);
  1439. }
  1440. static int __init carm_init(void)
  1441. {
  1442. return pci_module_init(&carm_driver);
  1443. }
  1444. static void __exit carm_exit(void)
  1445. {
  1446. pci_unregister_driver(&carm_driver);
  1447. }
  1448. module_init(carm_init);
  1449. module_exit(carm_exit);