pci.c 25 KB

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  1. /*
  2. * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
  3. *
  4. * PCI Bus Services, see include/linux/pci.h for further explanation.
  5. *
  6. * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
  7. * David Mosberger-Tang
  8. *
  9. * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/delay.h>
  13. #include <linux/init.h>
  14. #include <linux/pci.h>
  15. #include <linux/module.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/string.h>
  18. #include <asm/dma.h> /* isa_dma_bridge_buggy */
  19. #include "pci.h"
  20. /**
  21. * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
  22. * @bus: pointer to PCI bus structure to search
  23. *
  24. * Given a PCI bus, returns the highest PCI bus number present in the set
  25. * including the given PCI bus and its list of child PCI buses.
  26. */
  27. unsigned char __devinit
  28. pci_bus_max_busnr(struct pci_bus* bus)
  29. {
  30. struct list_head *tmp;
  31. unsigned char max, n;
  32. max = bus->subordinate;
  33. list_for_each(tmp, &bus->children) {
  34. n = pci_bus_max_busnr(pci_bus_b(tmp));
  35. if(n > max)
  36. max = n;
  37. }
  38. return max;
  39. }
  40. EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
  41. #if 0
  42. /**
  43. * pci_max_busnr - returns maximum PCI bus number
  44. *
  45. * Returns the highest PCI bus number present in the system global list of
  46. * PCI buses.
  47. */
  48. unsigned char __devinit
  49. pci_max_busnr(void)
  50. {
  51. struct pci_bus *bus = NULL;
  52. unsigned char max, n;
  53. max = 0;
  54. while ((bus = pci_find_next_bus(bus)) != NULL) {
  55. n = pci_bus_max_busnr(bus);
  56. if(n > max)
  57. max = n;
  58. }
  59. return max;
  60. }
  61. #endif /* 0 */
  62. static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
  63. {
  64. u8 id;
  65. int ttl = 48;
  66. while (ttl--) {
  67. pci_bus_read_config_byte(bus, devfn, pos, &pos);
  68. if (pos < 0x40)
  69. break;
  70. pos &= ~3;
  71. pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
  72. &id);
  73. if (id == 0xff)
  74. break;
  75. if (id == cap)
  76. return pos;
  77. pos += PCI_CAP_LIST_NEXT;
  78. }
  79. return 0;
  80. }
  81. int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
  82. {
  83. return __pci_find_next_cap(dev->bus, dev->devfn,
  84. pos + PCI_CAP_LIST_NEXT, cap);
  85. }
  86. EXPORT_SYMBOL_GPL(pci_find_next_capability);
  87. static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
  88. {
  89. u16 status;
  90. u8 pos;
  91. pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
  92. if (!(status & PCI_STATUS_CAP_LIST))
  93. return 0;
  94. switch (hdr_type) {
  95. case PCI_HEADER_TYPE_NORMAL:
  96. case PCI_HEADER_TYPE_BRIDGE:
  97. pos = PCI_CAPABILITY_LIST;
  98. break;
  99. case PCI_HEADER_TYPE_CARDBUS:
  100. pos = PCI_CB_CAPABILITY_LIST;
  101. break;
  102. default:
  103. return 0;
  104. }
  105. return __pci_find_next_cap(bus, devfn, pos, cap);
  106. }
  107. /**
  108. * pci_find_capability - query for devices' capabilities
  109. * @dev: PCI device to query
  110. * @cap: capability code
  111. *
  112. * Tell if a device supports a given PCI capability.
  113. * Returns the address of the requested capability structure within the
  114. * device's PCI configuration space or 0 in case the device does not
  115. * support it. Possible values for @cap:
  116. *
  117. * %PCI_CAP_ID_PM Power Management
  118. * %PCI_CAP_ID_AGP Accelerated Graphics Port
  119. * %PCI_CAP_ID_VPD Vital Product Data
  120. * %PCI_CAP_ID_SLOTID Slot Identification
  121. * %PCI_CAP_ID_MSI Message Signalled Interrupts
  122. * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
  123. * %PCI_CAP_ID_PCIX PCI-X
  124. * %PCI_CAP_ID_EXP PCI Express
  125. */
  126. int pci_find_capability(struct pci_dev *dev, int cap)
  127. {
  128. return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
  129. }
  130. /**
  131. * pci_bus_find_capability - query for devices' capabilities
  132. * @bus: the PCI bus to query
  133. * @devfn: PCI device to query
  134. * @cap: capability code
  135. *
  136. * Like pci_find_capability() but works for pci devices that do not have a
  137. * pci_dev structure set up yet.
  138. *
  139. * Returns the address of the requested capability structure within the
  140. * device's PCI configuration space or 0 in case the device does not
  141. * support it.
  142. */
  143. int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
  144. {
  145. u8 hdr_type;
  146. pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
  147. return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
  148. }
  149. #if 0
  150. /**
  151. * pci_find_ext_capability - Find an extended capability
  152. * @dev: PCI device to query
  153. * @cap: capability code
  154. *
  155. * Returns the address of the requested extended capability structure
  156. * within the device's PCI configuration space or 0 if the device does
  157. * not support it. Possible values for @cap:
  158. *
  159. * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
  160. * %PCI_EXT_CAP_ID_VC Virtual Channel
  161. * %PCI_EXT_CAP_ID_DSN Device Serial Number
  162. * %PCI_EXT_CAP_ID_PWR Power Budgeting
  163. */
  164. int pci_find_ext_capability(struct pci_dev *dev, int cap)
  165. {
  166. u32 header;
  167. int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
  168. int pos = 0x100;
  169. if (dev->cfg_size <= 256)
  170. return 0;
  171. if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
  172. return 0;
  173. /*
  174. * If we have no capabilities, this is indicated by cap ID,
  175. * cap version and next pointer all being 0.
  176. */
  177. if (header == 0)
  178. return 0;
  179. while (ttl-- > 0) {
  180. if (PCI_EXT_CAP_ID(header) == cap)
  181. return pos;
  182. pos = PCI_EXT_CAP_NEXT(header);
  183. if (pos < 0x100)
  184. break;
  185. if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
  186. break;
  187. }
  188. return 0;
  189. }
  190. #endif /* 0 */
  191. /**
  192. * pci_find_parent_resource - return resource region of parent bus of given region
  193. * @dev: PCI device structure contains resources to be searched
  194. * @res: child resource record for which parent is sought
  195. *
  196. * For given resource region of given device, return the resource
  197. * region of parent bus the given region is contained in or where
  198. * it should be allocated from.
  199. */
  200. struct resource *
  201. pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
  202. {
  203. const struct pci_bus *bus = dev->bus;
  204. int i;
  205. struct resource *best = NULL;
  206. for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
  207. struct resource *r = bus->resource[i];
  208. if (!r)
  209. continue;
  210. if (res->start && !(res->start >= r->start && res->end <= r->end))
  211. continue; /* Not contained */
  212. if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
  213. continue; /* Wrong type */
  214. if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
  215. return r; /* Exact match */
  216. if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
  217. best = r; /* Approximating prefetchable by non-prefetchable */
  218. }
  219. return best;
  220. }
  221. /**
  222. * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
  223. * @dev: PCI device to have its BARs restored
  224. *
  225. * Restore the BAR values for a given device, so as to make it
  226. * accessible by its driver.
  227. */
  228. void
  229. pci_restore_bars(struct pci_dev *dev)
  230. {
  231. int i, numres;
  232. switch (dev->hdr_type) {
  233. case PCI_HEADER_TYPE_NORMAL:
  234. numres = 6;
  235. break;
  236. case PCI_HEADER_TYPE_BRIDGE:
  237. numres = 2;
  238. break;
  239. case PCI_HEADER_TYPE_CARDBUS:
  240. numres = 1;
  241. break;
  242. default:
  243. /* Should never get here, but just in case... */
  244. return;
  245. }
  246. for (i = 0; i < numres; i ++)
  247. pci_update_resource(dev, &dev->resource[i], i);
  248. }
  249. int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
  250. /**
  251. * pci_set_power_state - Set the power state of a PCI device
  252. * @dev: PCI device to be suspended
  253. * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
  254. *
  255. * Transition a device to a new power state, using the Power Management
  256. * Capabilities in the device's config space.
  257. *
  258. * RETURN VALUE:
  259. * -EINVAL if trying to enter a lower state than we're already in.
  260. * 0 if we're already in the requested state.
  261. * -EIO if device does not support PCI PM.
  262. * 0 if we can successfully change the power state.
  263. */
  264. int
  265. pci_set_power_state(struct pci_dev *dev, pci_power_t state)
  266. {
  267. int pm, need_restore = 0;
  268. u16 pmcsr, pmc;
  269. /* bound the state we're entering */
  270. if (state > PCI_D3hot)
  271. state = PCI_D3hot;
  272. /* Validate current state:
  273. * Can enter D0 from any state, but if we can only go deeper
  274. * to sleep if we're already in a low power state
  275. */
  276. if (state != PCI_D0 && dev->current_state > state) {
  277. printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
  278. __FUNCTION__, pci_name(dev), state, dev->current_state);
  279. return -EINVAL;
  280. } else if (dev->current_state == state)
  281. return 0; /* we're already there */
  282. /* find PCI PM capability in list */
  283. pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  284. /* abort if the device doesn't support PM capabilities */
  285. if (!pm)
  286. return -EIO;
  287. pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
  288. if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
  289. printk(KERN_DEBUG
  290. "PCI: %s has unsupported PM cap regs version (%u)\n",
  291. pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
  292. return -EIO;
  293. }
  294. /* check if this device supports the desired state */
  295. if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
  296. return -EIO;
  297. else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
  298. return -EIO;
  299. pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
  300. /* If we're (effectively) in D3, force entire word to 0.
  301. * This doesn't affect PME_Status, disables PME_En, and
  302. * sets PowerState to 0.
  303. */
  304. switch (dev->current_state) {
  305. case PCI_D0:
  306. case PCI_D1:
  307. case PCI_D2:
  308. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  309. pmcsr |= state;
  310. break;
  311. case PCI_UNKNOWN: /* Boot-up */
  312. if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
  313. && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
  314. need_restore = 1;
  315. /* Fall-through: force to D0 */
  316. default:
  317. pmcsr = 0;
  318. break;
  319. }
  320. /* enter specified state */
  321. pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
  322. /* Mandatory power management transition delays */
  323. /* see PCI PM 1.1 5.6.1 table 18 */
  324. if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
  325. msleep(10);
  326. else if (state == PCI_D2 || dev->current_state == PCI_D2)
  327. udelay(200);
  328. /*
  329. * Give firmware a chance to be called, such as ACPI _PRx, _PSx
  330. * Firmware method after natice method ?
  331. */
  332. if (platform_pci_set_power_state)
  333. platform_pci_set_power_state(dev, state);
  334. dev->current_state = state;
  335. /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
  336. * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
  337. * from D3hot to D0 _may_ perform an internal reset, thereby
  338. * going to "D0 Uninitialized" rather than "D0 Initialized".
  339. * For example, at least some versions of the 3c905B and the
  340. * 3c556B exhibit this behaviour.
  341. *
  342. * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
  343. * devices in a D3hot state at boot. Consequently, we need to
  344. * restore at least the BARs so that the device will be
  345. * accessible to its driver.
  346. */
  347. if (need_restore)
  348. pci_restore_bars(dev);
  349. return 0;
  350. }
  351. int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
  352. /**
  353. * pci_choose_state - Choose the power state of a PCI device
  354. * @dev: PCI device to be suspended
  355. * @state: target sleep state for the whole system. This is the value
  356. * that is passed to suspend() function.
  357. *
  358. * Returns PCI power state suitable for given device and given system
  359. * message.
  360. */
  361. pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
  362. {
  363. int ret;
  364. if (!pci_find_capability(dev, PCI_CAP_ID_PM))
  365. return PCI_D0;
  366. if (platform_pci_choose_state) {
  367. ret = platform_pci_choose_state(dev, state);
  368. if (ret >= 0)
  369. state.event = ret;
  370. }
  371. switch (state.event) {
  372. case PM_EVENT_ON:
  373. return PCI_D0;
  374. case PM_EVENT_FREEZE:
  375. case PM_EVENT_SUSPEND:
  376. return PCI_D3hot;
  377. default:
  378. printk("They asked me for state %d\n", state.event);
  379. BUG();
  380. }
  381. return PCI_D0;
  382. }
  383. EXPORT_SYMBOL(pci_choose_state);
  384. /**
  385. * pci_save_state - save the PCI configuration space of a device before suspending
  386. * @dev: - PCI device that we're dealing with
  387. */
  388. int
  389. pci_save_state(struct pci_dev *dev)
  390. {
  391. int i;
  392. /* XXX: 100% dword access ok here? */
  393. for (i = 0; i < 16; i++)
  394. pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
  395. if ((i = pci_save_msi_state(dev)) != 0)
  396. return i;
  397. if ((i = pci_save_msix_state(dev)) != 0)
  398. return i;
  399. return 0;
  400. }
  401. /**
  402. * pci_restore_state - Restore the saved state of a PCI device
  403. * @dev: - PCI device that we're dealing with
  404. */
  405. int
  406. pci_restore_state(struct pci_dev *dev)
  407. {
  408. int i;
  409. int val;
  410. /*
  411. * The Base Address register should be programmed before the command
  412. * register(s)
  413. */
  414. for (i = 15; i >= 0; i--) {
  415. pci_read_config_dword(dev, i * 4, &val);
  416. if (val != dev->saved_config_space[i]) {
  417. printk(KERN_DEBUG "PM: Writing back config space on "
  418. "device %s at offset %x (was %x, writing %x)\n",
  419. pci_name(dev), i,
  420. val, (int)dev->saved_config_space[i]);
  421. pci_write_config_dword(dev,i * 4,
  422. dev->saved_config_space[i]);
  423. }
  424. }
  425. pci_restore_msi_state(dev);
  426. pci_restore_msix_state(dev);
  427. return 0;
  428. }
  429. /**
  430. * pci_enable_device_bars - Initialize some of a device for use
  431. * @dev: PCI device to be initialized
  432. * @bars: bitmask of BAR's that must be configured
  433. *
  434. * Initialize device before it's used by a driver. Ask low-level code
  435. * to enable selected I/O and memory resources. Wake up the device if it
  436. * was suspended. Beware, this function can fail.
  437. */
  438. int
  439. pci_enable_device_bars(struct pci_dev *dev, int bars)
  440. {
  441. int err;
  442. err = pci_set_power_state(dev, PCI_D0);
  443. if (err < 0 && err != -EIO)
  444. return err;
  445. err = pcibios_enable_device(dev, bars);
  446. if (err < 0)
  447. return err;
  448. return 0;
  449. }
  450. /**
  451. * pci_enable_device - Initialize device before it's used by a driver.
  452. * @dev: PCI device to be initialized
  453. *
  454. * Initialize device before it's used by a driver. Ask low-level code
  455. * to enable I/O and memory. Wake up the device if it was suspended.
  456. * Beware, this function can fail.
  457. */
  458. int
  459. pci_enable_device(struct pci_dev *dev)
  460. {
  461. int err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
  462. if (err)
  463. return err;
  464. pci_fixup_device(pci_fixup_enable, dev);
  465. dev->is_enabled = 1;
  466. return 0;
  467. }
  468. /**
  469. * pcibios_disable_device - disable arch specific PCI resources for device dev
  470. * @dev: the PCI device to disable
  471. *
  472. * Disables architecture specific PCI resources for the device. This
  473. * is the default implementation. Architecture implementations can
  474. * override this.
  475. */
  476. void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
  477. /**
  478. * pci_disable_device - Disable PCI device after use
  479. * @dev: PCI device to be disabled
  480. *
  481. * Signal to the system that the PCI device is not in use by the system
  482. * anymore. This only involves disabling PCI bus-mastering, if active.
  483. */
  484. void
  485. pci_disable_device(struct pci_dev *dev)
  486. {
  487. u16 pci_command;
  488. pci_read_config_word(dev, PCI_COMMAND, &pci_command);
  489. if (pci_command & PCI_COMMAND_MASTER) {
  490. pci_command &= ~PCI_COMMAND_MASTER;
  491. pci_write_config_word(dev, PCI_COMMAND, pci_command);
  492. }
  493. dev->is_busmaster = 0;
  494. pcibios_disable_device(dev);
  495. dev->is_enabled = 0;
  496. }
  497. /**
  498. * pci_enable_wake - enable device to generate PME# when suspended
  499. * @dev: - PCI device to operate on
  500. * @state: - Current state of device.
  501. * @enable: - Flag to enable or disable generation
  502. *
  503. * Set the bits in the device's PM Capabilities to generate PME# when
  504. * the system is suspended.
  505. *
  506. * -EIO is returned if device doesn't have PM Capabilities.
  507. * -EINVAL is returned if device supports it, but can't generate wake events.
  508. * 0 if operation is successful.
  509. *
  510. */
  511. int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
  512. {
  513. int pm;
  514. u16 value;
  515. /* find PCI PM capability in list */
  516. pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  517. /* If device doesn't support PM Capabilities, but request is to disable
  518. * wake events, it's a nop; otherwise fail */
  519. if (!pm)
  520. return enable ? -EIO : 0;
  521. /* Check device's ability to generate PME# */
  522. pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
  523. value &= PCI_PM_CAP_PME_MASK;
  524. value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
  525. /* Check if it can generate PME# from requested state. */
  526. if (!value || !(value & (1 << state)))
  527. return enable ? -EINVAL : 0;
  528. pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
  529. /* Clear PME_Status by writing 1 to it and enable PME# */
  530. value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
  531. if (!enable)
  532. value &= ~PCI_PM_CTRL_PME_ENABLE;
  533. pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
  534. return 0;
  535. }
  536. int
  537. pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
  538. {
  539. u8 pin;
  540. pin = dev->pin;
  541. if (!pin)
  542. return -1;
  543. pin--;
  544. while (dev->bus->self) {
  545. pin = (pin + PCI_SLOT(dev->devfn)) % 4;
  546. dev = dev->bus->self;
  547. }
  548. *bridge = dev;
  549. return pin;
  550. }
  551. /**
  552. * pci_release_region - Release a PCI bar
  553. * @pdev: PCI device whose resources were previously reserved by pci_request_region
  554. * @bar: BAR to release
  555. *
  556. * Releases the PCI I/O and memory resources previously reserved by a
  557. * successful call to pci_request_region. Call this function only
  558. * after all use of the PCI regions has ceased.
  559. */
  560. void pci_release_region(struct pci_dev *pdev, int bar)
  561. {
  562. if (pci_resource_len(pdev, bar) == 0)
  563. return;
  564. if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
  565. release_region(pci_resource_start(pdev, bar),
  566. pci_resource_len(pdev, bar));
  567. else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
  568. release_mem_region(pci_resource_start(pdev, bar),
  569. pci_resource_len(pdev, bar));
  570. }
  571. /**
  572. * pci_request_region - Reserved PCI I/O and memory resource
  573. * @pdev: PCI device whose resources are to be reserved
  574. * @bar: BAR to be reserved
  575. * @res_name: Name to be associated with resource.
  576. *
  577. * Mark the PCI region associated with PCI device @pdev BR @bar as
  578. * being reserved by owner @res_name. Do not access any
  579. * address inside the PCI regions unless this call returns
  580. * successfully.
  581. *
  582. * Returns 0 on success, or %EBUSY on error. A warning
  583. * message is also printed on failure.
  584. */
  585. int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
  586. {
  587. if (pci_resource_len(pdev, bar) == 0)
  588. return 0;
  589. if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
  590. if (!request_region(pci_resource_start(pdev, bar),
  591. pci_resource_len(pdev, bar), res_name))
  592. goto err_out;
  593. }
  594. else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
  595. if (!request_mem_region(pci_resource_start(pdev, bar),
  596. pci_resource_len(pdev, bar), res_name))
  597. goto err_out;
  598. }
  599. return 0;
  600. err_out:
  601. printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
  602. pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
  603. bar + 1, /* PCI BAR # */
  604. pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
  605. pci_name(pdev));
  606. return -EBUSY;
  607. }
  608. /**
  609. * pci_release_regions - Release reserved PCI I/O and memory resources
  610. * @pdev: PCI device whose resources were previously reserved by pci_request_regions
  611. *
  612. * Releases all PCI I/O and memory resources previously reserved by a
  613. * successful call to pci_request_regions. Call this function only
  614. * after all use of the PCI regions has ceased.
  615. */
  616. void pci_release_regions(struct pci_dev *pdev)
  617. {
  618. int i;
  619. for (i = 0; i < 6; i++)
  620. pci_release_region(pdev, i);
  621. }
  622. /**
  623. * pci_request_regions - Reserved PCI I/O and memory resources
  624. * @pdev: PCI device whose resources are to be reserved
  625. * @res_name: Name to be associated with resource.
  626. *
  627. * Mark all PCI regions associated with PCI device @pdev as
  628. * being reserved by owner @res_name. Do not access any
  629. * address inside the PCI regions unless this call returns
  630. * successfully.
  631. *
  632. * Returns 0 on success, or %EBUSY on error. A warning
  633. * message is also printed on failure.
  634. */
  635. int pci_request_regions(struct pci_dev *pdev, const char *res_name)
  636. {
  637. int i;
  638. for (i = 0; i < 6; i++)
  639. if(pci_request_region(pdev, i, res_name))
  640. goto err_out;
  641. return 0;
  642. err_out:
  643. while(--i >= 0)
  644. pci_release_region(pdev, i);
  645. return -EBUSY;
  646. }
  647. /**
  648. * pci_set_master - enables bus-mastering for device dev
  649. * @dev: the PCI device to enable
  650. *
  651. * Enables bus-mastering on the device and calls pcibios_set_master()
  652. * to do the needed arch specific settings.
  653. */
  654. void
  655. pci_set_master(struct pci_dev *dev)
  656. {
  657. u16 cmd;
  658. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  659. if (! (cmd & PCI_COMMAND_MASTER)) {
  660. pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
  661. cmd |= PCI_COMMAND_MASTER;
  662. pci_write_config_word(dev, PCI_COMMAND, cmd);
  663. }
  664. dev->is_busmaster = 1;
  665. pcibios_set_master(dev);
  666. }
  667. #ifndef HAVE_ARCH_PCI_MWI
  668. /* This can be overridden by arch code. */
  669. u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
  670. /**
  671. * pci_generic_prep_mwi - helper function for pci_set_mwi
  672. * @dev: the PCI device for which MWI is enabled
  673. *
  674. * Helper function for generic implementation of pcibios_prep_mwi
  675. * function. Originally copied from drivers/net/acenic.c.
  676. * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
  677. *
  678. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  679. */
  680. static int
  681. pci_generic_prep_mwi(struct pci_dev *dev)
  682. {
  683. u8 cacheline_size;
  684. if (!pci_cache_line_size)
  685. return -EINVAL; /* The system doesn't support MWI. */
  686. /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
  687. equal to or multiple of the right value. */
  688. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
  689. if (cacheline_size >= pci_cache_line_size &&
  690. (cacheline_size % pci_cache_line_size) == 0)
  691. return 0;
  692. /* Write the correct value. */
  693. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
  694. /* Read it back. */
  695. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
  696. if (cacheline_size == pci_cache_line_size)
  697. return 0;
  698. printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
  699. "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
  700. return -EINVAL;
  701. }
  702. #endif /* !HAVE_ARCH_PCI_MWI */
  703. /**
  704. * pci_set_mwi - enables memory-write-invalidate PCI transaction
  705. * @dev: the PCI device for which MWI is enabled
  706. *
  707. * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
  708. * and then calls @pcibios_set_mwi to do the needed arch specific
  709. * operations or a generic mwi-prep function.
  710. *
  711. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  712. */
  713. int
  714. pci_set_mwi(struct pci_dev *dev)
  715. {
  716. int rc;
  717. u16 cmd;
  718. #ifdef HAVE_ARCH_PCI_MWI
  719. rc = pcibios_prep_mwi(dev);
  720. #else
  721. rc = pci_generic_prep_mwi(dev);
  722. #endif
  723. if (rc)
  724. return rc;
  725. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  726. if (! (cmd & PCI_COMMAND_INVALIDATE)) {
  727. pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
  728. cmd |= PCI_COMMAND_INVALIDATE;
  729. pci_write_config_word(dev, PCI_COMMAND, cmd);
  730. }
  731. return 0;
  732. }
  733. /**
  734. * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
  735. * @dev: the PCI device to disable
  736. *
  737. * Disables PCI Memory-Write-Invalidate transaction on the device
  738. */
  739. void
  740. pci_clear_mwi(struct pci_dev *dev)
  741. {
  742. u16 cmd;
  743. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  744. if (cmd & PCI_COMMAND_INVALIDATE) {
  745. cmd &= ~PCI_COMMAND_INVALIDATE;
  746. pci_write_config_word(dev, PCI_COMMAND, cmd);
  747. }
  748. }
  749. /**
  750. * pci_intx - enables/disables PCI INTx for device dev
  751. * @pdev: the PCI device to operate on
  752. * @enable: boolean: whether to enable or disable PCI INTx
  753. *
  754. * Enables/disables PCI INTx for device dev
  755. */
  756. void
  757. pci_intx(struct pci_dev *pdev, int enable)
  758. {
  759. u16 pci_command, new;
  760. pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
  761. if (enable) {
  762. new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
  763. } else {
  764. new = pci_command | PCI_COMMAND_INTX_DISABLE;
  765. }
  766. if (new != pci_command) {
  767. pci_write_config_word(pdev, PCI_COMMAND, new);
  768. }
  769. }
  770. #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
  771. /*
  772. * These can be overridden by arch-specific implementations
  773. */
  774. int
  775. pci_set_dma_mask(struct pci_dev *dev, u64 mask)
  776. {
  777. if (!pci_dma_supported(dev, mask))
  778. return -EIO;
  779. dev->dma_mask = mask;
  780. return 0;
  781. }
  782. int
  783. pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
  784. {
  785. if (!pci_dma_supported(dev, mask))
  786. return -EIO;
  787. dev->dev.coherent_dma_mask = mask;
  788. return 0;
  789. }
  790. #endif
  791. static int __devinit pci_init(void)
  792. {
  793. struct pci_dev *dev = NULL;
  794. while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
  795. pci_fixup_device(pci_fixup_final, dev);
  796. }
  797. return 0;
  798. }
  799. static int __devinit pci_setup(char *str)
  800. {
  801. while (str) {
  802. char *k = strchr(str, ',');
  803. if (k)
  804. *k++ = 0;
  805. if (*str && (str = pcibios_setup(str)) && *str) {
  806. if (!strcmp(str, "nomsi")) {
  807. pci_no_msi();
  808. } else {
  809. printk(KERN_ERR "PCI: Unknown option `%s'\n",
  810. str);
  811. }
  812. }
  813. str = k;
  814. }
  815. return 1;
  816. }
  817. device_initcall(pci_init);
  818. __setup("pci=", pci_setup);
  819. #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
  820. /* FIXME: Some boxes have multiple ISA bridges! */
  821. struct pci_dev *isa_bridge;
  822. EXPORT_SYMBOL(isa_bridge);
  823. #endif
  824. EXPORT_SYMBOL_GPL(pci_restore_bars);
  825. EXPORT_SYMBOL(pci_enable_device_bars);
  826. EXPORT_SYMBOL(pci_enable_device);
  827. EXPORT_SYMBOL(pci_disable_device);
  828. EXPORT_SYMBOL(pci_find_capability);
  829. EXPORT_SYMBOL(pci_bus_find_capability);
  830. EXPORT_SYMBOL(pci_release_regions);
  831. EXPORT_SYMBOL(pci_request_regions);
  832. EXPORT_SYMBOL(pci_release_region);
  833. EXPORT_SYMBOL(pci_request_region);
  834. EXPORT_SYMBOL(pci_set_master);
  835. EXPORT_SYMBOL(pci_set_mwi);
  836. EXPORT_SYMBOL(pci_clear_mwi);
  837. EXPORT_SYMBOL_GPL(pci_intx);
  838. EXPORT_SYMBOL(pci_set_dma_mask);
  839. EXPORT_SYMBOL(pci_set_consistent_dma_mask);
  840. EXPORT_SYMBOL(pci_assign_resource);
  841. EXPORT_SYMBOL(pci_find_parent_resource);
  842. EXPORT_SYMBOL(pci_set_power_state);
  843. EXPORT_SYMBOL(pci_save_state);
  844. EXPORT_SYMBOL(pci_restore_state);
  845. EXPORT_SYMBOL(pci_enable_wake);
  846. /* Quirk info */
  847. EXPORT_SYMBOL(isa_dma_bridge_buggy);
  848. EXPORT_SYMBOL(pci_pci_problems);