main.c 47 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #define ATH_PCI_VERSION "0.1"
  20. #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
  21. static char *dev_info = "ath9k";
  22. MODULE_AUTHOR("Atheros Communications");
  23. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  24. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  25. MODULE_LICENSE("Dual BSD/GPL");
  26. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  27. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  28. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  29. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  31. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  32. { 0 }
  33. };
  34. static int ath_get_channel(struct ath_softc *sc,
  35. struct ieee80211_channel *chan)
  36. {
  37. int i;
  38. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  39. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  40. return i;
  41. }
  42. return -1;
  43. }
  44. static u32 ath_get_extchanmode(struct ath_softc *sc,
  45. struct ieee80211_channel *chan)
  46. {
  47. u32 chanmode = 0;
  48. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  49. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  50. switch (chan->band) {
  51. case IEEE80211_BAND_2GHZ:
  52. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  53. (tx_chan_width == ATH9K_HT_MACMODE_20))
  54. chanmode = CHANNEL_G_HT20;
  55. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  56. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  57. chanmode = CHANNEL_G_HT40PLUS;
  58. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  59. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  60. chanmode = CHANNEL_G_HT40MINUS;
  61. break;
  62. case IEEE80211_BAND_5GHZ:
  63. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  64. (tx_chan_width == ATH9K_HT_MACMODE_20))
  65. chanmode = CHANNEL_A_HT20;
  66. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  67. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  68. chanmode = CHANNEL_A_HT40PLUS;
  69. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  70. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  71. chanmode = CHANNEL_A_HT40MINUS;
  72. break;
  73. default:
  74. break;
  75. }
  76. return chanmode;
  77. }
  78. static int ath_setkey_tkip(struct ath_softc *sc,
  79. struct ieee80211_key_conf *key,
  80. struct ath9k_keyval *hk,
  81. const u8 *addr)
  82. {
  83. u8 *key_rxmic = NULL;
  84. u8 *key_txmic = NULL;
  85. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  86. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  87. if (addr == NULL) {
  88. /* Group key installation */
  89. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  90. return ath_keyset(sc, key->keyidx, hk, addr);
  91. }
  92. if (!sc->sc_splitmic) {
  93. /*
  94. * data key goes at first index,
  95. * the hal handles the MIC keys at index+64.
  96. */
  97. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  98. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  99. return ath_keyset(sc, key->keyidx, hk, addr);
  100. }
  101. /*
  102. * TX key goes at first index, RX key at +32.
  103. * The hal handles the MIC keys at index+64.
  104. */
  105. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  106. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  107. /* Txmic entry failed. No need to proceed further */
  108. DPRINTF(sc, ATH_DBG_KEYCACHE,
  109. "%s Setting TX MIC Key Failed\n", __func__);
  110. return 0;
  111. }
  112. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  113. /* XXX delete tx key on failure? */
  114. return ath_keyset(sc, key->keyidx+32, hk, addr);
  115. }
  116. static int ath_key_config(struct ath_softc *sc,
  117. const u8 *addr,
  118. struct ieee80211_key_conf *key)
  119. {
  120. struct ieee80211_vif *vif;
  121. struct ath9k_keyval hk;
  122. const u8 *mac = NULL;
  123. int ret = 0;
  124. enum nl80211_iftype opmode;
  125. memset(&hk, 0, sizeof(hk));
  126. switch (key->alg) {
  127. case ALG_WEP:
  128. hk.kv_type = ATH9K_CIPHER_WEP;
  129. break;
  130. case ALG_TKIP:
  131. hk.kv_type = ATH9K_CIPHER_TKIP;
  132. break;
  133. case ALG_CCMP:
  134. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  135. break;
  136. default:
  137. return -EINVAL;
  138. }
  139. hk.kv_len = key->keylen;
  140. memcpy(hk.kv_val, key->key, key->keylen);
  141. if (!sc->sc_vaps[0])
  142. return -EIO;
  143. vif = sc->sc_vaps[0]->av_if_data;
  144. opmode = vif->type;
  145. /*
  146. * Strategy:
  147. * For _M_STA mc tx, we will not setup a key at all since we never
  148. * tx mc.
  149. * _M_STA mc rx, we will use the keyID.
  150. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  151. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  152. * peer node. BUT we will plumb a cleartext key so that we can do
  153. * perSta default key table lookup in software.
  154. */
  155. if (is_broadcast_ether_addr(addr)) {
  156. switch (opmode) {
  157. case NL80211_IFTYPE_STATION:
  158. /* default key: could be group WPA key
  159. * or could be static WEP key */
  160. mac = NULL;
  161. break;
  162. case NL80211_IFTYPE_ADHOC:
  163. break;
  164. case NL80211_IFTYPE_AP:
  165. break;
  166. default:
  167. ASSERT(0);
  168. break;
  169. }
  170. } else {
  171. mac = addr;
  172. }
  173. if (key->alg == ALG_TKIP)
  174. ret = ath_setkey_tkip(sc, key, &hk, mac);
  175. else
  176. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  177. if (!ret)
  178. return -EIO;
  179. return 0;
  180. }
  181. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  182. {
  183. int freeslot;
  184. freeslot = (key->keyidx >= 4) ? 1 : 0;
  185. ath_key_reset(sc, key->keyidx, freeslot);
  186. }
  187. static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
  188. {
  189. #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  190. #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  191. ht_info->ht_supported = true;
  192. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  193. IEEE80211_HT_CAP_SM_PS |
  194. IEEE80211_HT_CAP_SGI_40 |
  195. IEEE80211_HT_CAP_DSSSCCK40;
  196. ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
  197. ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
  198. /* set up supported mcs set */
  199. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  200. ht_info->mcs.rx_mask[0] = 0xff;
  201. ht_info->mcs.rx_mask[1] = 0xff;
  202. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  203. }
  204. static int ath_rate2idx(struct ath_softc *sc, int rate)
  205. {
  206. int i = 0, cur_band, n_rates;
  207. struct ieee80211_hw *hw = sc->hw;
  208. cur_band = hw->conf.channel->band;
  209. n_rates = sc->sbands[cur_band].n_bitrates;
  210. for (i = 0; i < n_rates; i++) {
  211. if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
  212. break;
  213. }
  214. /*
  215. * NB:mac80211 validates rx rate index against the supported legacy rate
  216. * index only (should be done against ht rates also), return the highest
  217. * legacy rate index for rx rate which does not match any one of the
  218. * supported basic and extended rates to make mac80211 happy.
  219. * The following hack will be cleaned up once the issue with
  220. * the rx rate index validation in mac80211 is fixed.
  221. */
  222. if (i == n_rates)
  223. return n_rates - 1;
  224. return i;
  225. }
  226. static void ath9k_rx_prepare(struct ath_softc *sc,
  227. struct sk_buff *skb,
  228. struct ath_recv_status *status,
  229. struct ieee80211_rx_status *rx_status)
  230. {
  231. struct ieee80211_hw *hw = sc->hw;
  232. struct ieee80211_channel *curchan = hw->conf.channel;
  233. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  234. rx_status->mactime = status->tsf;
  235. rx_status->band = curchan->band;
  236. rx_status->freq = curchan->center_freq;
  237. rx_status->noise = sc->sc_ani.sc_noise_floor;
  238. rx_status->signal = rx_status->noise + status->rssi;
  239. rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
  240. rx_status->antenna = status->antenna;
  241. /* at 45 you will be able to use MCS 15 reliably. A more elaborate
  242. * scheme can be used here but it requires tables of SNR/throughput for
  243. * each possible mode used. */
  244. rx_status->qual = status->rssi * 100 / 45;
  245. /* rssi can be more than 45 though, anything above that
  246. * should be considered at 100% */
  247. if (rx_status->qual > 100)
  248. rx_status->qual = 100;
  249. if (status->flags & ATH_RX_MIC_ERROR)
  250. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  251. if (status->flags & ATH_RX_FCS_ERROR)
  252. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  253. rx_status->flag |= RX_FLAG_TSFT;
  254. }
  255. static u8 parse_mpdudensity(u8 mpdudensity)
  256. {
  257. /*
  258. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  259. * 0 for no restriction
  260. * 1 for 1/4 us
  261. * 2 for 1/2 us
  262. * 3 for 1 us
  263. * 4 for 2 us
  264. * 5 for 4 us
  265. * 6 for 8 us
  266. * 7 for 16 us
  267. */
  268. switch (mpdudensity) {
  269. case 0:
  270. return 0;
  271. case 1:
  272. case 2:
  273. case 3:
  274. /* Our lower layer calculations limit our precision to
  275. 1 microsecond */
  276. return 1;
  277. case 4:
  278. return 2;
  279. case 5:
  280. return 4;
  281. case 6:
  282. return 8;
  283. case 7:
  284. return 16;
  285. default:
  286. return 0;
  287. }
  288. }
  289. static void ath9k_ht_conf(struct ath_softc *sc,
  290. struct ieee80211_bss_conf *bss_conf)
  291. {
  292. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  293. if (sc->hw->conf.ht.enabled) {
  294. ht_info->ext_chan_offset = bss_conf->ht.secondary_channel_offset;
  295. if (bss_conf->ht.width_40_ok)
  296. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  297. else
  298. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  299. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  300. }
  301. }
  302. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  303. struct ieee80211_bss_conf *bss_conf)
  304. {
  305. struct ieee80211_hw *hw = sc->hw;
  306. struct ieee80211_channel *curchan = hw->conf.channel;
  307. struct ath_vap *avp;
  308. int pos;
  309. if (bss_conf->assoc) {
  310. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  311. __func__,
  312. bss_conf->aid);
  313. avp = sc->sc_vaps[0];
  314. if (avp == NULL) {
  315. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  316. __func__);
  317. return;
  318. }
  319. /* New association, store aid */
  320. if (avp->av_opmode == ATH9K_M_STA) {
  321. sc->sc_curaid = bss_conf->aid;
  322. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  323. sc->sc_curaid);
  324. }
  325. /* Configure the beacon */
  326. ath_beacon_config(sc, 0);
  327. sc->sc_flags |= SC_OP_BEACONS;
  328. /* Reset rssi stats */
  329. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  330. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  331. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  332. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  333. /* Update chainmask */
  334. ath_update_chainmask(sc, hw->conf.ht.enabled);
  335. DPRINTF(sc, ATH_DBG_CONFIG,
  336. "%s: bssid %pM aid 0x%x\n",
  337. __func__,
  338. sc->sc_curbssid, sc->sc_curaid);
  339. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  340. __func__,
  341. curchan->center_freq);
  342. pos = ath_get_channel(sc, curchan);
  343. if (pos == -1) {
  344. DPRINTF(sc, ATH_DBG_FATAL,
  345. "%s: Invalid channel\n", __func__);
  346. return;
  347. }
  348. if (hw->conf.ht.enabled)
  349. sc->sc_ah->ah_channels[pos].chanmode =
  350. ath_get_extchanmode(sc, curchan);
  351. else
  352. sc->sc_ah->ah_channels[pos].chanmode =
  353. (curchan->band == IEEE80211_BAND_2GHZ) ?
  354. CHANNEL_G : CHANNEL_A;
  355. /* set h/w channel */
  356. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  357. DPRINTF(sc, ATH_DBG_FATAL,
  358. "%s: Unable to set channel\n",
  359. __func__);
  360. ath_rate_newstate(sc, avp);
  361. /* Update ratectrl about the new state */
  362. ath_rc_node_update(hw, avp->rc_node);
  363. /* Start ANI */
  364. mod_timer(&sc->sc_ani.timer,
  365. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  366. } else {
  367. DPRINTF(sc, ATH_DBG_CONFIG,
  368. "%s: Bss Info DISSOC\n", __func__);
  369. sc->sc_curaid = 0;
  370. }
  371. }
  372. void ath_get_beaconconfig(struct ath_softc *sc,
  373. int if_id,
  374. struct ath_beacon_config *conf)
  375. {
  376. struct ieee80211_hw *hw = sc->hw;
  377. /* fill in beacon config data */
  378. conf->beacon_interval = hw->conf.beacon_int;
  379. conf->listen_interval = 100;
  380. conf->dtim_count = 1;
  381. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  382. }
  383. void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  384. struct ath_xmit_status *tx_status, struct ath_node *an)
  385. {
  386. struct ieee80211_hw *hw = sc->hw;
  387. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  388. DPRINTF(sc, ATH_DBG_XMIT,
  389. "%s: TX complete: skb: %p\n", __func__, skb);
  390. ieee80211_tx_info_clear_status(tx_info);
  391. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  392. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  393. /* free driver's private data area of tx_info, XXX: HACK! */
  394. if (tx_info->control.vif != NULL)
  395. kfree(tx_info->control.vif);
  396. tx_info->control.vif = NULL;
  397. }
  398. if (tx_status->flags & ATH_TX_BAR) {
  399. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  400. tx_status->flags &= ~ATH_TX_BAR;
  401. }
  402. if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
  403. /* Frame was ACKed */
  404. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  405. }
  406. tx_info->status.rates[0].count = tx_status->retries + 1;
  407. ieee80211_tx_status(hw, skb);
  408. if (an)
  409. ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE);
  410. }
  411. int _ath_rx_indicate(struct ath_softc *sc,
  412. struct sk_buff *skb,
  413. struct ath_recv_status *status,
  414. u16 keyix)
  415. {
  416. struct ieee80211_hw *hw = sc->hw;
  417. struct ath_node *an = NULL;
  418. struct ieee80211_rx_status rx_status;
  419. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  420. int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  421. int padsize;
  422. enum ATH_RX_TYPE st;
  423. /* see if any padding is done by the hw and remove it */
  424. if (hdrlen & 3) {
  425. padsize = hdrlen % 4;
  426. memmove(skb->data + padsize, skb->data, hdrlen);
  427. skb_pull(skb, padsize);
  428. }
  429. /* Prepare rx status */
  430. ath9k_rx_prepare(sc, skb, status, &rx_status);
  431. if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
  432. !(status->flags & ATH_RX_DECRYPT_ERROR)) {
  433. rx_status.flag |= RX_FLAG_DECRYPTED;
  434. } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
  435. && !(status->flags & ATH_RX_DECRYPT_ERROR)
  436. && skb->len >= hdrlen + 4) {
  437. keyix = skb->data[hdrlen + 3] >> 6;
  438. if (test_bit(keyix, sc->sc_keymap))
  439. rx_status.flag |= RX_FLAG_DECRYPTED;
  440. }
  441. spin_lock_bh(&sc->node_lock);
  442. an = ath_node_find(sc, hdr->addr2);
  443. spin_unlock_bh(&sc->node_lock);
  444. if (an) {
  445. ath_rx_input(sc, an,
  446. skb, status, &st);
  447. }
  448. if (!an || (st != ATH_RX_CONSUMED))
  449. __ieee80211_rx(hw, skb, &rx_status);
  450. return 0;
  451. }
  452. int ath_rx_subframe(struct ath_node *an,
  453. struct sk_buff *skb,
  454. struct ath_recv_status *status)
  455. {
  456. struct ath_softc *sc = an->an_sc;
  457. struct ieee80211_hw *hw = sc->hw;
  458. struct ieee80211_rx_status rx_status;
  459. /* Prepare rx status */
  460. ath9k_rx_prepare(sc, skb, status, &rx_status);
  461. if (!(status->flags & ATH_RX_DECRYPT_ERROR))
  462. rx_status.flag |= RX_FLAG_DECRYPTED;
  463. __ieee80211_rx(hw, skb, &rx_status);
  464. return 0;
  465. }
  466. /********************************/
  467. /* LED functions */
  468. /********************************/
  469. static void ath_led_brightness(struct led_classdev *led_cdev,
  470. enum led_brightness brightness)
  471. {
  472. struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
  473. struct ath_softc *sc = led->sc;
  474. switch (brightness) {
  475. case LED_OFF:
  476. if (led->led_type == ATH_LED_ASSOC ||
  477. led->led_type == ATH_LED_RADIO)
  478. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  479. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
  480. (led->led_type == ATH_LED_RADIO) ? 1 :
  481. !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
  482. break;
  483. case LED_FULL:
  484. if (led->led_type == ATH_LED_ASSOC)
  485. sc->sc_flags |= SC_OP_LED_ASSOCIATED;
  486. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
  487. break;
  488. default:
  489. break;
  490. }
  491. }
  492. static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
  493. char *trigger)
  494. {
  495. int ret;
  496. led->sc = sc;
  497. led->led_cdev.name = led->name;
  498. led->led_cdev.default_trigger = trigger;
  499. led->led_cdev.brightness_set = ath_led_brightness;
  500. ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
  501. if (ret)
  502. DPRINTF(sc, ATH_DBG_FATAL,
  503. "Failed to register led:%s", led->name);
  504. else
  505. led->registered = 1;
  506. return ret;
  507. }
  508. static void ath_unregister_led(struct ath_led *led)
  509. {
  510. if (led->registered) {
  511. led_classdev_unregister(&led->led_cdev);
  512. led->registered = 0;
  513. }
  514. }
  515. static void ath_deinit_leds(struct ath_softc *sc)
  516. {
  517. ath_unregister_led(&sc->assoc_led);
  518. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  519. ath_unregister_led(&sc->tx_led);
  520. ath_unregister_led(&sc->rx_led);
  521. ath_unregister_led(&sc->radio_led);
  522. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  523. }
  524. static void ath_init_leds(struct ath_softc *sc)
  525. {
  526. char *trigger;
  527. int ret;
  528. /* Configure gpio 1 for output */
  529. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  530. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  531. /* LED off, active low */
  532. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  533. trigger = ieee80211_get_radio_led_name(sc->hw);
  534. snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
  535. "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
  536. ret = ath_register_led(sc, &sc->radio_led, trigger);
  537. sc->radio_led.led_type = ATH_LED_RADIO;
  538. if (ret)
  539. goto fail;
  540. trigger = ieee80211_get_assoc_led_name(sc->hw);
  541. snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
  542. "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
  543. ret = ath_register_led(sc, &sc->assoc_led, trigger);
  544. sc->assoc_led.led_type = ATH_LED_ASSOC;
  545. if (ret)
  546. goto fail;
  547. trigger = ieee80211_get_tx_led_name(sc->hw);
  548. snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
  549. "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
  550. ret = ath_register_led(sc, &sc->tx_led, trigger);
  551. sc->tx_led.led_type = ATH_LED_TX;
  552. if (ret)
  553. goto fail;
  554. trigger = ieee80211_get_rx_led_name(sc->hw);
  555. snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
  556. "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
  557. ret = ath_register_led(sc, &sc->rx_led, trigger);
  558. sc->rx_led.led_type = ATH_LED_RX;
  559. if (ret)
  560. goto fail;
  561. return;
  562. fail:
  563. ath_deinit_leds(sc);
  564. }
  565. #ifdef CONFIG_RFKILL
  566. /*******************/
  567. /* Rfkill */
  568. /*******************/
  569. static void ath_radio_enable(struct ath_softc *sc)
  570. {
  571. struct ath_hal *ah = sc->sc_ah;
  572. int status;
  573. spin_lock_bh(&sc->sc_resetlock);
  574. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  575. sc->sc_ht_info.tx_chan_width,
  576. sc->sc_tx_chainmask,
  577. sc->sc_rx_chainmask,
  578. sc->sc_ht_extprotspacing,
  579. false, &status)) {
  580. DPRINTF(sc, ATH_DBG_FATAL,
  581. "%s: unable to reset channel %u (%uMhz) "
  582. "flags 0x%x hal status %u\n", __func__,
  583. ath9k_hw_mhz2ieee(ah,
  584. ah->ah_curchan->channel,
  585. ah->ah_curchan->channelFlags),
  586. ah->ah_curchan->channel,
  587. ah->ah_curchan->channelFlags, status);
  588. }
  589. spin_unlock_bh(&sc->sc_resetlock);
  590. ath_update_txpow(sc);
  591. if (ath_startrecv(sc) != 0) {
  592. DPRINTF(sc, ATH_DBG_FATAL,
  593. "%s: unable to restart recv logic\n", __func__);
  594. return;
  595. }
  596. if (sc->sc_flags & SC_OP_BEACONS)
  597. ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
  598. /* Re-Enable interrupts */
  599. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  600. /* Enable LED */
  601. ath9k_hw_cfg_output(ah, ATH_LED_PIN,
  602. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  603. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
  604. ieee80211_wake_queues(sc->hw);
  605. }
  606. static void ath_radio_disable(struct ath_softc *sc)
  607. {
  608. struct ath_hal *ah = sc->sc_ah;
  609. int status;
  610. ieee80211_stop_queues(sc->hw);
  611. /* Disable LED */
  612. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
  613. ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
  614. /* Disable interrupts */
  615. ath9k_hw_set_interrupts(ah, 0);
  616. ath_draintxq(sc, false); /* clear pending tx frames */
  617. ath_stoprecv(sc); /* turn off frame recv */
  618. ath_flushrecv(sc); /* flush recv queue */
  619. spin_lock_bh(&sc->sc_resetlock);
  620. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  621. sc->sc_ht_info.tx_chan_width,
  622. sc->sc_tx_chainmask,
  623. sc->sc_rx_chainmask,
  624. sc->sc_ht_extprotspacing,
  625. false, &status)) {
  626. DPRINTF(sc, ATH_DBG_FATAL,
  627. "%s: unable to reset channel %u (%uMhz) "
  628. "flags 0x%x hal status %u\n", __func__,
  629. ath9k_hw_mhz2ieee(ah,
  630. ah->ah_curchan->channel,
  631. ah->ah_curchan->channelFlags),
  632. ah->ah_curchan->channel,
  633. ah->ah_curchan->channelFlags, status);
  634. }
  635. spin_unlock_bh(&sc->sc_resetlock);
  636. ath9k_hw_phy_disable(ah);
  637. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  638. }
  639. static bool ath_is_rfkill_set(struct ath_softc *sc)
  640. {
  641. struct ath_hal *ah = sc->sc_ah;
  642. return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
  643. ah->ah_rfkill_polarity;
  644. }
  645. /* h/w rfkill poll function */
  646. static void ath_rfkill_poll(struct work_struct *work)
  647. {
  648. struct ath_softc *sc = container_of(work, struct ath_softc,
  649. rf_kill.rfkill_poll.work);
  650. bool radio_on;
  651. if (sc->sc_flags & SC_OP_INVALID)
  652. return;
  653. radio_on = !ath_is_rfkill_set(sc);
  654. /*
  655. * enable/disable radio only when there is a
  656. * state change in RF switch
  657. */
  658. if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
  659. enum rfkill_state state;
  660. if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
  661. state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
  662. : RFKILL_STATE_HARD_BLOCKED;
  663. } else if (radio_on) {
  664. ath_radio_enable(sc);
  665. state = RFKILL_STATE_UNBLOCKED;
  666. } else {
  667. ath_radio_disable(sc);
  668. state = RFKILL_STATE_HARD_BLOCKED;
  669. }
  670. if (state == RFKILL_STATE_HARD_BLOCKED)
  671. sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
  672. else
  673. sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
  674. rfkill_force_state(sc->rf_kill.rfkill, state);
  675. }
  676. queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
  677. msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
  678. }
  679. /* s/w rfkill handler */
  680. static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
  681. {
  682. struct ath_softc *sc = data;
  683. switch (state) {
  684. case RFKILL_STATE_SOFT_BLOCKED:
  685. if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
  686. SC_OP_RFKILL_SW_BLOCKED)))
  687. ath_radio_disable(sc);
  688. sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
  689. return 0;
  690. case RFKILL_STATE_UNBLOCKED:
  691. if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
  692. sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
  693. if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
  694. DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
  695. "radio as it is disabled by h/w \n");
  696. return -EPERM;
  697. }
  698. ath_radio_enable(sc);
  699. }
  700. return 0;
  701. default:
  702. return -EINVAL;
  703. }
  704. }
  705. /* Init s/w rfkill */
  706. static int ath_init_sw_rfkill(struct ath_softc *sc)
  707. {
  708. sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
  709. RFKILL_TYPE_WLAN);
  710. if (!sc->rf_kill.rfkill) {
  711. DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
  712. return -ENOMEM;
  713. }
  714. snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
  715. "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
  716. sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
  717. sc->rf_kill.rfkill->data = sc;
  718. sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
  719. sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
  720. sc->rf_kill.rfkill->user_claim_unsupported = 1;
  721. return 0;
  722. }
  723. /* Deinitialize rfkill */
  724. static void ath_deinit_rfkill(struct ath_softc *sc)
  725. {
  726. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  727. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  728. if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
  729. rfkill_unregister(sc->rf_kill.rfkill);
  730. sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
  731. sc->rf_kill.rfkill = NULL;
  732. }
  733. }
  734. #endif /* CONFIG_RFKILL */
  735. static int ath_detach(struct ath_softc *sc)
  736. {
  737. struct ieee80211_hw *hw = sc->hw;
  738. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  739. /* Deinit LED control */
  740. ath_deinit_leds(sc);
  741. #ifdef CONFIG_RFKILL
  742. /* deinit rfkill */
  743. ath_deinit_rfkill(sc);
  744. #endif
  745. /* Unregister hw */
  746. ieee80211_unregister_hw(hw);
  747. /* unregister Rate control */
  748. ath_rate_control_unregister();
  749. /* tx/rx cleanup */
  750. ath_rx_cleanup(sc);
  751. ath_tx_cleanup(sc);
  752. /* Deinit */
  753. ath_deinit(sc);
  754. return 0;
  755. }
  756. static int ath_attach(u16 devid,
  757. struct ath_softc *sc)
  758. {
  759. struct ieee80211_hw *hw = sc->hw;
  760. int error = 0;
  761. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  762. error = ath_init(devid, sc);
  763. if (error != 0)
  764. return error;
  765. /* Init nodes */
  766. INIT_LIST_HEAD(&sc->node_list);
  767. spin_lock_init(&sc->node_lock);
  768. /* get mac address from hardware and set in mac80211 */
  769. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  770. /* setup channels and rates */
  771. sc->sbands[IEEE80211_BAND_2GHZ].channels =
  772. sc->channels[IEEE80211_BAND_2GHZ];
  773. sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
  774. sc->rates[IEEE80211_BAND_2GHZ];
  775. sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  776. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  777. /* Setup HT capabilities for 2.4Ghz*/
  778. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  779. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  780. &sc->sbands[IEEE80211_BAND_2GHZ];
  781. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
  782. sc->sbands[IEEE80211_BAND_5GHZ].channels =
  783. sc->channels[IEEE80211_BAND_5GHZ];
  784. sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
  785. sc->rates[IEEE80211_BAND_5GHZ];
  786. sc->sbands[IEEE80211_BAND_5GHZ].band =
  787. IEEE80211_BAND_5GHZ;
  788. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  789. /* Setup HT capabilities for 5Ghz*/
  790. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  791. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  792. &sc->sbands[IEEE80211_BAND_5GHZ];
  793. }
  794. hw->queues = 4;
  795. /* Register rate control */
  796. hw->rate_control_algorithm = "ath9k_rate_control";
  797. error = ath_rate_control_register();
  798. if (error != 0) {
  799. DPRINTF(sc, ATH_DBG_FATAL,
  800. "%s: Unable to register rate control "
  801. "algorithm:%d\n", __func__, error);
  802. ath_rate_control_unregister();
  803. goto bad;
  804. }
  805. error = ieee80211_register_hw(hw);
  806. if (error != 0) {
  807. ath_rate_control_unregister();
  808. goto bad;
  809. }
  810. /* Initialize LED control */
  811. ath_init_leds(sc);
  812. #ifdef CONFIG_RFKILL
  813. /* Initialze h/w Rfkill */
  814. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  815. INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
  816. /* Initialize s/w rfkill */
  817. if (ath_init_sw_rfkill(sc))
  818. goto detach;
  819. #endif
  820. /* initialize tx/rx engine */
  821. error = ath_tx_init(sc, ATH_TXBUF);
  822. if (error != 0)
  823. goto detach;
  824. error = ath_rx_init(sc, ATH_RXBUF);
  825. if (error != 0)
  826. goto detach;
  827. return 0;
  828. detach:
  829. ath_detach(sc);
  830. bad:
  831. return error;
  832. }
  833. static int ath9k_start(struct ieee80211_hw *hw)
  834. {
  835. struct ath_softc *sc = hw->priv;
  836. struct ieee80211_channel *curchan = hw->conf.channel;
  837. int error = 0, pos;
  838. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  839. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  840. /* setup initial channel */
  841. pos = ath_get_channel(sc, curchan);
  842. if (pos == -1) {
  843. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  844. return -EINVAL;
  845. }
  846. sc->sc_ah->ah_channels[pos].chanmode =
  847. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  848. /* open ath_dev */
  849. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  850. if (error) {
  851. DPRINTF(sc, ATH_DBG_FATAL,
  852. "%s: Unable to complete ath_open\n", __func__);
  853. return error;
  854. }
  855. #ifdef CONFIG_RFKILL
  856. /* Start rfkill polling */
  857. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  858. queue_delayed_work(sc->hw->workqueue,
  859. &sc->rf_kill.rfkill_poll, 0);
  860. if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
  861. if (rfkill_register(sc->rf_kill.rfkill)) {
  862. DPRINTF(sc, ATH_DBG_FATAL,
  863. "Unable to register rfkill\n");
  864. rfkill_free(sc->rf_kill.rfkill);
  865. /* Deinitialize the device */
  866. if (sc->pdev->irq)
  867. free_irq(sc->pdev->irq, sc);
  868. ath_detach(sc);
  869. pci_iounmap(sc->pdev, sc->mem);
  870. pci_release_region(sc->pdev, 0);
  871. pci_disable_device(sc->pdev);
  872. ieee80211_free_hw(hw);
  873. return -EIO;
  874. } else {
  875. sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
  876. }
  877. }
  878. #endif
  879. ieee80211_wake_queues(hw);
  880. return 0;
  881. }
  882. static int ath9k_tx(struct ieee80211_hw *hw,
  883. struct sk_buff *skb)
  884. {
  885. struct ath_softc *sc = hw->priv;
  886. int hdrlen, padsize;
  887. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  888. /*
  889. * As a temporary workaround, assign seq# here; this will likely need
  890. * to be cleaned up to work better with Beacon transmission and virtual
  891. * BSSes.
  892. */
  893. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  894. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  895. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  896. sc->seq_no += 0x10;
  897. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  898. hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
  899. }
  900. /* Add the padding after the header if this is not already done */
  901. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  902. if (hdrlen & 3) {
  903. padsize = hdrlen % 4;
  904. if (skb_headroom(skb) < padsize)
  905. return -1;
  906. skb_push(skb, padsize);
  907. memmove(skb->data, skb->data + padsize, hdrlen);
  908. }
  909. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  910. __func__,
  911. skb);
  912. if (ath_tx_start(sc, skb) != 0) {
  913. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  914. dev_kfree_skb_any(skb);
  915. /* FIXME: Check for proper return value from ATH_DEV */
  916. return 0;
  917. }
  918. return 0;
  919. }
  920. static void ath9k_stop(struct ieee80211_hw *hw)
  921. {
  922. struct ath_softc *sc = hw->priv;
  923. int error;
  924. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  925. error = ath_suspend(sc);
  926. if (error)
  927. DPRINTF(sc, ATH_DBG_CONFIG,
  928. "%s: Device is no longer present\n", __func__);
  929. ieee80211_stop_queues(hw);
  930. #ifdef CONFIG_RFKILL
  931. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  932. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  933. #endif
  934. }
  935. static int ath9k_add_interface(struct ieee80211_hw *hw,
  936. struct ieee80211_if_init_conf *conf)
  937. {
  938. struct ath_softc *sc = hw->priv;
  939. int error, ic_opmode = 0;
  940. /* Support only vap for now */
  941. if (sc->sc_nvaps)
  942. return -ENOBUFS;
  943. switch (conf->type) {
  944. case NL80211_IFTYPE_STATION:
  945. ic_opmode = ATH9K_M_STA;
  946. break;
  947. case NL80211_IFTYPE_ADHOC:
  948. ic_opmode = ATH9K_M_IBSS;
  949. break;
  950. case NL80211_IFTYPE_AP:
  951. ic_opmode = ATH9K_M_HOSTAP;
  952. break;
  953. default:
  954. DPRINTF(sc, ATH_DBG_FATAL,
  955. "%s: Interface type %d not yet supported\n",
  956. __func__, conf->type);
  957. return -EOPNOTSUPP;
  958. }
  959. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  960. __func__,
  961. ic_opmode);
  962. error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
  963. if (error) {
  964. DPRINTF(sc, ATH_DBG_FATAL,
  965. "%s: Unable to attach vap, error: %d\n",
  966. __func__, error);
  967. return error;
  968. }
  969. if (conf->type == NL80211_IFTYPE_AP) {
  970. /* TODO: is this a suitable place to start ANI for AP mode? */
  971. /* Start ANI */
  972. mod_timer(&sc->sc_ani.timer,
  973. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  974. }
  975. return 0;
  976. }
  977. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  978. struct ieee80211_if_init_conf *conf)
  979. {
  980. struct ath_softc *sc = hw->priv;
  981. struct ath_vap *avp;
  982. int error;
  983. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  984. avp = sc->sc_vaps[0];
  985. if (avp == NULL) {
  986. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  987. __func__);
  988. return;
  989. }
  990. #ifdef CONFIG_SLOW_ANT_DIV
  991. ath_slow_ant_div_stop(&sc->sc_antdiv);
  992. #endif
  993. /* Stop ANI */
  994. del_timer_sync(&sc->sc_ani.timer);
  995. /* Update ratectrl */
  996. ath_rate_newstate(sc, avp);
  997. /* Reclaim beacon resources */
  998. if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
  999. sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
  1000. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  1001. ath_beacon_return(sc, avp);
  1002. }
  1003. /* Set interrupt mask */
  1004. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1005. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
  1006. sc->sc_flags &= ~SC_OP_BEACONS;
  1007. error = ath_vap_detach(sc, 0);
  1008. if (error)
  1009. DPRINTF(sc, ATH_DBG_FATAL,
  1010. "%s: Unable to detach vap, error: %d\n",
  1011. __func__, error);
  1012. }
  1013. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1014. {
  1015. struct ath_softc *sc = hw->priv;
  1016. struct ieee80211_channel *curchan = hw->conf.channel;
  1017. struct ieee80211_conf *conf = &hw->conf;
  1018. int pos;
  1019. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  1020. __func__,
  1021. curchan->center_freq);
  1022. /* Update chainmask */
  1023. ath_update_chainmask(sc, conf->ht.enabled);
  1024. pos = ath_get_channel(sc, curchan);
  1025. if (pos == -1) {
  1026. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  1027. return -EINVAL;
  1028. }
  1029. sc->sc_ah->ah_channels[pos].chanmode =
  1030. (curchan->band == IEEE80211_BAND_2GHZ) ?
  1031. CHANNEL_G : CHANNEL_A;
  1032. if (sc->sc_curaid && hw->conf.ht.enabled)
  1033. sc->sc_ah->ah_channels[pos].chanmode =
  1034. ath_get_extchanmode(sc, curchan);
  1035. if (changed & IEEE80211_CONF_CHANGE_POWER)
  1036. sc->sc_config.txpowlimit = 2 * conf->power_level;
  1037. /* set h/w channel */
  1038. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  1039. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  1040. __func__);
  1041. return 0;
  1042. }
  1043. static int ath9k_config_interface(struct ieee80211_hw *hw,
  1044. struct ieee80211_vif *vif,
  1045. struct ieee80211_if_conf *conf)
  1046. {
  1047. struct ath_softc *sc = hw->priv;
  1048. struct ath_hal *ah = sc->sc_ah;
  1049. struct ath_vap *avp;
  1050. u32 rfilt = 0;
  1051. int error, i;
  1052. avp = sc->sc_vaps[0];
  1053. if (avp == NULL) {
  1054. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  1055. __func__);
  1056. return -EINVAL;
  1057. }
  1058. /* TODO: Need to decide which hw opmode to use for multi-interface
  1059. * cases */
  1060. if (vif->type == NL80211_IFTYPE_AP &&
  1061. ah->ah_opmode != ATH9K_M_HOSTAP) {
  1062. ah->ah_opmode = ATH9K_M_HOSTAP;
  1063. ath9k_hw_setopmode(ah);
  1064. ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
  1065. /* Request full reset to get hw opmode changed properly */
  1066. sc->sc_flags |= SC_OP_FULL_RESET;
  1067. }
  1068. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  1069. !is_zero_ether_addr(conf->bssid)) {
  1070. switch (vif->type) {
  1071. case NL80211_IFTYPE_STATION:
  1072. case NL80211_IFTYPE_ADHOC:
  1073. /* Update ratectrl about the new state */
  1074. ath_rate_newstate(sc, avp);
  1075. /* Set BSSID */
  1076. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  1077. sc->sc_curaid = 0;
  1078. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  1079. sc->sc_curaid);
  1080. /* Set aggregation protection mode parameters */
  1081. sc->sc_config.ath_aggr_prot = 0;
  1082. /*
  1083. * Reset our TSF so that its value is lower than the
  1084. * beacon that we are trying to catch.
  1085. * Only then hw will update its TSF register with the
  1086. * new beacon. Reset the TSF before setting the BSSID
  1087. * to avoid allowing in any frames that would update
  1088. * our TSF only to have us clear it
  1089. * immediately thereafter.
  1090. */
  1091. ath9k_hw_reset_tsf(sc->sc_ah);
  1092. /* Disable BMISS interrupt when we're not associated */
  1093. ath9k_hw_set_interrupts(sc->sc_ah,
  1094. sc->sc_imask &
  1095. ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
  1096. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1097. DPRINTF(sc, ATH_DBG_CONFIG,
  1098. "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
  1099. __func__, rfilt,
  1100. sc->sc_curbssid, sc->sc_curaid);
  1101. /* need to reconfigure the beacon */
  1102. sc->sc_flags &= ~SC_OP_BEACONS ;
  1103. break;
  1104. default:
  1105. break;
  1106. }
  1107. }
  1108. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  1109. ((vif->type == NL80211_IFTYPE_ADHOC) ||
  1110. (vif->type == NL80211_IFTYPE_AP))) {
  1111. /*
  1112. * Allocate and setup the beacon frame.
  1113. *
  1114. * Stop any previous beacon DMA. This may be
  1115. * necessary, for example, when an ibss merge
  1116. * causes reconfiguration; we may be called
  1117. * with beacon transmission active.
  1118. */
  1119. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  1120. error = ath_beacon_alloc(sc, 0);
  1121. if (error != 0)
  1122. return error;
  1123. ath_beacon_sync(sc, 0);
  1124. }
  1125. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  1126. if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
  1127. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  1128. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  1129. ath9k_hw_keysetmac(sc->sc_ah,
  1130. (u16)i,
  1131. sc->sc_curbssid);
  1132. }
  1133. /* Only legacy IBSS for now */
  1134. if (vif->type == NL80211_IFTYPE_ADHOC)
  1135. ath_update_chainmask(sc, 0);
  1136. return 0;
  1137. }
  1138. #define SUPPORTED_FILTERS \
  1139. (FIF_PROMISC_IN_BSS | \
  1140. FIF_ALLMULTI | \
  1141. FIF_CONTROL | \
  1142. FIF_OTHER_BSS | \
  1143. FIF_BCN_PRBRESP_PROMISC | \
  1144. FIF_FCSFAIL)
  1145. /* FIXME: sc->sc_full_reset ? */
  1146. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1147. unsigned int changed_flags,
  1148. unsigned int *total_flags,
  1149. int mc_count,
  1150. struct dev_mc_list *mclist)
  1151. {
  1152. struct ath_softc *sc = hw->priv;
  1153. u32 rfilt;
  1154. changed_flags &= SUPPORTED_FILTERS;
  1155. *total_flags &= SUPPORTED_FILTERS;
  1156. sc->rx_filter = *total_flags;
  1157. rfilt = ath_calcrxfilter(sc);
  1158. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1159. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1160. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1161. ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
  1162. }
  1163. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
  1164. __func__, sc->rx_filter);
  1165. }
  1166. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1167. struct ieee80211_vif *vif,
  1168. enum sta_notify_cmd cmd,
  1169. struct ieee80211_sta *sta)
  1170. {
  1171. struct ath_softc *sc = hw->priv;
  1172. struct ath_node *an;
  1173. unsigned long flags;
  1174. spin_lock_irqsave(&sc->node_lock, flags);
  1175. an = ath_node_find(sc, sta->addr);
  1176. spin_unlock_irqrestore(&sc->node_lock, flags);
  1177. switch (cmd) {
  1178. case STA_NOTIFY_ADD:
  1179. spin_lock_irqsave(&sc->node_lock, flags);
  1180. if (!an) {
  1181. ath_node_attach(sc, sta->addr, 0);
  1182. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %pM\n",
  1183. __func__, sta->addr);
  1184. } else {
  1185. ath_node_get(sc, sta->addr);
  1186. }
  1187. /* XXX: Is this right? Can the capabilities change? */
  1188. an = ath_node_find(sc, sta->addr);
  1189. an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
  1190. sta->ht_cap.ampdu_factor);
  1191. an->mpdudensity =
  1192. parse_mpdudensity(sta->ht_cap.ampdu_density);
  1193. spin_unlock_irqrestore(&sc->node_lock, flags);
  1194. break;
  1195. case STA_NOTIFY_REMOVE:
  1196. if (!an)
  1197. DPRINTF(sc, ATH_DBG_FATAL,
  1198. "%s: Removal of a non-existent node\n",
  1199. __func__);
  1200. else {
  1201. ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
  1202. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %pM\n",
  1203. __func__,
  1204. sta->addr);
  1205. }
  1206. break;
  1207. default:
  1208. break;
  1209. }
  1210. }
  1211. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1212. u16 queue,
  1213. const struct ieee80211_tx_queue_params *params)
  1214. {
  1215. struct ath_softc *sc = hw->priv;
  1216. struct ath9k_tx_queue_info qi;
  1217. int ret = 0, qnum;
  1218. if (queue >= WME_NUM_AC)
  1219. return 0;
  1220. qi.tqi_aifs = params->aifs;
  1221. qi.tqi_cwmin = params->cw_min;
  1222. qi.tqi_cwmax = params->cw_max;
  1223. qi.tqi_burstTime = params->txop;
  1224. qnum = ath_get_hal_qnum(queue, sc);
  1225. DPRINTF(sc, ATH_DBG_CONFIG,
  1226. "%s: Configure tx [queue/halq] [%d/%d], "
  1227. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1228. __func__,
  1229. queue,
  1230. qnum,
  1231. params->aifs,
  1232. params->cw_min,
  1233. params->cw_max,
  1234. params->txop);
  1235. ret = ath_txq_update(sc, qnum, &qi);
  1236. if (ret)
  1237. DPRINTF(sc, ATH_DBG_FATAL,
  1238. "%s: TXQ Update failed\n", __func__);
  1239. return ret;
  1240. }
  1241. static int ath9k_set_key(struct ieee80211_hw *hw,
  1242. enum set_key_cmd cmd,
  1243. const u8 *local_addr,
  1244. const u8 *addr,
  1245. struct ieee80211_key_conf *key)
  1246. {
  1247. struct ath_softc *sc = hw->priv;
  1248. int ret = 0;
  1249. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  1250. switch (cmd) {
  1251. case SET_KEY:
  1252. ret = ath_key_config(sc, addr, key);
  1253. if (!ret) {
  1254. set_bit(key->keyidx, sc->sc_keymap);
  1255. key->hw_key_idx = key->keyidx;
  1256. /* push IV and Michael MIC generation to stack */
  1257. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1258. if (key->alg == ALG_TKIP)
  1259. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1260. }
  1261. break;
  1262. case DISABLE_KEY:
  1263. ath_key_delete(sc, key);
  1264. clear_bit(key->keyidx, sc->sc_keymap);
  1265. break;
  1266. default:
  1267. ret = -EINVAL;
  1268. }
  1269. return ret;
  1270. }
  1271. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1272. struct ieee80211_vif *vif,
  1273. struct ieee80211_bss_conf *bss_conf,
  1274. u32 changed)
  1275. {
  1276. struct ath_softc *sc = hw->priv;
  1277. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1278. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  1279. __func__,
  1280. bss_conf->use_short_preamble);
  1281. if (bss_conf->use_short_preamble)
  1282. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1283. else
  1284. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1285. }
  1286. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1287. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  1288. __func__,
  1289. bss_conf->use_cts_prot);
  1290. if (bss_conf->use_cts_prot &&
  1291. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1292. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1293. else
  1294. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1295. }
  1296. if (changed & BSS_CHANGED_HT) {
  1297. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT\n",
  1298. __func__);
  1299. ath9k_ht_conf(sc, bss_conf);
  1300. }
  1301. if (changed & BSS_CHANGED_ASSOC) {
  1302. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  1303. __func__,
  1304. bss_conf->assoc);
  1305. ath9k_bss_assoc_info(sc, bss_conf);
  1306. }
  1307. }
  1308. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1309. {
  1310. u64 tsf;
  1311. struct ath_softc *sc = hw->priv;
  1312. struct ath_hal *ah = sc->sc_ah;
  1313. tsf = ath9k_hw_gettsf64(ah);
  1314. return tsf;
  1315. }
  1316. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1317. {
  1318. struct ath_softc *sc = hw->priv;
  1319. struct ath_hal *ah = sc->sc_ah;
  1320. ath9k_hw_reset_tsf(ah);
  1321. }
  1322. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1323. enum ieee80211_ampdu_mlme_action action,
  1324. struct ieee80211_sta *sta,
  1325. u16 tid, u16 *ssn)
  1326. {
  1327. struct ath_softc *sc = hw->priv;
  1328. int ret = 0;
  1329. switch (action) {
  1330. case IEEE80211_AMPDU_RX_START:
  1331. ret = ath_rx_aggr_start(sc, sta->addr, tid, ssn);
  1332. if (ret < 0)
  1333. DPRINTF(sc, ATH_DBG_FATAL,
  1334. "%s: Unable to start RX aggregation\n",
  1335. __func__);
  1336. break;
  1337. case IEEE80211_AMPDU_RX_STOP:
  1338. ret = ath_rx_aggr_stop(sc, sta->addr, tid);
  1339. if (ret < 0)
  1340. DPRINTF(sc, ATH_DBG_FATAL,
  1341. "%s: Unable to stop RX aggregation\n",
  1342. __func__);
  1343. break;
  1344. case IEEE80211_AMPDU_TX_START:
  1345. ret = ath_tx_aggr_start(sc, sta->addr, tid, ssn);
  1346. if (ret < 0)
  1347. DPRINTF(sc, ATH_DBG_FATAL,
  1348. "%s: Unable to start TX aggregation\n",
  1349. __func__);
  1350. else
  1351. ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1352. break;
  1353. case IEEE80211_AMPDU_TX_STOP:
  1354. ret = ath_tx_aggr_stop(sc, sta->addr, tid);
  1355. if (ret < 0)
  1356. DPRINTF(sc, ATH_DBG_FATAL,
  1357. "%s: Unable to stop TX aggregation\n",
  1358. __func__);
  1359. ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1360. break;
  1361. default:
  1362. DPRINTF(sc, ATH_DBG_FATAL,
  1363. "%s: Unknown AMPDU action\n", __func__);
  1364. }
  1365. return ret;
  1366. }
  1367. static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
  1368. {
  1369. return -EOPNOTSUPP;
  1370. }
  1371. static struct ieee80211_ops ath9k_ops = {
  1372. .tx = ath9k_tx,
  1373. .start = ath9k_start,
  1374. .stop = ath9k_stop,
  1375. .add_interface = ath9k_add_interface,
  1376. .remove_interface = ath9k_remove_interface,
  1377. .config = ath9k_config,
  1378. .config_interface = ath9k_config_interface,
  1379. .configure_filter = ath9k_configure_filter,
  1380. .get_stats = NULL,
  1381. .sta_notify = ath9k_sta_notify,
  1382. .conf_tx = ath9k_conf_tx,
  1383. .get_tx_stats = NULL,
  1384. .bss_info_changed = ath9k_bss_info_changed,
  1385. .set_tim = NULL,
  1386. .set_key = ath9k_set_key,
  1387. .hw_scan = NULL,
  1388. .get_tkip_seq = NULL,
  1389. .set_rts_threshold = NULL,
  1390. .set_frag_threshold = NULL,
  1391. .get_tsf = ath9k_get_tsf,
  1392. .reset_tsf = ath9k_reset_tsf,
  1393. .tx_last_beacon = NULL,
  1394. .ampdu_action = ath9k_ampdu_action,
  1395. .set_frag_threshold = ath9k_no_fragmentation,
  1396. };
  1397. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1398. {
  1399. void __iomem *mem;
  1400. struct ath_softc *sc;
  1401. struct ieee80211_hw *hw;
  1402. const char *athname;
  1403. u8 csz;
  1404. u32 val;
  1405. int ret = 0;
  1406. if (pci_enable_device(pdev))
  1407. return -EIO;
  1408. /* XXX 32-bit addressing only */
  1409. if (pci_set_dma_mask(pdev, 0xffffffff)) {
  1410. printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
  1411. ret = -ENODEV;
  1412. goto bad;
  1413. }
  1414. /*
  1415. * Cache line size is used to size and align various
  1416. * structures used to communicate with the hardware.
  1417. */
  1418. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1419. if (csz == 0) {
  1420. /*
  1421. * Linux 2.4.18 (at least) writes the cache line size
  1422. * register as a 16-bit wide register which is wrong.
  1423. * We must have this setup properly for rx buffer
  1424. * DMA to work so force a reasonable value here if it
  1425. * comes up zero.
  1426. */
  1427. csz = L1_CACHE_BYTES / sizeof(u32);
  1428. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1429. }
  1430. /*
  1431. * The default setting of latency timer yields poor results,
  1432. * set it to the value used by other systems. It may be worth
  1433. * tweaking this setting more.
  1434. */
  1435. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1436. pci_set_master(pdev);
  1437. /*
  1438. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1439. * PCI Tx retries from interfering with C3 CPU state.
  1440. */
  1441. pci_read_config_dword(pdev, 0x40, &val);
  1442. if ((val & 0x0000ff00) != 0)
  1443. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1444. ret = pci_request_region(pdev, 0, "ath9k");
  1445. if (ret) {
  1446. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1447. ret = -ENODEV;
  1448. goto bad;
  1449. }
  1450. mem = pci_iomap(pdev, 0, 0);
  1451. if (!mem) {
  1452. printk(KERN_ERR "PCI memory map error\n") ;
  1453. ret = -EIO;
  1454. goto bad1;
  1455. }
  1456. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1457. if (hw == NULL) {
  1458. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1459. goto bad2;
  1460. }
  1461. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  1462. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  1463. IEEE80211_HW_SIGNAL_DBM |
  1464. IEEE80211_HW_NOISE_DBM |
  1465. IEEE80211_HW_AMPDU_AGGREGATION;
  1466. hw->wiphy->interface_modes =
  1467. BIT(NL80211_IFTYPE_AP) |
  1468. BIT(NL80211_IFTYPE_STATION) |
  1469. BIT(NL80211_IFTYPE_ADHOC);
  1470. SET_IEEE80211_DEV(hw, &pdev->dev);
  1471. pci_set_drvdata(pdev, hw);
  1472. sc = hw->priv;
  1473. sc->hw = hw;
  1474. sc->pdev = pdev;
  1475. sc->mem = mem;
  1476. if (ath_attach(id->device, sc) != 0) {
  1477. ret = -ENODEV;
  1478. goto bad3;
  1479. }
  1480. /* setup interrupt service routine */
  1481. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1482. printk(KERN_ERR "%s: request_irq failed\n",
  1483. wiphy_name(hw->wiphy));
  1484. ret = -EIO;
  1485. goto bad4;
  1486. }
  1487. athname = ath9k_hw_probe(id->vendor, id->device);
  1488. printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
  1489. wiphy_name(hw->wiphy),
  1490. athname ? athname : "Atheros ???",
  1491. (unsigned long)mem, pdev->irq);
  1492. return 0;
  1493. bad4:
  1494. ath_detach(sc);
  1495. bad3:
  1496. ieee80211_free_hw(hw);
  1497. bad2:
  1498. pci_iounmap(pdev, mem);
  1499. bad1:
  1500. pci_release_region(pdev, 0);
  1501. bad:
  1502. pci_disable_device(pdev);
  1503. return ret;
  1504. }
  1505. static void ath_pci_remove(struct pci_dev *pdev)
  1506. {
  1507. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1508. struct ath_softc *sc = hw->priv;
  1509. enum ath9k_int status;
  1510. if (pdev->irq) {
  1511. ath9k_hw_set_interrupts(sc->sc_ah, 0);
  1512. /* clear the ISR */
  1513. ath9k_hw_getisr(sc->sc_ah, &status);
  1514. sc->sc_flags |= SC_OP_INVALID;
  1515. free_irq(pdev->irq, sc);
  1516. }
  1517. ath_detach(sc);
  1518. pci_iounmap(pdev, sc->mem);
  1519. pci_release_region(pdev, 0);
  1520. pci_disable_device(pdev);
  1521. ieee80211_free_hw(hw);
  1522. }
  1523. #ifdef CONFIG_PM
  1524. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1525. {
  1526. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1527. struct ath_softc *sc = hw->priv;
  1528. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1529. #ifdef CONFIG_RFKILL
  1530. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1531. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  1532. #endif
  1533. pci_save_state(pdev);
  1534. pci_disable_device(pdev);
  1535. pci_set_power_state(pdev, 3);
  1536. return 0;
  1537. }
  1538. static int ath_pci_resume(struct pci_dev *pdev)
  1539. {
  1540. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1541. struct ath_softc *sc = hw->priv;
  1542. u32 val;
  1543. int err;
  1544. err = pci_enable_device(pdev);
  1545. if (err)
  1546. return err;
  1547. pci_restore_state(pdev);
  1548. /*
  1549. * Suspend/Resume resets the PCI configuration space, so we have to
  1550. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1551. * PCI Tx retries from interfering with C3 CPU state
  1552. */
  1553. pci_read_config_dword(pdev, 0x40, &val);
  1554. if ((val & 0x0000ff00) != 0)
  1555. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1556. /* Enable LED */
  1557. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  1558. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  1559. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1560. #ifdef CONFIG_RFKILL
  1561. /*
  1562. * check the h/w rfkill state on resume
  1563. * and start the rfkill poll timer
  1564. */
  1565. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1566. queue_delayed_work(sc->hw->workqueue,
  1567. &sc->rf_kill.rfkill_poll, 0);
  1568. #endif
  1569. return 0;
  1570. }
  1571. #endif /* CONFIG_PM */
  1572. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1573. static struct pci_driver ath_pci_driver = {
  1574. .name = "ath9k",
  1575. .id_table = ath_pci_id_table,
  1576. .probe = ath_pci_probe,
  1577. .remove = ath_pci_remove,
  1578. #ifdef CONFIG_PM
  1579. .suspend = ath_pci_suspend,
  1580. .resume = ath_pci_resume,
  1581. #endif /* CONFIG_PM */
  1582. };
  1583. static int __init init_ath_pci(void)
  1584. {
  1585. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1586. if (pci_register_driver(&ath_pci_driver) < 0) {
  1587. printk(KERN_ERR
  1588. "ath_pci: No devices found, driver not installed.\n");
  1589. pci_unregister_driver(&ath_pci_driver);
  1590. return -ENODEV;
  1591. }
  1592. return 0;
  1593. }
  1594. module_init(init_ath_pci);
  1595. static void __exit exit_ath_pci(void)
  1596. {
  1597. pci_unregister_driver(&ath_pci_driver);
  1598. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1599. }
  1600. module_exit(exit_ath_pci);