twl4030.c 73 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/slab.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/soc.h>
  34. #include <sound/soc-dapm.h>
  35. #include <sound/initval.h>
  36. #include <sound/tlv.h>
  37. #include "twl4030.h"
  38. /*
  39. * twl4030 register cache & default register settings
  40. */
  41. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  42. 0x00, /* this register not used */
  43. 0x00, /* REG_CODEC_MODE (0x1) */
  44. 0x00, /* REG_OPTION (0x2) */
  45. 0x00, /* REG_UNKNOWN (0x3) */
  46. 0x00, /* REG_MICBIAS_CTL (0x4) */
  47. 0x00, /* REG_ANAMICL (0x5) */
  48. 0x00, /* REG_ANAMICR (0x6) */
  49. 0x00, /* REG_AVADC_CTL (0x7) */
  50. 0x00, /* REG_ADCMICSEL (0x8) */
  51. 0x00, /* REG_DIGMIXING (0x9) */
  52. 0x0f, /* REG_ATXL1PGA (0xA) */
  53. 0x0f, /* REG_ATXR1PGA (0xB) */
  54. 0x0f, /* REG_AVTXL2PGA (0xC) */
  55. 0x0f, /* REG_AVTXR2PGA (0xD) */
  56. 0x00, /* REG_AUDIO_IF (0xE) */
  57. 0x00, /* REG_VOICE_IF (0xF) */
  58. 0x3f, /* REG_ARXR1PGA (0x10) */
  59. 0x3f, /* REG_ARXL1PGA (0x11) */
  60. 0x3f, /* REG_ARXR2PGA (0x12) */
  61. 0x3f, /* REG_ARXL2PGA (0x13) */
  62. 0x25, /* REG_VRXPGA (0x14) */
  63. 0x00, /* REG_VSTPGA (0x15) */
  64. 0x00, /* REG_VRX2ARXPGA (0x16) */
  65. 0x00, /* REG_AVDAC_CTL (0x17) */
  66. 0x00, /* REG_ARX2VTXPGA (0x18) */
  67. 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
  68. 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
  69. 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
  70. 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
  71. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  72. 0x00, /* REG_BT_IF (0x1E) */
  73. 0x55, /* REG_BTPGA (0x1F) */
  74. 0x00, /* REG_BTSTPGA (0x20) */
  75. 0x00, /* REG_EAR_CTL (0x21) */
  76. 0x00, /* REG_HS_SEL (0x22) */
  77. 0x00, /* REG_HS_GAIN_SET (0x23) */
  78. 0x00, /* REG_HS_POPN_SET (0x24) */
  79. 0x00, /* REG_PREDL_CTL (0x25) */
  80. 0x00, /* REG_PREDR_CTL (0x26) */
  81. 0x00, /* REG_PRECKL_CTL (0x27) */
  82. 0x00, /* REG_PRECKR_CTL (0x28) */
  83. 0x00, /* REG_HFL_CTL (0x29) */
  84. 0x00, /* REG_HFR_CTL (0x2A) */
  85. 0x05, /* REG_ALC_CTL (0x2B) */
  86. 0x00, /* REG_ALC_SET1 (0x2C) */
  87. 0x00, /* REG_ALC_SET2 (0x2D) */
  88. 0x00, /* REG_BOOST_CTL (0x2E) */
  89. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  90. 0x13, /* REG_DTMF_FREQSEL (0x30) */
  91. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  92. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  93. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  94. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  95. 0x79, /* REG_DTMF_TONOFF (0x35) */
  96. 0x11, /* REG_DTMF_WANONOFF (0x36) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  99. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  100. 0x06, /* REG_APLL_CTL (0x3A) */
  101. 0x00, /* REG_DTMF_CTL (0x3B) */
  102. 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
  103. 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
  104. 0x00, /* REG_MISC_SET_1 (0x3E) */
  105. 0x00, /* REG_PCMBTMUX (0x3F) */
  106. 0x00, /* not used (0x40) */
  107. 0x00, /* not used (0x41) */
  108. 0x00, /* not used (0x42) */
  109. 0x00, /* REG_RX_PATH_SEL (0x43) */
  110. 0x32, /* REG_VDL_APGA_CTL (0x44) */
  111. 0x00, /* REG_VIBRA_CTL (0x45) */
  112. 0x00, /* REG_VIBRA_SET (0x46) */
  113. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  114. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  115. 0x00, /* REG_MISC_SET_2 (0x49) */
  116. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  117. };
  118. /* codec private data */
  119. struct twl4030_priv {
  120. struct snd_soc_codec codec;
  121. unsigned int codec_powered;
  122. /* reference counts of AIF/APLL users */
  123. unsigned int apll_enabled;
  124. struct snd_pcm_substream *master_substream;
  125. struct snd_pcm_substream *slave_substream;
  126. unsigned int configured;
  127. unsigned int rate;
  128. unsigned int sample_bits;
  129. unsigned int channels;
  130. unsigned int sysclk;
  131. /* Output (with associated amp) states */
  132. u8 hsl_enabled, hsr_enabled;
  133. u8 earpiece_enabled;
  134. u8 predrivel_enabled, predriver_enabled;
  135. u8 carkitl_enabled, carkitr_enabled;
  136. };
  137. /*
  138. * read twl4030 register cache
  139. */
  140. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  141. unsigned int reg)
  142. {
  143. u8 *cache = codec->reg_cache;
  144. if (reg >= TWL4030_CACHEREGNUM)
  145. return -EIO;
  146. return cache[reg];
  147. }
  148. /*
  149. * write twl4030 register cache
  150. */
  151. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  152. u8 reg, u8 value)
  153. {
  154. u8 *cache = codec->reg_cache;
  155. if (reg >= TWL4030_CACHEREGNUM)
  156. return;
  157. cache[reg] = value;
  158. }
  159. /*
  160. * write to the twl4030 register space
  161. */
  162. static int twl4030_write(struct snd_soc_codec *codec,
  163. unsigned int reg, unsigned int value)
  164. {
  165. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  166. int write_to_reg = 0;
  167. twl4030_write_reg_cache(codec, reg, value);
  168. if (likely(reg < TWL4030_REG_SW_SHADOW)) {
  169. /* Decide if the given register can be written */
  170. switch (reg) {
  171. case TWL4030_REG_EAR_CTL:
  172. if (twl4030->earpiece_enabled)
  173. write_to_reg = 1;
  174. break;
  175. case TWL4030_REG_PREDL_CTL:
  176. if (twl4030->predrivel_enabled)
  177. write_to_reg = 1;
  178. break;
  179. case TWL4030_REG_PREDR_CTL:
  180. if (twl4030->predriver_enabled)
  181. write_to_reg = 1;
  182. break;
  183. case TWL4030_REG_PRECKL_CTL:
  184. if (twl4030->carkitl_enabled)
  185. write_to_reg = 1;
  186. break;
  187. case TWL4030_REG_PRECKR_CTL:
  188. if (twl4030->carkitr_enabled)
  189. write_to_reg = 1;
  190. break;
  191. case TWL4030_REG_HS_GAIN_SET:
  192. if (twl4030->hsl_enabled || twl4030->hsr_enabled)
  193. write_to_reg = 1;
  194. break;
  195. default:
  196. /* All other register can be written */
  197. write_to_reg = 1;
  198. break;
  199. }
  200. if (write_to_reg)
  201. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  202. value, reg);
  203. }
  204. return 0;
  205. }
  206. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  207. {
  208. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  209. int mode;
  210. if (enable == twl4030->codec_powered)
  211. return;
  212. if (enable)
  213. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  214. else
  215. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  216. if (mode >= 0) {
  217. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  218. twl4030->codec_powered = enable;
  219. }
  220. /* REVISIT: this delay is present in TI sample drivers */
  221. /* but there seems to be no TRM requirement for it */
  222. udelay(10);
  223. }
  224. static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
  225. {
  226. int i, difference = 0;
  227. u8 val;
  228. dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
  229. for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
  230. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
  231. if (val != twl4030_reg[i]) {
  232. difference++;
  233. dev_dbg(codec->dev,
  234. "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
  235. i, val, twl4030_reg[i]);
  236. }
  237. }
  238. dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
  239. difference, difference ? "Not OK" : "OK");
  240. }
  241. static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
  242. {
  243. int i;
  244. /* set all audio section registers to reasonable defaults */
  245. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  246. if (i != TWL4030_REG_APLL_CTL)
  247. twl4030_write(codec, i, twl4030_reg[i]);
  248. }
  249. static void twl4030_init_chip(struct platform_device *pdev)
  250. {
  251. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  252. struct twl4030_setup_data *setup = socdev->codec_data;
  253. struct snd_soc_codec *codec = socdev->card->codec;
  254. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  255. u8 reg, byte;
  256. int i = 0;
  257. /* Check defaults, if instructed before anything else */
  258. if (setup && setup->check_defaults)
  259. twl4030_check_defaults(codec);
  260. /* Reset registers, if no setup data or if instructed to do so */
  261. if (!setup || (setup && setup->reset_registers))
  262. twl4030_reset_registers(codec);
  263. /* Refresh APLL_CTL register from HW */
  264. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  265. TWL4030_REG_APLL_CTL);
  266. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
  267. /* anti-pop when changing analog gain */
  268. reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  269. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  270. reg | TWL4030_SMOOTH_ANAVOL_EN);
  271. twl4030_write(codec, TWL4030_REG_OPTION,
  272. TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
  273. TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
  274. /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
  275. twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
  276. /* Machine dependent setup */
  277. if (!setup)
  278. return;
  279. /* Configuration for headset ramp delay from setup data */
  280. if (setup->sysclk != twl4030->sysclk)
  281. dev_warn(codec->dev,
  282. "Mismatch in APLL mclk: %u (configured: %u)\n",
  283. setup->sysclk, twl4030->sysclk);
  284. reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  285. reg &= ~TWL4030_RAMP_DELAY;
  286. reg |= (setup->ramp_delay_value << 2);
  287. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
  288. /* initiate offset cancellation */
  289. twl4030_codec_enable(codec, 1);
  290. reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  291. reg &= ~TWL4030_OFFSET_CNCL_SEL;
  292. reg |= setup->offset_cncl_path;
  293. twl4030_write(codec, TWL4030_REG_ANAMICL,
  294. reg | TWL4030_CNCL_OFFSET_START);
  295. /* wait for offset cancellation to complete */
  296. do {
  297. /* this takes a little while, so don't slam i2c */
  298. udelay(2000);
  299. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  300. TWL4030_REG_ANAMICL);
  301. } while ((i++ < 100) &&
  302. ((byte & TWL4030_CNCL_OFFSET_START) ==
  303. TWL4030_CNCL_OFFSET_START));
  304. /* Make sure that the reg_cache has the same value as the HW */
  305. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  306. twl4030_codec_enable(codec, 0);
  307. }
  308. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  309. {
  310. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  311. int status = -1;
  312. if (enable) {
  313. twl4030->apll_enabled++;
  314. if (twl4030->apll_enabled == 1)
  315. status = twl4030_codec_enable_resource(
  316. TWL4030_CODEC_RES_APLL);
  317. } else {
  318. twl4030->apll_enabled--;
  319. if (!twl4030->apll_enabled)
  320. status = twl4030_codec_disable_resource(
  321. TWL4030_CODEC_RES_APLL);
  322. }
  323. if (status >= 0)
  324. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  325. }
  326. /* Earpiece */
  327. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  328. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  329. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  330. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  331. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  332. };
  333. /* PreDrive Left */
  334. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  335. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  336. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  337. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  338. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  339. };
  340. /* PreDrive Right */
  341. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  342. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  343. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  344. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  345. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  346. };
  347. /* Headset Left */
  348. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  349. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  350. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  351. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  352. };
  353. /* Headset Right */
  354. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  355. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  356. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  357. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  358. };
  359. /* Carkit Left */
  360. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  361. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  362. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  363. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  364. };
  365. /* Carkit Right */
  366. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  367. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  368. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  369. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  370. };
  371. /* Handsfree Left */
  372. static const char *twl4030_handsfreel_texts[] =
  373. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  374. static const struct soc_enum twl4030_handsfreel_enum =
  375. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  376. ARRAY_SIZE(twl4030_handsfreel_texts),
  377. twl4030_handsfreel_texts);
  378. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  379. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  380. /* Handsfree Left virtual mute */
  381. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  382. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  383. /* Handsfree Right */
  384. static const char *twl4030_handsfreer_texts[] =
  385. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  386. static const struct soc_enum twl4030_handsfreer_enum =
  387. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  388. ARRAY_SIZE(twl4030_handsfreer_texts),
  389. twl4030_handsfreer_texts);
  390. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  391. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  392. /* Handsfree Right virtual mute */
  393. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  394. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  395. /* Vibra */
  396. /* Vibra audio path selection */
  397. static const char *twl4030_vibra_texts[] =
  398. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  399. static const struct soc_enum twl4030_vibra_enum =
  400. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  401. ARRAY_SIZE(twl4030_vibra_texts),
  402. twl4030_vibra_texts);
  403. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  404. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  405. /* Vibra path selection: local vibrator (PWM) or audio driven */
  406. static const char *twl4030_vibrapath_texts[] =
  407. {"Local vibrator", "Audio"};
  408. static const struct soc_enum twl4030_vibrapath_enum =
  409. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  410. ARRAY_SIZE(twl4030_vibrapath_texts),
  411. twl4030_vibrapath_texts);
  412. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  413. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  414. /* Left analog microphone selection */
  415. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  416. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  417. TWL4030_REG_ANAMICL, 0, 1, 0),
  418. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  419. TWL4030_REG_ANAMICL, 1, 1, 0),
  420. SOC_DAPM_SINGLE("AUXL Capture Switch",
  421. TWL4030_REG_ANAMICL, 2, 1, 0),
  422. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  423. TWL4030_REG_ANAMICL, 3, 1, 0),
  424. };
  425. /* Right analog microphone selection */
  426. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  427. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  428. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  429. };
  430. /* TX1 L/R Analog/Digital microphone selection */
  431. static const char *twl4030_micpathtx1_texts[] =
  432. {"Analog", "Digimic0"};
  433. static const struct soc_enum twl4030_micpathtx1_enum =
  434. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  435. ARRAY_SIZE(twl4030_micpathtx1_texts),
  436. twl4030_micpathtx1_texts);
  437. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  438. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  439. /* TX2 L/R Analog/Digital microphone selection */
  440. static const char *twl4030_micpathtx2_texts[] =
  441. {"Analog", "Digimic1"};
  442. static const struct soc_enum twl4030_micpathtx2_enum =
  443. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  444. ARRAY_SIZE(twl4030_micpathtx2_texts),
  445. twl4030_micpathtx2_texts);
  446. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  447. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  448. /* Analog bypass for AudioR1 */
  449. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  450. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  451. /* Analog bypass for AudioL1 */
  452. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  453. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  454. /* Analog bypass for AudioR2 */
  455. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  456. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  457. /* Analog bypass for AudioL2 */
  458. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  459. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  460. /* Analog bypass for Voice */
  461. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  462. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  463. /* Digital bypass gain, mute instead of -30dB */
  464. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  465. TLV_DB_RANGE_HEAD(3),
  466. 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
  467. 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
  468. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  469. };
  470. /* Digital bypass left (TX1L -> RX2L) */
  471. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  472. SOC_DAPM_SINGLE_TLV("Volume",
  473. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  474. twl4030_dapm_dbypass_tlv);
  475. /* Digital bypass right (TX1R -> RX2R) */
  476. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  477. SOC_DAPM_SINGLE_TLV("Volume",
  478. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  479. twl4030_dapm_dbypass_tlv);
  480. /*
  481. * Voice Sidetone GAIN volume control:
  482. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  483. */
  484. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  485. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  486. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  487. SOC_DAPM_SINGLE_TLV("Volume",
  488. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  489. twl4030_dapm_dbypassv_tlv);
  490. static int micpath_event(struct snd_soc_dapm_widget *w,
  491. struct snd_kcontrol *kcontrol, int event)
  492. {
  493. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  494. unsigned char adcmicsel, micbias_ctl;
  495. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  496. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  497. /* Prepare the bits for the given TX path:
  498. * shift_l == 0: TX1 microphone path
  499. * shift_l == 2: TX2 microphone path */
  500. if (e->shift_l) {
  501. /* TX2 microphone path */
  502. if (adcmicsel & TWL4030_TX2IN_SEL)
  503. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  504. else
  505. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  506. } else {
  507. /* TX1 microphone path */
  508. if (adcmicsel & TWL4030_TX1IN_SEL)
  509. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  510. else
  511. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  512. }
  513. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  514. return 0;
  515. }
  516. /*
  517. * Output PGA builder:
  518. * Handle the muting and unmuting of the given output (turning off the
  519. * amplifier associated with the output pin)
  520. * On mute bypass the reg_cache and write 0 to the register
  521. * On unmute: restore the register content from the reg_cache
  522. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  523. */
  524. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  525. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  526. struct snd_kcontrol *kcontrol, int event) \
  527. { \
  528. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
  529. \
  530. switch (event) { \
  531. case SND_SOC_DAPM_POST_PMU: \
  532. twl4030->pin_name##_enabled = 1; \
  533. twl4030_write(w->codec, reg, \
  534. twl4030_read_reg_cache(w->codec, reg)); \
  535. break; \
  536. case SND_SOC_DAPM_POST_PMD: \
  537. twl4030->pin_name##_enabled = 0; \
  538. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  539. 0, reg); \
  540. break; \
  541. } \
  542. return 0; \
  543. }
  544. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  545. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  546. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  547. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  548. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  549. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  550. {
  551. unsigned char hs_ctl;
  552. hs_ctl = twl4030_read_reg_cache(codec, reg);
  553. if (ramp) {
  554. /* HF ramp-up */
  555. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  556. twl4030_write(codec, reg, hs_ctl);
  557. udelay(10);
  558. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  559. twl4030_write(codec, reg, hs_ctl);
  560. udelay(40);
  561. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  562. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  563. twl4030_write(codec, reg, hs_ctl);
  564. } else {
  565. /* HF ramp-down */
  566. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  567. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  568. twl4030_write(codec, reg, hs_ctl);
  569. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  570. twl4030_write(codec, reg, hs_ctl);
  571. udelay(40);
  572. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  573. twl4030_write(codec, reg, hs_ctl);
  574. }
  575. }
  576. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  577. struct snd_kcontrol *kcontrol, int event)
  578. {
  579. switch (event) {
  580. case SND_SOC_DAPM_POST_PMU:
  581. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  582. break;
  583. case SND_SOC_DAPM_POST_PMD:
  584. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  585. break;
  586. }
  587. return 0;
  588. }
  589. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  590. struct snd_kcontrol *kcontrol, int event)
  591. {
  592. switch (event) {
  593. case SND_SOC_DAPM_POST_PMU:
  594. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  595. break;
  596. case SND_SOC_DAPM_POST_PMD:
  597. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  598. break;
  599. }
  600. return 0;
  601. }
  602. static int vibramux_event(struct snd_soc_dapm_widget *w,
  603. struct snd_kcontrol *kcontrol, int event)
  604. {
  605. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  606. return 0;
  607. }
  608. static int apll_event(struct snd_soc_dapm_widget *w,
  609. struct snd_kcontrol *kcontrol, int event)
  610. {
  611. switch (event) {
  612. case SND_SOC_DAPM_PRE_PMU:
  613. twl4030_apll_enable(w->codec, 1);
  614. break;
  615. case SND_SOC_DAPM_POST_PMD:
  616. twl4030_apll_enable(w->codec, 0);
  617. break;
  618. }
  619. return 0;
  620. }
  621. static int aif_event(struct snd_soc_dapm_widget *w,
  622. struct snd_kcontrol *kcontrol, int event)
  623. {
  624. u8 audio_if;
  625. audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
  626. switch (event) {
  627. case SND_SOC_DAPM_PRE_PMU:
  628. /* Enable AIF */
  629. /* enable the PLL before we use it to clock the DAI */
  630. twl4030_apll_enable(w->codec, 1);
  631. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  632. audio_if | TWL4030_AIF_EN);
  633. break;
  634. case SND_SOC_DAPM_POST_PMD:
  635. /* disable the DAI before we stop it's source PLL */
  636. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  637. audio_if & ~TWL4030_AIF_EN);
  638. twl4030_apll_enable(w->codec, 0);
  639. break;
  640. }
  641. return 0;
  642. }
  643. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  644. {
  645. struct snd_soc_device *socdev = codec->socdev;
  646. struct twl4030_setup_data *setup = socdev->codec_data;
  647. unsigned char hs_gain, hs_pop;
  648. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  649. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  650. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  651. 8388608, 16777216, 33554432, 67108864};
  652. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  653. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  654. /* Enable external mute control, this dramatically reduces
  655. * the pop-noise */
  656. if (setup && setup->hs_extmute) {
  657. if (setup->set_hs_extmute) {
  658. setup->set_hs_extmute(1);
  659. } else {
  660. hs_pop |= TWL4030_EXTMUTE;
  661. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  662. }
  663. }
  664. if (ramp) {
  665. /* Headset ramp-up according to the TRM */
  666. hs_pop |= TWL4030_VMID_EN;
  667. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  668. /* Actually write to the register */
  669. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  670. hs_gain,
  671. TWL4030_REG_HS_GAIN_SET);
  672. hs_pop |= TWL4030_RAMP_EN;
  673. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  674. /* Wait ramp delay time + 1, so the VMID can settle */
  675. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  676. twl4030->sysclk) + 1);
  677. } else {
  678. /* Headset ramp-down _not_ according to
  679. * the TRM, but in a way that it is working */
  680. hs_pop &= ~TWL4030_RAMP_EN;
  681. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  682. /* Wait ramp delay time + 1, so the VMID can settle */
  683. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  684. twl4030->sysclk) + 1);
  685. /* Bypass the reg_cache to mute the headset */
  686. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  687. hs_gain & (~0x0f),
  688. TWL4030_REG_HS_GAIN_SET);
  689. hs_pop &= ~TWL4030_VMID_EN;
  690. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  691. }
  692. /* Disable external mute */
  693. if (setup && setup->hs_extmute) {
  694. if (setup->set_hs_extmute) {
  695. setup->set_hs_extmute(0);
  696. } else {
  697. hs_pop &= ~TWL4030_EXTMUTE;
  698. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  699. }
  700. }
  701. }
  702. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  703. struct snd_kcontrol *kcontrol, int event)
  704. {
  705. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  706. switch (event) {
  707. case SND_SOC_DAPM_POST_PMU:
  708. /* Do the ramp-up only once */
  709. if (!twl4030->hsr_enabled)
  710. headset_ramp(w->codec, 1);
  711. twl4030->hsl_enabled = 1;
  712. break;
  713. case SND_SOC_DAPM_POST_PMD:
  714. /* Do the ramp-down only if both headsetL/R is disabled */
  715. if (!twl4030->hsr_enabled)
  716. headset_ramp(w->codec, 0);
  717. twl4030->hsl_enabled = 0;
  718. break;
  719. }
  720. return 0;
  721. }
  722. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  723. struct snd_kcontrol *kcontrol, int event)
  724. {
  725. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  726. switch (event) {
  727. case SND_SOC_DAPM_POST_PMU:
  728. /* Do the ramp-up only once */
  729. if (!twl4030->hsl_enabled)
  730. headset_ramp(w->codec, 1);
  731. twl4030->hsr_enabled = 1;
  732. break;
  733. case SND_SOC_DAPM_POST_PMD:
  734. /* Do the ramp-down only if both headsetL/R is disabled */
  735. if (!twl4030->hsl_enabled)
  736. headset_ramp(w->codec, 0);
  737. twl4030->hsr_enabled = 0;
  738. break;
  739. }
  740. return 0;
  741. }
  742. /*
  743. * Some of the gain controls in TWL (mostly those which are associated with
  744. * the outputs) are implemented in an interesting way:
  745. * 0x0 : Power down (mute)
  746. * 0x1 : 6dB
  747. * 0x2 : 0 dB
  748. * 0x3 : -6 dB
  749. * Inverting not going to help with these.
  750. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  751. */
  752. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  753. xinvert, tlv_array) \
  754. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  755. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  756. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  757. .tlv.p = (tlv_array), \
  758. .info = snd_soc_info_volsw, \
  759. .get = snd_soc_get_volsw_twl4030, \
  760. .put = snd_soc_put_volsw_twl4030, \
  761. .private_value = (unsigned long)&(struct soc_mixer_control) \
  762. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  763. .max = xmax, .invert = xinvert} }
  764. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  765. xinvert, tlv_array) \
  766. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  767. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  768. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  769. .tlv.p = (tlv_array), \
  770. .info = snd_soc_info_volsw_2r, \
  771. .get = snd_soc_get_volsw_r2_twl4030,\
  772. .put = snd_soc_put_volsw_r2_twl4030, \
  773. .private_value = (unsigned long)&(struct soc_mixer_control) \
  774. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  775. .rshift = xshift, .max = xmax, .invert = xinvert} }
  776. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  777. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  778. xinvert, tlv_array)
  779. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  780. struct snd_ctl_elem_value *ucontrol)
  781. {
  782. struct soc_mixer_control *mc =
  783. (struct soc_mixer_control *)kcontrol->private_value;
  784. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  785. unsigned int reg = mc->reg;
  786. unsigned int shift = mc->shift;
  787. unsigned int rshift = mc->rshift;
  788. int max = mc->max;
  789. int mask = (1 << fls(max)) - 1;
  790. ucontrol->value.integer.value[0] =
  791. (snd_soc_read(codec, reg) >> shift) & mask;
  792. if (ucontrol->value.integer.value[0])
  793. ucontrol->value.integer.value[0] =
  794. max + 1 - ucontrol->value.integer.value[0];
  795. if (shift != rshift) {
  796. ucontrol->value.integer.value[1] =
  797. (snd_soc_read(codec, reg) >> rshift) & mask;
  798. if (ucontrol->value.integer.value[1])
  799. ucontrol->value.integer.value[1] =
  800. max + 1 - ucontrol->value.integer.value[1];
  801. }
  802. return 0;
  803. }
  804. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  805. struct snd_ctl_elem_value *ucontrol)
  806. {
  807. struct soc_mixer_control *mc =
  808. (struct soc_mixer_control *)kcontrol->private_value;
  809. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  810. unsigned int reg = mc->reg;
  811. unsigned int shift = mc->shift;
  812. unsigned int rshift = mc->rshift;
  813. int max = mc->max;
  814. int mask = (1 << fls(max)) - 1;
  815. unsigned short val, val2, val_mask;
  816. val = (ucontrol->value.integer.value[0] & mask);
  817. val_mask = mask << shift;
  818. if (val)
  819. val = max + 1 - val;
  820. val = val << shift;
  821. if (shift != rshift) {
  822. val2 = (ucontrol->value.integer.value[1] & mask);
  823. val_mask |= mask << rshift;
  824. if (val2)
  825. val2 = max + 1 - val2;
  826. val |= val2 << rshift;
  827. }
  828. return snd_soc_update_bits(codec, reg, val_mask, val);
  829. }
  830. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  831. struct snd_ctl_elem_value *ucontrol)
  832. {
  833. struct soc_mixer_control *mc =
  834. (struct soc_mixer_control *)kcontrol->private_value;
  835. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  836. unsigned int reg = mc->reg;
  837. unsigned int reg2 = mc->rreg;
  838. unsigned int shift = mc->shift;
  839. int max = mc->max;
  840. int mask = (1<<fls(max))-1;
  841. ucontrol->value.integer.value[0] =
  842. (snd_soc_read(codec, reg) >> shift) & mask;
  843. ucontrol->value.integer.value[1] =
  844. (snd_soc_read(codec, reg2) >> shift) & mask;
  845. if (ucontrol->value.integer.value[0])
  846. ucontrol->value.integer.value[0] =
  847. max + 1 - ucontrol->value.integer.value[0];
  848. if (ucontrol->value.integer.value[1])
  849. ucontrol->value.integer.value[1] =
  850. max + 1 - ucontrol->value.integer.value[1];
  851. return 0;
  852. }
  853. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  854. struct snd_ctl_elem_value *ucontrol)
  855. {
  856. struct soc_mixer_control *mc =
  857. (struct soc_mixer_control *)kcontrol->private_value;
  858. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  859. unsigned int reg = mc->reg;
  860. unsigned int reg2 = mc->rreg;
  861. unsigned int shift = mc->shift;
  862. int max = mc->max;
  863. int mask = (1 << fls(max)) - 1;
  864. int err;
  865. unsigned short val, val2, val_mask;
  866. val_mask = mask << shift;
  867. val = (ucontrol->value.integer.value[0] & mask);
  868. val2 = (ucontrol->value.integer.value[1] & mask);
  869. if (val)
  870. val = max + 1 - val;
  871. if (val2)
  872. val2 = max + 1 - val2;
  873. val = val << shift;
  874. val2 = val2 << shift;
  875. err = snd_soc_update_bits(codec, reg, val_mask, val);
  876. if (err < 0)
  877. return err;
  878. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  879. return err;
  880. }
  881. /* Codec operation modes */
  882. static const char *twl4030_op_modes_texts[] = {
  883. "Option 2 (voice/audio)", "Option 1 (audio)"
  884. };
  885. static const struct soc_enum twl4030_op_modes_enum =
  886. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  887. ARRAY_SIZE(twl4030_op_modes_texts),
  888. twl4030_op_modes_texts);
  889. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  890. struct snd_ctl_elem_value *ucontrol)
  891. {
  892. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  893. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  894. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  895. unsigned short val;
  896. unsigned short mask, bitmask;
  897. if (twl4030->configured) {
  898. printk(KERN_ERR "twl4030 operation mode cannot be "
  899. "changed on-the-fly\n");
  900. return -EBUSY;
  901. }
  902. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  903. ;
  904. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  905. return -EINVAL;
  906. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  907. mask = (bitmask - 1) << e->shift_l;
  908. if (e->shift_l != e->shift_r) {
  909. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  910. return -EINVAL;
  911. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  912. mask |= (bitmask - 1) << e->shift_r;
  913. }
  914. return snd_soc_update_bits(codec, e->reg, mask, val);
  915. }
  916. /*
  917. * FGAIN volume control:
  918. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  919. */
  920. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  921. /*
  922. * CGAIN volume control:
  923. * 0 dB to 12 dB in 6 dB steps
  924. * value 2 and 3 means 12 dB
  925. */
  926. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  927. /*
  928. * Voice Downlink GAIN volume control:
  929. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  930. */
  931. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  932. /*
  933. * Analog playback gain
  934. * -24 dB to 12 dB in 2 dB steps
  935. */
  936. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  937. /*
  938. * Gain controls tied to outputs
  939. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  940. */
  941. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  942. /*
  943. * Gain control for earpiece amplifier
  944. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  945. */
  946. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  947. /*
  948. * Capture gain after the ADCs
  949. * from 0 dB to 31 dB in 1 dB steps
  950. */
  951. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  952. /*
  953. * Gain control for input amplifiers
  954. * 0 dB to 30 dB in 6 dB steps
  955. */
  956. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  957. /* AVADC clock priority */
  958. static const char *twl4030_avadc_clk_priority_texts[] = {
  959. "Voice high priority", "HiFi high priority"
  960. };
  961. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  962. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  963. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  964. twl4030_avadc_clk_priority_texts);
  965. static const char *twl4030_rampdelay_texts[] = {
  966. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  967. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  968. "3495/2581/1748 ms"
  969. };
  970. static const struct soc_enum twl4030_rampdelay_enum =
  971. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  972. ARRAY_SIZE(twl4030_rampdelay_texts),
  973. twl4030_rampdelay_texts);
  974. /* Vibra H-bridge direction mode */
  975. static const char *twl4030_vibradirmode_texts[] = {
  976. "Vibra H-bridge direction", "Audio data MSB",
  977. };
  978. static const struct soc_enum twl4030_vibradirmode_enum =
  979. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  980. ARRAY_SIZE(twl4030_vibradirmode_texts),
  981. twl4030_vibradirmode_texts);
  982. /* Vibra H-bridge direction */
  983. static const char *twl4030_vibradir_texts[] = {
  984. "Positive polarity", "Negative polarity",
  985. };
  986. static const struct soc_enum twl4030_vibradir_enum =
  987. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  988. ARRAY_SIZE(twl4030_vibradir_texts),
  989. twl4030_vibradir_texts);
  990. /* Digimic Left and right swapping */
  991. static const char *twl4030_digimicswap_texts[] = {
  992. "Not swapped", "Swapped",
  993. };
  994. static const struct soc_enum twl4030_digimicswap_enum =
  995. SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
  996. ARRAY_SIZE(twl4030_digimicswap_texts),
  997. twl4030_digimicswap_texts);
  998. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  999. /* Codec operation mode control */
  1000. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  1001. snd_soc_get_enum_double,
  1002. snd_soc_put_twl4030_opmode_enum_double),
  1003. /* Common playback gain controls */
  1004. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  1005. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  1006. 0, 0x3f, 0, digital_fine_tlv),
  1007. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  1008. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1009. 0, 0x3f, 0, digital_fine_tlv),
  1010. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  1011. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  1012. 6, 0x2, 0, digital_coarse_tlv),
  1013. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  1014. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1015. 6, 0x2, 0, digital_coarse_tlv),
  1016. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  1017. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1018. 3, 0x12, 1, analog_tlv),
  1019. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  1020. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1021. 3, 0x12, 1, analog_tlv),
  1022. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  1023. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1024. 1, 1, 0),
  1025. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  1026. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1027. 1, 1, 0),
  1028. /* Common voice downlink gain controls */
  1029. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  1030. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  1031. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  1032. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  1033. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  1034. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  1035. /* Separate output gain controls */
  1036. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  1037. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  1038. 4, 3, 0, output_tvl),
  1039. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  1040. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  1041. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  1042. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  1043. 4, 3, 0, output_tvl),
  1044. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  1045. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  1046. /* Common capture gain controls */
  1047. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  1048. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  1049. 0, 0x1f, 0, digital_capture_tlv),
  1050. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  1051. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  1052. 0, 0x1f, 0, digital_capture_tlv),
  1053. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  1054. 0, 3, 5, 0, input_gain_tlv),
  1055. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  1056. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  1057. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  1058. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  1059. SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
  1060. };
  1061. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  1062. /* Left channel inputs */
  1063. SND_SOC_DAPM_INPUT("MAINMIC"),
  1064. SND_SOC_DAPM_INPUT("HSMIC"),
  1065. SND_SOC_DAPM_INPUT("AUXL"),
  1066. SND_SOC_DAPM_INPUT("CARKITMIC"),
  1067. /* Right channel inputs */
  1068. SND_SOC_DAPM_INPUT("SUBMIC"),
  1069. SND_SOC_DAPM_INPUT("AUXR"),
  1070. /* Digital microphones (Stereo) */
  1071. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1072. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1073. /* Outputs */
  1074. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1075. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1076. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1077. SND_SOC_DAPM_OUTPUT("HSOL"),
  1078. SND_SOC_DAPM_OUTPUT("HSOR"),
  1079. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1080. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1081. SND_SOC_DAPM_OUTPUT("HFL"),
  1082. SND_SOC_DAPM_OUTPUT("HFR"),
  1083. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1084. /* AIF and APLL clocks for running DAIs (including loopback) */
  1085. SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
  1086. SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
  1087. SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
  1088. /* DACs */
  1089. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1090. SND_SOC_NOPM, 0, 0),
  1091. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1092. SND_SOC_NOPM, 0, 0),
  1093. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1094. SND_SOC_NOPM, 0, 0),
  1095. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1096. SND_SOC_NOPM, 0, 0),
  1097. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1098. SND_SOC_NOPM, 0, 0),
  1099. /* Analog bypasses */
  1100. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1101. &twl4030_dapm_abypassr1_control),
  1102. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1103. &twl4030_dapm_abypassl1_control),
  1104. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1105. &twl4030_dapm_abypassr2_control),
  1106. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1107. &twl4030_dapm_abypassl2_control),
  1108. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1109. &twl4030_dapm_abypassv_control),
  1110. /* Master analog loopback switch */
  1111. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1112. NULL, 0),
  1113. /* Digital bypasses */
  1114. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1115. &twl4030_dapm_dbypassl_control),
  1116. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1117. &twl4030_dapm_dbypassr_control),
  1118. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1119. &twl4030_dapm_dbypassv_control),
  1120. /* Digital mixers, power control for the physical DACs */
  1121. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1122. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1123. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1124. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1125. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1126. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1127. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1128. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1129. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1130. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1131. /* Analog mixers, power control for the physical PGAs */
  1132. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1133. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1134. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1135. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1136. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1137. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1138. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1139. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1140. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1141. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1142. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1143. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1144. SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
  1145. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1146. /* Output MIXER controls */
  1147. /* Earpiece */
  1148. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1149. &twl4030_dapm_earpiece_controls[0],
  1150. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1151. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1152. 0, 0, NULL, 0, earpiecepga_event,
  1153. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1154. /* PreDrivL/R */
  1155. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1156. &twl4030_dapm_predrivel_controls[0],
  1157. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1158. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1159. 0, 0, NULL, 0, predrivelpga_event,
  1160. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1161. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1162. &twl4030_dapm_predriver_controls[0],
  1163. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1164. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1165. 0, 0, NULL, 0, predriverpga_event,
  1166. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1167. /* HeadsetL/R */
  1168. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1169. &twl4030_dapm_hsol_controls[0],
  1170. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1171. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1172. 0, 0, NULL, 0, headsetlpga_event,
  1173. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1174. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1175. &twl4030_dapm_hsor_controls[0],
  1176. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1177. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1178. 0, 0, NULL, 0, headsetrpga_event,
  1179. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1180. /* CarkitL/R */
  1181. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1182. &twl4030_dapm_carkitl_controls[0],
  1183. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1184. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1185. 0, 0, NULL, 0, carkitlpga_event,
  1186. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1187. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1188. &twl4030_dapm_carkitr_controls[0],
  1189. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1190. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1191. 0, 0, NULL, 0, carkitrpga_event,
  1192. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1193. /* Output MUX controls */
  1194. /* HandsfreeL/R */
  1195. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1196. &twl4030_dapm_handsfreel_control),
  1197. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1198. &twl4030_dapm_handsfreelmute_control),
  1199. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1200. 0, 0, NULL, 0, handsfreelpga_event,
  1201. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1202. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1203. &twl4030_dapm_handsfreer_control),
  1204. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1205. &twl4030_dapm_handsfreermute_control),
  1206. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1207. 0, 0, NULL, 0, handsfreerpga_event,
  1208. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1209. /* Vibra */
  1210. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1211. &twl4030_dapm_vibra_control, vibramux_event,
  1212. SND_SOC_DAPM_PRE_PMU),
  1213. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1214. &twl4030_dapm_vibrapath_control),
  1215. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1216. capture */
  1217. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1218. SND_SOC_NOPM, 0, 0),
  1219. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1220. SND_SOC_NOPM, 0, 0),
  1221. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1222. SND_SOC_NOPM, 0, 0),
  1223. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1224. SND_SOC_NOPM, 0, 0),
  1225. /* Analog/Digital mic path selection.
  1226. TX1 Left/Right: either analog Left/Right or Digimic0
  1227. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1228. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1229. &twl4030_dapm_micpathtx1_control, micpath_event,
  1230. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1231. SND_SOC_DAPM_POST_REG),
  1232. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1233. &twl4030_dapm_micpathtx2_control, micpath_event,
  1234. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1235. SND_SOC_DAPM_POST_REG),
  1236. /* Analog input mixers for the capture amplifiers */
  1237. SND_SOC_DAPM_MIXER("Analog Left",
  1238. TWL4030_REG_ANAMICL, 4, 0,
  1239. &twl4030_dapm_analoglmic_controls[0],
  1240. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1241. SND_SOC_DAPM_MIXER("Analog Right",
  1242. TWL4030_REG_ANAMICR, 4, 0,
  1243. &twl4030_dapm_analogrmic_controls[0],
  1244. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1245. SND_SOC_DAPM_PGA("ADC Physical Left",
  1246. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1247. SND_SOC_DAPM_PGA("ADC Physical Right",
  1248. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1249. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1250. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1251. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1252. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1253. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1254. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1255. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1256. };
  1257. static const struct snd_soc_dapm_route intercon[] = {
  1258. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1259. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1260. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1261. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1262. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1263. /* Supply for the digital part (APLL) */
  1264. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1265. {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
  1266. {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
  1267. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1268. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1269. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1270. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1271. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1272. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1273. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1274. /* Internal playback routings */
  1275. /* Earpiece */
  1276. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1277. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1278. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1279. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1280. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1281. /* PreDrivL */
  1282. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1283. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1284. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1285. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1286. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1287. /* PreDrivR */
  1288. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1289. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1290. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1291. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1292. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1293. /* HeadsetL */
  1294. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1295. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1296. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1297. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1298. /* HeadsetR */
  1299. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1300. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1301. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1302. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1303. /* CarkitL */
  1304. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1305. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1306. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1307. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1308. /* CarkitR */
  1309. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1310. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1311. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1312. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1313. /* HandsfreeL */
  1314. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1315. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1316. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1317. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1318. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1319. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1320. /* HandsfreeR */
  1321. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1322. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1323. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1324. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1325. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1326. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1327. /* Vibra */
  1328. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1329. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1330. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1331. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1332. /* outputs */
  1333. /* Must be always connected (for AIF and APLL) */
  1334. {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
  1335. {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
  1336. {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
  1337. {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
  1338. /* Must be always connected (for APLL) */
  1339. {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
  1340. /* Physical outputs */
  1341. {"EARPIECE", NULL, "Earpiece PGA"},
  1342. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1343. {"PREDRIVER", NULL, "PredriveR PGA"},
  1344. {"HSOL", NULL, "HeadsetL PGA"},
  1345. {"HSOR", NULL, "HeadsetR PGA"},
  1346. {"CARKITL", NULL, "CarkitL PGA"},
  1347. {"CARKITR", NULL, "CarkitR PGA"},
  1348. {"HFL", NULL, "HandsfreeL PGA"},
  1349. {"HFR", NULL, "HandsfreeR PGA"},
  1350. {"Vibra Route", "Audio", "Vibra Mux"},
  1351. {"VIBRA", NULL, "Vibra Route"},
  1352. /* Capture path */
  1353. /* Must be always connected (for AIF and APLL) */
  1354. {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
  1355. {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
  1356. {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
  1357. {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
  1358. /* Physical inputs */
  1359. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1360. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1361. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1362. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1363. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1364. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1365. {"ADC Physical Left", NULL, "Analog Left"},
  1366. {"ADC Physical Right", NULL, "Analog Right"},
  1367. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1368. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1369. /* TX1 Left capture path */
  1370. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1371. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1372. /* TX1 Right capture path */
  1373. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1374. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1375. /* TX2 Left capture path */
  1376. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1377. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1378. /* TX2 Right capture path */
  1379. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1380. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1381. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1382. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1383. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1384. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1385. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1386. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1387. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1388. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1389. /* Analog bypass routes */
  1390. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1391. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1392. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1393. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1394. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1395. /* Supply for the Analog loopbacks */
  1396. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1397. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1398. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1399. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1400. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1401. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1402. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1403. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1404. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1405. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1406. /* Digital bypass routes */
  1407. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1408. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1409. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1410. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1411. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1412. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1413. };
  1414. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1415. {
  1416. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1417. ARRAY_SIZE(twl4030_dapm_widgets));
  1418. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1419. return 0;
  1420. }
  1421. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1422. enum snd_soc_bias_level level)
  1423. {
  1424. switch (level) {
  1425. case SND_SOC_BIAS_ON:
  1426. break;
  1427. case SND_SOC_BIAS_PREPARE:
  1428. break;
  1429. case SND_SOC_BIAS_STANDBY:
  1430. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1431. twl4030_codec_enable(codec, 1);
  1432. break;
  1433. case SND_SOC_BIAS_OFF:
  1434. twl4030_codec_enable(codec, 0);
  1435. break;
  1436. }
  1437. codec->bias_level = level;
  1438. return 0;
  1439. }
  1440. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1441. struct snd_pcm_substream *mst_substream)
  1442. {
  1443. struct snd_pcm_substream *slv_substream;
  1444. /* Pick the stream, which need to be constrained */
  1445. if (mst_substream == twl4030->master_substream)
  1446. slv_substream = twl4030->slave_substream;
  1447. else if (mst_substream == twl4030->slave_substream)
  1448. slv_substream = twl4030->master_substream;
  1449. else /* This should not happen.. */
  1450. return;
  1451. /* Set the constraints according to the already configured stream */
  1452. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1453. SNDRV_PCM_HW_PARAM_RATE,
  1454. twl4030->rate,
  1455. twl4030->rate);
  1456. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1457. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1458. twl4030->sample_bits,
  1459. twl4030->sample_bits);
  1460. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1461. SNDRV_PCM_HW_PARAM_CHANNELS,
  1462. twl4030->channels,
  1463. twl4030->channels);
  1464. }
  1465. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1466. * capture has to be enabled/disabled. */
  1467. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1468. int enable)
  1469. {
  1470. u8 reg, mask;
  1471. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1472. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1473. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1474. else
  1475. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1476. if (enable)
  1477. reg |= mask;
  1478. else
  1479. reg &= ~mask;
  1480. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1481. }
  1482. static int twl4030_startup(struct snd_pcm_substream *substream,
  1483. struct snd_soc_dai *dai)
  1484. {
  1485. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1486. struct snd_soc_device *socdev = rtd->socdev;
  1487. struct snd_soc_codec *codec = socdev->card->codec;
  1488. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1489. if (twl4030->master_substream) {
  1490. twl4030->slave_substream = substream;
  1491. /* The DAI has one configuration for playback and capture, so
  1492. * if the DAI has been already configured then constrain this
  1493. * substream to match it. */
  1494. if (twl4030->configured)
  1495. twl4030_constraints(twl4030, twl4030->master_substream);
  1496. } else {
  1497. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1498. TWL4030_OPTION_1)) {
  1499. /* In option2 4 channel is not supported, set the
  1500. * constraint for the first stream for channels, the
  1501. * second stream will 'inherit' this cosntraint */
  1502. snd_pcm_hw_constraint_minmax(substream->runtime,
  1503. SNDRV_PCM_HW_PARAM_CHANNELS,
  1504. 2, 2);
  1505. }
  1506. twl4030->master_substream = substream;
  1507. }
  1508. return 0;
  1509. }
  1510. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1511. struct snd_soc_dai *dai)
  1512. {
  1513. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1514. struct snd_soc_device *socdev = rtd->socdev;
  1515. struct snd_soc_codec *codec = socdev->card->codec;
  1516. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1517. if (twl4030->master_substream == substream)
  1518. twl4030->master_substream = twl4030->slave_substream;
  1519. twl4030->slave_substream = NULL;
  1520. /* If all streams are closed, or the remaining stream has not yet
  1521. * been configured than set the DAI as not configured. */
  1522. if (!twl4030->master_substream)
  1523. twl4030->configured = 0;
  1524. else if (!twl4030->master_substream->runtime->channels)
  1525. twl4030->configured = 0;
  1526. /* If the closing substream had 4 channel, do the necessary cleanup */
  1527. if (substream->runtime->channels == 4)
  1528. twl4030_tdm_enable(codec, substream->stream, 0);
  1529. }
  1530. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1531. struct snd_pcm_hw_params *params,
  1532. struct snd_soc_dai *dai)
  1533. {
  1534. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1535. struct snd_soc_device *socdev = rtd->socdev;
  1536. struct snd_soc_codec *codec = socdev->card->codec;
  1537. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1538. u8 mode, old_mode, format, old_format;
  1539. /* If the substream has 4 channel, do the necessary setup */
  1540. if (params_channels(params) == 4) {
  1541. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1542. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1543. /* Safety check: are we in the correct operating mode and
  1544. * the interface is in TDM mode? */
  1545. if ((mode & TWL4030_OPTION_1) &&
  1546. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1547. twl4030_tdm_enable(codec, substream->stream, 1);
  1548. else
  1549. return -EINVAL;
  1550. }
  1551. if (twl4030->configured)
  1552. /* Ignoring hw_params for already configured DAI */
  1553. return 0;
  1554. /* bit rate */
  1555. old_mode = twl4030_read_reg_cache(codec,
  1556. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1557. mode = old_mode & ~TWL4030_APLL_RATE;
  1558. switch (params_rate(params)) {
  1559. case 8000:
  1560. mode |= TWL4030_APLL_RATE_8000;
  1561. break;
  1562. case 11025:
  1563. mode |= TWL4030_APLL_RATE_11025;
  1564. break;
  1565. case 12000:
  1566. mode |= TWL4030_APLL_RATE_12000;
  1567. break;
  1568. case 16000:
  1569. mode |= TWL4030_APLL_RATE_16000;
  1570. break;
  1571. case 22050:
  1572. mode |= TWL4030_APLL_RATE_22050;
  1573. break;
  1574. case 24000:
  1575. mode |= TWL4030_APLL_RATE_24000;
  1576. break;
  1577. case 32000:
  1578. mode |= TWL4030_APLL_RATE_32000;
  1579. break;
  1580. case 44100:
  1581. mode |= TWL4030_APLL_RATE_44100;
  1582. break;
  1583. case 48000:
  1584. mode |= TWL4030_APLL_RATE_48000;
  1585. break;
  1586. case 96000:
  1587. mode |= TWL4030_APLL_RATE_96000;
  1588. break;
  1589. default:
  1590. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1591. params_rate(params));
  1592. return -EINVAL;
  1593. }
  1594. /* sample size */
  1595. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1596. format = old_format;
  1597. format &= ~TWL4030_DATA_WIDTH;
  1598. switch (params_format(params)) {
  1599. case SNDRV_PCM_FORMAT_S16_LE:
  1600. format |= TWL4030_DATA_WIDTH_16S_16W;
  1601. break;
  1602. case SNDRV_PCM_FORMAT_S24_LE:
  1603. format |= TWL4030_DATA_WIDTH_32S_24W;
  1604. break;
  1605. default:
  1606. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1607. params_format(params));
  1608. return -EINVAL;
  1609. }
  1610. if (format != old_format || mode != old_mode) {
  1611. if (twl4030->codec_powered) {
  1612. /*
  1613. * If the codec is powered, than we need to toggle the
  1614. * codec power.
  1615. */
  1616. twl4030_codec_enable(codec, 0);
  1617. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1618. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1619. twl4030_codec_enable(codec, 1);
  1620. } else {
  1621. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1622. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1623. }
  1624. }
  1625. /* Store the important parameters for the DAI configuration and set
  1626. * the DAI as configured */
  1627. twl4030->configured = 1;
  1628. twl4030->rate = params_rate(params);
  1629. twl4030->sample_bits = hw_param_interval(params,
  1630. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1631. twl4030->channels = params_channels(params);
  1632. /* If both playback and capture streams are open, and one of them
  1633. * is setting the hw parameters right now (since we are here), set
  1634. * constraints to the other stream to match the current one. */
  1635. if (twl4030->slave_substream)
  1636. twl4030_constraints(twl4030, substream);
  1637. return 0;
  1638. }
  1639. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1640. int clk_id, unsigned int freq, int dir)
  1641. {
  1642. struct snd_soc_codec *codec = codec_dai->codec;
  1643. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1644. switch (freq) {
  1645. case 19200000:
  1646. case 26000000:
  1647. case 38400000:
  1648. break;
  1649. default:
  1650. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1651. return -EINVAL;
  1652. }
  1653. if ((freq / 1000) != twl4030->sysclk) {
  1654. dev_err(codec->dev,
  1655. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1656. freq, twl4030->sysclk * 1000);
  1657. return -EINVAL;
  1658. }
  1659. return 0;
  1660. }
  1661. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1662. unsigned int fmt)
  1663. {
  1664. struct snd_soc_codec *codec = codec_dai->codec;
  1665. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1666. u8 old_format, format;
  1667. /* get format */
  1668. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1669. format = old_format;
  1670. /* set master/slave audio interface */
  1671. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1672. case SND_SOC_DAIFMT_CBM_CFM:
  1673. format &= ~(TWL4030_AIF_SLAVE_EN);
  1674. format &= ~(TWL4030_CLK256FS_EN);
  1675. break;
  1676. case SND_SOC_DAIFMT_CBS_CFS:
  1677. format |= TWL4030_AIF_SLAVE_EN;
  1678. format |= TWL4030_CLK256FS_EN;
  1679. break;
  1680. default:
  1681. return -EINVAL;
  1682. }
  1683. /* interface format */
  1684. format &= ~TWL4030_AIF_FORMAT;
  1685. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1686. case SND_SOC_DAIFMT_I2S:
  1687. format |= TWL4030_AIF_FORMAT_CODEC;
  1688. break;
  1689. case SND_SOC_DAIFMT_DSP_A:
  1690. format |= TWL4030_AIF_FORMAT_TDM;
  1691. break;
  1692. default:
  1693. return -EINVAL;
  1694. }
  1695. if (format != old_format) {
  1696. if (twl4030->codec_powered) {
  1697. /*
  1698. * If the codec is powered, than we need to toggle the
  1699. * codec power.
  1700. */
  1701. twl4030_codec_enable(codec, 0);
  1702. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1703. twl4030_codec_enable(codec, 1);
  1704. } else {
  1705. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1706. }
  1707. }
  1708. return 0;
  1709. }
  1710. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1711. {
  1712. struct snd_soc_codec *codec = dai->codec;
  1713. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1714. if (tristate)
  1715. reg |= TWL4030_AIF_TRI_EN;
  1716. else
  1717. reg &= ~TWL4030_AIF_TRI_EN;
  1718. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1719. }
  1720. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1721. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1722. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1723. int enable)
  1724. {
  1725. u8 reg, mask;
  1726. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1727. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1728. mask = TWL4030_ARXL1_VRX_EN;
  1729. else
  1730. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1731. if (enable)
  1732. reg |= mask;
  1733. else
  1734. reg &= ~mask;
  1735. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1736. }
  1737. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1738. struct snd_soc_dai *dai)
  1739. {
  1740. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1741. struct snd_soc_device *socdev = rtd->socdev;
  1742. struct snd_soc_codec *codec = socdev->card->codec;
  1743. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1744. u8 mode;
  1745. /* If the system master clock is not 26MHz, the voice PCM interface is
  1746. * not avilable.
  1747. */
  1748. if (twl4030->sysclk != 26000) {
  1749. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1750. "the Voice interface needs 26MHz APLL mclk\n",
  1751. twl4030->sysclk * 1000);
  1752. return -EINVAL;
  1753. }
  1754. /* If the codec mode is not option2, the voice PCM interface is not
  1755. * avilable.
  1756. */
  1757. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1758. & TWL4030_OPT_MODE;
  1759. if (mode != TWL4030_OPTION_2) {
  1760. printk(KERN_ERR "TWL4030 voice startup: "
  1761. "the codec mode is not option2\n");
  1762. return -EINVAL;
  1763. }
  1764. return 0;
  1765. }
  1766. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1767. struct snd_soc_dai *dai)
  1768. {
  1769. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1770. struct snd_soc_device *socdev = rtd->socdev;
  1771. struct snd_soc_codec *codec = socdev->card->codec;
  1772. /* Enable voice digital filters */
  1773. twl4030_voice_enable(codec, substream->stream, 0);
  1774. }
  1775. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1776. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1777. {
  1778. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1779. struct snd_soc_device *socdev = rtd->socdev;
  1780. struct snd_soc_codec *codec = socdev->card->codec;
  1781. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1782. u8 old_mode, mode;
  1783. /* Enable voice digital filters */
  1784. twl4030_voice_enable(codec, substream->stream, 1);
  1785. /* bit rate */
  1786. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1787. & ~(TWL4030_CODECPDZ);
  1788. mode = old_mode;
  1789. switch (params_rate(params)) {
  1790. case 8000:
  1791. mode &= ~(TWL4030_SEL_16K);
  1792. break;
  1793. case 16000:
  1794. mode |= TWL4030_SEL_16K;
  1795. break;
  1796. default:
  1797. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1798. params_rate(params));
  1799. return -EINVAL;
  1800. }
  1801. if (mode != old_mode) {
  1802. if (twl4030->codec_powered) {
  1803. /*
  1804. * If the codec is powered, than we need to toggle the
  1805. * codec power.
  1806. */
  1807. twl4030_codec_enable(codec, 0);
  1808. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1809. twl4030_codec_enable(codec, 1);
  1810. } else {
  1811. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1812. }
  1813. }
  1814. return 0;
  1815. }
  1816. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1817. int clk_id, unsigned int freq, int dir)
  1818. {
  1819. struct snd_soc_codec *codec = codec_dai->codec;
  1820. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1821. if (freq != 26000000) {
  1822. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1823. "interface needs 26MHz APLL mclk\n", freq);
  1824. return -EINVAL;
  1825. }
  1826. if ((freq / 1000) != twl4030->sysclk) {
  1827. dev_err(codec->dev,
  1828. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1829. freq, twl4030->sysclk * 1000);
  1830. return -EINVAL;
  1831. }
  1832. return 0;
  1833. }
  1834. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1835. unsigned int fmt)
  1836. {
  1837. struct snd_soc_codec *codec = codec_dai->codec;
  1838. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1839. u8 old_format, format;
  1840. /* get format */
  1841. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1842. format = old_format;
  1843. /* set master/slave audio interface */
  1844. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1845. case SND_SOC_DAIFMT_CBM_CFM:
  1846. format &= ~(TWL4030_VIF_SLAVE_EN);
  1847. break;
  1848. case SND_SOC_DAIFMT_CBS_CFS:
  1849. format |= TWL4030_VIF_SLAVE_EN;
  1850. break;
  1851. default:
  1852. return -EINVAL;
  1853. }
  1854. /* clock inversion */
  1855. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1856. case SND_SOC_DAIFMT_IB_NF:
  1857. format &= ~(TWL4030_VIF_FORMAT);
  1858. break;
  1859. case SND_SOC_DAIFMT_NB_IF:
  1860. format |= TWL4030_VIF_FORMAT;
  1861. break;
  1862. default:
  1863. return -EINVAL;
  1864. }
  1865. if (format != old_format) {
  1866. if (twl4030->codec_powered) {
  1867. /*
  1868. * If the codec is powered, than we need to toggle the
  1869. * codec power.
  1870. */
  1871. twl4030_codec_enable(codec, 0);
  1872. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1873. twl4030_codec_enable(codec, 1);
  1874. } else {
  1875. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1876. }
  1877. }
  1878. return 0;
  1879. }
  1880. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1881. {
  1882. struct snd_soc_codec *codec = dai->codec;
  1883. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1884. if (tristate)
  1885. reg |= TWL4030_VIF_TRI_EN;
  1886. else
  1887. reg &= ~TWL4030_VIF_TRI_EN;
  1888. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1889. }
  1890. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1891. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1892. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1893. .startup = twl4030_startup,
  1894. .shutdown = twl4030_shutdown,
  1895. .hw_params = twl4030_hw_params,
  1896. .set_sysclk = twl4030_set_dai_sysclk,
  1897. .set_fmt = twl4030_set_dai_fmt,
  1898. .set_tristate = twl4030_set_tristate,
  1899. };
  1900. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1901. .startup = twl4030_voice_startup,
  1902. .shutdown = twl4030_voice_shutdown,
  1903. .hw_params = twl4030_voice_hw_params,
  1904. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1905. .set_fmt = twl4030_voice_set_dai_fmt,
  1906. .set_tristate = twl4030_voice_set_tristate,
  1907. };
  1908. struct snd_soc_dai twl4030_dai[] = {
  1909. {
  1910. .name = "twl4030",
  1911. .playback = {
  1912. .stream_name = "HiFi Playback",
  1913. .channels_min = 2,
  1914. .channels_max = 4,
  1915. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1916. .formats = TWL4030_FORMATS,},
  1917. .capture = {
  1918. .stream_name = "Capture",
  1919. .channels_min = 2,
  1920. .channels_max = 4,
  1921. .rates = TWL4030_RATES,
  1922. .formats = TWL4030_FORMATS,},
  1923. .ops = &twl4030_dai_ops,
  1924. },
  1925. {
  1926. .name = "twl4030 Voice",
  1927. .playback = {
  1928. .stream_name = "Voice Playback",
  1929. .channels_min = 1,
  1930. .channels_max = 1,
  1931. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1932. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1933. .capture = {
  1934. .stream_name = "Capture",
  1935. .channels_min = 1,
  1936. .channels_max = 2,
  1937. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1938. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1939. .ops = &twl4030_dai_voice_ops,
  1940. },
  1941. };
  1942. EXPORT_SYMBOL_GPL(twl4030_dai);
  1943. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1944. {
  1945. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1946. struct snd_soc_codec *codec = socdev->card->codec;
  1947. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1948. return 0;
  1949. }
  1950. static int twl4030_soc_resume(struct platform_device *pdev)
  1951. {
  1952. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1953. struct snd_soc_codec *codec = socdev->card->codec;
  1954. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1955. return 0;
  1956. }
  1957. static struct snd_soc_codec *twl4030_codec;
  1958. static int twl4030_soc_probe(struct platform_device *pdev)
  1959. {
  1960. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1961. struct snd_soc_codec *codec;
  1962. int ret;
  1963. BUG_ON(!twl4030_codec);
  1964. codec = twl4030_codec;
  1965. socdev->card->codec = codec;
  1966. twl4030_init_chip(pdev);
  1967. /* register pcms */
  1968. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1969. if (ret < 0) {
  1970. dev_err(&pdev->dev, "failed to create pcms\n");
  1971. return ret;
  1972. }
  1973. snd_soc_add_controls(codec, twl4030_snd_controls,
  1974. ARRAY_SIZE(twl4030_snd_controls));
  1975. twl4030_add_widgets(codec);
  1976. return 0;
  1977. }
  1978. static int twl4030_soc_remove(struct platform_device *pdev)
  1979. {
  1980. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1981. struct snd_soc_codec *codec = socdev->card->codec;
  1982. /* Reset registers to their chip default before leaving */
  1983. twl4030_reset_registers(codec);
  1984. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1985. snd_soc_free_pcms(socdev);
  1986. snd_soc_dapm_free(socdev);
  1987. return 0;
  1988. }
  1989. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1990. {
  1991. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1992. struct snd_soc_codec *codec;
  1993. struct twl4030_priv *twl4030;
  1994. int ret;
  1995. if (!pdata) {
  1996. dev_err(&pdev->dev, "platform_data is missing\n");
  1997. return -EINVAL;
  1998. }
  1999. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  2000. if (twl4030 == NULL) {
  2001. dev_err(&pdev->dev, "Can not allocate memroy\n");
  2002. return -ENOMEM;
  2003. }
  2004. codec = &twl4030->codec;
  2005. snd_soc_codec_set_drvdata(codec, twl4030);
  2006. codec->dev = &pdev->dev;
  2007. twl4030_dai[0].dev = &pdev->dev;
  2008. twl4030_dai[1].dev = &pdev->dev;
  2009. mutex_init(&codec->mutex);
  2010. INIT_LIST_HEAD(&codec->dapm_widgets);
  2011. INIT_LIST_HEAD(&codec->dapm_paths);
  2012. codec->name = "twl4030";
  2013. codec->owner = THIS_MODULE;
  2014. codec->read = twl4030_read_reg_cache;
  2015. codec->write = twl4030_write;
  2016. codec->set_bias_level = twl4030_set_bias_level;
  2017. codec->idle_bias_off = 1;
  2018. codec->dai = twl4030_dai;
  2019. codec->num_dai = ARRAY_SIZE(twl4030_dai);
  2020. codec->reg_cache_size = sizeof(twl4030_reg);
  2021. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  2022. GFP_KERNEL);
  2023. if (codec->reg_cache == NULL) {
  2024. ret = -ENOMEM;
  2025. goto error_cache;
  2026. }
  2027. platform_set_drvdata(pdev, twl4030);
  2028. twl4030_codec = codec;
  2029. /* Set the defaults, and power up the codec */
  2030. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  2031. codec->bias_level = SND_SOC_BIAS_OFF;
  2032. ret = snd_soc_register_codec(codec);
  2033. if (ret != 0) {
  2034. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  2035. goto error_codec;
  2036. }
  2037. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2038. if (ret != 0) {
  2039. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  2040. snd_soc_unregister_codec(codec);
  2041. goto error_codec;
  2042. }
  2043. return 0;
  2044. error_codec:
  2045. twl4030_codec_enable(codec, 0);
  2046. kfree(codec->reg_cache);
  2047. error_cache:
  2048. kfree(twl4030);
  2049. return ret;
  2050. }
  2051. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  2052. {
  2053. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  2054. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2055. snd_soc_unregister_codec(&twl4030->codec);
  2056. kfree(twl4030->codec.reg_cache);
  2057. kfree(twl4030);
  2058. twl4030_codec = NULL;
  2059. return 0;
  2060. }
  2061. MODULE_ALIAS("platform:twl4030_codec_audio");
  2062. static struct platform_driver twl4030_codec_driver = {
  2063. .probe = twl4030_codec_probe,
  2064. .remove = __devexit_p(twl4030_codec_remove),
  2065. .driver = {
  2066. .name = "twl4030_codec_audio",
  2067. .owner = THIS_MODULE,
  2068. },
  2069. };
  2070. static int __init twl4030_modinit(void)
  2071. {
  2072. return platform_driver_register(&twl4030_codec_driver);
  2073. }
  2074. module_init(twl4030_modinit);
  2075. static void __exit twl4030_exit(void)
  2076. {
  2077. platform_driver_unregister(&twl4030_codec_driver);
  2078. }
  2079. module_exit(twl4030_exit);
  2080. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  2081. .probe = twl4030_soc_probe,
  2082. .remove = twl4030_soc_remove,
  2083. .suspend = twl4030_soc_suspend,
  2084. .resume = twl4030_soc_resume,
  2085. };
  2086. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  2087. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  2088. MODULE_AUTHOR("Steve Sakoman");
  2089. MODULE_LICENSE("GPL");