ql4_mbx.c 50 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine issue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. uint32_t dev_state;
  33. /* Make sure that pointers are valid */
  34. if (!mbx_cmd || !mbx_sts) {
  35. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  36. "pointer\n", ha->host_no, __func__));
  37. return status;
  38. }
  39. if (is_qla8022(ha)) {
  40. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  41. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  42. "prematurely completing mbx cmd as firmware "
  43. "recovery detected\n", ha->host_no, __func__));
  44. return status;
  45. }
  46. /* Do not send any mbx cmd if h/w is in failed state*/
  47. qla4_8xxx_idc_lock(ha);
  48. dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  49. qla4_8xxx_idc_unlock(ha);
  50. if (dev_state == QLA82XX_DEV_FAILED) {
  51. ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: H/W is in "
  52. "failed state, do not send any mailbox commands\n",
  53. ha->host_no, __func__);
  54. return status;
  55. }
  56. }
  57. if ((is_aer_supported(ha)) &&
  58. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  59. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  60. "timeout MBX Exiting.\n", ha->host_no, __func__));
  61. return status;
  62. }
  63. /* Mailbox code active */
  64. wait_count = MBOX_TOV * 100;
  65. while (wait_count--) {
  66. mutex_lock(&ha->mbox_sem);
  67. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  68. set_bit(AF_MBOX_COMMAND, &ha->flags);
  69. mutex_unlock(&ha->mbox_sem);
  70. break;
  71. }
  72. mutex_unlock(&ha->mbox_sem);
  73. if (!wait_count) {
  74. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  75. ha->host_no, __func__));
  76. return status;
  77. }
  78. msleep(10);
  79. }
  80. spin_lock_irqsave(&ha->hardware_lock, flags);
  81. ha->mbox_status_count = outCount;
  82. for (i = 0; i < outCount; i++)
  83. ha->mbox_status[i] = 0;
  84. if (is_qla8022(ha)) {
  85. /* Load all mailbox registers, except mailbox 0. */
  86. DEBUG5(
  87. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  88. for (i = 0; i < inCount; i++)
  89. printk("mb%d=%04x ", i, mbx_cmd[i]);
  90. printk("\n"));
  91. for (i = 1; i < inCount; i++)
  92. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  93. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  94. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  95. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  96. } else {
  97. /* Load all mailbox registers, except mailbox 0. */
  98. for (i = 1; i < inCount; i++)
  99. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  100. /* Wakeup firmware */
  101. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  102. readl(&ha->reg->mailbox[0]);
  103. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  104. readl(&ha->reg->ctrl_status);
  105. }
  106. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  107. /* Wait for completion */
  108. /*
  109. * If we don't want status, don't wait for the mailbox command to
  110. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  111. * you must poll the inbound Interrupt Mask for completion.
  112. */
  113. if (outCount == 0) {
  114. status = QLA_SUCCESS;
  115. goto mbox_exit;
  116. }
  117. /*
  118. * Wait for completion: Poll or completion queue
  119. */
  120. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  121. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  122. test_bit(AF_ONLINE, &ha->flags) &&
  123. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  124. /* Do not poll for completion. Use completion queue */
  125. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  127. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  128. } else {
  129. /* Poll for command to complete */
  130. wait_count = jiffies + MBOX_TOV * HZ;
  131. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  132. if (time_after_eq(jiffies, wait_count))
  133. break;
  134. /*
  135. * Service the interrupt.
  136. * The ISR will save the mailbox status registers
  137. * to a temporary storage location in the adapter
  138. * structure.
  139. */
  140. spin_lock_irqsave(&ha->hardware_lock, flags);
  141. if (is_qla8022(ha)) {
  142. intr_status =
  143. readl(&ha->qla4_8xxx_reg->host_int);
  144. if (intr_status & ISRX_82XX_RISC_INT) {
  145. ha->mbox_status_count = outCount;
  146. intr_status =
  147. readl(&ha->qla4_8xxx_reg->host_status);
  148. ha->isp_ops->interrupt_service_routine(
  149. ha, intr_status);
  150. if (test_bit(AF_INTERRUPTS_ON,
  151. &ha->flags) &&
  152. test_bit(AF_INTx_ENABLED,
  153. &ha->flags))
  154. qla4_8xxx_wr_32(ha,
  155. ha->nx_legacy_intr.tgt_mask_reg,
  156. 0xfbff);
  157. }
  158. } else {
  159. intr_status = readl(&ha->reg->ctrl_status);
  160. if (intr_status & INTR_PENDING) {
  161. /*
  162. * Service the interrupt.
  163. * The ISR will save the mailbox status
  164. * registers to a temporary storage
  165. * location in the adapter structure.
  166. */
  167. ha->mbox_status_count = outCount;
  168. ha->isp_ops->interrupt_service_routine(
  169. ha, intr_status);
  170. }
  171. }
  172. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  173. msleep(10);
  174. }
  175. }
  176. /* Check for mailbox timeout. */
  177. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  178. if (is_qla8022(ha) &&
  179. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  180. DEBUG2(ql4_printk(KERN_INFO, ha,
  181. "scsi%ld: %s: prematurely completing mbx cmd as "
  182. "firmware recovery detected\n",
  183. ha->host_no, __func__));
  184. goto mbox_exit;
  185. }
  186. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  187. " Scheduling Adapter Reset\n", ha->host_no,
  188. mbx_cmd[0]));
  189. ha->mailbox_timeout_count++;
  190. mbx_sts[0] = (-1);
  191. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  192. goto mbox_exit;
  193. }
  194. /*
  195. * Copy the mailbox out registers to the caller's mailbox in/out
  196. * structure.
  197. */
  198. spin_lock_irqsave(&ha->hardware_lock, flags);
  199. for (i = 0; i < outCount; i++)
  200. mbx_sts[i] = ha->mbox_status[i];
  201. /* Set return status and error flags (if applicable). */
  202. switch (ha->mbox_status[0]) {
  203. case MBOX_STS_COMMAND_COMPLETE:
  204. status = QLA_SUCCESS;
  205. break;
  206. case MBOX_STS_INTERMEDIATE_COMPLETION:
  207. status = QLA_SUCCESS;
  208. break;
  209. case MBOX_STS_BUSY:
  210. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  211. ha->host_no, __func__, mbx_cmd[0]));
  212. ha->mailbox_timeout_count++;
  213. break;
  214. default:
  215. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  216. "sts = %08X ****\n", ha->host_no, __func__,
  217. mbx_cmd[0], mbx_sts[0]));
  218. break;
  219. }
  220. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  221. mbox_exit:
  222. mutex_lock(&ha->mbox_sem);
  223. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  224. mutex_unlock(&ha->mbox_sem);
  225. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  226. return status;
  227. }
  228. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  229. {
  230. set_bit(AF_FW_RECOVERY, &ha->flags);
  231. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  232. ha->host_no, __func__);
  233. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  234. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  235. complete(&ha->mbx_intr_comp);
  236. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  237. "recovery, doing premature completion of "
  238. "mbx cmd\n", ha->host_no, __func__);
  239. } else {
  240. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  241. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  242. "recovery, doing premature completion of "
  243. "polling mbx cmd\n", ha->host_no, __func__);
  244. }
  245. }
  246. }
  247. static uint8_t
  248. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  249. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  250. {
  251. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  252. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  253. if (is_qla8022(ha))
  254. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  255. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  256. mbox_cmd[1] = 0;
  257. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  258. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  259. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  260. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  261. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  262. QLA_SUCCESS) {
  263. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  264. "MBOX_CMD_INITIALIZE_FIRMWARE"
  265. " failed w/ status %04X\n",
  266. ha->host_no, __func__, mbox_sts[0]));
  267. return QLA_ERROR;
  268. }
  269. return QLA_SUCCESS;
  270. }
  271. uint8_t
  272. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  273. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  274. {
  275. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  276. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  277. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  278. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  279. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  280. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  281. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  282. QLA_SUCCESS) {
  283. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  284. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  285. " failed w/ status %04X\n",
  286. ha->host_no, __func__, mbox_sts[0]));
  287. return QLA_ERROR;
  288. }
  289. return QLA_SUCCESS;
  290. }
  291. static void
  292. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  293. struct addr_ctrl_blk *init_fw_cb)
  294. {
  295. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  296. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  297. ha->ip_config.ipv4_addr_state =
  298. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  299. ha->ip_config.eth_mtu_size =
  300. le16_to_cpu(init_fw_cb->eth_mtu_size);
  301. if (ha->acb_version == ACB_SUPPORTED) {
  302. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  303. ha->ip_config.ipv6_addl_options =
  304. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  305. }
  306. /* Save IPv4 Address Info */
  307. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  308. min(sizeof(ha->ip_config.ip_address),
  309. sizeof(init_fw_cb->ipv4_addr)));
  310. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  311. min(sizeof(ha->ip_config.subnet_mask),
  312. sizeof(init_fw_cb->ipv4_subnet)));
  313. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  314. min(sizeof(ha->ip_config.gateway),
  315. sizeof(init_fw_cb->ipv4_gw_addr)));
  316. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  317. if (is_ipv6_enabled(ha)) {
  318. /* Save IPv6 Address */
  319. ha->ip_config.ipv6_link_local_state =
  320. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  321. ha->ip_config.ipv6_addr0_state =
  322. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  323. ha->ip_config.ipv6_addr1_state =
  324. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  325. ha->ip_config.ipv6_default_router_state =
  326. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  327. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  328. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  329. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  330. init_fw_cb->ipv6_if_id,
  331. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  332. sizeof(init_fw_cb->ipv6_if_id)));
  333. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  334. min(sizeof(ha->ip_config.ipv6_addr0),
  335. sizeof(init_fw_cb->ipv6_addr0)));
  336. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  337. min(sizeof(ha->ip_config.ipv6_addr1),
  338. sizeof(init_fw_cb->ipv6_addr1)));
  339. memcpy(&ha->ip_config.ipv6_default_router_addr,
  340. init_fw_cb->ipv6_dflt_rtr_addr,
  341. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  342. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  343. ha->ip_config.ipv6_vlan_tag =
  344. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  345. }
  346. }
  347. uint8_t
  348. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  349. uint32_t *mbox_cmd,
  350. uint32_t *mbox_sts,
  351. struct addr_ctrl_blk *init_fw_cb,
  352. dma_addr_t init_fw_cb_dma)
  353. {
  354. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  355. != QLA_SUCCESS) {
  356. DEBUG2(printk(KERN_WARNING
  357. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  358. ha->host_no, __func__));
  359. return QLA_ERROR;
  360. }
  361. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  362. /* Save some info in adapter structure. */
  363. ha->acb_version = init_fw_cb->acb_version;
  364. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  365. ha->heartbeat_interval = init_fw_cb->hb_interval;
  366. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  367. min(sizeof(ha->name_string),
  368. sizeof(init_fw_cb->iscsi_name)));
  369. /*memcpy(ha->alias, init_fw_cb->Alias,
  370. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  371. qla4xxx_update_local_ip(ha, init_fw_cb);
  372. return QLA_SUCCESS;
  373. }
  374. /**
  375. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  376. * @ha: Pointer to host adapter structure.
  377. **/
  378. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  379. {
  380. struct addr_ctrl_blk *init_fw_cb;
  381. dma_addr_t init_fw_cb_dma;
  382. uint32_t mbox_cmd[MBOX_REG_COUNT];
  383. uint32_t mbox_sts[MBOX_REG_COUNT];
  384. int status = QLA_ERROR;
  385. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  386. sizeof(struct addr_ctrl_blk),
  387. &init_fw_cb_dma, GFP_KERNEL);
  388. if (init_fw_cb == NULL) {
  389. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  390. ha->host_no, __func__));
  391. goto exit_init_fw_cb_no_free;
  392. }
  393. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  394. /* Get Initialize Firmware Control Block. */
  395. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  396. memset(&mbox_sts, 0, sizeof(mbox_sts));
  397. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  398. QLA_SUCCESS) {
  399. dma_free_coherent(&ha->pdev->dev,
  400. sizeof(struct addr_ctrl_blk),
  401. init_fw_cb, init_fw_cb_dma);
  402. goto exit_init_fw_cb;
  403. }
  404. /* Initialize request and response queues. */
  405. qla4xxx_init_rings(ha);
  406. /* Fill in the request and response queue information. */
  407. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  408. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  409. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  410. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  411. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  412. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  413. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  414. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  415. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  416. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  417. /* Set up required options. */
  418. init_fw_cb->fw_options |=
  419. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  420. FWOPT_INITIATOR_MODE);
  421. if (is_qla8022(ha))
  422. init_fw_cb->fw_options |=
  423. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  424. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  425. init_fw_cb->add_fw_options = 0;
  426. init_fw_cb->add_fw_options |=
  427. __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
  428. init_fw_cb->add_fw_options |=
  429. __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
  430. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  431. != QLA_SUCCESS) {
  432. DEBUG2(printk(KERN_WARNING
  433. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  434. ha->host_no, __func__));
  435. goto exit_init_fw_cb;
  436. }
  437. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  438. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  439. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  440. ha->host_no, __func__));
  441. goto exit_init_fw_cb;
  442. }
  443. status = QLA_SUCCESS;
  444. exit_init_fw_cb:
  445. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  446. init_fw_cb, init_fw_cb_dma);
  447. exit_init_fw_cb_no_free:
  448. return status;
  449. }
  450. /**
  451. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  452. * @ha: Pointer to host adapter structure.
  453. **/
  454. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  455. {
  456. struct addr_ctrl_blk *init_fw_cb;
  457. dma_addr_t init_fw_cb_dma;
  458. uint32_t mbox_cmd[MBOX_REG_COUNT];
  459. uint32_t mbox_sts[MBOX_REG_COUNT];
  460. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  461. sizeof(struct addr_ctrl_blk),
  462. &init_fw_cb_dma, GFP_KERNEL);
  463. if (init_fw_cb == NULL) {
  464. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  465. __func__);
  466. return QLA_ERROR;
  467. }
  468. /* Get Initialize Firmware Control Block. */
  469. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  470. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  471. QLA_SUCCESS) {
  472. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  473. ha->host_no, __func__));
  474. dma_free_coherent(&ha->pdev->dev,
  475. sizeof(struct addr_ctrl_blk),
  476. init_fw_cb, init_fw_cb_dma);
  477. return QLA_ERROR;
  478. }
  479. /* Save IP Address. */
  480. qla4xxx_update_local_ip(ha, init_fw_cb);
  481. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  482. init_fw_cb, init_fw_cb_dma);
  483. return QLA_SUCCESS;
  484. }
  485. /**
  486. * qla4xxx_get_firmware_state - gets firmware state of HBA
  487. * @ha: Pointer to host adapter structure.
  488. **/
  489. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  490. {
  491. uint32_t mbox_cmd[MBOX_REG_COUNT];
  492. uint32_t mbox_sts[MBOX_REG_COUNT];
  493. /* Get firmware version */
  494. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  495. memset(&mbox_sts, 0, sizeof(mbox_sts));
  496. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  497. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  498. QLA_SUCCESS) {
  499. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  500. "status %04X\n", ha->host_no, __func__,
  501. mbox_sts[0]));
  502. return QLA_ERROR;
  503. }
  504. ha->firmware_state = mbox_sts[1];
  505. ha->board_id = mbox_sts[2];
  506. ha->addl_fw_state = mbox_sts[3];
  507. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  508. ha->host_no, __func__, ha->firmware_state);)
  509. return QLA_SUCCESS;
  510. }
  511. /**
  512. * qla4xxx_get_firmware_status - retrieves firmware status
  513. * @ha: Pointer to host adapter structure.
  514. **/
  515. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  516. {
  517. uint32_t mbox_cmd[MBOX_REG_COUNT];
  518. uint32_t mbox_sts[MBOX_REG_COUNT];
  519. /* Get firmware version */
  520. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  521. memset(&mbox_sts, 0, sizeof(mbox_sts));
  522. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  523. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  524. QLA_SUCCESS) {
  525. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  526. "status %04X\n", ha->host_no, __func__,
  527. mbox_sts[0]));
  528. return QLA_ERROR;
  529. }
  530. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  531. ha->host_no, mbox_sts[2]);
  532. return QLA_SUCCESS;
  533. }
  534. /**
  535. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  536. * @ha: Pointer to host adapter structure.
  537. * @fw_ddb_index: Firmware's device database index
  538. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  539. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  540. * @next_ddb_index: Pointer to next valid device database index
  541. * @fw_ddb_device_state: Pointer to device state
  542. **/
  543. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  544. uint16_t fw_ddb_index,
  545. struct dev_db_entry *fw_ddb_entry,
  546. dma_addr_t fw_ddb_entry_dma,
  547. uint32_t *num_valid_ddb_entries,
  548. uint32_t *next_ddb_index,
  549. uint32_t *fw_ddb_device_state,
  550. uint32_t *conn_err_detail,
  551. uint16_t *tcp_source_port_num,
  552. uint16_t *connection_id)
  553. {
  554. int status = QLA_ERROR;
  555. uint16_t options;
  556. uint32_t mbox_cmd[MBOX_REG_COUNT];
  557. uint32_t mbox_sts[MBOX_REG_COUNT];
  558. /* Make sure the device index is valid */
  559. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  560. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  561. ha->host_no, __func__, fw_ddb_index));
  562. goto exit_get_fwddb;
  563. }
  564. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  565. memset(&mbox_sts, 0, sizeof(mbox_sts));
  566. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  567. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  568. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  569. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  570. mbox_cmd[4] = sizeof(struct dev_db_entry);
  571. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  572. QLA_ERROR) {
  573. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  574. " with status 0x%04X\n", ha->host_no, __func__,
  575. mbox_sts[0]));
  576. goto exit_get_fwddb;
  577. }
  578. if (fw_ddb_index != mbox_sts[1]) {
  579. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  580. ha->host_no, __func__, fw_ddb_index,
  581. mbox_sts[1]));
  582. goto exit_get_fwddb;
  583. }
  584. if (fw_ddb_entry) {
  585. options = le16_to_cpu(fw_ddb_entry->options);
  586. if (options & DDB_OPT_IPV6_DEVICE) {
  587. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  588. "Next %d State %04x ConnErr %08x %pI6 "
  589. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  590. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  591. mbox_sts[4], mbox_sts[5],
  592. fw_ddb_entry->ip_addr,
  593. le16_to_cpu(fw_ddb_entry->port),
  594. fw_ddb_entry->iscsi_name);
  595. } else {
  596. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  597. "Next %d State %04x ConnErr %08x %pI4 "
  598. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  599. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  600. mbox_sts[4], mbox_sts[5],
  601. fw_ddb_entry->ip_addr,
  602. le16_to_cpu(fw_ddb_entry->port),
  603. fw_ddb_entry->iscsi_name);
  604. }
  605. }
  606. if (num_valid_ddb_entries)
  607. *num_valid_ddb_entries = mbox_sts[2];
  608. if (next_ddb_index)
  609. *next_ddb_index = mbox_sts[3];
  610. if (fw_ddb_device_state)
  611. *fw_ddb_device_state = mbox_sts[4];
  612. /*
  613. * RA: This mailbox has been changed to pass connection error and
  614. * details. Its true for ISP4010 as per Version E - Not sure when it
  615. * was changed. Get the time2wait from the fw_dd_entry field :
  616. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  617. * struct.
  618. */
  619. if (conn_err_detail)
  620. *conn_err_detail = mbox_sts[5];
  621. if (tcp_source_port_num)
  622. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  623. if (connection_id)
  624. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  625. status = QLA_SUCCESS;
  626. exit_get_fwddb:
  627. return status;
  628. }
  629. int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
  630. {
  631. uint32_t mbox_cmd[MBOX_REG_COUNT];
  632. uint32_t mbox_sts[MBOX_REG_COUNT];
  633. int status;
  634. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  635. memset(&mbox_sts, 0, sizeof(mbox_sts));
  636. mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
  637. mbox_cmd[1] = fw_ddb_index;
  638. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  639. &mbox_sts[0]);
  640. DEBUG2(ql4_printk(KERN_INFO, ha,
  641. "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
  642. __func__, status, mbox_sts[0], mbox_sts[1]));
  643. return status;
  644. }
  645. /**
  646. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  647. * @ha: Pointer to host adapter structure.
  648. * @fw_ddb_index: Firmware's device database index
  649. * @fw_ddb_entry_dma: dma address of ddb entry
  650. * @mbx_sts: mailbox 0 to be returned or NULL
  651. *
  652. * This routine initializes or updates the adapter's device database
  653. * entry for the specified device.
  654. **/
  655. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  656. dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
  657. {
  658. uint32_t mbox_cmd[MBOX_REG_COUNT];
  659. uint32_t mbox_sts[MBOX_REG_COUNT];
  660. int status;
  661. /* Do not wait for completion. The firmware will send us an
  662. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  663. */
  664. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  665. memset(&mbox_sts, 0, sizeof(mbox_sts));
  666. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  667. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  668. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  669. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  670. mbox_cmd[4] = sizeof(struct dev_db_entry);
  671. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  672. &mbox_sts[0]);
  673. if (mbx_sts)
  674. *mbx_sts = mbox_sts[0];
  675. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  676. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  677. return status;
  678. }
  679. int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
  680. struct ddb_entry *ddb_entry, int options)
  681. {
  682. int status;
  683. uint32_t mbox_cmd[MBOX_REG_COUNT];
  684. uint32_t mbox_sts[MBOX_REG_COUNT];
  685. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  686. memset(&mbox_sts, 0, sizeof(mbox_sts));
  687. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  688. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  689. mbox_cmd[3] = options;
  690. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  691. &mbox_sts[0]);
  692. if (status != QLA_SUCCESS) {
  693. DEBUG2(ql4_printk(KERN_INFO, ha,
  694. "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
  695. "failed sts %04X %04X", __func__,
  696. mbox_sts[0], mbox_sts[1]));
  697. }
  698. return status;
  699. }
  700. /**
  701. * qla4xxx_get_crash_record - retrieves crash record.
  702. * @ha: Pointer to host adapter structure.
  703. *
  704. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  705. **/
  706. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  707. {
  708. uint32_t mbox_cmd[MBOX_REG_COUNT];
  709. uint32_t mbox_sts[MBOX_REG_COUNT];
  710. struct crash_record *crash_record = NULL;
  711. dma_addr_t crash_record_dma = 0;
  712. uint32_t crash_record_size = 0;
  713. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  714. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  715. /* Get size of crash record. */
  716. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  717. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  718. QLA_SUCCESS) {
  719. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  720. ha->host_no, __func__));
  721. goto exit_get_crash_record;
  722. }
  723. crash_record_size = mbox_sts[4];
  724. if (crash_record_size == 0) {
  725. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  726. ha->host_no, __func__));
  727. goto exit_get_crash_record;
  728. }
  729. /* Alloc Memory for Crash Record. */
  730. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  731. &crash_record_dma, GFP_KERNEL);
  732. if (crash_record == NULL)
  733. goto exit_get_crash_record;
  734. /* Get Crash Record. */
  735. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  736. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  737. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  738. mbox_cmd[2] = LSDW(crash_record_dma);
  739. mbox_cmd[3] = MSDW(crash_record_dma);
  740. mbox_cmd[4] = crash_record_size;
  741. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  742. QLA_SUCCESS)
  743. goto exit_get_crash_record;
  744. /* Dump Crash Record. */
  745. exit_get_crash_record:
  746. if (crash_record)
  747. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  748. crash_record, crash_record_dma);
  749. }
  750. /**
  751. * qla4xxx_get_conn_event_log - retrieves connection event log
  752. * @ha: Pointer to host adapter structure.
  753. **/
  754. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  755. {
  756. uint32_t mbox_cmd[MBOX_REG_COUNT];
  757. uint32_t mbox_sts[MBOX_REG_COUNT];
  758. struct conn_event_log_entry *event_log = NULL;
  759. dma_addr_t event_log_dma = 0;
  760. uint32_t event_log_size = 0;
  761. uint32_t num_valid_entries;
  762. uint32_t oldest_entry = 0;
  763. uint32_t max_event_log_entries;
  764. uint8_t i;
  765. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  766. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  767. /* Get size of crash record. */
  768. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  769. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  770. QLA_SUCCESS)
  771. goto exit_get_event_log;
  772. event_log_size = mbox_sts[4];
  773. if (event_log_size == 0)
  774. goto exit_get_event_log;
  775. /* Alloc Memory for Crash Record. */
  776. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  777. &event_log_dma, GFP_KERNEL);
  778. if (event_log == NULL)
  779. goto exit_get_event_log;
  780. /* Get Crash Record. */
  781. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  782. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  783. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  784. mbox_cmd[2] = LSDW(event_log_dma);
  785. mbox_cmd[3] = MSDW(event_log_dma);
  786. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  787. QLA_SUCCESS) {
  788. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  789. "log!\n", ha->host_no, __func__));
  790. goto exit_get_event_log;
  791. }
  792. /* Dump Event Log. */
  793. num_valid_entries = mbox_sts[1];
  794. max_event_log_entries = event_log_size /
  795. sizeof(struct conn_event_log_entry);
  796. if (num_valid_entries > max_event_log_entries)
  797. oldest_entry = num_valid_entries % max_event_log_entries;
  798. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  799. ha->host_no, num_valid_entries));
  800. if (ql4xextended_error_logging == 3) {
  801. if (oldest_entry == 0) {
  802. /* Circular Buffer has not wrapped around */
  803. for (i=0; i < num_valid_entries; i++) {
  804. qla4xxx_dump_buffer((uint8_t *)event_log+
  805. (i*sizeof(*event_log)),
  806. sizeof(*event_log));
  807. }
  808. }
  809. else {
  810. /* Circular Buffer has wrapped around -
  811. * display accordingly*/
  812. for (i=oldest_entry; i < max_event_log_entries; i++) {
  813. qla4xxx_dump_buffer((uint8_t *)event_log+
  814. (i*sizeof(*event_log)),
  815. sizeof(*event_log));
  816. }
  817. for (i=0; i < oldest_entry; i++) {
  818. qla4xxx_dump_buffer((uint8_t *)event_log+
  819. (i*sizeof(*event_log)),
  820. sizeof(*event_log));
  821. }
  822. }
  823. }
  824. exit_get_event_log:
  825. if (event_log)
  826. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  827. event_log_dma);
  828. }
  829. /**
  830. * qla4xxx_abort_task - issues Abort Task
  831. * @ha: Pointer to host adapter structure.
  832. * @srb: Pointer to srb entry
  833. *
  834. * This routine performs a LUN RESET on the specified target/lun.
  835. * The caller must ensure that the ddb_entry and lun_entry pointers
  836. * are valid before calling this routine.
  837. **/
  838. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  839. {
  840. uint32_t mbox_cmd[MBOX_REG_COUNT];
  841. uint32_t mbox_sts[MBOX_REG_COUNT];
  842. struct scsi_cmnd *cmd = srb->cmd;
  843. int status = QLA_SUCCESS;
  844. unsigned long flags = 0;
  845. uint32_t index;
  846. /*
  847. * Send abort task command to ISP, so that the ISP will return
  848. * request with ABORT status
  849. */
  850. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  851. memset(&mbox_sts, 0, sizeof(mbox_sts));
  852. spin_lock_irqsave(&ha->hardware_lock, flags);
  853. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  854. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  855. /* Firmware already posted completion on response queue */
  856. if (index == MAX_SRBS)
  857. return status;
  858. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  859. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  860. mbox_cmd[2] = index;
  861. /* Immediate Command Enable */
  862. mbox_cmd[5] = 0x01;
  863. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  864. &mbox_sts[0]);
  865. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  866. status = QLA_ERROR;
  867. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  868. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  869. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  870. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  871. }
  872. return status;
  873. }
  874. /**
  875. * qla4xxx_reset_lun - issues LUN Reset
  876. * @ha: Pointer to host adapter structure.
  877. * @ddb_entry: Pointer to device database entry
  878. * @lun: lun number
  879. *
  880. * This routine performs a LUN RESET on the specified target/lun.
  881. * The caller must ensure that the ddb_entry and lun_entry pointers
  882. * are valid before calling this routine.
  883. **/
  884. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  885. int lun)
  886. {
  887. uint32_t mbox_cmd[MBOX_REG_COUNT];
  888. uint32_t mbox_sts[MBOX_REG_COUNT];
  889. int status = QLA_SUCCESS;
  890. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  891. ddb_entry->fw_ddb_index, lun));
  892. /*
  893. * Send lun reset command to ISP, so that the ISP will return all
  894. * outstanding requests with RESET status
  895. */
  896. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  897. memset(&mbox_sts, 0, sizeof(mbox_sts));
  898. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  899. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  900. mbox_cmd[2] = lun << 8;
  901. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  902. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  903. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  904. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  905. status = QLA_ERROR;
  906. return status;
  907. }
  908. /**
  909. * qla4xxx_reset_target - issues target Reset
  910. * @ha: Pointer to host adapter structure.
  911. * @db_entry: Pointer to device database entry
  912. * @un_entry: Pointer to lun entry structure
  913. *
  914. * This routine performs a TARGET RESET on the specified target.
  915. * The caller must ensure that the ddb_entry pointers
  916. * are valid before calling this routine.
  917. **/
  918. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  919. struct ddb_entry *ddb_entry)
  920. {
  921. uint32_t mbox_cmd[MBOX_REG_COUNT];
  922. uint32_t mbox_sts[MBOX_REG_COUNT];
  923. int status = QLA_SUCCESS;
  924. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  925. ddb_entry->fw_ddb_index));
  926. /*
  927. * Send target reset command to ISP, so that the ISP will return all
  928. * outstanding requests with RESET status
  929. */
  930. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  931. memset(&mbox_sts, 0, sizeof(mbox_sts));
  932. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  933. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  934. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  935. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  936. &mbox_sts[0]);
  937. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  938. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  939. status = QLA_ERROR;
  940. return status;
  941. }
  942. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  943. uint32_t offset, uint32_t len)
  944. {
  945. uint32_t mbox_cmd[MBOX_REG_COUNT];
  946. uint32_t mbox_sts[MBOX_REG_COUNT];
  947. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  948. memset(&mbox_sts, 0, sizeof(mbox_sts));
  949. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  950. mbox_cmd[1] = LSDW(dma_addr);
  951. mbox_cmd[2] = MSDW(dma_addr);
  952. mbox_cmd[3] = offset;
  953. mbox_cmd[4] = len;
  954. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  955. QLA_SUCCESS) {
  956. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  957. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  958. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  959. return QLA_ERROR;
  960. }
  961. return QLA_SUCCESS;
  962. }
  963. /**
  964. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  965. * @ha: Pointer to host adapter structure.
  966. *
  967. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  968. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  969. * those mailboxes, if unused.
  970. **/
  971. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  972. {
  973. struct about_fw_info *about_fw = NULL;
  974. dma_addr_t about_fw_dma;
  975. uint32_t mbox_cmd[MBOX_REG_COUNT];
  976. uint32_t mbox_sts[MBOX_REG_COUNT];
  977. int status = QLA_ERROR;
  978. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  979. sizeof(struct about_fw_info),
  980. &about_fw_dma, GFP_KERNEL);
  981. if (!about_fw) {
  982. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  983. "for about_fw\n", __func__));
  984. return status;
  985. }
  986. memset(about_fw, 0, sizeof(struct about_fw_info));
  987. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  988. memset(&mbox_sts, 0, sizeof(mbox_sts));
  989. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  990. mbox_cmd[2] = LSDW(about_fw_dma);
  991. mbox_cmd[3] = MSDW(about_fw_dma);
  992. mbox_cmd[4] = sizeof(struct about_fw_info);
  993. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  994. &mbox_cmd[0], &mbox_sts[0]);
  995. if (status != QLA_SUCCESS) {
  996. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  997. "failed w/ status %04X\n", __func__,
  998. mbox_sts[0]));
  999. goto exit_about_fw;
  1000. }
  1001. /* Save version information. */
  1002. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  1003. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  1004. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  1005. ha->build_number = le16_to_cpu(about_fw->fw_build);
  1006. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  1007. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  1008. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  1009. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  1010. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  1011. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  1012. status = QLA_SUCCESS;
  1013. exit_about_fw:
  1014. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  1015. about_fw, about_fw_dma);
  1016. return status;
  1017. }
  1018. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
  1019. dma_addr_t dma_addr)
  1020. {
  1021. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1022. uint32_t mbox_sts[MBOX_REG_COUNT];
  1023. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1024. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1025. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  1026. mbox_cmd[1] = options;
  1027. mbox_cmd[2] = LSDW(dma_addr);
  1028. mbox_cmd[3] = MSDW(dma_addr);
  1029. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  1030. QLA_SUCCESS) {
  1031. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1032. ha->host_no, __func__, mbox_sts[0]));
  1033. return QLA_ERROR;
  1034. }
  1035. return QLA_SUCCESS;
  1036. }
  1037. int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
  1038. uint32_t *mbx_sts)
  1039. {
  1040. int status;
  1041. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1042. uint32_t mbox_sts[MBOX_REG_COUNT];
  1043. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1044. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1045. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1046. mbox_cmd[1] = ddb_index;
  1047. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1048. &mbox_sts[0]);
  1049. if (status != QLA_SUCCESS) {
  1050. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1051. __func__, mbox_sts[0]));
  1052. }
  1053. *mbx_sts = mbox_sts[0];
  1054. return status;
  1055. }
  1056. int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
  1057. {
  1058. int status;
  1059. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1060. uint32_t mbox_sts[MBOX_REG_COUNT];
  1061. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1062. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1063. mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
  1064. mbox_cmd[1] = ddb_index;
  1065. status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
  1066. &mbox_sts[0]);
  1067. if (status != QLA_SUCCESS) {
  1068. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1069. __func__, mbox_sts[0]));
  1070. }
  1071. return status;
  1072. }
  1073. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1074. uint32_t offset, uint32_t length, uint32_t options)
  1075. {
  1076. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1077. uint32_t mbox_sts[MBOX_REG_COUNT];
  1078. int status = QLA_SUCCESS;
  1079. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1080. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1081. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1082. mbox_cmd[1] = LSDW(dma_addr);
  1083. mbox_cmd[2] = MSDW(dma_addr);
  1084. mbox_cmd[3] = offset;
  1085. mbox_cmd[4] = length;
  1086. mbox_cmd[5] = options;
  1087. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1088. if (status != QLA_SUCCESS) {
  1089. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1090. "failed w/ status %04X, mbx1 %04X\n",
  1091. __func__, mbox_sts[0], mbox_sts[1]));
  1092. }
  1093. return status;
  1094. }
  1095. int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
  1096. struct dev_db_entry *fw_ddb_entry,
  1097. dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
  1098. {
  1099. uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
  1100. uint32_t dev_db_end_offset;
  1101. int status = QLA_ERROR;
  1102. memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
  1103. dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
  1104. dev_db_end_offset = FLASH_OFFSET_DB_END;
  1105. if (dev_db_start_offset > dev_db_end_offset) {
  1106. DEBUG2(ql4_printk(KERN_ERR, ha,
  1107. "%s:Invalid DDB index %d", __func__,
  1108. ddb_index));
  1109. goto exit_bootdb_failed;
  1110. }
  1111. if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
  1112. sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
  1113. ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
  1114. "failed\n", ha->host_no, __func__);
  1115. goto exit_bootdb_failed;
  1116. }
  1117. if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
  1118. status = QLA_SUCCESS;
  1119. exit_bootdb_failed:
  1120. return status;
  1121. }
  1122. int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
  1123. uint16_t idx)
  1124. {
  1125. int ret = 0;
  1126. int rval = QLA_ERROR;
  1127. uint32_t offset = 0;
  1128. struct ql4_chap_table *chap_table;
  1129. dma_addr_t chap_dma;
  1130. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1131. if (chap_table == NULL) {
  1132. ret = -ENOMEM;
  1133. goto exit_get_chap;
  1134. }
  1135. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1136. offset = 0x06000000 | (idx * sizeof(struct ql4_chap_table));
  1137. rval = qla4xxx_get_flash(ha, chap_dma, offset,
  1138. sizeof(struct ql4_chap_table));
  1139. if (rval != QLA_SUCCESS) {
  1140. ret = -EINVAL;
  1141. goto exit_get_chap;
  1142. }
  1143. DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
  1144. __le16_to_cpu(chap_table->cookie)));
  1145. if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
  1146. ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
  1147. goto exit_get_chap;
  1148. }
  1149. strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
  1150. strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
  1151. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1152. exit_get_chap:
  1153. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1154. return ret;
  1155. }
  1156. static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
  1157. char *password, uint16_t idx, int bidi)
  1158. {
  1159. int ret = 0;
  1160. int rval = QLA_ERROR;
  1161. uint32_t offset = 0;
  1162. struct ql4_chap_table *chap_table;
  1163. dma_addr_t chap_dma;
  1164. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1165. if (chap_table == NULL) {
  1166. ret = -ENOMEM;
  1167. goto exit_set_chap;
  1168. }
  1169. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1170. if (bidi)
  1171. chap_table->flags |= BIT_6; /* peer */
  1172. else
  1173. chap_table->flags |= BIT_7; /* local */
  1174. chap_table->secret_len = strlen(password);
  1175. strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
  1176. strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
  1177. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1178. offset = 0x06000000 | (idx * sizeof(struct ql4_chap_table));
  1179. rval = qla4xxx_set_flash(ha, chap_dma, offset,
  1180. sizeof(struct ql4_chap_table),
  1181. FLASH_OPT_RMW_COMMIT);
  1182. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1183. if (rval != QLA_SUCCESS)
  1184. ret = -EINVAL;
  1185. exit_set_chap:
  1186. return ret;
  1187. }
  1188. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1189. uint16_t fw_ddb_index,
  1190. uint16_t connection_id,
  1191. uint16_t option)
  1192. {
  1193. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1194. uint32_t mbox_sts[MBOX_REG_COUNT];
  1195. int status = QLA_SUCCESS;
  1196. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1197. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1198. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1199. mbox_cmd[1] = fw_ddb_index;
  1200. mbox_cmd[2] = connection_id;
  1201. mbox_cmd[3] = option;
  1202. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1203. if (status != QLA_SUCCESS) {
  1204. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1205. "option %04x failed w/ status %04X %04X\n",
  1206. __func__, option, mbox_sts[0], mbox_sts[1]));
  1207. }
  1208. return status;
  1209. }
  1210. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1211. {
  1212. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1213. uint32_t mbox_sts[MBOX_REG_COUNT];
  1214. int status = QLA_SUCCESS;
  1215. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1216. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1217. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1218. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1219. if (status != QLA_SUCCESS) {
  1220. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1221. "failed w/ status %04X %04X %04X", __func__,
  1222. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1223. }
  1224. return status;
  1225. }
  1226. int qla4xxx_get_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1227. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1228. {
  1229. int status = QLA_SUCCESS;
  1230. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1231. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1232. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1233. mbox_cmd[1] = 0; /* Primary ACB */
  1234. mbox_cmd[2] = LSDW(acb_dma);
  1235. mbox_cmd[3] = MSDW(acb_dma);
  1236. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1237. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1238. if (status != QLA_SUCCESS) {
  1239. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1240. "failed w/ status %04X\n", __func__,
  1241. mbox_sts[0]));
  1242. }
  1243. return status;
  1244. }
  1245. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1246. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1247. {
  1248. int status = QLA_SUCCESS;
  1249. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1250. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1251. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1252. mbox_cmd[1] = 0; /* Primary ACB */
  1253. mbox_cmd[2] = LSDW(acb_dma);
  1254. mbox_cmd[3] = MSDW(acb_dma);
  1255. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1256. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1257. if (status != QLA_SUCCESS) {
  1258. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1259. "failed w/ status %04X\n", __func__,
  1260. mbox_sts[0]));
  1261. }
  1262. return status;
  1263. }
  1264. int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
  1265. struct ddb_entry *ddb_entry,
  1266. struct iscsi_cls_conn *cls_conn,
  1267. uint32_t *mbx_sts)
  1268. {
  1269. struct dev_db_entry *fw_ddb_entry;
  1270. struct iscsi_conn *conn;
  1271. struct iscsi_session *sess;
  1272. struct qla_conn *qla_conn;
  1273. struct sockaddr *dst_addr;
  1274. dma_addr_t fw_ddb_entry_dma;
  1275. int status = QLA_SUCCESS;
  1276. int rval = 0;
  1277. struct sockaddr_in *addr;
  1278. struct sockaddr_in6 *addr6;
  1279. char *ip;
  1280. uint16_t iscsi_opts = 0;
  1281. uint32_t options = 0;
  1282. uint16_t idx;
  1283. int max_chap_entries = 0;
  1284. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1285. &fw_ddb_entry_dma, GFP_KERNEL);
  1286. if (!fw_ddb_entry) {
  1287. DEBUG2(ql4_printk(KERN_ERR, ha,
  1288. "%s: Unable to allocate dma buffer.\n",
  1289. __func__));
  1290. rval = -ENOMEM;
  1291. goto exit_set_param_no_free;
  1292. }
  1293. conn = cls_conn->dd_data;
  1294. qla_conn = conn->dd_data;
  1295. sess = conn->session;
  1296. dst_addr = &qla_conn->qla_ep->dst_addr;
  1297. if (dst_addr->sa_family == AF_INET6)
  1298. options |= IPV6_DEFAULT_DDB_ENTRY;
  1299. status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1300. if (status == QLA_ERROR) {
  1301. rval = -EINVAL;
  1302. goto exit_set_param;
  1303. }
  1304. iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
  1305. memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
  1306. memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
  1307. if (sess->targetname != NULL) {
  1308. memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
  1309. min(strlen(sess->targetname),
  1310. sizeof(fw_ddb_entry->iscsi_name)));
  1311. }
  1312. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1313. memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
  1314. fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
  1315. if (dst_addr->sa_family == AF_INET) {
  1316. addr = (struct sockaddr_in *)dst_addr;
  1317. ip = (char *)&addr->sin_addr;
  1318. memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
  1319. fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
  1320. DEBUG2(ql4_printk(KERN_INFO, ha,
  1321. "%s: Destination Address [%pI4]: index [%d]\n",
  1322. __func__, fw_ddb_entry->ip_addr,
  1323. ddb_entry->fw_ddb_index));
  1324. } else if (dst_addr->sa_family == AF_INET6) {
  1325. addr6 = (struct sockaddr_in6 *)dst_addr;
  1326. ip = (char *)&addr6->sin6_addr;
  1327. memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
  1328. fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
  1329. fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
  1330. DEBUG2(ql4_printk(KERN_INFO, ha,
  1331. "%s: Destination Address [%pI6]: index [%d]\n",
  1332. __func__, fw_ddb_entry->ip_addr,
  1333. ddb_entry->fw_ddb_index));
  1334. } else {
  1335. ql4_printk(KERN_ERR, ha,
  1336. "%s: Failed to get IP Address\n",
  1337. __func__);
  1338. rval = -EINVAL;
  1339. goto exit_set_param;
  1340. }
  1341. if (is_qla8022(ha))
  1342. max_chap_entries = MAX_CHAP_ENTRIES_82XX;
  1343. else
  1344. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1345. /* CHAP */
  1346. if (sess->username != NULL && sess->password != NULL) {
  1347. if (strlen(sess->username) && strlen(sess->password)) {
  1348. iscsi_opts |= BIT_7;
  1349. idx = ddb_entry->fw_ddb_index * 2;
  1350. if (idx > max_chap_entries) {
  1351. ql4_printk(KERN_ERR, ha,
  1352. "%s: Invalid ddb or chap index\n",
  1353. __func__);
  1354. rval = -EINVAL;
  1355. goto exit_set_param;
  1356. }
  1357. rval = qla4xxx_set_chap(ha, sess->username,
  1358. sess->password, idx, 0);
  1359. if (rval)
  1360. goto exit_set_param;
  1361. fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
  1362. }
  1363. }
  1364. if (sess->username_in != NULL && sess->password_in != NULL) {
  1365. /* Check if BIDI CHAP */
  1366. if (strlen(sess->username_in) && strlen(sess->password_in)) {
  1367. iscsi_opts |= BIT_4;
  1368. idx = (ddb_entry->fw_ddb_index * 2) + 1;
  1369. if (idx > max_chap_entries) {
  1370. ql4_printk(KERN_ERR, ha,
  1371. "%s: Invalid ddb or bidi chap "
  1372. "index\n", __func__);
  1373. rval = -EINVAL;
  1374. goto exit_set_param;
  1375. }
  1376. rval = qla4xxx_set_chap(ha, sess->username_in,
  1377. sess->password_in, idx, 0);
  1378. if (rval)
  1379. goto exit_set_param;
  1380. }
  1381. }
  1382. if (sess->initial_r2t_en)
  1383. iscsi_opts |= BIT_10;
  1384. if (sess->imm_data_en)
  1385. iscsi_opts |= BIT_11;
  1386. fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
  1387. if (conn->max_recv_dlength)
  1388. fw_ddb_entry->iscsi_max_rcv_data_seg_len =
  1389. __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
  1390. if (sess->max_r2t)
  1391. fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
  1392. if (sess->first_burst)
  1393. fw_ddb_entry->iscsi_first_burst_len =
  1394. __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
  1395. if (sess->max_burst)
  1396. fw_ddb_entry->iscsi_max_burst_len =
  1397. __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
  1398. if (sess->time2wait)
  1399. fw_ddb_entry->iscsi_def_time2wait =
  1400. cpu_to_le16(sess->time2wait);
  1401. if (sess->time2retain)
  1402. fw_ddb_entry->iscsi_def_time2retain =
  1403. cpu_to_le16(sess->time2retain);
  1404. status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
  1405. fw_ddb_entry_dma, mbx_sts);
  1406. if (status != QLA_SUCCESS)
  1407. rval = -EINVAL;
  1408. exit_set_param:
  1409. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1410. fw_ddb_entry, fw_ddb_entry_dma);
  1411. exit_set_param_no_free:
  1412. return rval;
  1413. }
  1414. int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
  1415. uint16_t stats_size, dma_addr_t stats_dma)
  1416. {
  1417. int status = QLA_SUCCESS;
  1418. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1419. uint32_t mbox_sts[MBOX_REG_COUNT];
  1420. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1421. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1422. mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
  1423. mbox_cmd[1] = fw_ddb_index;
  1424. mbox_cmd[2] = LSDW(stats_dma);
  1425. mbox_cmd[3] = MSDW(stats_dma);
  1426. mbox_cmd[4] = stats_size;
  1427. status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
  1428. if (status != QLA_SUCCESS) {
  1429. DEBUG2(ql4_printk(KERN_WARNING, ha,
  1430. "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
  1431. "failed w/ status %04X\n", __func__,
  1432. mbox_sts[0]));
  1433. }
  1434. return status;
  1435. }
  1436. int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
  1437. uint32_t ip_idx, uint32_t *sts)
  1438. {
  1439. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1440. uint32_t mbox_sts[MBOX_REG_COUNT];
  1441. int status = QLA_SUCCESS;
  1442. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1443. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1444. mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
  1445. mbox_cmd[1] = acb_idx;
  1446. mbox_cmd[2] = ip_idx;
  1447. status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
  1448. if (status != QLA_SUCCESS) {
  1449. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
  1450. "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
  1451. "status %04X\n", __func__, mbox_sts[0]));
  1452. }
  1453. memcpy(sts, mbox_sts, sizeof(mbox_sts));
  1454. return status;
  1455. }