pcxhr.c 38 KB

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  1. /*
  2. * Driver for Digigram pcxhr compatible soundcards
  3. *
  4. * main file with alsa callbacks
  5. *
  6. * Copyright (c) 2004 by Digigram <alsa@digigram.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/slab.h>
  25. #include <linux/pci.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/delay.h>
  28. #include <linux/moduleparam.h>
  29. #include <linux/mutex.h>
  30. #include <sound/core.h>
  31. #include <sound/initval.h>
  32. #include <sound/info.h>
  33. #include <sound/control.h>
  34. #include <sound/pcm.h>
  35. #include <sound/pcm_params.h>
  36. #include "pcxhr.h"
  37. #include "pcxhr_mixer.h"
  38. #include "pcxhr_hwdep.h"
  39. #include "pcxhr_core.h"
  40. #define DRIVER_NAME "pcxhr"
  41. MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>");
  42. MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
  43. MODULE_LICENSE("GPL");
  44. MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
  45. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  46. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  47. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  48. static int mono[SNDRV_CARDS]; /* capture in mono only */
  49. module_param_array(index, int, NULL, 0444);
  50. MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
  51. module_param_array(id, charp, NULL, 0444);
  52. MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
  53. module_param_array(enable, bool, NULL, 0444);
  54. MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
  55. module_param_array(mono, bool, NULL, 0444);
  56. MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
  57. enum {
  58. PCI_ID_VX882HR,
  59. PCI_ID_PCX882HR,
  60. PCI_ID_VX881HR,
  61. PCI_ID_PCX881HR,
  62. PCI_ID_PCX1222HR,
  63. PCI_ID_PCX1221HR,
  64. PCI_ID_LAST
  65. };
  66. static struct pci_device_id pcxhr_ids[] = {
  67. { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, /* VX882HR */
  68. { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, /* PCX882HR */
  69. { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, /* VX881HR */
  70. { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, /* PCX881HR */
  71. { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */
  72. { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */
  73. { 0, }
  74. };
  75. MODULE_DEVICE_TABLE(pci, pcxhr_ids);
  76. struct board_parameters {
  77. char* board_name;
  78. short playback_chips;
  79. short capture_chips;
  80. short firmware_num;
  81. };
  82. static struct board_parameters pcxhr_board_params[] = {
  83. [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, },
  84. [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, },
  85. [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, },
  86. [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, },
  87. [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, },
  88. [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, },
  89. };
  90. static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
  91. unsigned int* realfreq)
  92. {
  93. unsigned int reg;
  94. if (freq < 6900 || freq > 110250)
  95. return -EINVAL;
  96. reg = (28224000 * 10) / freq;
  97. reg = (reg + 5) / 10;
  98. if (reg < 0x200)
  99. *pllreg = reg + 0x800;
  100. else if (reg < 0x400)
  101. *pllreg = reg & 0x1ff;
  102. else if (reg < 0x800) {
  103. *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
  104. reg &= ~1;
  105. } else {
  106. *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
  107. reg &= ~3;
  108. }
  109. if (realfreq)
  110. *realfreq = ((28224000 * 10) / reg + 5) / 10;
  111. return 0;
  112. }
  113. #define PCXHR_FREQ_REG_MASK 0x1f
  114. #define PCXHR_FREQ_QUARTZ_48000 0x00
  115. #define PCXHR_FREQ_QUARTZ_24000 0x01
  116. #define PCXHR_FREQ_QUARTZ_12000 0x09
  117. #define PCXHR_FREQ_QUARTZ_32000 0x08
  118. #define PCXHR_FREQ_QUARTZ_16000 0x04
  119. #define PCXHR_FREQ_QUARTZ_8000 0x0c
  120. #define PCXHR_FREQ_QUARTZ_44100 0x02
  121. #define PCXHR_FREQ_QUARTZ_22050 0x0a
  122. #define PCXHR_FREQ_QUARTZ_11025 0x06
  123. #define PCXHR_FREQ_PLL 0x05
  124. #define PCXHR_FREQ_QUARTZ_192000 0x10
  125. #define PCXHR_FREQ_QUARTZ_96000 0x18
  126. #define PCXHR_FREQ_QUARTZ_176400 0x14
  127. #define PCXHR_FREQ_QUARTZ_88200 0x1c
  128. #define PCXHR_FREQ_QUARTZ_128000 0x12
  129. #define PCXHR_FREQ_QUARTZ_64000 0x1a
  130. #define PCXHR_FREQ_WORD_CLOCK 0x0f
  131. #define PCXHR_FREQ_SYNC_AES 0x0e
  132. #define PCXHR_FREQ_AES_1 0x07
  133. #define PCXHR_FREQ_AES_2 0x0b
  134. #define PCXHR_FREQ_AES_3 0x03
  135. #define PCXHR_FREQ_AES_4 0x0d
  136. #define PCXHR_MODIFY_CLOCK_S_BIT 0x04
  137. #define PCXHR_IRQ_TIMER_FREQ 92000
  138. #define PCXHR_IRQ_TIMER_PERIOD 48
  139. static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
  140. unsigned int *reg, unsigned int *freq)
  141. {
  142. unsigned int val, realfreq, pllreg;
  143. struct pcxhr_rmh rmh;
  144. int err;
  145. realfreq = rate;
  146. switch (mgr->use_clock_type) {
  147. case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */
  148. switch (rate) {
  149. case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
  150. case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
  151. case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
  152. case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
  153. case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
  154. case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
  155. case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
  156. case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
  157. case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
  158. case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
  159. case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
  160. case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
  161. case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
  162. case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
  163. case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
  164. default :
  165. val = PCXHR_FREQ_PLL;
  166. /* get the value for the pll register */
  167. err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
  168. if (err)
  169. return err;
  170. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
  171. rmh.cmd[0] |= IO_NUM_REG_GENCLK;
  172. rmh.cmd[1] = pllreg & MASK_DSP_WORD;
  173. rmh.cmd[2] = pllreg >> 24;
  174. rmh.cmd_len = 3;
  175. err = pcxhr_send_msg(mgr, &rmh);
  176. if (err < 0) {
  177. snd_printk(KERN_ERR
  178. "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n",
  179. err );
  180. return err;
  181. }
  182. }
  183. break;
  184. case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break;
  185. case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break;
  186. case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break;
  187. case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break;
  188. case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break;
  189. case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break;
  190. default : return -EINVAL;
  191. }
  192. *reg = val;
  193. *freq = realfreq;
  194. return 0;
  195. }
  196. int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
  197. {
  198. unsigned int val, realfreq, speed;
  199. struct pcxhr_rmh rmh;
  200. int err, changed;
  201. if (rate == 0)
  202. return 0; /* nothing to do */
  203. err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
  204. if (err)
  205. return err;
  206. /* codec speed modes */
  207. if (rate < 55000)
  208. speed = 0; /* single speed */
  209. else if (rate < 100000)
  210. speed = 1; /* dual speed */
  211. else
  212. speed = 2; /* quad speed */
  213. if (mgr->codec_speed != speed) {
  214. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
  215. rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
  216. err = pcxhr_send_msg(mgr, &rmh);
  217. if (err)
  218. return err;
  219. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
  220. rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
  221. rmh.cmd[1] = speed;
  222. rmh.cmd_len = 2;
  223. err = pcxhr_send_msg(mgr, &rmh);
  224. if (err)
  225. return err;
  226. }
  227. /* set the new frequency */
  228. snd_printdd("clock register : set %x\n", val);
  229. err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed);
  230. if (err)
  231. return err;
  232. mgr->sample_rate_real = realfreq;
  233. mgr->cur_clock_type = mgr->use_clock_type;
  234. /* unmute after codec speed modes */
  235. if (mgr->codec_speed != speed) {
  236. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
  237. rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
  238. err = pcxhr_send_msg(mgr, &rmh);
  239. if (err)
  240. return err;
  241. mgr->codec_speed = speed; /* save new codec speed */
  242. }
  243. if (changed) {
  244. pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
  245. rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
  246. if (rate < PCXHR_IRQ_TIMER_FREQ)
  247. rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
  248. else
  249. rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
  250. rmh.cmd[2] = rate;
  251. rmh.cmd_len = 3;
  252. err = pcxhr_send_msg(mgr, &rmh);
  253. if (err)
  254. return err;
  255. }
  256. snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq);
  257. return 0;
  258. }
  259. int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type,
  260. int *sample_rate)
  261. {
  262. struct pcxhr_rmh rmh;
  263. unsigned char reg;
  264. int err, rate;
  265. switch (clock_type) {
  266. case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break;
  267. case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break;
  268. case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break;
  269. case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break;
  270. case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break;
  271. case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break;
  272. default : return -EINVAL;
  273. }
  274. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
  275. rmh.cmd_len = 2;
  276. rmh.cmd[0] |= IO_NUM_REG_STATUS;
  277. if (mgr->last_reg_stat != reg) {
  278. rmh.cmd[1] = reg;
  279. err = pcxhr_send_msg(mgr, &rmh);
  280. if (err)
  281. return err;
  282. udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */
  283. mgr->last_reg_stat = reg;
  284. }
  285. rmh.cmd[1] = REG_STATUS_CURRENT;
  286. err = pcxhr_send_msg(mgr, &rmh);
  287. if (err)
  288. return err;
  289. switch (rmh.stat[1] & 0x0f) {
  290. case REG_STATUS_SYNC_32000 : rate = 32000; break;
  291. case REG_STATUS_SYNC_44100 : rate = 44100; break;
  292. case REG_STATUS_SYNC_48000 : rate = 48000; break;
  293. case REG_STATUS_SYNC_64000 : rate = 64000; break;
  294. case REG_STATUS_SYNC_88200 : rate = 88200; break;
  295. case REG_STATUS_SYNC_96000 : rate = 96000; break;
  296. case REG_STATUS_SYNC_128000 : rate = 128000; break;
  297. case REG_STATUS_SYNC_176400 : rate = 176400; break;
  298. case REG_STATUS_SYNC_192000 : rate = 192000; break;
  299. default: rate = 0;
  300. }
  301. snd_printdd("External clock is at %d Hz\n", rate);
  302. *sample_rate = rate;
  303. return 0;
  304. }
  305. /*
  306. * start or stop playback/capture substream
  307. */
  308. static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
  309. {
  310. int err;
  311. struct snd_pcxhr *chip;
  312. struct pcxhr_rmh rmh;
  313. int stream_mask, start;
  314. if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
  315. start = 1;
  316. else {
  317. if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
  318. snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n");
  319. return -EINVAL;
  320. }
  321. start = 0;
  322. }
  323. if (!stream->substream)
  324. return -EINVAL;
  325. stream->timer_abs_periods = 0;
  326. stream->timer_period_frag = 0; /* reset theoretical stream pos */
  327. stream->timer_buf_periods = 0;
  328. stream->timer_is_synced = 0;
  329. stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
  330. pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
  331. pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
  332. stream->pipe->first_audio, 0, stream_mask);
  333. chip = snd_pcm_substream_chip(stream->substream);
  334. err = pcxhr_send_msg(chip->mgr, &rmh);
  335. if (err)
  336. snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err);
  337. stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
  338. return err;
  339. }
  340. #define HEADER_FMT_BASE_LIN 0xfed00000
  341. #define HEADER_FMT_BASE_FLOAT 0xfad00000
  342. #define HEADER_FMT_INTEL 0x00008000
  343. #define HEADER_FMT_24BITS 0x00004000
  344. #define HEADER_FMT_16BITS 0x00002000
  345. #define HEADER_FMT_UPTO11 0x00000200
  346. #define HEADER_FMT_UPTO32 0x00000100
  347. #define HEADER_FMT_MONO 0x00000080
  348. static int pcxhr_set_format(struct pcxhr_stream *stream)
  349. {
  350. int err, is_capture, sample_rate, stream_num;
  351. struct snd_pcxhr *chip;
  352. struct pcxhr_rmh rmh;
  353. unsigned int header;
  354. switch (stream->format) {
  355. case SNDRV_PCM_FORMAT_U8:
  356. header = HEADER_FMT_BASE_LIN;
  357. break;
  358. case SNDRV_PCM_FORMAT_S16_LE:
  359. header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL;
  360. break;
  361. case SNDRV_PCM_FORMAT_S16_BE:
  362. header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
  363. break;
  364. case SNDRV_PCM_FORMAT_S24_3LE:
  365. header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL;
  366. break;
  367. case SNDRV_PCM_FORMAT_S24_3BE:
  368. header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
  369. break;
  370. case SNDRV_PCM_FORMAT_FLOAT_LE:
  371. header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
  372. break;
  373. default:
  374. snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n");
  375. return -EINVAL;
  376. }
  377. chip = snd_pcm_substream_chip(stream->substream);
  378. sample_rate = chip->mgr->sample_rate;
  379. if (sample_rate <= 32000 && sample_rate !=0) {
  380. if (sample_rate <= 11025)
  381. header |= HEADER_FMT_UPTO11;
  382. else
  383. header |= HEADER_FMT_UPTO32;
  384. }
  385. if (stream->channels == 1)
  386. header |= HEADER_FMT_MONO;
  387. is_capture = stream->pipe->is_capture;
  388. stream_num = is_capture ? 0 : stream->substream->number;
  389. pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
  390. pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
  391. if (is_capture)
  392. rmh.cmd[0] |= 1<<12;
  393. rmh.cmd[1] = 0;
  394. rmh.cmd[2] = header >> 8;
  395. rmh.cmd[3] = (header & 0xff) << 16;
  396. rmh.cmd_len = 4;
  397. err = pcxhr_send_msg(chip->mgr, &rmh);
  398. if (err)
  399. snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
  400. return err;
  401. }
  402. static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
  403. {
  404. int err, is_capture, stream_num;
  405. struct pcxhr_rmh rmh;
  406. struct snd_pcm_substream *subs = stream->substream;
  407. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  408. is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
  409. stream_num = is_capture ? 0 : subs->number;
  410. snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n",
  411. is_capture ? 'c' : 'p',
  412. chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
  413. subs->runtime->dma_bytes, subs->number);
  414. pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
  415. pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
  416. /* max buffer size is 2 MByte */
  417. snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
  418. rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* size in bits */
  419. rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* most significant byte */
  420. rmh.cmd[2] |= 1<<19; /* this is a circular buffer */
  421. rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; /* least 3 significant bytes */
  422. rmh.cmd_len = 4;
  423. err = pcxhr_send_msg(chip->mgr, &rmh);
  424. if (err)
  425. snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
  426. return err;
  427. }
  428. #if 0
  429. static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count)
  430. {
  431. struct pcxhr_rmh rmh;
  432. int err;
  433. pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
  434. pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
  435. pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
  436. 1<<stream->pipe->first_audio);
  437. err = pcxhr_send_msg(chip->mgr, &rmh);
  438. if (err == 0) {
  439. *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
  440. *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
  441. }
  442. snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
  443. return err;
  444. }
  445. #endif
  446. static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
  447. struct pcxhr_pipe **pipe)
  448. {
  449. if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
  450. *pipe = stream->pipe;
  451. return 1;
  452. }
  453. return 0;
  454. }
  455. static void pcxhr_trigger_tasklet(unsigned long arg)
  456. {
  457. unsigned long flags;
  458. int i, j, err;
  459. struct pcxhr_pipe *pipe;
  460. struct snd_pcxhr *chip;
  461. struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg);
  462. int capture_mask = 0;
  463. int playback_mask = 0;
  464. #ifdef CONFIG_SND_DEBUG_VERBOSE
  465. struct timeval my_tv1, my_tv2;
  466. do_gettimeofday(&my_tv1);
  467. #endif
  468. mutex_lock(&mgr->setup_mutex);
  469. /* check the pipes concerned and build pipe_array */
  470. for (i = 0; i < mgr->num_cards; i++) {
  471. chip = mgr->chip[i];
  472. for (j = 0; j < chip->nb_streams_capt; j++) {
  473. if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
  474. capture_mask |= (1 << pipe->first_audio);
  475. }
  476. for (j = 0; j < chip->nb_streams_play; j++) {
  477. if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
  478. playback_mask |= (1 << pipe->first_audio);
  479. break; /* add only once, as all playback streams of
  480. * one chip use the same pipe
  481. */
  482. }
  483. }
  484. }
  485. if (capture_mask == 0 && playback_mask == 0) {
  486. mutex_unlock(&mgr->setup_mutex);
  487. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n");
  488. return;
  489. }
  490. snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n",
  491. playback_mask, capture_mask);
  492. /* synchronous stop of all the pipes concerned */
  493. err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
  494. if (err) {
  495. mutex_unlock(&mgr->setup_mutex);
  496. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n",
  497. playback_mask, capture_mask);
  498. return;
  499. }
  500. /* unfortunately the dsp lost format and buffer info with the stop pipe */
  501. for (i = 0; i < mgr->num_cards; i++) {
  502. struct pcxhr_stream *stream;
  503. chip = mgr->chip[i];
  504. for (j = 0; j < chip->nb_streams_capt; j++) {
  505. stream = &chip->capture_stream[j];
  506. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
  507. err = pcxhr_set_format(stream);
  508. err = pcxhr_update_r_buffer(stream);
  509. }
  510. }
  511. for (j = 0; j < chip->nb_streams_play; j++) {
  512. stream = &chip->playback_stream[j];
  513. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
  514. err = pcxhr_set_format(stream);
  515. err = pcxhr_update_r_buffer(stream);
  516. }
  517. }
  518. }
  519. /* start all the streams */
  520. for (i = 0; i < mgr->num_cards; i++) {
  521. struct pcxhr_stream *stream;
  522. chip = mgr->chip[i];
  523. for (j = 0; j < chip->nb_streams_capt; j++) {
  524. stream = &chip->capture_stream[j];
  525. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
  526. err = pcxhr_set_stream_state(stream);
  527. }
  528. for (j = 0; j < chip->nb_streams_play; j++) {
  529. stream = &chip->playback_stream[j];
  530. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
  531. err = pcxhr_set_stream_state(stream);
  532. }
  533. }
  534. /* synchronous start of all the pipes concerned */
  535. err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
  536. if (err) {
  537. mutex_unlock(&mgr->setup_mutex);
  538. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n",
  539. playback_mask, capture_mask);
  540. return;
  541. }
  542. /* put the streams into the running state now (increment pointer by interrupt) */
  543. spin_lock_irqsave(&mgr->lock, flags);
  544. for ( i =0; i < mgr->num_cards; i++) {
  545. struct pcxhr_stream *stream;
  546. chip = mgr->chip[i];
  547. for(j = 0; j < chip->nb_streams_capt; j++) {
  548. stream = &chip->capture_stream[j];
  549. if(stream->status == PCXHR_STREAM_STATUS_STARTED)
  550. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  551. }
  552. for (j = 0; j < chip->nb_streams_play; j++) {
  553. stream = &chip->playback_stream[j];
  554. if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
  555. /* playback will already have advanced ! */
  556. stream->timer_period_frag += PCXHR_GRANULARITY;
  557. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  558. }
  559. }
  560. }
  561. spin_unlock_irqrestore(&mgr->lock, flags);
  562. mutex_unlock(&mgr->setup_mutex);
  563. #ifdef CONFIG_SND_DEBUG_VERBOSE
  564. do_gettimeofday(&my_tv2);
  565. snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n",
  566. (long)(my_tv2.tv_usec - my_tv1.tv_usec), err);
  567. #endif
  568. }
  569. /*
  570. * trigger callback
  571. */
  572. static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
  573. {
  574. struct pcxhr_stream *stream;
  575. struct snd_pcm_substream *s;
  576. switch (cmd) {
  577. case SNDRV_PCM_TRIGGER_START:
  578. snd_printdd("SNDRV_PCM_TRIGGER_START\n");
  579. if (snd_pcm_stream_linked(subs)) {
  580. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  581. snd_pcm_group_for_each_entry(s, subs) {
  582. if (snd_pcm_substream_chip(s) != chip)
  583. continue;
  584. stream = s->runtime->private_data;
  585. stream->status =
  586. PCXHR_STREAM_STATUS_SCHEDULE_RUN;
  587. snd_pcm_trigger_done(s, subs);
  588. }
  589. tasklet_schedule(&chip->mgr->trigger_taskq);
  590. } else {
  591. stream = subs->runtime->private_data;
  592. snd_printdd("Only one Substream %c %d\n",
  593. stream->pipe->is_capture ? 'C' : 'P',
  594. stream->pipe->first_audio);
  595. if (pcxhr_set_format(stream))
  596. return -EINVAL;
  597. if (pcxhr_update_r_buffer(stream))
  598. return -EINVAL;
  599. stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
  600. if (pcxhr_set_stream_state(stream))
  601. return -EINVAL;
  602. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  603. }
  604. break;
  605. case SNDRV_PCM_TRIGGER_STOP:
  606. snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
  607. snd_pcm_group_for_each_entry(s, subs) {
  608. stream = s->runtime->private_data;
  609. stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
  610. if (pcxhr_set_stream_state(stream))
  611. return -EINVAL;
  612. snd_pcm_trigger_done(s, subs);
  613. }
  614. break;
  615. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  616. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  617. /* TODO */
  618. default:
  619. return -EINVAL;
  620. }
  621. return 0;
  622. }
  623. static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
  624. {
  625. struct pcxhr_rmh rmh;
  626. int err;
  627. pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
  628. if (start) {
  629. mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; /* last dsp time invalid */
  630. rmh.cmd[0] |= PCXHR_GRANULARITY;
  631. }
  632. err = pcxhr_send_msg(mgr, &rmh);
  633. if (err < 0)
  634. snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err);
  635. return err;
  636. }
  637. /*
  638. * prepare callback for all pcms
  639. */
  640. static int pcxhr_prepare(struct snd_pcm_substream *subs)
  641. {
  642. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  643. struct pcxhr_mgr *mgr = chip->mgr;
  644. /*
  645. struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data;
  646. */
  647. int err = 0;
  648. snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
  649. subs->runtime->period_size, subs->runtime->periods,
  650. subs->runtime->buffer_size);
  651. /*
  652. if(subs->runtime->period_size <= PCXHR_GRANULARITY) {
  653. snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n",
  654. (unsigned int)subs->runtime->period_size);
  655. return -EINVAL;
  656. }
  657. */
  658. mutex_lock(&mgr->setup_mutex);
  659. do {
  660. /* if the stream was stopped before, format and buffer were reset */
  661. /*
  662. if(stream->status == PCXHR_STREAM_STATUS_STOPPED) {
  663. err = pcxhr_set_format(stream);
  664. if(err) break;
  665. err = pcxhr_update_r_buffer(stream);
  666. if(err) break;
  667. }
  668. */
  669. /* only the first stream can choose the sample rate */
  670. /* the further opened streams will be limited to its frequency (see open) */
  671. /* set the clock only once (first stream) */
  672. if (mgr->sample_rate != subs->runtime->rate) {
  673. err = pcxhr_set_clock(mgr, subs->runtime->rate);
  674. if (err)
  675. break;
  676. if (mgr->sample_rate == 0)
  677. /* start the DSP-timer */
  678. err = pcxhr_hardware_timer(mgr, 1);
  679. mgr->sample_rate = subs->runtime->rate;
  680. }
  681. } while(0); /* do only once (so we can use break instead of goto) */
  682. mutex_unlock(&mgr->setup_mutex);
  683. return err;
  684. }
  685. /*
  686. * HW_PARAMS callback for all pcms
  687. */
  688. static int pcxhr_hw_params(struct snd_pcm_substream *subs,
  689. struct snd_pcm_hw_params *hw)
  690. {
  691. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  692. struct pcxhr_mgr *mgr = chip->mgr;
  693. struct pcxhr_stream *stream = subs->runtime->private_data;
  694. snd_pcm_format_t format;
  695. int err;
  696. int channels;
  697. /* set up channels */
  698. channels = params_channels(hw);
  699. /* set up format for the stream */
  700. format = params_format(hw);
  701. mutex_lock(&mgr->setup_mutex);
  702. stream->channels = channels;
  703. stream->format = format;
  704. /* set the format to the board */
  705. /*
  706. err = pcxhr_set_format(stream);
  707. if(err) {
  708. mutex_unlock(&mgr->setup_mutex);
  709. return err;
  710. }
  711. */
  712. /* allocate buffer */
  713. err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
  714. /*
  715. if (err > 0) {
  716. err = pcxhr_update_r_buffer(stream);
  717. }
  718. */
  719. mutex_unlock(&mgr->setup_mutex);
  720. return err;
  721. }
  722. static int pcxhr_hw_free(struct snd_pcm_substream *subs)
  723. {
  724. snd_pcm_lib_free_pages(subs);
  725. return 0;
  726. }
  727. /*
  728. * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
  729. */
  730. static struct snd_pcm_hardware pcxhr_caps =
  731. {
  732. .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  733. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START |
  734. 0 /*SNDRV_PCM_INFO_PAUSE*/),
  735. .formats = ( SNDRV_PCM_FMTBIT_U8 |
  736. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
  737. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE |
  738. SNDRV_PCM_FMTBIT_FLOAT_LE ),
  739. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000,
  740. .rate_min = 8000,
  741. .rate_max = 192000,
  742. .channels_min = 1,
  743. .channels_max = 2,
  744. .buffer_bytes_max = (32*1024),
  745. /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
  746. .period_bytes_min = (2*PCXHR_GRANULARITY),
  747. .period_bytes_max = (16*1024),
  748. .periods_min = 2,
  749. .periods_max = (32*1024/PCXHR_GRANULARITY),
  750. };
  751. static int pcxhr_open(struct snd_pcm_substream *subs)
  752. {
  753. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  754. struct pcxhr_mgr *mgr = chip->mgr;
  755. struct snd_pcm_runtime *runtime = subs->runtime;
  756. struct pcxhr_stream *stream;
  757. mutex_lock(&mgr->setup_mutex);
  758. /* copy the struct snd_pcm_hardware struct */
  759. runtime->hw = pcxhr_caps;
  760. if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
  761. snd_printdd("pcxhr_open playback chip%d subs%d\n",
  762. chip->chip_idx, subs->number);
  763. stream = &chip->playback_stream[subs->number];
  764. } else {
  765. snd_printdd("pcxhr_open capture chip%d subs%d\n",
  766. chip->chip_idx, subs->number);
  767. if (mgr->mono_capture)
  768. runtime->hw.channels_max = 1;
  769. else
  770. runtime->hw.channels_min = 2;
  771. stream = &chip->capture_stream[subs->number];
  772. }
  773. if (stream->status != PCXHR_STREAM_STATUS_FREE){
  774. /* streams in use */
  775. snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n",
  776. chip->chip_idx, subs->number);
  777. mutex_unlock(&mgr->setup_mutex);
  778. return -EBUSY;
  779. }
  780. /* if a sample rate is already used or fixed by external clock,
  781. * the stream cannot change
  782. */
  783. if (mgr->sample_rate)
  784. runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
  785. else {
  786. if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
  787. int external_rate;
  788. if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
  789. &external_rate) ||
  790. external_rate == 0) {
  791. /* cannot detect the external clock rate */
  792. mutex_unlock(&mgr->setup_mutex);
  793. return -EBUSY;
  794. }
  795. runtime->hw.rate_min = runtime->hw.rate_max = external_rate;
  796. }
  797. }
  798. stream->status = PCXHR_STREAM_STATUS_OPEN;
  799. stream->substream = subs;
  800. stream->channels = 0; /* not configured yet */
  801. runtime->private_data = stream;
  802. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4);
  803. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
  804. snd_pcm_set_sync(subs);
  805. mgr->ref_count_rate++;
  806. mutex_unlock(&mgr->setup_mutex);
  807. return 0;
  808. }
  809. static int pcxhr_close(struct snd_pcm_substream *subs)
  810. {
  811. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  812. struct pcxhr_mgr *mgr = chip->mgr;
  813. struct pcxhr_stream *stream = subs->runtime->private_data;
  814. mutex_lock(&mgr->setup_mutex);
  815. snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number);
  816. /* sample rate released */
  817. if (--mgr->ref_count_rate == 0) {
  818. mgr->sample_rate = 0; /* the sample rate is no more locked */
  819. pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */
  820. }
  821. stream->status = PCXHR_STREAM_STATUS_FREE;
  822. stream->substream = NULL;
  823. mutex_unlock(&mgr->setup_mutex);
  824. return 0;
  825. }
  826. static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
  827. {
  828. unsigned long flags;
  829. u_int32_t timer_period_frag;
  830. int timer_buf_periods;
  831. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  832. struct snd_pcm_runtime *runtime = subs->runtime;
  833. struct pcxhr_stream *stream = runtime->private_data;
  834. spin_lock_irqsave(&chip->mgr->lock, flags);
  835. /* get the period fragment and the nb of periods in the buffer */
  836. timer_period_frag = stream->timer_period_frag;
  837. timer_buf_periods = stream->timer_buf_periods;
  838. spin_unlock_irqrestore(&chip->mgr->lock, flags);
  839. return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
  840. timer_period_frag);
  841. }
  842. static struct snd_pcm_ops pcxhr_ops = {
  843. .open = pcxhr_open,
  844. .close = pcxhr_close,
  845. .ioctl = snd_pcm_lib_ioctl,
  846. .prepare = pcxhr_prepare,
  847. .hw_params = pcxhr_hw_params,
  848. .hw_free = pcxhr_hw_free,
  849. .trigger = pcxhr_trigger,
  850. .pointer = pcxhr_stream_pointer,
  851. };
  852. /*
  853. */
  854. int pcxhr_create_pcm(struct snd_pcxhr *chip)
  855. {
  856. int err;
  857. struct snd_pcm *pcm;
  858. char name[32];
  859. sprintf(name, "pcxhr %d", chip->chip_idx);
  860. if ((err = snd_pcm_new(chip->card, name, 0,
  861. chip->nb_streams_play,
  862. chip->nb_streams_capt, &pcm)) < 0) {
  863. snd_printk(KERN_ERR "cannot create pcm %s\n", name);
  864. return err;
  865. }
  866. pcm->private_data = chip;
  867. if (chip->nb_streams_play)
  868. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
  869. if (chip->nb_streams_capt)
  870. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
  871. pcm->info_flags = 0;
  872. strcpy(pcm->name, name);
  873. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  874. snd_dma_pci_data(chip->mgr->pci),
  875. 32*1024, 32*1024);
  876. chip->pcm = pcm;
  877. return 0;
  878. }
  879. static int pcxhr_chip_free(struct snd_pcxhr *chip)
  880. {
  881. kfree(chip);
  882. return 0;
  883. }
  884. static int pcxhr_chip_dev_free(struct snd_device *device)
  885. {
  886. struct snd_pcxhr *chip = device->device_data;
  887. return pcxhr_chip_free(chip);
  888. }
  889. /*
  890. */
  891. static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx)
  892. {
  893. int err;
  894. struct snd_pcxhr *chip;
  895. static struct snd_device_ops ops = {
  896. .dev_free = pcxhr_chip_dev_free,
  897. };
  898. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  899. if (! chip) {
  900. snd_printk(KERN_ERR "cannot allocate chip\n");
  901. return -ENOMEM;
  902. }
  903. chip->card = card;
  904. chip->chip_idx = idx;
  905. chip->mgr = mgr;
  906. if (idx < mgr->playback_chips)
  907. /* stereo or mono streams */
  908. chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
  909. if (idx < mgr->capture_chips) {
  910. if (mgr->mono_capture)
  911. chip->nb_streams_capt = 2; /* 2 mono streams (left+right) */
  912. else
  913. chip->nb_streams_capt = 1; /* or 1 stereo stream */
  914. }
  915. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  916. pcxhr_chip_free(chip);
  917. return err;
  918. }
  919. mgr->chip[idx] = chip;
  920. snd_card_set_dev(card, &mgr->pci->dev);
  921. return 0;
  922. }
  923. /* proc interface */
  924. static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  925. {
  926. struct snd_pcxhr *chip = entry->private_data;
  927. struct pcxhr_mgr *mgr = chip->mgr;
  928. snd_iprintf(buffer, "\n%s\n", mgr->longname);
  929. /* stats available when embedded DSP is running */
  930. if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
  931. struct pcxhr_rmh rmh;
  932. short ver_maj = (mgr->dsp_version >> 16) & 0xff;
  933. short ver_min = (mgr->dsp_version >> 8) & 0xff;
  934. short ver_build = mgr->dsp_version & 0xff;
  935. snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING);
  936. snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build);
  937. if (mgr->board_has_analog)
  938. snd_iprintf(buffer, "analog io available\n");
  939. else
  940. snd_iprintf(buffer, "digital only board\n");
  941. /* calc cpu load of the dsp */
  942. pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
  943. if( ! pcxhr_send_msg(mgr, &rmh) ) {
  944. int cur = rmh.stat[0];
  945. int ref = rmh.stat[1];
  946. if (ref > 0) {
  947. if (mgr->sample_rate_real != 0 &&
  948. mgr->sample_rate_real != 48000) {
  949. ref = (ref * 48000) / mgr->sample_rate_real;
  950. if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ)
  951. ref *= 2;
  952. }
  953. cur = 100 - (100 * cur) / ref;
  954. snd_iprintf(buffer, "cpu load %d%%\n", cur);
  955. snd_iprintf(buffer, "buffer pool %d/%d kWords\n",
  956. rmh.stat[2], rmh.stat[3]);
  957. }
  958. }
  959. snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY);
  960. snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err);
  961. snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
  962. mgr->async_err_pipe_xrun);
  963. snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
  964. mgr->async_err_stream_xrun);
  965. snd_iprintf(buffer, "dsp async last other error : %x\n",
  966. mgr->async_err_other_last);
  967. /* debug zone dsp */
  968. rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
  969. rmh.cmd_len = 1;
  970. rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
  971. rmh.dsp_stat = 0;
  972. rmh.cmd_idx = CMD_LAST_INDEX;
  973. if( ! pcxhr_send_msg(mgr, &rmh) ) {
  974. int i;
  975. for (i = 0; i < rmh.stat_len; i++)
  976. snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]);
  977. }
  978. } else
  979. snd_iprintf(buffer, "no firmware loaded\n");
  980. snd_iprintf(buffer, "\n");
  981. }
  982. static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  983. {
  984. struct snd_pcxhr *chip = entry->private_data;
  985. struct pcxhr_mgr *mgr = chip->mgr;
  986. static char *texts[7] = {
  987. "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4"
  988. };
  989. snd_iprintf(buffer, "\n%s\n", mgr->longname);
  990. snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]);
  991. snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real);
  992. /* commands available when embedded DSP is running */
  993. if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
  994. int i, err, sample_rate;
  995. for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) {
  996. err = pcxhr_get_external_clock(mgr, i, &sample_rate);
  997. if (err)
  998. break;
  999. snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate);
  1000. }
  1001. } else
  1002. snd_iprintf(buffer, "no firmware loaded\n");
  1003. snd_iprintf(buffer, "\n");
  1004. }
  1005. static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
  1006. {
  1007. struct snd_info_entry *entry;
  1008. if (! snd_card_proc_new(chip->card, "info", &entry))
  1009. snd_info_set_text_ops(entry, chip, pcxhr_proc_info);
  1010. if (! snd_card_proc_new(chip->card, "sync", &entry))
  1011. snd_info_set_text_ops(entry, chip, pcxhr_proc_sync);
  1012. }
  1013. /* end of proc interface */
  1014. /*
  1015. * release all the cards assigned to a manager instance
  1016. */
  1017. static int pcxhr_free(struct pcxhr_mgr *mgr)
  1018. {
  1019. unsigned int i;
  1020. for (i = 0; i < mgr->num_cards; i++) {
  1021. if (mgr->chip[i])
  1022. snd_card_free(mgr->chip[i]->card);
  1023. }
  1024. /* reset board if some firmware was loaded */
  1025. if(mgr->dsp_loaded) {
  1026. pcxhr_reset_board(mgr);
  1027. snd_printdd("reset pcxhr !\n");
  1028. }
  1029. /* release irq */
  1030. if (mgr->irq >= 0)
  1031. free_irq(mgr->irq, mgr);
  1032. pci_release_regions(mgr->pci);
  1033. /* free hostport purgebuffer */
  1034. if (mgr->hostport.area) {
  1035. snd_dma_free_pages(&mgr->hostport);
  1036. mgr->hostport.area = NULL;
  1037. }
  1038. kfree(mgr->prmh);
  1039. pci_disable_device(mgr->pci);
  1040. kfree(mgr);
  1041. return 0;
  1042. }
  1043. /*
  1044. * probe function - creates the card manager
  1045. */
  1046. static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1047. {
  1048. static int dev;
  1049. struct pcxhr_mgr *mgr;
  1050. unsigned int i;
  1051. int err;
  1052. size_t size;
  1053. char *card_name;
  1054. if (dev >= SNDRV_CARDS)
  1055. return -ENODEV;
  1056. if (! enable[dev]) {
  1057. dev++;
  1058. return -ENOENT;
  1059. }
  1060. /* enable PCI device */
  1061. if ((err = pci_enable_device(pci)) < 0)
  1062. return err;
  1063. pci_set_master(pci);
  1064. /* check if we can restrict PCI DMA transfers to 32 bits */
  1065. if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) {
  1066. snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n");
  1067. pci_disable_device(pci);
  1068. return -ENXIO;
  1069. }
  1070. /* alloc card manager */
  1071. mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
  1072. if (! mgr) {
  1073. pci_disable_device(pci);
  1074. return -ENOMEM;
  1075. }
  1076. if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) {
  1077. kfree(mgr);
  1078. pci_disable_device(pci);
  1079. return -ENODEV;
  1080. }
  1081. card_name = pcxhr_board_params[pci_id->driver_data].board_name;
  1082. mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips;
  1083. mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips;
  1084. mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num;
  1085. mgr->mono_capture = mono[dev];
  1086. /* resource assignment */
  1087. if ((err = pci_request_regions(pci, card_name)) < 0) {
  1088. kfree(mgr);
  1089. pci_disable_device(pci);
  1090. return err;
  1091. }
  1092. for (i = 0; i < 3; i++)
  1093. mgr->port[i] = pci_resource_start(pci, i);
  1094. mgr->pci = pci;
  1095. mgr->irq = -1;
  1096. if (request_irq(pci->irq, pcxhr_interrupt, IRQF_SHARED,
  1097. card_name, mgr)) {
  1098. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1099. pcxhr_free(mgr);
  1100. return -EBUSY;
  1101. }
  1102. mgr->irq = pci->irq;
  1103. sprintf(mgr->shortname, "Digigram %s", card_name);
  1104. sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname,
  1105. mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
  1106. /* ISR spinlock */
  1107. spin_lock_init(&mgr->lock);
  1108. spin_lock_init(&mgr->msg_lock);
  1109. /* init setup mutex*/
  1110. mutex_init(&mgr->setup_mutex);
  1111. /* init taslket */
  1112. tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr);
  1113. tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr);
  1114. mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
  1115. sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS),
  1116. GFP_KERNEL);
  1117. if (! mgr->prmh) {
  1118. pcxhr_free(mgr);
  1119. return -ENOMEM;
  1120. }
  1121. for (i=0; i < PCXHR_MAX_CARDS; i++) {
  1122. struct snd_card *card;
  1123. char tmpid[16];
  1124. int idx;
  1125. if (i >= max(mgr->playback_chips, mgr->capture_chips))
  1126. break;
  1127. mgr->num_cards++;
  1128. if (index[dev] < 0)
  1129. idx = index[dev];
  1130. else
  1131. idx = index[dev] + i;
  1132. snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i);
  1133. card = snd_card_new(idx, tmpid, THIS_MODULE, 0);
  1134. if (! card) {
  1135. snd_printk(KERN_ERR "cannot allocate the card %d\n", i);
  1136. pcxhr_free(mgr);
  1137. return -ENOMEM;
  1138. }
  1139. strcpy(card->driver, DRIVER_NAME);
  1140. sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
  1141. sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
  1142. if ((err = pcxhr_create(mgr, card, i)) < 0) {
  1143. snd_card_free(card);
  1144. pcxhr_free(mgr);
  1145. return err;
  1146. }
  1147. if (i == 0)
  1148. /* init proc interface only for chip0 */
  1149. pcxhr_proc_init(mgr->chip[i]);
  1150. if ((err = snd_card_register(card)) < 0) {
  1151. pcxhr_free(mgr);
  1152. return err;
  1153. }
  1154. }
  1155. /* create hostport purgebuffer */
  1156. size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
  1157. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
  1158. size, &mgr->hostport) < 0) {
  1159. pcxhr_free(mgr);
  1160. return -ENOMEM;
  1161. }
  1162. /* init purgebuffer */
  1163. memset(mgr->hostport.area, 0, size);
  1164. /* create a DSP loader */
  1165. err = pcxhr_setup_firmware(mgr);
  1166. if (err < 0) {
  1167. pcxhr_free(mgr);
  1168. return err;
  1169. }
  1170. pci_set_drvdata(pci, mgr);
  1171. dev++;
  1172. return 0;
  1173. }
  1174. static void __devexit pcxhr_remove(struct pci_dev *pci)
  1175. {
  1176. pcxhr_free(pci_get_drvdata(pci));
  1177. pci_set_drvdata(pci, NULL);
  1178. }
  1179. static struct pci_driver driver = {
  1180. .name = "Digigram pcxhr",
  1181. .id_table = pcxhr_ids,
  1182. .probe = pcxhr_probe,
  1183. .remove = __devexit_p(pcxhr_remove),
  1184. };
  1185. static int __init pcxhr_module_init(void)
  1186. {
  1187. return pci_register_driver(&driver);
  1188. }
  1189. static void __exit pcxhr_module_exit(void)
  1190. {
  1191. pci_unregister_driver(&driver);
  1192. }
  1193. module_init(pcxhr_module_init)
  1194. module_exit(pcxhr_module_exit)