qla_isr.c 82 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. #include "qla_target.h"
  15. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  16. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  17. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  18. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  19. sts_entry_t *);
  20. /**
  21. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  22. * @irq:
  23. * @dev_id: SCSI driver HA context
  24. *
  25. * Called by system whenever the host adapter generates an interrupt.
  26. *
  27. * Returns handled flag.
  28. */
  29. irqreturn_t
  30. qla2100_intr_handler(int irq, void *dev_id)
  31. {
  32. scsi_qla_host_t *vha;
  33. struct qla_hw_data *ha;
  34. struct device_reg_2xxx __iomem *reg;
  35. int status;
  36. unsigned long iter;
  37. uint16_t hccr;
  38. uint16_t mb[4];
  39. struct rsp_que *rsp;
  40. unsigned long flags;
  41. rsp = (struct rsp_que *) dev_id;
  42. if (!rsp) {
  43. ql_log(ql_log_info, NULL, 0x505d,
  44. "%s: NULL response queue pointer.\n", __func__);
  45. return (IRQ_NONE);
  46. }
  47. ha = rsp->hw;
  48. reg = &ha->iobase->isp;
  49. status = 0;
  50. spin_lock_irqsave(&ha->hardware_lock, flags);
  51. vha = pci_get_drvdata(ha->pdev);
  52. for (iter = 50; iter--; ) {
  53. hccr = RD_REG_WORD(&reg->hccr);
  54. if (hccr & HCCR_RISC_PAUSE) {
  55. if (pci_channel_offline(ha->pdev))
  56. break;
  57. /*
  58. * Issue a "HARD" reset in order for the RISC interrupt
  59. * bit to be cleared. Schedule a big hammer to get
  60. * out of the RISC PAUSED state.
  61. */
  62. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  63. RD_REG_WORD(&reg->hccr);
  64. ha->isp_ops->fw_dump(vha, 1);
  65. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  66. break;
  67. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  68. break;
  69. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  70. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  71. RD_REG_WORD(&reg->hccr);
  72. /* Get mailbox data. */
  73. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  74. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  75. qla2x00_mbx_completion(vha, mb[0]);
  76. status |= MBX_INTERRUPT;
  77. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  78. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  79. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  80. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  81. qla2x00_async_event(vha, rsp, mb);
  82. } else {
  83. /*EMPTY*/
  84. ql_dbg(ql_dbg_async, vha, 0x5025,
  85. "Unrecognized interrupt type (%d).\n",
  86. mb[0]);
  87. }
  88. /* Release mailbox registers. */
  89. WRT_REG_WORD(&reg->semaphore, 0);
  90. RD_REG_WORD(&reg->semaphore);
  91. } else {
  92. qla2x00_process_response_queue(rsp);
  93. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  94. RD_REG_WORD(&reg->hccr);
  95. }
  96. }
  97. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  98. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  99. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  100. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  101. complete(&ha->mbx_intr_comp);
  102. }
  103. return (IRQ_HANDLED);
  104. }
  105. /**
  106. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  107. * @irq:
  108. * @dev_id: SCSI driver HA context
  109. *
  110. * Called by system whenever the host adapter generates an interrupt.
  111. *
  112. * Returns handled flag.
  113. */
  114. irqreturn_t
  115. qla2300_intr_handler(int irq, void *dev_id)
  116. {
  117. scsi_qla_host_t *vha;
  118. struct device_reg_2xxx __iomem *reg;
  119. int status;
  120. unsigned long iter;
  121. uint32_t stat;
  122. uint16_t hccr;
  123. uint16_t mb[4];
  124. struct rsp_que *rsp;
  125. struct qla_hw_data *ha;
  126. unsigned long flags;
  127. rsp = (struct rsp_que *) dev_id;
  128. if (!rsp) {
  129. ql_log(ql_log_info, NULL, 0x5058,
  130. "%s: NULL response queue pointer.\n", __func__);
  131. return (IRQ_NONE);
  132. }
  133. ha = rsp->hw;
  134. reg = &ha->iobase->isp;
  135. status = 0;
  136. spin_lock_irqsave(&ha->hardware_lock, flags);
  137. vha = pci_get_drvdata(ha->pdev);
  138. for (iter = 50; iter--; ) {
  139. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  140. if (stat & HSR_RISC_PAUSED) {
  141. if (unlikely(pci_channel_offline(ha->pdev)))
  142. break;
  143. hccr = RD_REG_WORD(&reg->hccr);
  144. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  145. ql_log(ql_log_warn, vha, 0x5026,
  146. "Parity error -- HCCR=%x, Dumping "
  147. "firmware.\n", hccr);
  148. else
  149. ql_log(ql_log_warn, vha, 0x5027,
  150. "RISC paused -- HCCR=%x, Dumping "
  151. "firmware.\n", hccr);
  152. /*
  153. * Issue a "HARD" reset in order for the RISC
  154. * interrupt bit to be cleared. Schedule a big
  155. * hammer to get out of the RISC PAUSED state.
  156. */
  157. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  158. RD_REG_WORD(&reg->hccr);
  159. ha->isp_ops->fw_dump(vha, 1);
  160. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  161. break;
  162. } else if ((stat & HSR_RISC_INT) == 0)
  163. break;
  164. switch (stat & 0xff) {
  165. case 0x1:
  166. case 0x2:
  167. case 0x10:
  168. case 0x11:
  169. qla2x00_mbx_completion(vha, MSW(stat));
  170. status |= MBX_INTERRUPT;
  171. /* Release mailbox registers. */
  172. WRT_REG_WORD(&reg->semaphore, 0);
  173. break;
  174. case 0x12:
  175. mb[0] = MSW(stat);
  176. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  177. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  178. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  179. qla2x00_async_event(vha, rsp, mb);
  180. break;
  181. case 0x13:
  182. qla2x00_process_response_queue(rsp);
  183. break;
  184. case 0x15:
  185. mb[0] = MBA_CMPLT_1_16BIT;
  186. mb[1] = MSW(stat);
  187. qla2x00_async_event(vha, rsp, mb);
  188. break;
  189. case 0x16:
  190. mb[0] = MBA_SCSI_COMPLETION;
  191. mb[1] = MSW(stat);
  192. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  193. qla2x00_async_event(vha, rsp, mb);
  194. break;
  195. default:
  196. ql_dbg(ql_dbg_async, vha, 0x5028,
  197. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  198. break;
  199. }
  200. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  201. RD_REG_WORD_RELAXED(&reg->hccr);
  202. }
  203. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  204. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  205. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  206. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  207. complete(&ha->mbx_intr_comp);
  208. }
  209. return (IRQ_HANDLED);
  210. }
  211. /**
  212. * qla2x00_mbx_completion() - Process mailbox command completions.
  213. * @ha: SCSI driver HA context
  214. * @mb0: Mailbox0 register
  215. */
  216. static void
  217. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  218. {
  219. uint16_t cnt;
  220. uint32_t mboxes;
  221. uint16_t __iomem *wptr;
  222. struct qla_hw_data *ha = vha->hw;
  223. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  224. /* Read all mbox registers? */
  225. mboxes = (1 << ha->mbx_count) - 1;
  226. if (!ha->mcp)
  227. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  228. else
  229. mboxes = ha->mcp->in_mb;
  230. /* Load return mailbox registers. */
  231. ha->flags.mbox_int = 1;
  232. ha->mailbox_out[0] = mb0;
  233. mboxes >>= 1;
  234. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  235. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  236. if (IS_QLA2200(ha) && cnt == 8)
  237. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  238. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  239. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  240. else if (mboxes & BIT_0)
  241. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  242. wptr++;
  243. mboxes >>= 1;
  244. }
  245. }
  246. static void
  247. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  248. {
  249. static char *event[] =
  250. { "Complete", "Request Notification", "Time Extension" };
  251. int rval;
  252. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  253. uint16_t __iomem *wptr;
  254. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  255. /* Seed data -- mailbox1 -> mailbox7. */
  256. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  257. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  258. mb[cnt] = RD_REG_WORD(wptr);
  259. ql_dbg(ql_dbg_async, vha, 0x5021,
  260. "Inter-Driver Communication %s -- "
  261. "%04x %04x %04x %04x %04x %04x %04x.\n",
  262. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  263. mb[4], mb[5], mb[6]);
  264. if ((aen == MBA_IDC_COMPLETE && mb[1] >> 15)) {
  265. vha->hw->flags.idc_compl_status = 1;
  266. if (vha->hw->notify_dcbx_comp)
  267. complete(&vha->hw->dcbx_comp);
  268. }
  269. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  270. timeout = (descr >> 8) & 0xf;
  271. if (aen != MBA_IDC_NOTIFY || !timeout)
  272. return;
  273. ql_dbg(ql_dbg_async, vha, 0x5022,
  274. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  275. vha->host_no, event[aen & 0xff], timeout);
  276. rval = qla2x00_post_idc_ack_work(vha, mb);
  277. if (rval != QLA_SUCCESS)
  278. ql_log(ql_log_warn, vha, 0x5023,
  279. "IDC failed to post ACK.\n");
  280. }
  281. #define LS_UNKNOWN 2
  282. const char *
  283. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  284. {
  285. static const char * const link_speeds[] = {
  286. "1", "2", "?", "4", "8", "16", "10"
  287. };
  288. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  289. return link_speeds[0];
  290. else if (speed == 0x13)
  291. return link_speeds[6];
  292. else if (speed < 6)
  293. return link_speeds[speed];
  294. else
  295. return link_speeds[LS_UNKNOWN];
  296. }
  297. static void
  298. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  299. {
  300. struct qla_hw_data *ha = vha->hw;
  301. /*
  302. * 8200 AEN Interpretation:
  303. * mb[0] = AEN code
  304. * mb[1] = AEN Reason code
  305. * mb[2] = LSW of Peg-Halt Status-1 Register
  306. * mb[6] = MSW of Peg-Halt Status-1 Register
  307. * mb[3] = LSW of Peg-Halt Status-2 register
  308. * mb[7] = MSW of Peg-Halt Status-2 register
  309. * mb[4] = IDC Device-State Register value
  310. * mb[5] = IDC Driver-Presence Register value
  311. */
  312. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  313. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  314. mb[0], mb[1], mb[2], mb[6]);
  315. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  316. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  317. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  318. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  319. IDC_HEARTBEAT_FAILURE)) {
  320. ha->flags.nic_core_hung = 1;
  321. ql_log(ql_log_warn, vha, 0x5060,
  322. "83XX: F/W Error Reported: Check if reset required.\n");
  323. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  324. uint32_t protocol_engine_id, fw_err_code, err_level;
  325. /*
  326. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  327. * - PEG-Halt Status-1 Register:
  328. * (LSW = mb[2], MSW = mb[6])
  329. * Bits 0-7 = protocol-engine ID
  330. * Bits 8-28 = f/w error code
  331. * Bits 29-31 = Error-level
  332. * Error-level 0x1 = Non-Fatal error
  333. * Error-level 0x2 = Recoverable Fatal error
  334. * Error-level 0x4 = UnRecoverable Fatal error
  335. * - PEG-Halt Status-2 Register:
  336. * (LSW = mb[3], MSW = mb[7])
  337. */
  338. protocol_engine_id = (mb[2] & 0xff);
  339. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  340. ((mb[6] & 0x1fff) << 8));
  341. err_level = ((mb[6] & 0xe000) >> 13);
  342. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  343. "Register: protocol_engine_id=0x%x "
  344. "fw_err_code=0x%x err_level=0x%x.\n",
  345. protocol_engine_id, fw_err_code, err_level);
  346. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  347. "Register: 0x%x%x.\n", mb[7], mb[3]);
  348. if (err_level == ERR_LEVEL_NON_FATAL) {
  349. ql_log(ql_log_warn, vha, 0x5063,
  350. "Not a fatal error, f/w has recovered "
  351. "iteself.\n");
  352. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  353. ql_log(ql_log_fatal, vha, 0x5064,
  354. "Recoverable Fatal error: Chip reset "
  355. "required.\n");
  356. qla83xx_schedule_work(vha,
  357. QLA83XX_NIC_CORE_RESET);
  358. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  359. ql_log(ql_log_fatal, vha, 0x5065,
  360. "Unrecoverable Fatal error: Set FAILED "
  361. "state, reboot required.\n");
  362. qla83xx_schedule_work(vha,
  363. QLA83XX_NIC_CORE_UNRECOVERABLE);
  364. }
  365. }
  366. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  367. uint16_t peg_fw_state, nw_interface_link_up;
  368. uint16_t nw_interface_signal_detect, sfp_status;
  369. uint16_t htbt_counter, htbt_monitor_enable;
  370. uint16_t sfp_additonal_info, sfp_multirate;
  371. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  372. /*
  373. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  374. * - PEG-to-FC Status Register:
  375. * (LSW = mb[2], MSW = mb[6])
  376. * Bits 0-7 = Peg-Firmware state
  377. * Bit 8 = N/W Interface Link-up
  378. * Bit 9 = N/W Interface signal detected
  379. * Bits 10-11 = SFP Status
  380. * SFP Status 0x0 = SFP+ transceiver not expected
  381. * SFP Status 0x1 = SFP+ transceiver not present
  382. * SFP Status 0x2 = SFP+ transceiver invalid
  383. * SFP Status 0x3 = SFP+ transceiver present and
  384. * valid
  385. * Bits 12-14 = Heartbeat Counter
  386. * Bit 15 = Heartbeat Monitor Enable
  387. * Bits 16-17 = SFP Additional Info
  388. * SFP info 0x0 = Unregocnized transceiver for
  389. * Ethernet
  390. * SFP info 0x1 = SFP+ brand validation failed
  391. * SFP info 0x2 = SFP+ speed validation failed
  392. * SFP info 0x3 = SFP+ access error
  393. * Bit 18 = SFP Multirate
  394. * Bit 19 = SFP Tx Fault
  395. * Bits 20-22 = Link Speed
  396. * Bits 23-27 = Reserved
  397. * Bits 28-30 = DCBX Status
  398. * DCBX Status 0x0 = DCBX Disabled
  399. * DCBX Status 0x1 = DCBX Enabled
  400. * DCBX Status 0x2 = DCBX Exchange error
  401. * Bit 31 = Reserved
  402. */
  403. peg_fw_state = (mb[2] & 0x00ff);
  404. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  405. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  406. sfp_status = ((mb[2] & 0x0c00) >> 10);
  407. htbt_counter = ((mb[2] & 0x7000) >> 12);
  408. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  409. sfp_additonal_info = (mb[6] & 0x0003);
  410. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  411. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  412. link_speed = ((mb[6] & 0x0070) >> 4);
  413. dcbx_status = ((mb[6] & 0x7000) >> 12);
  414. ql_log(ql_log_warn, vha, 0x5066,
  415. "Peg-to-Fc Status Register:\n"
  416. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  417. "nw_interface_signal_detect=0x%x"
  418. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  419. nw_interface_link_up, nw_interface_signal_detect,
  420. sfp_status);
  421. ql_log(ql_log_warn, vha, 0x5067,
  422. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  423. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  424. htbt_counter, htbt_monitor_enable,
  425. sfp_additonal_info, sfp_multirate);
  426. ql_log(ql_log_warn, vha, 0x5068,
  427. "sfp_tx_fault=0x%x, link_state=0x%x, "
  428. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  429. dcbx_status);
  430. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  431. }
  432. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  433. ql_log(ql_log_warn, vha, 0x5069,
  434. "Heartbeat Failure encountered, chip reset "
  435. "required.\n");
  436. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  437. }
  438. }
  439. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  440. ql_log(ql_log_info, vha, 0x506a,
  441. "IDC Device-State changed = 0x%x.\n", mb[4]);
  442. if (ha->flags.nic_core_reset_owner)
  443. return;
  444. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  445. }
  446. }
  447. int
  448. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  449. {
  450. struct qla_hw_data *ha = vha->hw;
  451. scsi_qla_host_t *vp;
  452. uint32_t vp_did;
  453. unsigned long flags;
  454. int ret = 0;
  455. if (!ha->num_vhosts)
  456. return ret;
  457. spin_lock_irqsave(&ha->vport_slock, flags);
  458. list_for_each_entry(vp, &ha->vp_list, list) {
  459. vp_did = vp->d_id.b24;
  460. if (vp_did == rscn_entry) {
  461. ret = 1;
  462. break;
  463. }
  464. }
  465. spin_unlock_irqrestore(&ha->vport_slock, flags);
  466. return ret;
  467. }
  468. /**
  469. * qla2x00_async_event() - Process aynchronous events.
  470. * @ha: SCSI driver HA context
  471. * @mb: Mailbox registers (0 - 3)
  472. */
  473. void
  474. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  475. {
  476. uint16_t handle_cnt;
  477. uint16_t cnt, mbx;
  478. uint32_t handles[5];
  479. struct qla_hw_data *ha = vha->hw;
  480. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  481. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  482. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  483. uint32_t rscn_entry, host_pid;
  484. unsigned long flags;
  485. /* Setup to process RIO completion. */
  486. handle_cnt = 0;
  487. if (IS_CNA_CAPABLE(ha))
  488. goto skip_rio;
  489. switch (mb[0]) {
  490. case MBA_SCSI_COMPLETION:
  491. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  492. handle_cnt = 1;
  493. break;
  494. case MBA_CMPLT_1_16BIT:
  495. handles[0] = mb[1];
  496. handle_cnt = 1;
  497. mb[0] = MBA_SCSI_COMPLETION;
  498. break;
  499. case MBA_CMPLT_2_16BIT:
  500. handles[0] = mb[1];
  501. handles[1] = mb[2];
  502. handle_cnt = 2;
  503. mb[0] = MBA_SCSI_COMPLETION;
  504. break;
  505. case MBA_CMPLT_3_16BIT:
  506. handles[0] = mb[1];
  507. handles[1] = mb[2];
  508. handles[2] = mb[3];
  509. handle_cnt = 3;
  510. mb[0] = MBA_SCSI_COMPLETION;
  511. break;
  512. case MBA_CMPLT_4_16BIT:
  513. handles[0] = mb[1];
  514. handles[1] = mb[2];
  515. handles[2] = mb[3];
  516. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  517. handle_cnt = 4;
  518. mb[0] = MBA_SCSI_COMPLETION;
  519. break;
  520. case MBA_CMPLT_5_16BIT:
  521. handles[0] = mb[1];
  522. handles[1] = mb[2];
  523. handles[2] = mb[3];
  524. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  525. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  526. handle_cnt = 5;
  527. mb[0] = MBA_SCSI_COMPLETION;
  528. break;
  529. case MBA_CMPLT_2_32BIT:
  530. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  531. handles[1] = le32_to_cpu(
  532. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  533. RD_MAILBOX_REG(ha, reg, 6));
  534. handle_cnt = 2;
  535. mb[0] = MBA_SCSI_COMPLETION;
  536. break;
  537. default:
  538. break;
  539. }
  540. skip_rio:
  541. switch (mb[0]) {
  542. case MBA_SCSI_COMPLETION: /* Fast Post */
  543. if (!vha->flags.online)
  544. break;
  545. for (cnt = 0; cnt < handle_cnt; cnt++)
  546. qla2x00_process_completed_request(vha, rsp->req,
  547. handles[cnt]);
  548. break;
  549. case MBA_RESET: /* Reset */
  550. ql_dbg(ql_dbg_async, vha, 0x5002,
  551. "Asynchronous RESET.\n");
  552. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  553. break;
  554. case MBA_SYSTEM_ERR: /* System Error */
  555. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  556. RD_REG_WORD(&reg24->mailbox7) : 0;
  557. ql_log(ql_log_warn, vha, 0x5003,
  558. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  559. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  560. ha->isp_ops->fw_dump(vha, 1);
  561. if (IS_FWI2_CAPABLE(ha)) {
  562. if (mb[1] == 0 && mb[2] == 0) {
  563. ql_log(ql_log_fatal, vha, 0x5004,
  564. "Unrecoverable Hardware Error: adapter "
  565. "marked OFFLINE!\n");
  566. vha->flags.online = 0;
  567. vha->device_flags |= DFLG_DEV_FAILED;
  568. } else {
  569. /* Check to see if MPI timeout occurred */
  570. if ((mbx & MBX_3) && (ha->flags.port0))
  571. set_bit(MPI_RESET_NEEDED,
  572. &vha->dpc_flags);
  573. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  574. }
  575. } else if (mb[1] == 0) {
  576. ql_log(ql_log_fatal, vha, 0x5005,
  577. "Unrecoverable Hardware Error: adapter marked "
  578. "OFFLINE!\n");
  579. vha->flags.online = 0;
  580. vha->device_flags |= DFLG_DEV_FAILED;
  581. } else
  582. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  583. break;
  584. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  585. ql_log(ql_log_warn, vha, 0x5006,
  586. "ISP Request Transfer Error (%x).\n", mb[1]);
  587. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  588. break;
  589. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  590. ql_log(ql_log_warn, vha, 0x5007,
  591. "ISP Response Transfer Error.\n");
  592. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  593. break;
  594. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  595. ql_dbg(ql_dbg_async, vha, 0x5008,
  596. "Asynchronous WAKEUP_THRES.\n");
  597. break;
  598. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  599. ql_dbg(ql_dbg_async, vha, 0x5009,
  600. "LIP occurred (%x).\n", mb[1]);
  601. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  602. atomic_set(&vha->loop_state, LOOP_DOWN);
  603. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  604. qla2x00_mark_all_devices_lost(vha, 1);
  605. }
  606. if (vha->vp_idx) {
  607. atomic_set(&vha->vp_state, VP_FAILED);
  608. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  609. }
  610. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  611. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  612. vha->flags.management_server_logged_in = 0;
  613. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  614. break;
  615. case MBA_LOOP_UP: /* Loop Up Event */
  616. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  617. ha->link_data_rate = PORT_SPEED_1GB;
  618. else
  619. ha->link_data_rate = mb[1];
  620. ql_dbg(ql_dbg_async, vha, 0x500a,
  621. "LOOP UP detected (%s Gbps).\n",
  622. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  623. vha->flags.management_server_logged_in = 0;
  624. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  625. break;
  626. case MBA_LOOP_DOWN: /* Loop Down Event */
  627. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  628. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  629. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  630. ql_dbg(ql_dbg_async, vha, 0x500b,
  631. "LOOP DOWN detected (%x %x %x %x).\n",
  632. mb[1], mb[2], mb[3], mbx);
  633. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  634. atomic_set(&vha->loop_state, LOOP_DOWN);
  635. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  636. vha->device_flags |= DFLG_NO_CABLE;
  637. qla2x00_mark_all_devices_lost(vha, 1);
  638. }
  639. if (vha->vp_idx) {
  640. atomic_set(&vha->vp_state, VP_FAILED);
  641. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  642. }
  643. vha->flags.management_server_logged_in = 0;
  644. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  645. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  646. break;
  647. case MBA_LIP_RESET: /* LIP reset occurred */
  648. ql_dbg(ql_dbg_async, vha, 0x500c,
  649. "LIP reset occurred (%x).\n", mb[1]);
  650. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  651. atomic_set(&vha->loop_state, LOOP_DOWN);
  652. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  653. qla2x00_mark_all_devices_lost(vha, 1);
  654. }
  655. if (vha->vp_idx) {
  656. atomic_set(&vha->vp_state, VP_FAILED);
  657. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  658. }
  659. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  660. ha->operating_mode = LOOP;
  661. vha->flags.management_server_logged_in = 0;
  662. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  663. break;
  664. /* case MBA_DCBX_COMPLETE: */
  665. case MBA_POINT_TO_POINT: /* Point-to-Point */
  666. if (IS_QLA2100(ha))
  667. break;
  668. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  669. ql_dbg(ql_dbg_async, vha, 0x500d,
  670. "DCBX Completed -- %04x %04x %04x.\n",
  671. mb[1], mb[2], mb[3]);
  672. if (ha->notify_dcbx_comp)
  673. complete(&ha->dcbx_comp);
  674. } else
  675. ql_dbg(ql_dbg_async, vha, 0x500e,
  676. "Asynchronous P2P MODE received.\n");
  677. /*
  678. * Until there's a transition from loop down to loop up, treat
  679. * this as loop down only.
  680. */
  681. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  682. atomic_set(&vha->loop_state, LOOP_DOWN);
  683. if (!atomic_read(&vha->loop_down_timer))
  684. atomic_set(&vha->loop_down_timer,
  685. LOOP_DOWN_TIME);
  686. qla2x00_mark_all_devices_lost(vha, 1);
  687. }
  688. if (vha->vp_idx) {
  689. atomic_set(&vha->vp_state, VP_FAILED);
  690. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  691. }
  692. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  693. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  694. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  695. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  696. ha->flags.gpsc_supported = 1;
  697. vha->flags.management_server_logged_in = 0;
  698. break;
  699. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  700. if (IS_QLA2100(ha))
  701. break;
  702. ql_dbg(ql_dbg_async, vha, 0x500f,
  703. "Configuration change detected: value=%x.\n", mb[1]);
  704. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  705. atomic_set(&vha->loop_state, LOOP_DOWN);
  706. if (!atomic_read(&vha->loop_down_timer))
  707. atomic_set(&vha->loop_down_timer,
  708. LOOP_DOWN_TIME);
  709. qla2x00_mark_all_devices_lost(vha, 1);
  710. }
  711. if (vha->vp_idx) {
  712. atomic_set(&vha->vp_state, VP_FAILED);
  713. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  714. }
  715. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  716. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  717. break;
  718. case MBA_PORT_UPDATE: /* Port database update */
  719. /*
  720. * Handle only global and vn-port update events
  721. *
  722. * Relevant inputs:
  723. * mb[1] = N_Port handle of changed port
  724. * OR 0xffff for global event
  725. * mb[2] = New login state
  726. * 7 = Port logged out
  727. * mb[3] = LSB is vp_idx, 0xff = all vps
  728. *
  729. * Skip processing if:
  730. * Event is global, vp_idx is NOT all vps,
  731. * vp_idx does not match
  732. * Event is not global, vp_idx does not match
  733. */
  734. if (IS_QLA2XXX_MIDTYPE(ha) &&
  735. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  736. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  737. break;
  738. /* Global event -- port logout or port unavailable. */
  739. if (mb[1] == 0xffff && mb[2] == 0x7) {
  740. ql_dbg(ql_dbg_async, vha, 0x5010,
  741. "Port unavailable %04x %04x %04x.\n",
  742. mb[1], mb[2], mb[3]);
  743. ql_log(ql_log_warn, vha, 0x505e,
  744. "Link is offline.\n");
  745. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  746. atomic_set(&vha->loop_state, LOOP_DOWN);
  747. atomic_set(&vha->loop_down_timer,
  748. LOOP_DOWN_TIME);
  749. vha->device_flags |= DFLG_NO_CABLE;
  750. qla2x00_mark_all_devices_lost(vha, 1);
  751. }
  752. if (vha->vp_idx) {
  753. atomic_set(&vha->vp_state, VP_FAILED);
  754. fc_vport_set_state(vha->fc_vport,
  755. FC_VPORT_FAILED);
  756. qla2x00_mark_all_devices_lost(vha, 1);
  757. }
  758. vha->flags.management_server_logged_in = 0;
  759. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  760. break;
  761. }
  762. /*
  763. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  764. * event etc. earlier indicating loop is down) then process
  765. * it. Otherwise ignore it and Wait for RSCN to come in.
  766. */
  767. atomic_set(&vha->loop_down_timer, 0);
  768. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  769. ql_dbg(ql_dbg_async, vha, 0x5011,
  770. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  771. mb[1], mb[2], mb[3]);
  772. qlt_async_event(mb[0], vha, mb);
  773. break;
  774. }
  775. ql_dbg(ql_dbg_async, vha, 0x5012,
  776. "Port database changed %04x %04x %04x.\n",
  777. mb[1], mb[2], mb[3]);
  778. ql_log(ql_log_warn, vha, 0x505f,
  779. "Link is operational (%s Gbps).\n",
  780. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  781. /*
  782. * Mark all devices as missing so we will login again.
  783. */
  784. atomic_set(&vha->loop_state, LOOP_UP);
  785. qla2x00_mark_all_devices_lost(vha, 1);
  786. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  787. set_bit(SCR_PENDING, &vha->dpc_flags);
  788. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  789. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  790. qlt_async_event(mb[0], vha, mb);
  791. break;
  792. case MBA_RSCN_UPDATE: /* State Change Registration */
  793. /* Check if the Vport has issued a SCR */
  794. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  795. break;
  796. /* Only handle SCNs for our Vport index. */
  797. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  798. break;
  799. ql_dbg(ql_dbg_async, vha, 0x5013,
  800. "RSCN database changed -- %04x %04x %04x.\n",
  801. mb[1], mb[2], mb[3]);
  802. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  803. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  804. | vha->d_id.b.al_pa;
  805. if (rscn_entry == host_pid) {
  806. ql_dbg(ql_dbg_async, vha, 0x5014,
  807. "Ignoring RSCN update to local host "
  808. "port ID (%06x).\n", host_pid);
  809. break;
  810. }
  811. /* Ignore reserved bits from RSCN-payload. */
  812. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  813. /* Skip RSCNs for virtual ports on the same physical port */
  814. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  815. break;
  816. atomic_set(&vha->loop_down_timer, 0);
  817. vha->flags.management_server_logged_in = 0;
  818. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  819. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  820. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  821. break;
  822. /* case MBA_RIO_RESPONSE: */
  823. case MBA_ZIO_RESPONSE:
  824. ql_dbg(ql_dbg_async, vha, 0x5015,
  825. "[R|Z]IO update completion.\n");
  826. if (IS_FWI2_CAPABLE(ha))
  827. qla24xx_process_response_queue(vha, rsp);
  828. else
  829. qla2x00_process_response_queue(rsp);
  830. break;
  831. case MBA_DISCARD_RND_FRAME:
  832. ql_dbg(ql_dbg_async, vha, 0x5016,
  833. "Discard RND Frame -- %04x %04x %04x.\n",
  834. mb[1], mb[2], mb[3]);
  835. break;
  836. case MBA_TRACE_NOTIFICATION:
  837. ql_dbg(ql_dbg_async, vha, 0x5017,
  838. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  839. break;
  840. case MBA_ISP84XX_ALERT:
  841. ql_dbg(ql_dbg_async, vha, 0x5018,
  842. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  843. mb[1], mb[2], mb[3]);
  844. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  845. switch (mb[1]) {
  846. case A84_PANIC_RECOVERY:
  847. ql_log(ql_log_info, vha, 0x5019,
  848. "Alert 84XX: panic recovery %04x %04x.\n",
  849. mb[2], mb[3]);
  850. break;
  851. case A84_OP_LOGIN_COMPLETE:
  852. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  853. ql_log(ql_log_info, vha, 0x501a,
  854. "Alert 84XX: firmware version %x.\n",
  855. ha->cs84xx->op_fw_version);
  856. break;
  857. case A84_DIAG_LOGIN_COMPLETE:
  858. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  859. ql_log(ql_log_info, vha, 0x501b,
  860. "Alert 84XX: diagnostic firmware version %x.\n",
  861. ha->cs84xx->diag_fw_version);
  862. break;
  863. case A84_GOLD_LOGIN_COMPLETE:
  864. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  865. ha->cs84xx->fw_update = 1;
  866. ql_log(ql_log_info, vha, 0x501c,
  867. "Alert 84XX: gold firmware version %x.\n",
  868. ha->cs84xx->gold_fw_version);
  869. break;
  870. default:
  871. ql_log(ql_log_warn, vha, 0x501d,
  872. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  873. mb[1], mb[2], mb[3]);
  874. }
  875. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  876. break;
  877. case MBA_DCBX_START:
  878. ql_dbg(ql_dbg_async, vha, 0x501e,
  879. "DCBX Started -- %04x %04x %04x.\n",
  880. mb[1], mb[2], mb[3]);
  881. break;
  882. case MBA_DCBX_PARAM_UPDATE:
  883. ql_dbg(ql_dbg_async, vha, 0x501f,
  884. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  885. mb[1], mb[2], mb[3]);
  886. break;
  887. case MBA_FCF_CONF_ERR:
  888. ql_dbg(ql_dbg_async, vha, 0x5020,
  889. "FCF Configuration Error -- %04x %04x %04x.\n",
  890. mb[1], mb[2], mb[3]);
  891. break;
  892. case MBA_IDC_NOTIFY:
  893. if (IS_QLA8031(vha->hw)) {
  894. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  895. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  896. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  897. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  898. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  899. /*
  900. * Extend loop down timer since port is active.
  901. */
  902. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  903. atomic_set(&vha->loop_down_timer,
  904. LOOP_DOWN_TIME);
  905. qla2xxx_wake_dpc(vha);
  906. }
  907. }
  908. case MBA_IDC_COMPLETE:
  909. if (ha->notify_lb_portup_comp)
  910. complete(&ha->lb_portup_comp);
  911. /* Fallthru */
  912. case MBA_IDC_TIME_EXT:
  913. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw))
  914. qla81xx_idc_event(vha, mb[0], mb[1]);
  915. break;
  916. case MBA_IDC_AEN:
  917. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  918. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  919. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  920. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  921. qla83xx_handle_8200_aen(vha, mb);
  922. break;
  923. default:
  924. ql_dbg(ql_dbg_async, vha, 0x5057,
  925. "Unknown AEN:%04x %04x %04x %04x\n",
  926. mb[0], mb[1], mb[2], mb[3]);
  927. }
  928. qlt_async_event(mb[0], vha, mb);
  929. if (!vha->vp_idx && ha->num_vhosts)
  930. qla2x00_alert_all_vps(rsp, mb);
  931. }
  932. /**
  933. * qla2x00_process_completed_request() - Process a Fast Post response.
  934. * @ha: SCSI driver HA context
  935. * @index: SRB index
  936. */
  937. void
  938. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  939. struct req_que *req, uint32_t index)
  940. {
  941. srb_t *sp;
  942. struct qla_hw_data *ha = vha->hw;
  943. /* Validate handle. */
  944. if (index >= req->num_outstanding_cmds) {
  945. ql_log(ql_log_warn, vha, 0x3014,
  946. "Invalid SCSI command index (%x).\n", index);
  947. if (IS_QLA82XX(ha))
  948. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  949. else
  950. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  951. return;
  952. }
  953. sp = req->outstanding_cmds[index];
  954. if (sp) {
  955. /* Free outstanding command slot. */
  956. req->outstanding_cmds[index] = NULL;
  957. /* Save ISP completion status */
  958. sp->done(ha, sp, DID_OK << 16);
  959. } else {
  960. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  961. if (IS_QLA82XX(ha))
  962. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  963. else
  964. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  965. }
  966. }
  967. srb_t *
  968. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  969. struct req_que *req, void *iocb)
  970. {
  971. struct qla_hw_data *ha = vha->hw;
  972. sts_entry_t *pkt = iocb;
  973. srb_t *sp = NULL;
  974. uint16_t index;
  975. index = LSW(pkt->handle);
  976. if (index >= req->num_outstanding_cmds) {
  977. ql_log(ql_log_warn, vha, 0x5031,
  978. "Invalid command index (%x).\n", index);
  979. if (IS_QLA82XX(ha))
  980. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  981. else
  982. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  983. goto done;
  984. }
  985. sp = req->outstanding_cmds[index];
  986. if (!sp) {
  987. ql_log(ql_log_warn, vha, 0x5032,
  988. "Invalid completion handle (%x) -- timed-out.\n", index);
  989. return sp;
  990. }
  991. if (sp->handle != index) {
  992. ql_log(ql_log_warn, vha, 0x5033,
  993. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  994. return NULL;
  995. }
  996. req->outstanding_cmds[index] = NULL;
  997. done:
  998. return sp;
  999. }
  1000. static void
  1001. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1002. struct mbx_entry *mbx)
  1003. {
  1004. const char func[] = "MBX-IOCB";
  1005. const char *type;
  1006. fc_port_t *fcport;
  1007. srb_t *sp;
  1008. struct srb_iocb *lio;
  1009. uint16_t *data;
  1010. uint16_t status;
  1011. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1012. if (!sp)
  1013. return;
  1014. lio = &sp->u.iocb_cmd;
  1015. type = sp->name;
  1016. fcport = sp->fcport;
  1017. data = lio->u.logio.data;
  1018. data[0] = MBS_COMMAND_ERROR;
  1019. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1020. QLA_LOGIO_LOGIN_RETRIED : 0;
  1021. if (mbx->entry_status) {
  1022. ql_dbg(ql_dbg_async, vha, 0x5043,
  1023. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1024. "entry-status=%x status=%x state-flag=%x "
  1025. "status-flags=%x.\n", type, sp->handle,
  1026. fcport->d_id.b.domain, fcport->d_id.b.area,
  1027. fcport->d_id.b.al_pa, mbx->entry_status,
  1028. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1029. le16_to_cpu(mbx->status_flags));
  1030. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1031. (uint8_t *)mbx, sizeof(*mbx));
  1032. goto logio_done;
  1033. }
  1034. status = le16_to_cpu(mbx->status);
  1035. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1036. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1037. status = 0;
  1038. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1039. ql_dbg(ql_dbg_async, vha, 0x5045,
  1040. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1041. type, sp->handle, fcport->d_id.b.domain,
  1042. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1043. le16_to_cpu(mbx->mb1));
  1044. data[0] = MBS_COMMAND_COMPLETE;
  1045. if (sp->type == SRB_LOGIN_CMD) {
  1046. fcport->port_type = FCT_TARGET;
  1047. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1048. fcport->port_type = FCT_INITIATOR;
  1049. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1050. fcport->flags |= FCF_FCP2_DEVICE;
  1051. }
  1052. goto logio_done;
  1053. }
  1054. data[0] = le16_to_cpu(mbx->mb0);
  1055. switch (data[0]) {
  1056. case MBS_PORT_ID_USED:
  1057. data[1] = le16_to_cpu(mbx->mb1);
  1058. break;
  1059. case MBS_LOOP_ID_USED:
  1060. break;
  1061. default:
  1062. data[0] = MBS_COMMAND_ERROR;
  1063. break;
  1064. }
  1065. ql_log(ql_log_warn, vha, 0x5046,
  1066. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1067. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1068. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1069. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1070. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1071. le16_to_cpu(mbx->mb7));
  1072. logio_done:
  1073. sp->done(vha, sp, 0);
  1074. }
  1075. static void
  1076. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1077. sts_entry_t *pkt, int iocb_type)
  1078. {
  1079. const char func[] = "CT_IOCB";
  1080. const char *type;
  1081. srb_t *sp;
  1082. struct fc_bsg_job *bsg_job;
  1083. uint16_t comp_status;
  1084. int res;
  1085. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1086. if (!sp)
  1087. return;
  1088. bsg_job = sp->u.bsg_job;
  1089. type = "ct pass-through";
  1090. comp_status = le16_to_cpu(pkt->comp_status);
  1091. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1092. * fc payload to the caller
  1093. */
  1094. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1095. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1096. if (comp_status != CS_COMPLETE) {
  1097. if (comp_status == CS_DATA_UNDERRUN) {
  1098. res = DID_OK << 16;
  1099. bsg_job->reply->reply_payload_rcv_len =
  1100. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1101. ql_log(ql_log_warn, vha, 0x5048,
  1102. "CT pass-through-%s error "
  1103. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1104. type, comp_status,
  1105. bsg_job->reply->reply_payload_rcv_len);
  1106. } else {
  1107. ql_log(ql_log_warn, vha, 0x5049,
  1108. "CT pass-through-%s error "
  1109. "comp_status-status=0x%x.\n", type, comp_status);
  1110. res = DID_ERROR << 16;
  1111. bsg_job->reply->reply_payload_rcv_len = 0;
  1112. }
  1113. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1114. (uint8_t *)pkt, sizeof(*pkt));
  1115. } else {
  1116. res = DID_OK << 16;
  1117. bsg_job->reply->reply_payload_rcv_len =
  1118. bsg_job->reply_payload.payload_len;
  1119. bsg_job->reply_len = 0;
  1120. }
  1121. sp->done(vha, sp, res);
  1122. }
  1123. static void
  1124. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1125. struct sts_entry_24xx *pkt, int iocb_type)
  1126. {
  1127. const char func[] = "ELS_CT_IOCB";
  1128. const char *type;
  1129. srb_t *sp;
  1130. struct fc_bsg_job *bsg_job;
  1131. uint16_t comp_status;
  1132. uint32_t fw_status[3];
  1133. uint8_t* fw_sts_ptr;
  1134. int res;
  1135. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1136. if (!sp)
  1137. return;
  1138. bsg_job = sp->u.bsg_job;
  1139. type = NULL;
  1140. switch (sp->type) {
  1141. case SRB_ELS_CMD_RPT:
  1142. case SRB_ELS_CMD_HST:
  1143. type = "els";
  1144. break;
  1145. case SRB_CT_CMD:
  1146. type = "ct pass-through";
  1147. break;
  1148. default:
  1149. ql_dbg(ql_dbg_user, vha, 0x503e,
  1150. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1151. return;
  1152. }
  1153. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1154. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1155. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1156. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1157. * fc payload to the caller
  1158. */
  1159. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1160. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1161. if (comp_status != CS_COMPLETE) {
  1162. if (comp_status == CS_DATA_UNDERRUN) {
  1163. res = DID_OK << 16;
  1164. bsg_job->reply->reply_payload_rcv_len =
  1165. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1166. ql_dbg(ql_dbg_user, vha, 0x503f,
  1167. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1168. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1169. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1170. le16_to_cpu(((struct els_sts_entry_24xx *)
  1171. pkt)->total_byte_count));
  1172. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1173. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1174. }
  1175. else {
  1176. ql_dbg(ql_dbg_user, vha, 0x5040,
  1177. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1178. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1179. type, sp->handle, comp_status,
  1180. le16_to_cpu(((struct els_sts_entry_24xx *)
  1181. pkt)->error_subcode_1),
  1182. le16_to_cpu(((struct els_sts_entry_24xx *)
  1183. pkt)->error_subcode_2));
  1184. res = DID_ERROR << 16;
  1185. bsg_job->reply->reply_payload_rcv_len = 0;
  1186. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1187. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1188. }
  1189. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1190. (uint8_t *)pkt, sizeof(*pkt));
  1191. }
  1192. else {
  1193. res = DID_OK << 16;
  1194. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1195. bsg_job->reply_len = 0;
  1196. }
  1197. sp->done(vha, sp, res);
  1198. }
  1199. static void
  1200. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1201. struct logio_entry_24xx *logio)
  1202. {
  1203. const char func[] = "LOGIO-IOCB";
  1204. const char *type;
  1205. fc_port_t *fcport;
  1206. srb_t *sp;
  1207. struct srb_iocb *lio;
  1208. uint16_t *data;
  1209. uint32_t iop[2];
  1210. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1211. if (!sp)
  1212. return;
  1213. lio = &sp->u.iocb_cmd;
  1214. type = sp->name;
  1215. fcport = sp->fcport;
  1216. data = lio->u.logio.data;
  1217. data[0] = MBS_COMMAND_ERROR;
  1218. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1219. QLA_LOGIO_LOGIN_RETRIED : 0;
  1220. if (logio->entry_status) {
  1221. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1222. "Async-%s error entry - hdl=%x"
  1223. "portid=%02x%02x%02x entry-status=%x.\n",
  1224. type, sp->handle, fcport->d_id.b.domain,
  1225. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1226. logio->entry_status);
  1227. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1228. (uint8_t *)logio, sizeof(*logio));
  1229. goto logio_done;
  1230. }
  1231. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1232. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1233. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1234. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1235. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1236. le32_to_cpu(logio->io_parameter[0]));
  1237. data[0] = MBS_COMMAND_COMPLETE;
  1238. if (sp->type != SRB_LOGIN_CMD)
  1239. goto logio_done;
  1240. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1241. if (iop[0] & BIT_4) {
  1242. fcport->port_type = FCT_TARGET;
  1243. if (iop[0] & BIT_8)
  1244. fcport->flags |= FCF_FCP2_DEVICE;
  1245. } else if (iop[0] & BIT_5)
  1246. fcport->port_type = FCT_INITIATOR;
  1247. if (iop[0] & BIT_7)
  1248. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1249. if (logio->io_parameter[7] || logio->io_parameter[8])
  1250. fcport->supported_classes |= FC_COS_CLASS2;
  1251. if (logio->io_parameter[9] || logio->io_parameter[10])
  1252. fcport->supported_classes |= FC_COS_CLASS3;
  1253. goto logio_done;
  1254. }
  1255. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1256. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1257. switch (iop[0]) {
  1258. case LSC_SCODE_PORTID_USED:
  1259. data[0] = MBS_PORT_ID_USED;
  1260. data[1] = LSW(iop[1]);
  1261. break;
  1262. case LSC_SCODE_NPORT_USED:
  1263. data[0] = MBS_LOOP_ID_USED;
  1264. break;
  1265. default:
  1266. data[0] = MBS_COMMAND_ERROR;
  1267. break;
  1268. }
  1269. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1270. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1271. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1272. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1273. le16_to_cpu(logio->comp_status),
  1274. le32_to_cpu(logio->io_parameter[0]),
  1275. le32_to_cpu(logio->io_parameter[1]));
  1276. logio_done:
  1277. sp->done(vha, sp, 0);
  1278. }
  1279. static void
  1280. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1281. struct tsk_mgmt_entry *tsk)
  1282. {
  1283. const char func[] = "TMF-IOCB";
  1284. const char *type;
  1285. fc_port_t *fcport;
  1286. srb_t *sp;
  1287. struct srb_iocb *iocb;
  1288. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1289. int error = 1;
  1290. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1291. if (!sp)
  1292. return;
  1293. iocb = &sp->u.iocb_cmd;
  1294. type = sp->name;
  1295. fcport = sp->fcport;
  1296. if (sts->entry_status) {
  1297. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1298. "Async-%s error - hdl=%x entry-status(%x).\n",
  1299. type, sp->handle, sts->entry_status);
  1300. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1301. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1302. "Async-%s error - hdl=%x completion status(%x).\n",
  1303. type, sp->handle, sts->comp_status);
  1304. } else if (!(le16_to_cpu(sts->scsi_status) &
  1305. SS_RESPONSE_INFO_LEN_VALID)) {
  1306. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1307. "Async-%s error - hdl=%x no response info(%x).\n",
  1308. type, sp->handle, sts->scsi_status);
  1309. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1310. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1311. "Async-%s error - hdl=%x not enough response(%d).\n",
  1312. type, sp->handle, sts->rsp_data_len);
  1313. } else if (sts->data[3]) {
  1314. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1315. "Async-%s error - hdl=%x response(%x).\n",
  1316. type, sp->handle, sts->data[3]);
  1317. } else {
  1318. error = 0;
  1319. }
  1320. if (error) {
  1321. iocb->u.tmf.data = error;
  1322. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1323. (uint8_t *)sts, sizeof(*sts));
  1324. }
  1325. sp->done(vha, sp, 0);
  1326. }
  1327. /**
  1328. * qla2x00_process_response_queue() - Process response queue entries.
  1329. * @ha: SCSI driver HA context
  1330. */
  1331. void
  1332. qla2x00_process_response_queue(struct rsp_que *rsp)
  1333. {
  1334. struct scsi_qla_host *vha;
  1335. struct qla_hw_data *ha = rsp->hw;
  1336. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1337. sts_entry_t *pkt;
  1338. uint16_t handle_cnt;
  1339. uint16_t cnt;
  1340. vha = pci_get_drvdata(ha->pdev);
  1341. if (!vha->flags.online)
  1342. return;
  1343. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1344. pkt = (sts_entry_t *)rsp->ring_ptr;
  1345. rsp->ring_index++;
  1346. if (rsp->ring_index == rsp->length) {
  1347. rsp->ring_index = 0;
  1348. rsp->ring_ptr = rsp->ring;
  1349. } else {
  1350. rsp->ring_ptr++;
  1351. }
  1352. if (pkt->entry_status != 0) {
  1353. qla2x00_error_entry(vha, rsp, pkt);
  1354. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1355. wmb();
  1356. continue;
  1357. }
  1358. switch (pkt->entry_type) {
  1359. case STATUS_TYPE:
  1360. qla2x00_status_entry(vha, rsp, pkt);
  1361. break;
  1362. case STATUS_TYPE_21:
  1363. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1364. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1365. qla2x00_process_completed_request(vha, rsp->req,
  1366. ((sts21_entry_t *)pkt)->handle[cnt]);
  1367. }
  1368. break;
  1369. case STATUS_TYPE_22:
  1370. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1371. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1372. qla2x00_process_completed_request(vha, rsp->req,
  1373. ((sts22_entry_t *)pkt)->handle[cnt]);
  1374. }
  1375. break;
  1376. case STATUS_CONT_TYPE:
  1377. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1378. break;
  1379. case MBX_IOCB_TYPE:
  1380. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1381. (struct mbx_entry *)pkt);
  1382. break;
  1383. case CT_IOCB_TYPE:
  1384. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1385. break;
  1386. default:
  1387. /* Type Not Supported. */
  1388. ql_log(ql_log_warn, vha, 0x504a,
  1389. "Received unknown response pkt type %x "
  1390. "entry status=%x.\n",
  1391. pkt->entry_type, pkt->entry_status);
  1392. break;
  1393. }
  1394. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1395. wmb();
  1396. }
  1397. /* Adjust ring index */
  1398. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1399. }
  1400. static inline void
  1401. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1402. uint32_t sense_len, struct rsp_que *rsp, int res)
  1403. {
  1404. struct scsi_qla_host *vha = sp->fcport->vha;
  1405. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1406. uint32_t track_sense_len;
  1407. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1408. sense_len = SCSI_SENSE_BUFFERSIZE;
  1409. SET_CMD_SENSE_LEN(sp, sense_len);
  1410. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1411. track_sense_len = sense_len;
  1412. if (sense_len > par_sense_len)
  1413. sense_len = par_sense_len;
  1414. memcpy(cp->sense_buffer, sense_data, sense_len);
  1415. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1416. track_sense_len -= sense_len;
  1417. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1418. if (track_sense_len != 0) {
  1419. rsp->status_srb = sp;
  1420. cp->result = res;
  1421. }
  1422. if (sense_len) {
  1423. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1424. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1425. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1426. cp);
  1427. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1428. cp->sense_buffer, sense_len);
  1429. }
  1430. }
  1431. struct scsi_dif_tuple {
  1432. __be16 guard; /* Checksum */
  1433. __be16 app_tag; /* APPL identifier */
  1434. __be32 ref_tag; /* Target LBA or indirect LBA */
  1435. };
  1436. /*
  1437. * Checks the guard or meta-data for the type of error
  1438. * detected by the HBA. In case of errors, we set the
  1439. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1440. * to indicate to the kernel that the HBA detected error.
  1441. */
  1442. static inline int
  1443. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1444. {
  1445. struct scsi_qla_host *vha = sp->fcport->vha;
  1446. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1447. uint8_t *ap = &sts24->data[12];
  1448. uint8_t *ep = &sts24->data[20];
  1449. uint32_t e_ref_tag, a_ref_tag;
  1450. uint16_t e_app_tag, a_app_tag;
  1451. uint16_t e_guard, a_guard;
  1452. /*
  1453. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1454. * would make guard field appear at offset 2
  1455. */
  1456. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1457. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1458. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1459. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1460. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1461. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1462. ql_dbg(ql_dbg_io, vha, 0x3023,
  1463. "iocb(s) %p Returned STATUS.\n", sts24);
  1464. ql_dbg(ql_dbg_io, vha, 0x3024,
  1465. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1466. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1467. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1468. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1469. a_app_tag, e_app_tag, a_guard, e_guard);
  1470. /*
  1471. * Ignore sector if:
  1472. * For type 3: ref & app tag is all 'f's
  1473. * For type 0,1,2: app tag is all 'f's
  1474. */
  1475. if ((a_app_tag == 0xffff) &&
  1476. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1477. (a_ref_tag == 0xffffffff))) {
  1478. uint32_t blocks_done, resid;
  1479. sector_t lba_s = scsi_get_lba(cmd);
  1480. /* 2TB boundary case covered automatically with this */
  1481. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1482. resid = scsi_bufflen(cmd) - (blocks_done *
  1483. cmd->device->sector_size);
  1484. scsi_set_resid(cmd, resid);
  1485. cmd->result = DID_OK << 16;
  1486. /* Update protection tag */
  1487. if (scsi_prot_sg_count(cmd)) {
  1488. uint32_t i, j = 0, k = 0, num_ent;
  1489. struct scatterlist *sg;
  1490. struct sd_dif_tuple *spt;
  1491. /* Patch the corresponding protection tags */
  1492. scsi_for_each_prot_sg(cmd, sg,
  1493. scsi_prot_sg_count(cmd), i) {
  1494. num_ent = sg_dma_len(sg) / 8;
  1495. if (k + num_ent < blocks_done) {
  1496. k += num_ent;
  1497. continue;
  1498. }
  1499. j = blocks_done - k - 1;
  1500. k = blocks_done;
  1501. break;
  1502. }
  1503. if (k != blocks_done) {
  1504. ql_log(ql_log_warn, vha, 0x302f,
  1505. "unexpected tag values tag:lba=%x:%llx)\n",
  1506. e_ref_tag, (unsigned long long)lba_s);
  1507. return 1;
  1508. }
  1509. spt = page_address(sg_page(sg)) + sg->offset;
  1510. spt += j;
  1511. spt->app_tag = 0xffff;
  1512. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1513. spt->ref_tag = 0xffffffff;
  1514. }
  1515. return 0;
  1516. }
  1517. /* check guard */
  1518. if (e_guard != a_guard) {
  1519. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1520. 0x10, 0x1);
  1521. set_driver_byte(cmd, DRIVER_SENSE);
  1522. set_host_byte(cmd, DID_ABORT);
  1523. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1524. return 1;
  1525. }
  1526. /* check ref tag */
  1527. if (e_ref_tag != a_ref_tag) {
  1528. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1529. 0x10, 0x3);
  1530. set_driver_byte(cmd, DRIVER_SENSE);
  1531. set_host_byte(cmd, DID_ABORT);
  1532. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1533. return 1;
  1534. }
  1535. /* check appl tag */
  1536. if (e_app_tag != a_app_tag) {
  1537. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1538. 0x10, 0x2);
  1539. set_driver_byte(cmd, DRIVER_SENSE);
  1540. set_host_byte(cmd, DID_ABORT);
  1541. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1542. return 1;
  1543. }
  1544. return 1;
  1545. }
  1546. static void
  1547. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1548. struct req_que *req, uint32_t index)
  1549. {
  1550. struct qla_hw_data *ha = vha->hw;
  1551. srb_t *sp;
  1552. uint16_t comp_status;
  1553. uint16_t scsi_status;
  1554. uint16_t thread_id;
  1555. uint32_t rval = EXT_STATUS_OK;
  1556. struct fc_bsg_job *bsg_job = NULL;
  1557. sts_entry_t *sts;
  1558. struct sts_entry_24xx *sts24;
  1559. sts = (sts_entry_t *) pkt;
  1560. sts24 = (struct sts_entry_24xx *) pkt;
  1561. /* Validate handle. */
  1562. if (index >= req->num_outstanding_cmds) {
  1563. ql_log(ql_log_warn, vha, 0x70af,
  1564. "Invalid SCSI completion handle 0x%x.\n", index);
  1565. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1566. return;
  1567. }
  1568. sp = req->outstanding_cmds[index];
  1569. if (sp) {
  1570. /* Free outstanding command slot. */
  1571. req->outstanding_cmds[index] = NULL;
  1572. bsg_job = sp->u.bsg_job;
  1573. } else {
  1574. ql_log(ql_log_warn, vha, 0x70b0,
  1575. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1576. req->id, index);
  1577. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1578. return;
  1579. }
  1580. if (IS_FWI2_CAPABLE(ha)) {
  1581. comp_status = le16_to_cpu(sts24->comp_status);
  1582. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1583. } else {
  1584. comp_status = le16_to_cpu(sts->comp_status);
  1585. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1586. }
  1587. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1588. switch (comp_status) {
  1589. case CS_COMPLETE:
  1590. if (scsi_status == 0) {
  1591. bsg_job->reply->reply_payload_rcv_len =
  1592. bsg_job->reply_payload.payload_len;
  1593. rval = EXT_STATUS_OK;
  1594. }
  1595. goto done;
  1596. case CS_DATA_OVERRUN:
  1597. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1598. "Command completed with date overrun thread_id=%d\n",
  1599. thread_id);
  1600. rval = EXT_STATUS_DATA_OVERRUN;
  1601. break;
  1602. case CS_DATA_UNDERRUN:
  1603. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1604. "Command completed with date underrun thread_id=%d\n",
  1605. thread_id);
  1606. rval = EXT_STATUS_DATA_UNDERRUN;
  1607. break;
  1608. case CS_BIDIR_RD_OVERRUN:
  1609. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1610. "Command completed with read data overrun thread_id=%d\n",
  1611. thread_id);
  1612. rval = EXT_STATUS_DATA_OVERRUN;
  1613. break;
  1614. case CS_BIDIR_RD_WR_OVERRUN:
  1615. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1616. "Command completed with read and write data overrun "
  1617. "thread_id=%d\n", thread_id);
  1618. rval = EXT_STATUS_DATA_OVERRUN;
  1619. break;
  1620. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1621. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1622. "Command completed with read data over and write data "
  1623. "underrun thread_id=%d\n", thread_id);
  1624. rval = EXT_STATUS_DATA_OVERRUN;
  1625. break;
  1626. case CS_BIDIR_RD_UNDERRUN:
  1627. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1628. "Command completed with read data data underrun "
  1629. "thread_id=%d\n", thread_id);
  1630. rval = EXT_STATUS_DATA_UNDERRUN;
  1631. break;
  1632. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1633. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1634. "Command completed with read data under and write data "
  1635. "overrun thread_id=%d\n", thread_id);
  1636. rval = EXT_STATUS_DATA_UNDERRUN;
  1637. break;
  1638. case CS_BIDIR_RD_WR_UNDERRUN:
  1639. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1640. "Command completed with read and write data underrun "
  1641. "thread_id=%d\n", thread_id);
  1642. rval = EXT_STATUS_DATA_UNDERRUN;
  1643. break;
  1644. case CS_BIDIR_DMA:
  1645. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1646. "Command completed with data DMA error thread_id=%d\n",
  1647. thread_id);
  1648. rval = EXT_STATUS_DMA_ERR;
  1649. break;
  1650. case CS_TIMEOUT:
  1651. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1652. "Command completed with timeout thread_id=%d\n",
  1653. thread_id);
  1654. rval = EXT_STATUS_TIMEOUT;
  1655. break;
  1656. default:
  1657. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1658. "Command completed with completion status=0x%x "
  1659. "thread_id=%d\n", comp_status, thread_id);
  1660. rval = EXT_STATUS_ERR;
  1661. break;
  1662. }
  1663. bsg_job->reply->reply_payload_rcv_len = 0;
  1664. done:
  1665. /* Return the vendor specific reply to API */
  1666. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1667. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1668. /* Always return DID_OK, bsg will send the vendor specific response
  1669. * in this case only */
  1670. sp->done(vha, sp, (DID_OK << 6));
  1671. }
  1672. /**
  1673. * qla2x00_status_entry() - Process a Status IOCB entry.
  1674. * @ha: SCSI driver HA context
  1675. * @pkt: Entry pointer
  1676. */
  1677. static void
  1678. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1679. {
  1680. srb_t *sp;
  1681. fc_port_t *fcport;
  1682. struct scsi_cmnd *cp;
  1683. sts_entry_t *sts;
  1684. struct sts_entry_24xx *sts24;
  1685. uint16_t comp_status;
  1686. uint16_t scsi_status;
  1687. uint16_t ox_id;
  1688. uint8_t lscsi_status;
  1689. int32_t resid;
  1690. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1691. fw_resid_len;
  1692. uint8_t *rsp_info, *sense_data;
  1693. struct qla_hw_data *ha = vha->hw;
  1694. uint32_t handle;
  1695. uint16_t que;
  1696. struct req_que *req;
  1697. int logit = 1;
  1698. int res = 0;
  1699. uint16_t state_flags = 0;
  1700. sts = (sts_entry_t *) pkt;
  1701. sts24 = (struct sts_entry_24xx *) pkt;
  1702. if (IS_FWI2_CAPABLE(ha)) {
  1703. comp_status = le16_to_cpu(sts24->comp_status);
  1704. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1705. state_flags = le16_to_cpu(sts24->state_flags);
  1706. } else {
  1707. comp_status = le16_to_cpu(sts->comp_status);
  1708. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1709. }
  1710. handle = (uint32_t) LSW(sts->handle);
  1711. que = MSW(sts->handle);
  1712. req = ha->req_q_map[que];
  1713. /* Validate handle. */
  1714. if (handle < req->num_outstanding_cmds)
  1715. sp = req->outstanding_cmds[handle];
  1716. else
  1717. sp = NULL;
  1718. if (sp == NULL) {
  1719. ql_dbg(ql_dbg_io, vha, 0x3017,
  1720. "Invalid status handle (0x%x).\n", sts->handle);
  1721. if (IS_QLA82XX(ha))
  1722. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1723. else
  1724. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1725. qla2xxx_wake_dpc(vha);
  1726. return;
  1727. }
  1728. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1729. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1730. return;
  1731. }
  1732. /* Fast path completion. */
  1733. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1734. qla2x00_do_host_ramp_up(vha);
  1735. qla2x00_process_completed_request(vha, req, handle);
  1736. return;
  1737. }
  1738. req->outstanding_cmds[handle] = NULL;
  1739. cp = GET_CMD_SP(sp);
  1740. if (cp == NULL) {
  1741. ql_dbg(ql_dbg_io, vha, 0x3018,
  1742. "Command already returned (0x%x/%p).\n",
  1743. sts->handle, sp);
  1744. return;
  1745. }
  1746. lscsi_status = scsi_status & STATUS_MASK;
  1747. fcport = sp->fcport;
  1748. ox_id = 0;
  1749. sense_len = par_sense_len = rsp_info_len = resid_len =
  1750. fw_resid_len = 0;
  1751. if (IS_FWI2_CAPABLE(ha)) {
  1752. if (scsi_status & SS_SENSE_LEN_VALID)
  1753. sense_len = le32_to_cpu(sts24->sense_len);
  1754. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1755. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1756. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1757. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1758. if (comp_status == CS_DATA_UNDERRUN)
  1759. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1760. rsp_info = sts24->data;
  1761. sense_data = sts24->data;
  1762. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1763. ox_id = le16_to_cpu(sts24->ox_id);
  1764. par_sense_len = sizeof(sts24->data);
  1765. } else {
  1766. if (scsi_status & SS_SENSE_LEN_VALID)
  1767. sense_len = le16_to_cpu(sts->req_sense_length);
  1768. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1769. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1770. resid_len = le32_to_cpu(sts->residual_length);
  1771. rsp_info = sts->rsp_info;
  1772. sense_data = sts->req_sense_data;
  1773. par_sense_len = sizeof(sts->req_sense_data);
  1774. }
  1775. /* Check for any FCP transport errors. */
  1776. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1777. /* Sense data lies beyond any FCP RESPONSE data. */
  1778. if (IS_FWI2_CAPABLE(ha)) {
  1779. sense_data += rsp_info_len;
  1780. par_sense_len -= rsp_info_len;
  1781. }
  1782. if (rsp_info_len > 3 && rsp_info[3]) {
  1783. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1784. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1785. rsp_info_len, rsp_info[3]);
  1786. res = DID_BUS_BUSY << 16;
  1787. goto out;
  1788. }
  1789. }
  1790. /* Check for overrun. */
  1791. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1792. scsi_status & SS_RESIDUAL_OVER)
  1793. comp_status = CS_DATA_OVERRUN;
  1794. /*
  1795. * Based on Host and scsi status generate status code for Linux
  1796. */
  1797. switch (comp_status) {
  1798. case CS_COMPLETE:
  1799. case CS_QUEUE_FULL:
  1800. if (scsi_status == 0) {
  1801. res = DID_OK << 16;
  1802. break;
  1803. }
  1804. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1805. resid = resid_len;
  1806. scsi_set_resid(cp, resid);
  1807. if (!lscsi_status &&
  1808. ((unsigned)(scsi_bufflen(cp) - resid) <
  1809. cp->underflow)) {
  1810. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1811. "Mid-layer underflow "
  1812. "detected (0x%x of 0x%x bytes).\n",
  1813. resid, scsi_bufflen(cp));
  1814. res = DID_ERROR << 16;
  1815. break;
  1816. }
  1817. }
  1818. res = DID_OK << 16 | lscsi_status;
  1819. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1820. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1821. "QUEUE FULL detected.\n");
  1822. break;
  1823. }
  1824. logit = 0;
  1825. if (lscsi_status != SS_CHECK_CONDITION)
  1826. break;
  1827. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1828. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1829. break;
  1830. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1831. rsp, res);
  1832. break;
  1833. case CS_DATA_UNDERRUN:
  1834. /* Use F/W calculated residual length. */
  1835. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1836. scsi_set_resid(cp, resid);
  1837. if (scsi_status & SS_RESIDUAL_UNDER) {
  1838. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1839. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1840. "Dropped frame(s) detected "
  1841. "(0x%x of 0x%x bytes).\n",
  1842. resid, scsi_bufflen(cp));
  1843. res = DID_ERROR << 16 | lscsi_status;
  1844. goto check_scsi_status;
  1845. }
  1846. if (!lscsi_status &&
  1847. ((unsigned)(scsi_bufflen(cp) - resid) <
  1848. cp->underflow)) {
  1849. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1850. "Mid-layer underflow "
  1851. "detected (0x%x of 0x%x bytes).\n",
  1852. resid, scsi_bufflen(cp));
  1853. res = DID_ERROR << 16;
  1854. break;
  1855. }
  1856. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1857. lscsi_status != SAM_STAT_BUSY) {
  1858. /*
  1859. * scsi status of task set and busy are considered to be
  1860. * task not completed.
  1861. */
  1862. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1863. "Dropped frame(s) detected (0x%x "
  1864. "of 0x%x bytes).\n", resid,
  1865. scsi_bufflen(cp));
  1866. res = DID_ERROR << 16 | lscsi_status;
  1867. goto check_scsi_status;
  1868. } else {
  1869. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1870. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1871. scsi_status, lscsi_status);
  1872. }
  1873. res = DID_OK << 16 | lscsi_status;
  1874. logit = 0;
  1875. check_scsi_status:
  1876. /*
  1877. * Check to see if SCSI Status is non zero. If so report SCSI
  1878. * Status.
  1879. */
  1880. if (lscsi_status != 0) {
  1881. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1882. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1883. "QUEUE FULL detected.\n");
  1884. logit = 1;
  1885. break;
  1886. }
  1887. if (lscsi_status != SS_CHECK_CONDITION)
  1888. break;
  1889. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1890. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1891. break;
  1892. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1893. sense_len, rsp, res);
  1894. }
  1895. break;
  1896. case CS_PORT_LOGGED_OUT:
  1897. case CS_PORT_CONFIG_CHG:
  1898. case CS_PORT_BUSY:
  1899. case CS_INCOMPLETE:
  1900. case CS_PORT_UNAVAILABLE:
  1901. case CS_TIMEOUT:
  1902. case CS_RESET:
  1903. /*
  1904. * We are going to have the fc class block the rport
  1905. * while we try to recover so instruct the mid layer
  1906. * to requeue until the class decides how to handle this.
  1907. */
  1908. res = DID_TRANSPORT_DISRUPTED << 16;
  1909. if (comp_status == CS_TIMEOUT) {
  1910. if (IS_FWI2_CAPABLE(ha))
  1911. break;
  1912. else if ((le16_to_cpu(sts->status_flags) &
  1913. SF_LOGOUT_SENT) == 0)
  1914. break;
  1915. }
  1916. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1917. "Port down status: port-state=0x%x.\n",
  1918. atomic_read(&fcport->state));
  1919. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1920. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1921. break;
  1922. case CS_ABORTED:
  1923. res = DID_RESET << 16;
  1924. break;
  1925. case CS_DIF_ERROR:
  1926. logit = qla2x00_handle_dif_error(sp, sts24);
  1927. res = cp->result;
  1928. break;
  1929. case CS_TRANSPORT:
  1930. res = DID_ERROR << 16;
  1931. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  1932. break;
  1933. if (state_flags & BIT_4)
  1934. scmd_printk(KERN_WARNING, cp,
  1935. "Unsupported device '%s' found.\n",
  1936. cp->device->vendor);
  1937. break;
  1938. default:
  1939. res = DID_ERROR << 16;
  1940. break;
  1941. }
  1942. out:
  1943. if (logit)
  1944. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1945. "FCP command status: 0x%x-0x%x (0x%x) "
  1946. "nexus=%ld:%d:%d portid=%02x%02x%02x oxid=0x%x "
  1947. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  1948. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1949. comp_status, scsi_status, res, vha->host_no,
  1950. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1951. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1952. cp->cmnd[0], cp->cmnd[1], cp->cmnd[2], cp->cmnd[3],
  1953. cp->cmnd[4], cp->cmnd[5], cp->cmnd[6], cp->cmnd[7],
  1954. cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp), rsp_info_len,
  1955. resid_len, fw_resid_len);
  1956. if (!res)
  1957. qla2x00_do_host_ramp_up(vha);
  1958. if (rsp->status_srb == NULL)
  1959. sp->done(ha, sp, res);
  1960. }
  1961. /**
  1962. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1963. * @ha: SCSI driver HA context
  1964. * @pkt: Entry pointer
  1965. *
  1966. * Extended sense data.
  1967. */
  1968. static void
  1969. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1970. {
  1971. uint8_t sense_sz = 0;
  1972. struct qla_hw_data *ha = rsp->hw;
  1973. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1974. srb_t *sp = rsp->status_srb;
  1975. struct scsi_cmnd *cp;
  1976. uint32_t sense_len;
  1977. uint8_t *sense_ptr;
  1978. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1979. return;
  1980. sense_len = GET_CMD_SENSE_LEN(sp);
  1981. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1982. cp = GET_CMD_SP(sp);
  1983. if (cp == NULL) {
  1984. ql_log(ql_log_warn, vha, 0x3025,
  1985. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1986. rsp->status_srb = NULL;
  1987. return;
  1988. }
  1989. if (sense_len > sizeof(pkt->data))
  1990. sense_sz = sizeof(pkt->data);
  1991. else
  1992. sense_sz = sense_len;
  1993. /* Move sense data. */
  1994. if (IS_FWI2_CAPABLE(ha))
  1995. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1996. memcpy(sense_ptr, pkt->data, sense_sz);
  1997. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1998. sense_ptr, sense_sz);
  1999. sense_len -= sense_sz;
  2000. sense_ptr += sense_sz;
  2001. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2002. SET_CMD_SENSE_LEN(sp, sense_len);
  2003. /* Place command on done queue. */
  2004. if (sense_len == 0) {
  2005. rsp->status_srb = NULL;
  2006. sp->done(ha, sp, cp->result);
  2007. }
  2008. }
  2009. /**
  2010. * qla2x00_error_entry() - Process an error entry.
  2011. * @ha: SCSI driver HA context
  2012. * @pkt: Entry pointer
  2013. */
  2014. static void
  2015. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2016. {
  2017. srb_t *sp;
  2018. struct qla_hw_data *ha = vha->hw;
  2019. const char func[] = "ERROR-IOCB";
  2020. uint16_t que = MSW(pkt->handle);
  2021. struct req_que *req = NULL;
  2022. int res = DID_ERROR << 16;
  2023. ql_dbg(ql_dbg_async, vha, 0x502a,
  2024. "type of error status in response: 0x%x\n", pkt->entry_status);
  2025. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2026. goto fatal;
  2027. req = ha->req_q_map[que];
  2028. if (pkt->entry_status & RF_BUSY)
  2029. res = DID_BUS_BUSY << 16;
  2030. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2031. if (sp) {
  2032. sp->done(ha, sp, res);
  2033. return;
  2034. }
  2035. fatal:
  2036. ql_log(ql_log_warn, vha, 0x5030,
  2037. "Error entry - invalid handle/queue.\n");
  2038. if (IS_QLA82XX(ha))
  2039. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2040. else
  2041. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2042. qla2xxx_wake_dpc(vha);
  2043. }
  2044. /**
  2045. * qla24xx_mbx_completion() - Process mailbox command completions.
  2046. * @ha: SCSI driver HA context
  2047. * @mb0: Mailbox0 register
  2048. */
  2049. static void
  2050. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2051. {
  2052. uint16_t cnt;
  2053. uint32_t mboxes;
  2054. uint16_t __iomem *wptr;
  2055. struct qla_hw_data *ha = vha->hw;
  2056. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2057. /* Read all mbox registers? */
  2058. mboxes = (1 << ha->mbx_count) - 1;
  2059. if (!ha->mcp)
  2060. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2061. else
  2062. mboxes = ha->mcp->in_mb;
  2063. /* Load return mailbox registers. */
  2064. ha->flags.mbox_int = 1;
  2065. ha->mailbox_out[0] = mb0;
  2066. mboxes >>= 1;
  2067. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2068. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2069. if (mboxes & BIT_0)
  2070. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2071. mboxes >>= 1;
  2072. wptr++;
  2073. }
  2074. }
  2075. /**
  2076. * qla24xx_process_response_queue() - Process response queue entries.
  2077. * @ha: SCSI driver HA context
  2078. */
  2079. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2080. struct rsp_que *rsp)
  2081. {
  2082. struct sts_entry_24xx *pkt;
  2083. struct qla_hw_data *ha = vha->hw;
  2084. if (!vha->flags.online)
  2085. return;
  2086. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2087. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2088. rsp->ring_index++;
  2089. if (rsp->ring_index == rsp->length) {
  2090. rsp->ring_index = 0;
  2091. rsp->ring_ptr = rsp->ring;
  2092. } else {
  2093. rsp->ring_ptr++;
  2094. }
  2095. if (pkt->entry_status != 0) {
  2096. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2097. (void)qlt_24xx_process_response_error(vha, pkt);
  2098. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2099. wmb();
  2100. continue;
  2101. }
  2102. switch (pkt->entry_type) {
  2103. case STATUS_TYPE:
  2104. qla2x00_status_entry(vha, rsp, pkt);
  2105. break;
  2106. case STATUS_CONT_TYPE:
  2107. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2108. break;
  2109. case VP_RPT_ID_IOCB_TYPE:
  2110. qla24xx_report_id_acquisition(vha,
  2111. (struct vp_rpt_id_entry_24xx *)pkt);
  2112. break;
  2113. case LOGINOUT_PORT_IOCB_TYPE:
  2114. qla24xx_logio_entry(vha, rsp->req,
  2115. (struct logio_entry_24xx *)pkt);
  2116. break;
  2117. case TSK_MGMT_IOCB_TYPE:
  2118. qla24xx_tm_iocb_entry(vha, rsp->req,
  2119. (struct tsk_mgmt_entry *)pkt);
  2120. break;
  2121. case CT_IOCB_TYPE:
  2122. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2123. break;
  2124. case ELS_IOCB_TYPE:
  2125. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2126. break;
  2127. case ABTS_RECV_24XX:
  2128. /* ensure that the ATIO queue is empty */
  2129. qlt_24xx_process_atio_queue(vha);
  2130. case ABTS_RESP_24XX:
  2131. case CTIO_TYPE7:
  2132. case NOTIFY_ACK_TYPE:
  2133. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2134. break;
  2135. case MARKER_TYPE:
  2136. /* Do nothing in this case, this check is to prevent it
  2137. * from falling into default case
  2138. */
  2139. break;
  2140. default:
  2141. /* Type Not Supported. */
  2142. ql_dbg(ql_dbg_async, vha, 0x5042,
  2143. "Received unknown response pkt type %x "
  2144. "entry status=%x.\n",
  2145. pkt->entry_type, pkt->entry_status);
  2146. break;
  2147. }
  2148. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2149. wmb();
  2150. }
  2151. /* Adjust ring index */
  2152. if (IS_QLA82XX(ha)) {
  2153. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2154. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2155. } else
  2156. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2157. }
  2158. static void
  2159. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2160. {
  2161. int rval;
  2162. uint32_t cnt;
  2163. struct qla_hw_data *ha = vha->hw;
  2164. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2165. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2166. return;
  2167. rval = QLA_SUCCESS;
  2168. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2169. RD_REG_DWORD(&reg->iobase_addr);
  2170. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2171. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2172. rval == QLA_SUCCESS; cnt--) {
  2173. if (cnt) {
  2174. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2175. udelay(10);
  2176. } else
  2177. rval = QLA_FUNCTION_TIMEOUT;
  2178. }
  2179. if (rval == QLA_SUCCESS)
  2180. goto next_test;
  2181. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2182. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2183. rval == QLA_SUCCESS; cnt--) {
  2184. if (cnt) {
  2185. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2186. udelay(10);
  2187. } else
  2188. rval = QLA_FUNCTION_TIMEOUT;
  2189. }
  2190. if (rval != QLA_SUCCESS)
  2191. goto done;
  2192. next_test:
  2193. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2194. ql_log(ql_log_info, vha, 0x504c,
  2195. "Additional code -- 0x55AA.\n");
  2196. done:
  2197. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2198. RD_REG_DWORD(&reg->iobase_window);
  2199. }
  2200. /**
  2201. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2202. * @irq:
  2203. * @dev_id: SCSI driver HA context
  2204. *
  2205. * Called by system whenever the host adapter generates an interrupt.
  2206. *
  2207. * Returns handled flag.
  2208. */
  2209. irqreturn_t
  2210. qla24xx_intr_handler(int irq, void *dev_id)
  2211. {
  2212. scsi_qla_host_t *vha;
  2213. struct qla_hw_data *ha;
  2214. struct device_reg_24xx __iomem *reg;
  2215. int status;
  2216. unsigned long iter;
  2217. uint32_t stat;
  2218. uint32_t hccr;
  2219. uint16_t mb[8];
  2220. struct rsp_que *rsp;
  2221. unsigned long flags;
  2222. rsp = (struct rsp_que *) dev_id;
  2223. if (!rsp) {
  2224. ql_log(ql_log_info, NULL, 0x5059,
  2225. "%s: NULL response queue pointer.\n", __func__);
  2226. return IRQ_NONE;
  2227. }
  2228. ha = rsp->hw;
  2229. reg = &ha->iobase->isp24;
  2230. status = 0;
  2231. if (unlikely(pci_channel_offline(ha->pdev)))
  2232. return IRQ_HANDLED;
  2233. spin_lock_irqsave(&ha->hardware_lock, flags);
  2234. vha = pci_get_drvdata(ha->pdev);
  2235. for (iter = 50; iter--; ) {
  2236. stat = RD_REG_DWORD(&reg->host_status);
  2237. if (stat & HSRX_RISC_PAUSED) {
  2238. if (unlikely(pci_channel_offline(ha->pdev)))
  2239. break;
  2240. hccr = RD_REG_DWORD(&reg->hccr);
  2241. ql_log(ql_log_warn, vha, 0x504b,
  2242. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2243. hccr);
  2244. qla2xxx_check_risc_status(vha);
  2245. ha->isp_ops->fw_dump(vha, 1);
  2246. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2247. break;
  2248. } else if ((stat & HSRX_RISC_INT) == 0)
  2249. break;
  2250. switch (stat & 0xff) {
  2251. case INTR_ROM_MB_SUCCESS:
  2252. case INTR_ROM_MB_FAILED:
  2253. case INTR_MB_SUCCESS:
  2254. case INTR_MB_FAILED:
  2255. qla24xx_mbx_completion(vha, MSW(stat));
  2256. status |= MBX_INTERRUPT;
  2257. break;
  2258. case INTR_ASYNC_EVENT:
  2259. mb[0] = MSW(stat);
  2260. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2261. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2262. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2263. qla2x00_async_event(vha, rsp, mb);
  2264. break;
  2265. case INTR_RSP_QUE_UPDATE:
  2266. case INTR_RSP_QUE_UPDATE_83XX:
  2267. qla24xx_process_response_queue(vha, rsp);
  2268. break;
  2269. case INTR_ATIO_QUE_UPDATE:
  2270. qlt_24xx_process_atio_queue(vha);
  2271. break;
  2272. case INTR_ATIO_RSP_QUE_UPDATE:
  2273. qlt_24xx_process_atio_queue(vha);
  2274. qla24xx_process_response_queue(vha, rsp);
  2275. break;
  2276. default:
  2277. ql_dbg(ql_dbg_async, vha, 0x504f,
  2278. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2279. break;
  2280. }
  2281. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2282. RD_REG_DWORD_RELAXED(&reg->hccr);
  2283. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2284. ndelay(3500);
  2285. }
  2286. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2287. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2288. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2289. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2290. complete(&ha->mbx_intr_comp);
  2291. }
  2292. return IRQ_HANDLED;
  2293. }
  2294. static irqreturn_t
  2295. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2296. {
  2297. struct qla_hw_data *ha;
  2298. struct rsp_que *rsp;
  2299. struct device_reg_24xx __iomem *reg;
  2300. struct scsi_qla_host *vha;
  2301. unsigned long flags;
  2302. rsp = (struct rsp_que *) dev_id;
  2303. if (!rsp) {
  2304. ql_log(ql_log_info, NULL, 0x505a,
  2305. "%s: NULL response queue pointer.\n", __func__);
  2306. return IRQ_NONE;
  2307. }
  2308. ha = rsp->hw;
  2309. reg = &ha->iobase->isp24;
  2310. spin_lock_irqsave(&ha->hardware_lock, flags);
  2311. vha = pci_get_drvdata(ha->pdev);
  2312. qla24xx_process_response_queue(vha, rsp);
  2313. if (!ha->flags.disable_msix_handshake) {
  2314. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2315. RD_REG_DWORD_RELAXED(&reg->hccr);
  2316. }
  2317. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2318. return IRQ_HANDLED;
  2319. }
  2320. static irqreturn_t
  2321. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2322. {
  2323. struct qla_hw_data *ha;
  2324. struct rsp_que *rsp;
  2325. struct device_reg_24xx __iomem *reg;
  2326. unsigned long flags;
  2327. rsp = (struct rsp_que *) dev_id;
  2328. if (!rsp) {
  2329. ql_log(ql_log_info, NULL, 0x505b,
  2330. "%s: NULL response queue pointer.\n", __func__);
  2331. return IRQ_NONE;
  2332. }
  2333. ha = rsp->hw;
  2334. /* Clear the interrupt, if enabled, for this response queue */
  2335. if (!ha->flags.disable_msix_handshake) {
  2336. reg = &ha->iobase->isp24;
  2337. spin_lock_irqsave(&ha->hardware_lock, flags);
  2338. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2339. RD_REG_DWORD_RELAXED(&reg->hccr);
  2340. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2341. }
  2342. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2343. return IRQ_HANDLED;
  2344. }
  2345. static irqreturn_t
  2346. qla24xx_msix_default(int irq, void *dev_id)
  2347. {
  2348. scsi_qla_host_t *vha;
  2349. struct qla_hw_data *ha;
  2350. struct rsp_que *rsp;
  2351. struct device_reg_24xx __iomem *reg;
  2352. int status;
  2353. uint32_t stat;
  2354. uint32_t hccr;
  2355. uint16_t mb[8];
  2356. unsigned long flags;
  2357. rsp = (struct rsp_que *) dev_id;
  2358. if (!rsp) {
  2359. ql_log(ql_log_info, NULL, 0x505c,
  2360. "%s: NULL response queue pointer.\n", __func__);
  2361. return IRQ_NONE;
  2362. }
  2363. ha = rsp->hw;
  2364. reg = &ha->iobase->isp24;
  2365. status = 0;
  2366. spin_lock_irqsave(&ha->hardware_lock, flags);
  2367. vha = pci_get_drvdata(ha->pdev);
  2368. do {
  2369. stat = RD_REG_DWORD(&reg->host_status);
  2370. if (stat & HSRX_RISC_PAUSED) {
  2371. if (unlikely(pci_channel_offline(ha->pdev)))
  2372. break;
  2373. hccr = RD_REG_DWORD(&reg->hccr);
  2374. ql_log(ql_log_info, vha, 0x5050,
  2375. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2376. hccr);
  2377. qla2xxx_check_risc_status(vha);
  2378. ha->isp_ops->fw_dump(vha, 1);
  2379. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2380. break;
  2381. } else if ((stat & HSRX_RISC_INT) == 0)
  2382. break;
  2383. switch (stat & 0xff) {
  2384. case INTR_ROM_MB_SUCCESS:
  2385. case INTR_ROM_MB_FAILED:
  2386. case INTR_MB_SUCCESS:
  2387. case INTR_MB_FAILED:
  2388. qla24xx_mbx_completion(vha, MSW(stat));
  2389. status |= MBX_INTERRUPT;
  2390. break;
  2391. case INTR_ASYNC_EVENT:
  2392. mb[0] = MSW(stat);
  2393. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2394. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2395. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2396. qla2x00_async_event(vha, rsp, mb);
  2397. break;
  2398. case INTR_RSP_QUE_UPDATE:
  2399. case INTR_RSP_QUE_UPDATE_83XX:
  2400. qla24xx_process_response_queue(vha, rsp);
  2401. break;
  2402. case INTR_ATIO_QUE_UPDATE:
  2403. qlt_24xx_process_atio_queue(vha);
  2404. break;
  2405. case INTR_ATIO_RSP_QUE_UPDATE:
  2406. qlt_24xx_process_atio_queue(vha);
  2407. qla24xx_process_response_queue(vha, rsp);
  2408. break;
  2409. default:
  2410. ql_dbg(ql_dbg_async, vha, 0x5051,
  2411. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2412. break;
  2413. }
  2414. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2415. } while (0);
  2416. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2417. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2418. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2419. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2420. complete(&ha->mbx_intr_comp);
  2421. }
  2422. return IRQ_HANDLED;
  2423. }
  2424. /* Interrupt handling helpers. */
  2425. struct qla_init_msix_entry {
  2426. const char *name;
  2427. irq_handler_t handler;
  2428. };
  2429. static struct qla_init_msix_entry msix_entries[3] = {
  2430. { "qla2xxx (default)", qla24xx_msix_default },
  2431. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2432. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2433. };
  2434. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2435. { "qla2xxx (default)", qla82xx_msix_default },
  2436. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2437. };
  2438. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2439. { "qla2xxx (default)", qla24xx_msix_default },
  2440. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2441. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2442. };
  2443. static void
  2444. qla24xx_disable_msix(struct qla_hw_data *ha)
  2445. {
  2446. int i;
  2447. struct qla_msix_entry *qentry;
  2448. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2449. for (i = 0; i < ha->msix_count; i++) {
  2450. qentry = &ha->msix_entries[i];
  2451. if (qentry->have_irq)
  2452. free_irq(qentry->vector, qentry->rsp);
  2453. }
  2454. pci_disable_msix(ha->pdev);
  2455. kfree(ha->msix_entries);
  2456. ha->msix_entries = NULL;
  2457. ha->flags.msix_enabled = 0;
  2458. ql_dbg(ql_dbg_init, vha, 0x0042,
  2459. "Disabled the MSI.\n");
  2460. }
  2461. static int
  2462. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2463. {
  2464. #define MIN_MSIX_COUNT 2
  2465. int i, ret;
  2466. struct msix_entry *entries;
  2467. struct qla_msix_entry *qentry;
  2468. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2469. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2470. GFP_KERNEL);
  2471. if (!entries) {
  2472. ql_log(ql_log_warn, vha, 0x00bc,
  2473. "Failed to allocate memory for msix_entry.\n");
  2474. return -ENOMEM;
  2475. }
  2476. for (i = 0; i < ha->msix_count; i++)
  2477. entries[i].entry = i;
  2478. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2479. if (ret) {
  2480. if (ret < MIN_MSIX_COUNT)
  2481. goto msix_failed;
  2482. ql_log(ql_log_warn, vha, 0x00c6,
  2483. "MSI-X: Failed to enable support "
  2484. "-- %d/%d\n Retry with %d vectors.\n",
  2485. ha->msix_count, ret, ret);
  2486. ha->msix_count = ret;
  2487. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2488. if (ret) {
  2489. msix_failed:
  2490. ql_log(ql_log_fatal, vha, 0x00c7,
  2491. "MSI-X: Failed to enable support, "
  2492. "giving up -- %d/%d.\n",
  2493. ha->msix_count, ret);
  2494. goto msix_out;
  2495. }
  2496. ha->max_rsp_queues = ha->msix_count - 1;
  2497. }
  2498. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2499. ha->msix_count, GFP_KERNEL);
  2500. if (!ha->msix_entries) {
  2501. ql_log(ql_log_fatal, vha, 0x00c8,
  2502. "Failed to allocate memory for ha->msix_entries.\n");
  2503. ret = -ENOMEM;
  2504. goto msix_out;
  2505. }
  2506. ha->flags.msix_enabled = 1;
  2507. for (i = 0; i < ha->msix_count; i++) {
  2508. qentry = &ha->msix_entries[i];
  2509. qentry->vector = entries[i].vector;
  2510. qentry->entry = entries[i].entry;
  2511. qentry->have_irq = 0;
  2512. qentry->rsp = NULL;
  2513. }
  2514. /* Enable MSI-X vectors for the base queue */
  2515. for (i = 0; i < ha->msix_count; i++) {
  2516. qentry = &ha->msix_entries[i];
  2517. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2518. ret = request_irq(qentry->vector,
  2519. qla83xx_msix_entries[i].handler,
  2520. 0, qla83xx_msix_entries[i].name, rsp);
  2521. } else if (IS_QLA82XX(ha)) {
  2522. ret = request_irq(qentry->vector,
  2523. qla82xx_msix_entries[i].handler,
  2524. 0, qla82xx_msix_entries[i].name, rsp);
  2525. } else {
  2526. ret = request_irq(qentry->vector,
  2527. msix_entries[i].handler,
  2528. 0, msix_entries[i].name, rsp);
  2529. }
  2530. if (ret) {
  2531. ql_log(ql_log_fatal, vha, 0x00cb,
  2532. "MSI-X: unable to register handler -- %x/%d.\n",
  2533. qentry->vector, ret);
  2534. qla24xx_disable_msix(ha);
  2535. ha->mqenable = 0;
  2536. goto msix_out;
  2537. }
  2538. qentry->have_irq = 1;
  2539. qentry->rsp = rsp;
  2540. rsp->msix = qentry;
  2541. }
  2542. /* Enable MSI-X vector for response queue update for queue 0 */
  2543. if (IS_QLA83XX(ha)) {
  2544. if (ha->msixbase && ha->mqiobase &&
  2545. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2546. ha->mqenable = 1;
  2547. } else
  2548. if (ha->mqiobase
  2549. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2550. ha->mqenable = 1;
  2551. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2552. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2553. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2554. ql_dbg(ql_dbg_init, vha, 0x0055,
  2555. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2556. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2557. msix_out:
  2558. kfree(entries);
  2559. return ret;
  2560. }
  2561. int
  2562. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2563. {
  2564. int ret;
  2565. device_reg_t __iomem *reg = ha->iobase;
  2566. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2567. /* If possible, enable MSI-X. */
  2568. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2569. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha))
  2570. goto skip_msi;
  2571. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2572. (ha->pdev->subsystem_device == 0x7040 ||
  2573. ha->pdev->subsystem_device == 0x7041 ||
  2574. ha->pdev->subsystem_device == 0x1705)) {
  2575. ql_log(ql_log_warn, vha, 0x0034,
  2576. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2577. ha->pdev->subsystem_vendor,
  2578. ha->pdev->subsystem_device);
  2579. goto skip_msi;
  2580. }
  2581. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2582. ql_log(ql_log_warn, vha, 0x0035,
  2583. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2584. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2585. goto skip_msix;
  2586. }
  2587. ret = qla24xx_enable_msix(ha, rsp);
  2588. if (!ret) {
  2589. ql_dbg(ql_dbg_init, vha, 0x0036,
  2590. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2591. ha->chip_revision, ha->fw_attributes);
  2592. goto clear_risc_ints;
  2593. }
  2594. ql_log(ql_log_info, vha, 0x0037,
  2595. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2596. skip_msix:
  2597. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2598. !IS_QLA8001(ha) && !IS_QLA82XX(ha) && !IS_QLAFX00(ha))
  2599. goto skip_msi;
  2600. ret = pci_enable_msi(ha->pdev);
  2601. if (!ret) {
  2602. ql_dbg(ql_dbg_init, vha, 0x0038,
  2603. "MSI: Enabled.\n");
  2604. ha->flags.msi_enabled = 1;
  2605. } else
  2606. ql_log(ql_log_warn, vha, 0x0039,
  2607. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2608. /* Skip INTx on ISP82xx. */
  2609. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2610. return QLA_FUNCTION_FAILED;
  2611. skip_msi:
  2612. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2613. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2614. QLA2XXX_DRIVER_NAME, rsp);
  2615. if (ret) {
  2616. ql_log(ql_log_warn, vha, 0x003a,
  2617. "Failed to reserve interrupt %d already in use.\n",
  2618. ha->pdev->irq);
  2619. goto fail;
  2620. } else if (!ha->flags.msi_enabled) {
  2621. ql_dbg(ql_dbg_init, vha, 0x0125,
  2622. "INTa mode: Enabled.\n");
  2623. ha->flags.mr_intr_valid = 1;
  2624. }
  2625. clear_risc_ints:
  2626. spin_lock_irq(&ha->hardware_lock);
  2627. if (!IS_FWI2_CAPABLE(ha))
  2628. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2629. spin_unlock_irq(&ha->hardware_lock);
  2630. fail:
  2631. return ret;
  2632. }
  2633. void
  2634. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2635. {
  2636. struct qla_hw_data *ha = vha->hw;
  2637. struct rsp_que *rsp;
  2638. /*
  2639. * We need to check that ha->rsp_q_map is valid in case we are called
  2640. * from a probe failure context.
  2641. */
  2642. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2643. return;
  2644. rsp = ha->rsp_q_map[0];
  2645. if (ha->flags.msix_enabled)
  2646. qla24xx_disable_msix(ha);
  2647. else if (ha->flags.msi_enabled) {
  2648. free_irq(ha->pdev->irq, rsp);
  2649. pci_disable_msi(ha->pdev);
  2650. } else
  2651. free_irq(ha->pdev->irq, rsp);
  2652. }
  2653. int qla25xx_request_irq(struct rsp_que *rsp)
  2654. {
  2655. struct qla_hw_data *ha = rsp->hw;
  2656. struct qla_init_msix_entry *intr = &msix_entries[2];
  2657. struct qla_msix_entry *msix = rsp->msix;
  2658. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2659. int ret;
  2660. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2661. if (ret) {
  2662. ql_log(ql_log_fatal, vha, 0x00e6,
  2663. "MSI-X: Unable to register handler -- %x/%d.\n",
  2664. msix->vector, ret);
  2665. return ret;
  2666. }
  2667. msix->have_irq = 1;
  2668. msix->rsp = rsp;
  2669. return ret;
  2670. }