cnic.c 126 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  55. static LIST_HEAD(cnic_dev_list);
  56. static LIST_HEAD(cnic_udev_list);
  57. static DEFINE_RWLOCK(cnic_dev_lock);
  58. static DEFINE_MUTEX(cnic_lock);
  59. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  60. static int cnic_service_bnx2(void *, void *);
  61. static int cnic_service_bnx2x(void *, void *);
  62. static int cnic_ctl(void *, struct cnic_ctl_info *);
  63. static struct cnic_ops cnic_bnx2_ops = {
  64. .cnic_owner = THIS_MODULE,
  65. .cnic_handler = cnic_service_bnx2,
  66. .cnic_ctl = cnic_ctl,
  67. };
  68. static struct cnic_ops cnic_bnx2x_ops = {
  69. .cnic_owner = THIS_MODULE,
  70. .cnic_handler = cnic_service_bnx2x,
  71. .cnic_ctl = cnic_ctl,
  72. };
  73. static struct workqueue_struct *cnic_wq;
  74. static void cnic_shutdown_rings(struct cnic_dev *);
  75. static void cnic_init_rings(struct cnic_dev *);
  76. static int cnic_cm_set_pg(struct cnic_sock *);
  77. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  78. {
  79. struct cnic_uio_dev *udev = uinfo->priv;
  80. struct cnic_dev *dev;
  81. if (!capable(CAP_NET_ADMIN))
  82. return -EPERM;
  83. if (udev->uio_dev != -1)
  84. return -EBUSY;
  85. rtnl_lock();
  86. dev = udev->dev;
  87. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  88. rtnl_unlock();
  89. return -ENODEV;
  90. }
  91. udev->uio_dev = iminor(inode);
  92. cnic_shutdown_rings(dev);
  93. cnic_init_rings(dev);
  94. rtnl_unlock();
  95. return 0;
  96. }
  97. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  98. {
  99. struct cnic_uio_dev *udev = uinfo->priv;
  100. udev->uio_dev = -1;
  101. return 0;
  102. }
  103. static inline void cnic_hold(struct cnic_dev *dev)
  104. {
  105. atomic_inc(&dev->ref_count);
  106. }
  107. static inline void cnic_put(struct cnic_dev *dev)
  108. {
  109. atomic_dec(&dev->ref_count);
  110. }
  111. static inline void csk_hold(struct cnic_sock *csk)
  112. {
  113. atomic_inc(&csk->ref_count);
  114. }
  115. static inline void csk_put(struct cnic_sock *csk)
  116. {
  117. atomic_dec(&csk->ref_count);
  118. }
  119. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  120. {
  121. struct cnic_dev *cdev;
  122. read_lock(&cnic_dev_lock);
  123. list_for_each_entry(cdev, &cnic_dev_list, list) {
  124. if (netdev == cdev->netdev) {
  125. cnic_hold(cdev);
  126. read_unlock(&cnic_dev_lock);
  127. return cdev;
  128. }
  129. }
  130. read_unlock(&cnic_dev_lock);
  131. return NULL;
  132. }
  133. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  134. {
  135. atomic_inc(&ulp_ops->ref_count);
  136. }
  137. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  138. {
  139. atomic_dec(&ulp_ops->ref_count);
  140. }
  141. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  142. {
  143. struct cnic_local *cp = dev->cnic_priv;
  144. struct cnic_eth_dev *ethdev = cp->ethdev;
  145. struct drv_ctl_info info;
  146. struct drv_ctl_io *io = &info.data.io;
  147. info.cmd = DRV_CTL_CTX_WR_CMD;
  148. io->cid_addr = cid_addr;
  149. io->offset = off;
  150. io->data = val;
  151. ethdev->drv_ctl(dev->netdev, &info);
  152. }
  153. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  154. {
  155. struct cnic_local *cp = dev->cnic_priv;
  156. struct cnic_eth_dev *ethdev = cp->ethdev;
  157. struct drv_ctl_info info;
  158. struct drv_ctl_io *io = &info.data.io;
  159. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  160. io->offset = off;
  161. io->dma_addr = addr;
  162. ethdev->drv_ctl(dev->netdev, &info);
  163. }
  164. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  165. {
  166. struct cnic_local *cp = dev->cnic_priv;
  167. struct cnic_eth_dev *ethdev = cp->ethdev;
  168. struct drv_ctl_info info;
  169. struct drv_ctl_l2_ring *ring = &info.data.ring;
  170. if (start)
  171. info.cmd = DRV_CTL_START_L2_CMD;
  172. else
  173. info.cmd = DRV_CTL_STOP_L2_CMD;
  174. ring->cid = cid;
  175. ring->client_id = cl_id;
  176. ethdev->drv_ctl(dev->netdev, &info);
  177. }
  178. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  179. {
  180. struct cnic_local *cp = dev->cnic_priv;
  181. struct cnic_eth_dev *ethdev = cp->ethdev;
  182. struct drv_ctl_info info;
  183. struct drv_ctl_io *io = &info.data.io;
  184. info.cmd = DRV_CTL_IO_WR_CMD;
  185. io->offset = off;
  186. io->data = val;
  187. ethdev->drv_ctl(dev->netdev, &info);
  188. }
  189. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  190. {
  191. struct cnic_local *cp = dev->cnic_priv;
  192. struct cnic_eth_dev *ethdev = cp->ethdev;
  193. struct drv_ctl_info info;
  194. struct drv_ctl_io *io = &info.data.io;
  195. info.cmd = DRV_CTL_IO_RD_CMD;
  196. io->offset = off;
  197. ethdev->drv_ctl(dev->netdev, &info);
  198. return io->data;
  199. }
  200. static int cnic_in_use(struct cnic_sock *csk)
  201. {
  202. return test_bit(SK_F_INUSE, &csk->flags);
  203. }
  204. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  205. {
  206. struct cnic_local *cp = dev->cnic_priv;
  207. struct cnic_eth_dev *ethdev = cp->ethdev;
  208. struct drv_ctl_info info;
  209. info.cmd = cmd;
  210. info.data.credit.credit_count = count;
  211. ethdev->drv_ctl(dev->netdev, &info);
  212. }
  213. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  214. {
  215. u32 i;
  216. for (i = 0; i < cp->max_cid_space; i++) {
  217. if (cp->ctx_tbl[i].cid == cid) {
  218. *l5_cid = i;
  219. return 0;
  220. }
  221. }
  222. return -EINVAL;
  223. }
  224. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  225. struct cnic_sock *csk)
  226. {
  227. struct iscsi_path path_req;
  228. char *buf = NULL;
  229. u16 len = 0;
  230. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  231. struct cnic_ulp_ops *ulp_ops;
  232. struct cnic_uio_dev *udev = cp->udev;
  233. if (!udev || udev->uio_dev == -1)
  234. return -ENODEV;
  235. if (csk) {
  236. len = sizeof(path_req);
  237. buf = (char *) &path_req;
  238. memset(&path_req, 0, len);
  239. msg_type = ISCSI_KEVENT_PATH_REQ;
  240. path_req.handle = (u64) csk->l5_cid;
  241. if (test_bit(SK_F_IPV6, &csk->flags)) {
  242. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  243. sizeof(struct in6_addr));
  244. path_req.ip_addr_len = 16;
  245. } else {
  246. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  247. sizeof(struct in_addr));
  248. path_req.ip_addr_len = 4;
  249. }
  250. path_req.vlan_id = csk->vlan_id;
  251. path_req.pmtu = csk->mtu;
  252. }
  253. rcu_read_lock();
  254. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  255. if (ulp_ops)
  256. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  257. rcu_read_unlock();
  258. return 0;
  259. }
  260. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  261. char *buf, u16 len)
  262. {
  263. int rc = -EINVAL;
  264. switch (msg_type) {
  265. case ISCSI_UEVENT_PATH_UPDATE: {
  266. struct cnic_local *cp;
  267. u32 l5_cid;
  268. struct cnic_sock *csk;
  269. struct iscsi_path *path_resp;
  270. if (len < sizeof(*path_resp))
  271. break;
  272. path_resp = (struct iscsi_path *) buf;
  273. cp = dev->cnic_priv;
  274. l5_cid = (u32) path_resp->handle;
  275. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  276. break;
  277. rcu_read_lock();
  278. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  279. rc = -ENODEV;
  280. rcu_read_unlock();
  281. break;
  282. }
  283. csk = &cp->csk_tbl[l5_cid];
  284. csk_hold(csk);
  285. if (cnic_in_use(csk)) {
  286. memcpy(csk->ha, path_resp->mac_addr, 6);
  287. if (test_bit(SK_F_IPV6, &csk->flags))
  288. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  289. sizeof(struct in6_addr));
  290. else
  291. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  292. sizeof(struct in_addr));
  293. if (is_valid_ether_addr(csk->ha))
  294. cnic_cm_set_pg(csk);
  295. }
  296. csk_put(csk);
  297. rcu_read_unlock();
  298. rc = 0;
  299. }
  300. }
  301. return rc;
  302. }
  303. static int cnic_offld_prep(struct cnic_sock *csk)
  304. {
  305. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  306. return 0;
  307. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  308. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  309. return 0;
  310. }
  311. return 1;
  312. }
  313. static int cnic_close_prep(struct cnic_sock *csk)
  314. {
  315. clear_bit(SK_F_CONNECT_START, &csk->flags);
  316. smp_mb__after_clear_bit();
  317. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  318. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  319. msleep(1);
  320. return 1;
  321. }
  322. return 0;
  323. }
  324. static int cnic_abort_prep(struct cnic_sock *csk)
  325. {
  326. clear_bit(SK_F_CONNECT_START, &csk->flags);
  327. smp_mb__after_clear_bit();
  328. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  329. msleep(1);
  330. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  331. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  332. return 1;
  333. }
  334. return 0;
  335. }
  336. static void cnic_uio_stop(void)
  337. {
  338. struct cnic_dev *dev;
  339. read_lock(&cnic_dev_lock);
  340. list_for_each_entry(dev, &cnic_dev_list, list) {
  341. struct cnic_local *cp = dev->cnic_priv;
  342. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  343. }
  344. read_unlock(&cnic_dev_lock);
  345. }
  346. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  347. {
  348. struct cnic_dev *dev;
  349. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  350. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  351. return -EINVAL;
  352. }
  353. mutex_lock(&cnic_lock);
  354. if (cnic_ulp_tbl[ulp_type]) {
  355. pr_err("%s: Type %d has already been registered\n",
  356. __func__, ulp_type);
  357. mutex_unlock(&cnic_lock);
  358. return -EBUSY;
  359. }
  360. read_lock(&cnic_dev_lock);
  361. list_for_each_entry(dev, &cnic_dev_list, list) {
  362. struct cnic_local *cp = dev->cnic_priv;
  363. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  364. }
  365. read_unlock(&cnic_dev_lock);
  366. atomic_set(&ulp_ops->ref_count, 0);
  367. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  368. mutex_unlock(&cnic_lock);
  369. /* Prevent race conditions with netdev_event */
  370. rtnl_lock();
  371. list_for_each_entry(dev, &cnic_dev_list, list) {
  372. struct cnic_local *cp = dev->cnic_priv;
  373. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  374. ulp_ops->cnic_init(dev);
  375. }
  376. rtnl_unlock();
  377. return 0;
  378. }
  379. int cnic_unregister_driver(int ulp_type)
  380. {
  381. struct cnic_dev *dev;
  382. struct cnic_ulp_ops *ulp_ops;
  383. int i = 0;
  384. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  385. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  386. return -EINVAL;
  387. }
  388. mutex_lock(&cnic_lock);
  389. ulp_ops = cnic_ulp_tbl[ulp_type];
  390. if (!ulp_ops) {
  391. pr_err("%s: Type %d has not been registered\n",
  392. __func__, ulp_type);
  393. goto out_unlock;
  394. }
  395. read_lock(&cnic_dev_lock);
  396. list_for_each_entry(dev, &cnic_dev_list, list) {
  397. struct cnic_local *cp = dev->cnic_priv;
  398. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  399. pr_err("%s: Type %d still has devices registered\n",
  400. __func__, ulp_type);
  401. read_unlock(&cnic_dev_lock);
  402. goto out_unlock;
  403. }
  404. }
  405. read_unlock(&cnic_dev_lock);
  406. if (ulp_type == CNIC_ULP_ISCSI)
  407. cnic_uio_stop();
  408. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  409. mutex_unlock(&cnic_lock);
  410. synchronize_rcu();
  411. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  412. msleep(100);
  413. i++;
  414. }
  415. if (atomic_read(&ulp_ops->ref_count) != 0)
  416. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  417. return 0;
  418. out_unlock:
  419. mutex_unlock(&cnic_lock);
  420. return -EINVAL;
  421. }
  422. static int cnic_start_hw(struct cnic_dev *);
  423. static void cnic_stop_hw(struct cnic_dev *);
  424. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  425. void *ulp_ctx)
  426. {
  427. struct cnic_local *cp = dev->cnic_priv;
  428. struct cnic_ulp_ops *ulp_ops;
  429. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  430. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  431. return -EINVAL;
  432. }
  433. mutex_lock(&cnic_lock);
  434. if (cnic_ulp_tbl[ulp_type] == NULL) {
  435. pr_err("%s: Driver with type %d has not been registered\n",
  436. __func__, ulp_type);
  437. mutex_unlock(&cnic_lock);
  438. return -EAGAIN;
  439. }
  440. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  441. pr_err("%s: Type %d has already been registered to this device\n",
  442. __func__, ulp_type);
  443. mutex_unlock(&cnic_lock);
  444. return -EBUSY;
  445. }
  446. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  447. cp->ulp_handle[ulp_type] = ulp_ctx;
  448. ulp_ops = cnic_ulp_tbl[ulp_type];
  449. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  450. cnic_hold(dev);
  451. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  452. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  453. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  454. mutex_unlock(&cnic_lock);
  455. return 0;
  456. }
  457. EXPORT_SYMBOL(cnic_register_driver);
  458. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  459. {
  460. struct cnic_local *cp = dev->cnic_priv;
  461. int i = 0;
  462. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  463. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  464. return -EINVAL;
  465. }
  466. mutex_lock(&cnic_lock);
  467. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  468. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  469. cnic_put(dev);
  470. } else {
  471. pr_err("%s: device not registered to this ulp type %d\n",
  472. __func__, ulp_type);
  473. mutex_unlock(&cnic_lock);
  474. return -EINVAL;
  475. }
  476. mutex_unlock(&cnic_lock);
  477. synchronize_rcu();
  478. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  479. i < 20) {
  480. msleep(100);
  481. i++;
  482. }
  483. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  484. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  485. return 0;
  486. }
  487. EXPORT_SYMBOL(cnic_unregister_driver);
  488. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  489. {
  490. id_tbl->start = start_id;
  491. id_tbl->max = size;
  492. id_tbl->next = 0;
  493. spin_lock_init(&id_tbl->lock);
  494. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  495. if (!id_tbl->table)
  496. return -ENOMEM;
  497. return 0;
  498. }
  499. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  500. {
  501. kfree(id_tbl->table);
  502. id_tbl->table = NULL;
  503. }
  504. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  505. {
  506. int ret = -1;
  507. id -= id_tbl->start;
  508. if (id >= id_tbl->max)
  509. return ret;
  510. spin_lock(&id_tbl->lock);
  511. if (!test_bit(id, id_tbl->table)) {
  512. set_bit(id, id_tbl->table);
  513. ret = 0;
  514. }
  515. spin_unlock(&id_tbl->lock);
  516. return ret;
  517. }
  518. /* Returns -1 if not successful */
  519. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  520. {
  521. u32 id;
  522. spin_lock(&id_tbl->lock);
  523. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  524. if (id >= id_tbl->max) {
  525. id = -1;
  526. if (id_tbl->next != 0) {
  527. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  528. if (id >= id_tbl->next)
  529. id = -1;
  530. }
  531. }
  532. if (id < id_tbl->max) {
  533. set_bit(id, id_tbl->table);
  534. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  535. id += id_tbl->start;
  536. }
  537. spin_unlock(&id_tbl->lock);
  538. return id;
  539. }
  540. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  541. {
  542. if (id == -1)
  543. return;
  544. id -= id_tbl->start;
  545. if (id >= id_tbl->max)
  546. return;
  547. clear_bit(id, id_tbl->table);
  548. }
  549. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  550. {
  551. int i;
  552. if (!dma->pg_arr)
  553. return;
  554. for (i = 0; i < dma->num_pages; i++) {
  555. if (dma->pg_arr[i]) {
  556. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  557. dma->pg_arr[i], dma->pg_map_arr[i]);
  558. dma->pg_arr[i] = NULL;
  559. }
  560. }
  561. if (dma->pgtbl) {
  562. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  563. dma->pgtbl, dma->pgtbl_map);
  564. dma->pgtbl = NULL;
  565. }
  566. kfree(dma->pg_arr);
  567. dma->pg_arr = NULL;
  568. dma->num_pages = 0;
  569. }
  570. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  571. {
  572. int i;
  573. u32 *page_table = dma->pgtbl;
  574. for (i = 0; i < dma->num_pages; i++) {
  575. /* Each entry needs to be in big endian format. */
  576. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  577. page_table++;
  578. *page_table = (u32) dma->pg_map_arr[i];
  579. page_table++;
  580. }
  581. }
  582. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  583. {
  584. int i;
  585. u32 *page_table = dma->pgtbl;
  586. for (i = 0; i < dma->num_pages; i++) {
  587. /* Each entry needs to be in little endian format. */
  588. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  589. page_table++;
  590. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  591. page_table++;
  592. }
  593. }
  594. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  595. int pages, int use_pg_tbl)
  596. {
  597. int i, size;
  598. struct cnic_local *cp = dev->cnic_priv;
  599. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  600. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  601. if (dma->pg_arr == NULL)
  602. return -ENOMEM;
  603. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  604. dma->num_pages = pages;
  605. for (i = 0; i < pages; i++) {
  606. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  607. BCM_PAGE_SIZE,
  608. &dma->pg_map_arr[i],
  609. GFP_ATOMIC);
  610. if (dma->pg_arr[i] == NULL)
  611. goto error;
  612. }
  613. if (!use_pg_tbl)
  614. return 0;
  615. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  616. ~(BCM_PAGE_SIZE - 1);
  617. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  618. &dma->pgtbl_map, GFP_ATOMIC);
  619. if (dma->pgtbl == NULL)
  620. goto error;
  621. cp->setup_pgtbl(dev, dma);
  622. return 0;
  623. error:
  624. cnic_free_dma(dev, dma);
  625. return -ENOMEM;
  626. }
  627. static void cnic_free_context(struct cnic_dev *dev)
  628. {
  629. struct cnic_local *cp = dev->cnic_priv;
  630. int i;
  631. for (i = 0; i < cp->ctx_blks; i++) {
  632. if (cp->ctx_arr[i].ctx) {
  633. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  634. cp->ctx_arr[i].ctx,
  635. cp->ctx_arr[i].mapping);
  636. cp->ctx_arr[i].ctx = NULL;
  637. }
  638. }
  639. }
  640. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  641. {
  642. uio_unregister_device(&udev->cnic_uinfo);
  643. if (udev->l2_buf) {
  644. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  645. udev->l2_buf, udev->l2_buf_map);
  646. udev->l2_buf = NULL;
  647. }
  648. if (udev->l2_ring) {
  649. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  650. udev->l2_ring, udev->l2_ring_map);
  651. udev->l2_ring = NULL;
  652. }
  653. pci_dev_put(udev->pdev);
  654. kfree(udev);
  655. }
  656. static void cnic_free_uio(struct cnic_uio_dev *udev)
  657. {
  658. if (!udev)
  659. return;
  660. write_lock(&cnic_dev_lock);
  661. list_del_init(&udev->list);
  662. write_unlock(&cnic_dev_lock);
  663. __cnic_free_uio(udev);
  664. }
  665. static void cnic_free_resc(struct cnic_dev *dev)
  666. {
  667. struct cnic_local *cp = dev->cnic_priv;
  668. struct cnic_uio_dev *udev = cp->udev;
  669. if (udev) {
  670. udev->dev = NULL;
  671. cp->udev = NULL;
  672. }
  673. cnic_free_context(dev);
  674. kfree(cp->ctx_arr);
  675. cp->ctx_arr = NULL;
  676. cp->ctx_blks = 0;
  677. cnic_free_dma(dev, &cp->gbl_buf_info);
  678. cnic_free_dma(dev, &cp->conn_buf_info);
  679. cnic_free_dma(dev, &cp->kwq_info);
  680. cnic_free_dma(dev, &cp->kwq_16_data_info);
  681. cnic_free_dma(dev, &cp->kcq1.dma);
  682. kfree(cp->iscsi_tbl);
  683. cp->iscsi_tbl = NULL;
  684. kfree(cp->ctx_tbl);
  685. cp->ctx_tbl = NULL;
  686. cnic_free_id_tbl(&cp->cid_tbl);
  687. }
  688. static int cnic_alloc_context(struct cnic_dev *dev)
  689. {
  690. struct cnic_local *cp = dev->cnic_priv;
  691. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  692. int i, k, arr_size;
  693. cp->ctx_blk_size = BCM_PAGE_SIZE;
  694. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  695. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  696. sizeof(struct cnic_ctx);
  697. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  698. if (cp->ctx_arr == NULL)
  699. return -ENOMEM;
  700. k = 0;
  701. for (i = 0; i < 2; i++) {
  702. u32 j, reg, off, lo, hi;
  703. if (i == 0)
  704. off = BNX2_PG_CTX_MAP;
  705. else
  706. off = BNX2_ISCSI_CTX_MAP;
  707. reg = cnic_reg_rd_ind(dev, off);
  708. lo = reg >> 16;
  709. hi = reg & 0xffff;
  710. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  711. cp->ctx_arr[k].cid = j;
  712. }
  713. cp->ctx_blks = k;
  714. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  715. cp->ctx_blks = 0;
  716. return -ENOMEM;
  717. }
  718. for (i = 0; i < cp->ctx_blks; i++) {
  719. cp->ctx_arr[i].ctx =
  720. dma_alloc_coherent(&dev->pcidev->dev,
  721. BCM_PAGE_SIZE,
  722. &cp->ctx_arr[i].mapping,
  723. GFP_KERNEL);
  724. if (cp->ctx_arr[i].ctx == NULL)
  725. return -ENOMEM;
  726. }
  727. }
  728. return 0;
  729. }
  730. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  731. {
  732. int err, i, is_bnx2 = 0;
  733. struct kcqe **kcq;
  734. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  735. is_bnx2 = 1;
  736. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  737. if (err)
  738. return err;
  739. kcq = (struct kcqe **) info->dma.pg_arr;
  740. info->kcq = kcq;
  741. if (is_bnx2)
  742. return 0;
  743. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  744. struct bnx2x_bd_chain_next *next =
  745. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  746. int j = i + 1;
  747. if (j >= KCQ_PAGE_CNT)
  748. j = 0;
  749. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  750. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  751. }
  752. return 0;
  753. }
  754. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  755. {
  756. struct cnic_local *cp = dev->cnic_priv;
  757. struct cnic_uio_dev *udev;
  758. read_lock(&cnic_dev_lock);
  759. list_for_each_entry(udev, &cnic_udev_list, list) {
  760. if (udev->pdev == dev->pcidev) {
  761. udev->dev = dev;
  762. cp->udev = udev;
  763. read_unlock(&cnic_dev_lock);
  764. return 0;
  765. }
  766. }
  767. read_unlock(&cnic_dev_lock);
  768. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  769. if (!udev)
  770. return -ENOMEM;
  771. udev->uio_dev = -1;
  772. udev->dev = dev;
  773. udev->pdev = dev->pcidev;
  774. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  775. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  776. &udev->l2_ring_map,
  777. GFP_KERNEL | __GFP_COMP);
  778. if (!udev->l2_ring)
  779. return -ENOMEM;
  780. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  781. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  782. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  783. &udev->l2_buf_map,
  784. GFP_KERNEL | __GFP_COMP);
  785. if (!udev->l2_buf)
  786. return -ENOMEM;
  787. write_lock(&cnic_dev_lock);
  788. list_add(&udev->list, &cnic_udev_list);
  789. write_unlock(&cnic_dev_lock);
  790. pci_dev_get(udev->pdev);
  791. cp->udev = udev;
  792. return 0;
  793. }
  794. static int cnic_init_uio(struct cnic_dev *dev)
  795. {
  796. struct cnic_local *cp = dev->cnic_priv;
  797. struct cnic_uio_dev *udev = cp->udev;
  798. struct uio_info *uinfo;
  799. int ret = 0;
  800. if (!udev)
  801. return -ENOMEM;
  802. uinfo = &udev->cnic_uinfo;
  803. uinfo->mem[0].addr = dev->netdev->base_addr;
  804. uinfo->mem[0].internal_addr = dev->regview;
  805. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  806. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  807. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  808. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  809. PAGE_MASK;
  810. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  811. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  812. else
  813. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  814. uinfo->name = "bnx2_cnic";
  815. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  816. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  817. PAGE_MASK;
  818. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  819. uinfo->name = "bnx2x_cnic";
  820. }
  821. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  822. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  823. uinfo->mem[2].size = udev->l2_ring_size;
  824. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  825. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  826. uinfo->mem[3].size = udev->l2_buf_size;
  827. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  828. uinfo->version = CNIC_MODULE_VERSION;
  829. uinfo->irq = UIO_IRQ_CUSTOM;
  830. uinfo->open = cnic_uio_open;
  831. uinfo->release = cnic_uio_close;
  832. if (udev->uio_dev == -1) {
  833. if (!uinfo->priv) {
  834. uinfo->priv = udev;
  835. ret = uio_register_device(&udev->pdev->dev, uinfo);
  836. }
  837. } else {
  838. cnic_init_rings(dev);
  839. }
  840. return ret;
  841. }
  842. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  843. {
  844. struct cnic_local *cp = dev->cnic_priv;
  845. int ret;
  846. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  847. if (ret)
  848. goto error;
  849. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  850. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  851. if (ret)
  852. goto error;
  853. ret = cnic_alloc_context(dev);
  854. if (ret)
  855. goto error;
  856. ret = cnic_alloc_uio_rings(dev, 2);
  857. if (ret)
  858. goto error;
  859. ret = cnic_init_uio(dev);
  860. if (ret)
  861. goto error;
  862. return 0;
  863. error:
  864. cnic_free_resc(dev);
  865. return ret;
  866. }
  867. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  868. {
  869. struct cnic_local *cp = dev->cnic_priv;
  870. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  871. int total_mem, blks, i;
  872. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  873. blks = total_mem / ctx_blk_size;
  874. if (total_mem % ctx_blk_size)
  875. blks++;
  876. if (blks > cp->ethdev->ctx_tbl_len)
  877. return -ENOMEM;
  878. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  879. if (cp->ctx_arr == NULL)
  880. return -ENOMEM;
  881. cp->ctx_blks = blks;
  882. cp->ctx_blk_size = ctx_blk_size;
  883. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  884. cp->ctx_align = 0;
  885. else
  886. cp->ctx_align = ctx_blk_size;
  887. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  888. for (i = 0; i < blks; i++) {
  889. cp->ctx_arr[i].ctx =
  890. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  891. &cp->ctx_arr[i].mapping,
  892. GFP_KERNEL);
  893. if (cp->ctx_arr[i].ctx == NULL)
  894. return -ENOMEM;
  895. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  896. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  897. cnic_free_context(dev);
  898. cp->ctx_blk_size += cp->ctx_align;
  899. i = -1;
  900. continue;
  901. }
  902. }
  903. }
  904. return 0;
  905. }
  906. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  907. {
  908. struct cnic_local *cp = dev->cnic_priv;
  909. struct cnic_eth_dev *ethdev = cp->ethdev;
  910. u32 start_cid = ethdev->starting_cid;
  911. int i, j, n, ret, pages;
  912. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  913. cp->iro_arr = ethdev->iro_arr;
  914. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  915. cp->iscsi_start_cid = start_cid;
  916. if (start_cid < BNX2X_ISCSI_START_CID) {
  917. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  918. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  919. cp->max_cid_space += delta;
  920. }
  921. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  922. GFP_KERNEL);
  923. if (!cp->iscsi_tbl)
  924. goto error;
  925. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  926. cp->max_cid_space, GFP_KERNEL);
  927. if (!cp->ctx_tbl)
  928. goto error;
  929. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  930. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  931. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  932. }
  933. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  934. PAGE_SIZE;
  935. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  936. if (ret)
  937. return -ENOMEM;
  938. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  939. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  940. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  941. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  942. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  943. off;
  944. if ((i % n) == (n - 1))
  945. j++;
  946. }
  947. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  948. if (ret)
  949. goto error;
  950. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  951. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  952. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  953. if (ret)
  954. goto error;
  955. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  956. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  957. if (ret)
  958. goto error;
  959. ret = cnic_alloc_bnx2x_context(dev);
  960. if (ret)
  961. goto error;
  962. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  963. cp->l2_rx_ring_size = 15;
  964. ret = cnic_alloc_uio_rings(dev, 4);
  965. if (ret)
  966. goto error;
  967. ret = cnic_init_uio(dev);
  968. if (ret)
  969. goto error;
  970. return 0;
  971. error:
  972. cnic_free_resc(dev);
  973. return -ENOMEM;
  974. }
  975. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  976. {
  977. return cp->max_kwq_idx -
  978. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  979. }
  980. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  981. u32 num_wqes)
  982. {
  983. struct cnic_local *cp = dev->cnic_priv;
  984. struct kwqe *prod_qe;
  985. u16 prod, sw_prod, i;
  986. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  987. return -EAGAIN; /* bnx2 is down */
  988. spin_lock_bh(&cp->cnic_ulp_lock);
  989. if (num_wqes > cnic_kwq_avail(cp) &&
  990. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  991. spin_unlock_bh(&cp->cnic_ulp_lock);
  992. return -EAGAIN;
  993. }
  994. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  995. prod = cp->kwq_prod_idx;
  996. sw_prod = prod & MAX_KWQ_IDX;
  997. for (i = 0; i < num_wqes; i++) {
  998. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  999. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1000. prod++;
  1001. sw_prod = prod & MAX_KWQ_IDX;
  1002. }
  1003. cp->kwq_prod_idx = prod;
  1004. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1005. spin_unlock_bh(&cp->cnic_ulp_lock);
  1006. return 0;
  1007. }
  1008. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1009. union l5cm_specific_data *l5_data)
  1010. {
  1011. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1012. dma_addr_t map;
  1013. map = ctx->kwqe_data_mapping;
  1014. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1015. l5_data->phy_address.hi = (u64) map >> 32;
  1016. return ctx->kwqe_data;
  1017. }
  1018. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1019. u32 type, union l5cm_specific_data *l5_data)
  1020. {
  1021. struct cnic_local *cp = dev->cnic_priv;
  1022. struct l5cm_spe kwqe;
  1023. struct kwqe_16 *kwq[1];
  1024. int ret;
  1025. kwqe.hdr.conn_and_cmd_data =
  1026. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1027. BNX2X_HW_CID(cp, cid)));
  1028. kwqe.hdr.type = cpu_to_le16(type);
  1029. kwqe.hdr.reserved1 = 0;
  1030. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1031. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1032. kwq[0] = (struct kwqe_16 *) &kwqe;
  1033. spin_lock_bh(&cp->cnic_ulp_lock);
  1034. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1035. spin_unlock_bh(&cp->cnic_ulp_lock);
  1036. if (ret == 1)
  1037. return 0;
  1038. return -EBUSY;
  1039. }
  1040. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1041. struct kcqe *cqes[], u32 num_cqes)
  1042. {
  1043. struct cnic_local *cp = dev->cnic_priv;
  1044. struct cnic_ulp_ops *ulp_ops;
  1045. rcu_read_lock();
  1046. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1047. if (likely(ulp_ops)) {
  1048. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1049. cqes, num_cqes);
  1050. }
  1051. rcu_read_unlock();
  1052. }
  1053. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1054. {
  1055. struct cnic_local *cp = dev->cnic_priv;
  1056. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1057. int hq_bds, pages;
  1058. u32 pfid = cp->pfid;
  1059. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1060. cp->num_ccells = req1->num_ccells_per_conn;
  1061. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1062. cp->num_iscsi_tasks;
  1063. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1064. BNX2X_ISCSI_R2TQE_SIZE;
  1065. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1066. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1067. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1068. cp->num_cqs = req1->num_cqs;
  1069. if (!dev->max_iscsi_conn)
  1070. return 0;
  1071. /* init Tstorm RAM */
  1072. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1073. req1->rq_num_wqes);
  1074. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1075. PAGE_SIZE);
  1076. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1077. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1078. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1079. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1080. req1->num_tasks_per_conn);
  1081. /* init Ustorm RAM */
  1082. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1083. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1084. req1->rq_buffer_size);
  1085. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1086. PAGE_SIZE);
  1087. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1088. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1089. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1090. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1091. req1->num_tasks_per_conn);
  1092. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1093. req1->rq_num_wqes);
  1094. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1095. req1->cq_num_wqes);
  1096. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1097. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1098. /* init Xstorm RAM */
  1099. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1100. PAGE_SIZE);
  1101. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1102. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1103. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1104. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1105. req1->num_tasks_per_conn);
  1106. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1107. hq_bds);
  1108. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1109. req1->num_tasks_per_conn);
  1110. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1111. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1112. /* init Cstorm RAM */
  1113. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1114. PAGE_SIZE);
  1115. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1116. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1117. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1118. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1119. req1->num_tasks_per_conn);
  1120. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1121. req1->cq_num_wqes);
  1122. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1123. hq_bds);
  1124. return 0;
  1125. }
  1126. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1127. {
  1128. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1129. struct cnic_local *cp = dev->cnic_priv;
  1130. u32 pfid = cp->pfid;
  1131. struct iscsi_kcqe kcqe;
  1132. struct kcqe *cqes[1];
  1133. memset(&kcqe, 0, sizeof(kcqe));
  1134. if (!dev->max_iscsi_conn) {
  1135. kcqe.completion_status =
  1136. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1137. goto done;
  1138. }
  1139. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1140. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1141. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1142. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1143. req2->error_bit_map[1]);
  1144. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1145. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1146. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1147. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1148. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1149. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1150. req2->error_bit_map[1]);
  1151. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1152. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1153. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1154. done:
  1155. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1156. cqes[0] = (struct kcqe *) &kcqe;
  1157. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1158. return 0;
  1159. }
  1160. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1161. {
  1162. struct cnic_local *cp = dev->cnic_priv;
  1163. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1164. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1165. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1166. cnic_free_dma(dev, &iscsi->hq_info);
  1167. cnic_free_dma(dev, &iscsi->r2tq_info);
  1168. cnic_free_dma(dev, &iscsi->task_array_info);
  1169. }
  1170. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1171. ctx->cid = 0;
  1172. }
  1173. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1174. {
  1175. u32 cid;
  1176. int ret, pages;
  1177. struct cnic_local *cp = dev->cnic_priv;
  1178. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1179. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1180. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1181. if (cid == -1) {
  1182. ret = -ENOMEM;
  1183. goto error;
  1184. }
  1185. ctx->cid = cid;
  1186. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1187. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1188. if (ret)
  1189. goto error;
  1190. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1191. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1192. if (ret)
  1193. goto error;
  1194. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1195. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1196. if (ret)
  1197. goto error;
  1198. return 0;
  1199. error:
  1200. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1201. return ret;
  1202. }
  1203. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1204. struct regpair *ctx_addr)
  1205. {
  1206. struct cnic_local *cp = dev->cnic_priv;
  1207. struct cnic_eth_dev *ethdev = cp->ethdev;
  1208. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1209. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1210. unsigned long align_off = 0;
  1211. dma_addr_t ctx_map;
  1212. void *ctx;
  1213. if (cp->ctx_align) {
  1214. unsigned long mask = cp->ctx_align - 1;
  1215. if (cp->ctx_arr[blk].mapping & mask)
  1216. align_off = cp->ctx_align -
  1217. (cp->ctx_arr[blk].mapping & mask);
  1218. }
  1219. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1220. (off * BNX2X_CONTEXT_MEM_SIZE);
  1221. ctx = cp->ctx_arr[blk].ctx + align_off +
  1222. (off * BNX2X_CONTEXT_MEM_SIZE);
  1223. if (init)
  1224. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1225. ctx_addr->lo = ctx_map & 0xffffffff;
  1226. ctx_addr->hi = (u64) ctx_map >> 32;
  1227. return ctx;
  1228. }
  1229. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1230. u32 num)
  1231. {
  1232. struct cnic_local *cp = dev->cnic_priv;
  1233. struct iscsi_kwqe_conn_offload1 *req1 =
  1234. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1235. struct iscsi_kwqe_conn_offload2 *req2 =
  1236. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1237. struct iscsi_kwqe_conn_offload3 *req3;
  1238. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1239. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1240. u32 cid = ctx->cid;
  1241. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1242. struct iscsi_context *ictx;
  1243. struct regpair context_addr;
  1244. int i, j, n = 2, n_max;
  1245. ctx->ctx_flags = 0;
  1246. if (!req2->num_additional_wqes)
  1247. return -EINVAL;
  1248. n_max = req2->num_additional_wqes + 2;
  1249. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1250. if (ictx == NULL)
  1251. return -ENOMEM;
  1252. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1253. ictx->xstorm_ag_context.hq_prod = 1;
  1254. ictx->xstorm_st_context.iscsi.first_burst_length =
  1255. ISCSI_DEF_FIRST_BURST_LEN;
  1256. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1257. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1258. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1259. req1->sq_page_table_addr_lo;
  1260. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1261. req1->sq_page_table_addr_hi;
  1262. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1263. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1264. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1265. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1266. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1267. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1268. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1269. iscsi->hq_info.pgtbl[0];
  1270. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1271. iscsi->hq_info.pgtbl[1];
  1272. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1273. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1274. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1275. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1276. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1277. iscsi->r2tq_info.pgtbl[0];
  1278. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1279. iscsi->r2tq_info.pgtbl[1];
  1280. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1281. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1282. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1283. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1284. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1285. BNX2X_ISCSI_PBL_NOT_CACHED;
  1286. ictx->xstorm_st_context.iscsi.flags.flags |=
  1287. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1288. ictx->xstorm_st_context.iscsi.flags.flags |=
  1289. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1290. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1291. /* TSTORM requires the base address of RQ DB & not PTE */
  1292. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1293. req2->rq_page_table_addr_lo & PAGE_MASK;
  1294. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1295. req2->rq_page_table_addr_hi;
  1296. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1297. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1298. ictx->tstorm_st_context.tcp.flags2 |=
  1299. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1300. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1301. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1302. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1303. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1304. req2->rq_page_table_addr_lo;
  1305. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1306. req2->rq_page_table_addr_hi;
  1307. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1308. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1309. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1310. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1311. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1312. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1313. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1314. iscsi->r2tq_info.pgtbl[0];
  1315. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1316. iscsi->r2tq_info.pgtbl[1];
  1317. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1318. req1->cq_page_table_addr_lo;
  1319. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1320. req1->cq_page_table_addr_hi;
  1321. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1322. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1323. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1324. ictx->ustorm_st_context.task_pbe_cache_index =
  1325. BNX2X_ISCSI_PBL_NOT_CACHED;
  1326. ictx->ustorm_st_context.task_pdu_cache_index =
  1327. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1328. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1329. if (j == 3) {
  1330. if (n >= n_max)
  1331. break;
  1332. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1333. j = 0;
  1334. }
  1335. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1336. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1337. req3->qp_first_pte[j].hi;
  1338. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1339. req3->qp_first_pte[j].lo;
  1340. }
  1341. ictx->ustorm_st_context.task_pbl_base.lo =
  1342. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1343. ictx->ustorm_st_context.task_pbl_base.hi =
  1344. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1345. ictx->ustorm_st_context.tce_phy_addr.lo =
  1346. iscsi->task_array_info.pgtbl[0];
  1347. ictx->ustorm_st_context.tce_phy_addr.hi =
  1348. iscsi->task_array_info.pgtbl[1];
  1349. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1350. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1351. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1352. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1353. ISCSI_DEF_MAX_BURST_LEN;
  1354. ictx->ustorm_st_context.negotiated_rx |=
  1355. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1356. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1357. ictx->cstorm_st_context.hq_pbl_base.lo =
  1358. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1359. ictx->cstorm_st_context.hq_pbl_base.hi =
  1360. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1361. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1362. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1363. ictx->cstorm_st_context.task_pbl_base.lo =
  1364. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1365. ictx->cstorm_st_context.task_pbl_base.hi =
  1366. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1367. /* CSTORM and USTORM initialization is different, CSTORM requires
  1368. * CQ DB base & not PTE addr */
  1369. ictx->cstorm_st_context.cq_db_base.lo =
  1370. req1->cq_page_table_addr_lo & PAGE_MASK;
  1371. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1372. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1373. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1374. for (i = 0; i < cp->num_cqs; i++) {
  1375. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1376. ISCSI_INITIAL_SN;
  1377. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1378. ISCSI_INITIAL_SN;
  1379. }
  1380. ictx->xstorm_ag_context.cdu_reserved =
  1381. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1382. ISCSI_CONNECTION_TYPE);
  1383. ictx->ustorm_ag_context.cdu_usage =
  1384. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1385. ISCSI_CONNECTION_TYPE);
  1386. return 0;
  1387. }
  1388. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1389. u32 num, int *work)
  1390. {
  1391. struct iscsi_kwqe_conn_offload1 *req1;
  1392. struct iscsi_kwqe_conn_offload2 *req2;
  1393. struct cnic_local *cp = dev->cnic_priv;
  1394. struct cnic_context *ctx;
  1395. struct iscsi_kcqe kcqe;
  1396. struct kcqe *cqes[1];
  1397. u32 l5_cid;
  1398. int ret = 0;
  1399. if (num < 2) {
  1400. *work = num;
  1401. return -EINVAL;
  1402. }
  1403. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1404. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1405. if ((num - 2) < req2->num_additional_wqes) {
  1406. *work = num;
  1407. return -EINVAL;
  1408. }
  1409. *work = 2 + req2->num_additional_wqes;
  1410. l5_cid = req1->iscsi_conn_id;
  1411. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1412. return -EINVAL;
  1413. memset(&kcqe, 0, sizeof(kcqe));
  1414. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1415. kcqe.iscsi_conn_id = l5_cid;
  1416. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1417. ctx = &cp->ctx_tbl[l5_cid];
  1418. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1419. kcqe.completion_status =
  1420. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1421. goto done;
  1422. }
  1423. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1424. atomic_dec(&cp->iscsi_conn);
  1425. goto done;
  1426. }
  1427. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1428. if (ret) {
  1429. atomic_dec(&cp->iscsi_conn);
  1430. ret = 0;
  1431. goto done;
  1432. }
  1433. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1434. if (ret < 0) {
  1435. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1436. atomic_dec(&cp->iscsi_conn);
  1437. goto done;
  1438. }
  1439. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1440. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1441. done:
  1442. cqes[0] = (struct kcqe *) &kcqe;
  1443. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1444. return ret;
  1445. }
  1446. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1447. {
  1448. struct cnic_local *cp = dev->cnic_priv;
  1449. struct iscsi_kwqe_conn_update *req =
  1450. (struct iscsi_kwqe_conn_update *) kwqe;
  1451. void *data;
  1452. union l5cm_specific_data l5_data;
  1453. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1454. int ret;
  1455. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1456. return -EINVAL;
  1457. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1458. if (!data)
  1459. return -ENOMEM;
  1460. memcpy(data, kwqe, sizeof(struct kwqe));
  1461. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1462. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1463. return ret;
  1464. }
  1465. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1466. {
  1467. struct cnic_local *cp = dev->cnic_priv;
  1468. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1469. union l5cm_specific_data l5_data;
  1470. int ret;
  1471. u32 hw_cid, type;
  1472. init_waitqueue_head(&ctx->waitq);
  1473. ctx->wait_cond = 0;
  1474. memset(&l5_data, 0, sizeof(l5_data));
  1475. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1476. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  1477. & SPE_HDR_CONN_TYPE;
  1478. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1479. SPE_HDR_FUNCTION_ID);
  1480. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1481. hw_cid, type, &l5_data);
  1482. if (ret == 0)
  1483. wait_event(ctx->waitq, ctx->wait_cond);
  1484. return ret;
  1485. }
  1486. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1487. {
  1488. struct cnic_local *cp = dev->cnic_priv;
  1489. struct iscsi_kwqe_conn_destroy *req =
  1490. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1491. u32 l5_cid = req->reserved0;
  1492. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1493. int ret = 0;
  1494. struct iscsi_kcqe kcqe;
  1495. struct kcqe *cqes[1];
  1496. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1497. goto skip_cfc_delete;
  1498. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1499. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1500. if (delta > (2 * HZ))
  1501. delta = 0;
  1502. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1503. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1504. goto destroy_reply;
  1505. }
  1506. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1507. skip_cfc_delete:
  1508. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1509. atomic_dec(&cp->iscsi_conn);
  1510. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1511. destroy_reply:
  1512. memset(&kcqe, 0, sizeof(kcqe));
  1513. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1514. kcqe.iscsi_conn_id = l5_cid;
  1515. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1516. kcqe.iscsi_conn_context_id = req->context_id;
  1517. cqes[0] = (struct kcqe *) &kcqe;
  1518. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1519. return ret;
  1520. }
  1521. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1522. struct l4_kwq_connect_req1 *kwqe1,
  1523. struct l4_kwq_connect_req3 *kwqe3,
  1524. struct l5cm_active_conn_buffer *conn_buf)
  1525. {
  1526. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1527. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1528. &conn_buf->xstorm_conn_buffer;
  1529. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1530. &conn_buf->tstorm_conn_buffer;
  1531. struct regpair context_addr;
  1532. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1533. struct in6_addr src_ip, dst_ip;
  1534. int i;
  1535. u32 *addrp;
  1536. addrp = (u32 *) &conn_addr->local_ip_addr;
  1537. for (i = 0; i < 4; i++, addrp++)
  1538. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1539. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1540. for (i = 0; i < 4; i++, addrp++)
  1541. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1542. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1543. xstorm_buf->context_addr.hi = context_addr.hi;
  1544. xstorm_buf->context_addr.lo = context_addr.lo;
  1545. xstorm_buf->mss = 0xffff;
  1546. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1547. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1548. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1549. xstorm_buf->pseudo_header_checksum =
  1550. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1551. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1552. tstorm_buf->params |=
  1553. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1554. if (kwqe3->ka_timeout) {
  1555. tstorm_buf->ka_enable = 1;
  1556. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1557. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1558. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1559. }
  1560. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1561. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1562. tstorm_buf->max_rt_time = 0xffffffff;
  1563. }
  1564. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1565. {
  1566. struct cnic_local *cp = dev->cnic_priv;
  1567. u32 pfid = cp->pfid;
  1568. u8 *mac = dev->mac_addr;
  1569. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1570. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1571. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1572. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1573. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1574. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1575. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1576. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1577. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1578. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1579. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1580. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1581. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1582. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1583. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1584. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1585. mac[4]);
  1586. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1587. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1588. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1589. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1590. mac[2]);
  1591. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1592. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1593. mac[1]);
  1594. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1595. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1596. mac[0]);
  1597. }
  1598. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1599. {
  1600. struct cnic_local *cp = dev->cnic_priv;
  1601. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1602. u16 tstorm_flags = 0;
  1603. if (tcp_ts) {
  1604. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1605. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1606. }
  1607. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1608. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1609. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1610. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1611. }
  1612. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1613. u32 num, int *work)
  1614. {
  1615. struct cnic_local *cp = dev->cnic_priv;
  1616. struct l4_kwq_connect_req1 *kwqe1 =
  1617. (struct l4_kwq_connect_req1 *) wqes[0];
  1618. struct l4_kwq_connect_req3 *kwqe3;
  1619. struct l5cm_active_conn_buffer *conn_buf;
  1620. struct l5cm_conn_addr_params *conn_addr;
  1621. union l5cm_specific_data l5_data;
  1622. u32 l5_cid = kwqe1->pg_cid;
  1623. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1624. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1625. int ret;
  1626. if (num < 2) {
  1627. *work = num;
  1628. return -EINVAL;
  1629. }
  1630. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1631. *work = 3;
  1632. else
  1633. *work = 2;
  1634. if (num < *work) {
  1635. *work = num;
  1636. return -EINVAL;
  1637. }
  1638. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1639. netdev_err(dev->netdev, "conn_buf size too big\n");
  1640. return -ENOMEM;
  1641. }
  1642. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1643. if (!conn_buf)
  1644. return -ENOMEM;
  1645. memset(conn_buf, 0, sizeof(*conn_buf));
  1646. conn_addr = &conn_buf->conn_addr_buf;
  1647. conn_addr->remote_addr_0 = csk->ha[0];
  1648. conn_addr->remote_addr_1 = csk->ha[1];
  1649. conn_addr->remote_addr_2 = csk->ha[2];
  1650. conn_addr->remote_addr_3 = csk->ha[3];
  1651. conn_addr->remote_addr_4 = csk->ha[4];
  1652. conn_addr->remote_addr_5 = csk->ha[5];
  1653. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1654. struct l4_kwq_connect_req2 *kwqe2 =
  1655. (struct l4_kwq_connect_req2 *) wqes[1];
  1656. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1657. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1658. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1659. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1660. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1661. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1662. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1663. }
  1664. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1665. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1666. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1667. conn_addr->local_tcp_port = kwqe1->src_port;
  1668. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1669. conn_addr->pmtu = kwqe3->pmtu;
  1670. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1671. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1672. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1673. cnic_bnx2x_set_tcp_timestamp(dev,
  1674. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1675. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1676. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1677. if (!ret)
  1678. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1679. return ret;
  1680. }
  1681. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1682. {
  1683. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1684. union l5cm_specific_data l5_data;
  1685. int ret;
  1686. memset(&l5_data, 0, sizeof(l5_data));
  1687. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1688. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1689. return ret;
  1690. }
  1691. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1692. {
  1693. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1694. union l5cm_specific_data l5_data;
  1695. int ret;
  1696. memset(&l5_data, 0, sizeof(l5_data));
  1697. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1698. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1699. return ret;
  1700. }
  1701. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1702. {
  1703. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1704. struct l4_kcq kcqe;
  1705. struct kcqe *cqes[1];
  1706. memset(&kcqe, 0, sizeof(kcqe));
  1707. kcqe.pg_host_opaque = req->host_opaque;
  1708. kcqe.pg_cid = req->host_opaque;
  1709. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1710. cqes[0] = (struct kcqe *) &kcqe;
  1711. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1712. return 0;
  1713. }
  1714. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1715. {
  1716. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1717. struct l4_kcq kcqe;
  1718. struct kcqe *cqes[1];
  1719. memset(&kcqe, 0, sizeof(kcqe));
  1720. kcqe.pg_host_opaque = req->pg_host_opaque;
  1721. kcqe.pg_cid = req->pg_cid;
  1722. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1723. cqes[0] = (struct kcqe *) &kcqe;
  1724. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1725. return 0;
  1726. }
  1727. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1728. u32 num_wqes)
  1729. {
  1730. int i, work, ret;
  1731. u32 opcode;
  1732. struct kwqe *kwqe;
  1733. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1734. return -EAGAIN; /* bnx2 is down */
  1735. for (i = 0; i < num_wqes; ) {
  1736. kwqe = wqes[i];
  1737. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1738. work = 1;
  1739. switch (opcode) {
  1740. case ISCSI_KWQE_OPCODE_INIT1:
  1741. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1742. break;
  1743. case ISCSI_KWQE_OPCODE_INIT2:
  1744. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1745. break;
  1746. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1747. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1748. num_wqes - i, &work);
  1749. break;
  1750. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1751. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1752. break;
  1753. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1754. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1755. break;
  1756. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1757. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1758. &work);
  1759. break;
  1760. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1761. ret = cnic_bnx2x_close(dev, kwqe);
  1762. break;
  1763. case L4_KWQE_OPCODE_VALUE_RESET:
  1764. ret = cnic_bnx2x_reset(dev, kwqe);
  1765. break;
  1766. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1767. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1768. break;
  1769. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1770. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1771. break;
  1772. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1773. ret = 0;
  1774. break;
  1775. default:
  1776. ret = 0;
  1777. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1778. opcode);
  1779. break;
  1780. }
  1781. if (ret < 0)
  1782. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1783. opcode);
  1784. i += work;
  1785. }
  1786. return 0;
  1787. }
  1788. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1789. {
  1790. struct cnic_local *cp = dev->cnic_priv;
  1791. int i, j, comp = 0;
  1792. i = 0;
  1793. j = 1;
  1794. while (num_cqes) {
  1795. struct cnic_ulp_ops *ulp_ops;
  1796. int ulp_type;
  1797. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1798. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1799. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1800. comp++;
  1801. while (j < num_cqes) {
  1802. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1803. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1804. break;
  1805. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1806. comp++;
  1807. j++;
  1808. }
  1809. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1810. ulp_type = CNIC_ULP_RDMA;
  1811. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1812. ulp_type = CNIC_ULP_ISCSI;
  1813. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1814. ulp_type = CNIC_ULP_L4;
  1815. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1816. goto end;
  1817. else {
  1818. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1819. kcqe_op_flag);
  1820. goto end;
  1821. }
  1822. rcu_read_lock();
  1823. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1824. if (likely(ulp_ops)) {
  1825. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1826. cp->completed_kcq + i, j);
  1827. }
  1828. rcu_read_unlock();
  1829. end:
  1830. num_cqes -= j;
  1831. i += j;
  1832. j = 1;
  1833. }
  1834. if (unlikely(comp))
  1835. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  1836. }
  1837. static u16 cnic_bnx2_next_idx(u16 idx)
  1838. {
  1839. return idx + 1;
  1840. }
  1841. static u16 cnic_bnx2_hw_idx(u16 idx)
  1842. {
  1843. return idx;
  1844. }
  1845. static u16 cnic_bnx2x_next_idx(u16 idx)
  1846. {
  1847. idx++;
  1848. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1849. idx++;
  1850. return idx;
  1851. }
  1852. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1853. {
  1854. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1855. idx++;
  1856. return idx;
  1857. }
  1858. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  1859. {
  1860. struct cnic_local *cp = dev->cnic_priv;
  1861. u16 i, ri, hw_prod, last;
  1862. struct kcqe *kcqe;
  1863. int kcqe_cnt = 0, last_cnt = 0;
  1864. i = ri = last = info->sw_prod_idx;
  1865. ri &= MAX_KCQ_IDX;
  1866. hw_prod = *info->hw_prod_idx_ptr;
  1867. hw_prod = cp->hw_idx(hw_prod);
  1868. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1869. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1870. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1871. i = cp->next_idx(i);
  1872. ri = i & MAX_KCQ_IDX;
  1873. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1874. last_cnt = kcqe_cnt;
  1875. last = i;
  1876. }
  1877. }
  1878. info->sw_prod_idx = last;
  1879. return last_cnt;
  1880. }
  1881. static int cnic_l2_completion(struct cnic_local *cp)
  1882. {
  1883. u16 hw_cons, sw_cons;
  1884. struct cnic_uio_dev *udev = cp->udev;
  1885. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  1886. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  1887. u32 cmd;
  1888. int comp = 0;
  1889. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  1890. return 0;
  1891. hw_cons = *cp->rx_cons_ptr;
  1892. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  1893. hw_cons++;
  1894. sw_cons = cp->rx_cons;
  1895. while (sw_cons != hw_cons) {
  1896. u8 cqe_fp_flags;
  1897. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  1898. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1899. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  1900. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  1901. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  1902. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  1903. cmd == RAMROD_CMD_ID_ETH_HALT)
  1904. comp++;
  1905. }
  1906. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  1907. }
  1908. return comp;
  1909. }
  1910. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1911. {
  1912. u16 rx_cons, tx_cons;
  1913. int comp = 0;
  1914. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  1915. return;
  1916. rx_cons = *cp->rx_cons_ptr;
  1917. tx_cons = *cp->tx_cons_ptr;
  1918. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1919. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  1920. comp = cnic_l2_completion(cp);
  1921. cp->tx_cons = tx_cons;
  1922. cp->rx_cons = rx_cons;
  1923. if (cp->udev)
  1924. uio_event_notify(&cp->udev->cnic_uinfo);
  1925. }
  1926. if (comp)
  1927. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  1928. }
  1929. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  1930. {
  1931. struct cnic_local *cp = dev->cnic_priv;
  1932. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1933. int kcqe_cnt;
  1934. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1935. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  1936. service_kcqes(dev, kcqe_cnt);
  1937. /* Tell compiler that status_blk fields can change. */
  1938. barrier();
  1939. if (status_idx != *cp->kcq1.status_idx_ptr) {
  1940. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1941. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1942. } else
  1943. break;
  1944. }
  1945. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  1946. cnic_chk_pkt_rings(cp);
  1947. return status_idx;
  1948. }
  1949. static int cnic_service_bnx2(void *data, void *status_blk)
  1950. {
  1951. struct cnic_dev *dev = data;
  1952. struct cnic_local *cp = dev->cnic_priv;
  1953. u32 status_idx = *cp->kcq1.status_idx_ptr;
  1954. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1955. return status_idx;
  1956. return cnic_service_bnx2_queues(dev);
  1957. }
  1958. static void cnic_service_bnx2_msix(unsigned long data)
  1959. {
  1960. struct cnic_dev *dev = (struct cnic_dev *) data;
  1961. struct cnic_local *cp = dev->cnic_priv;
  1962. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  1963. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1964. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1965. }
  1966. static void cnic_doirq(struct cnic_dev *dev)
  1967. {
  1968. struct cnic_local *cp = dev->cnic_priv;
  1969. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  1970. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  1971. prefetch(cp->status_blk.gen);
  1972. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1973. tasklet_schedule(&cp->cnic_irq_task);
  1974. }
  1975. }
  1976. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1977. {
  1978. struct cnic_dev *dev = dev_instance;
  1979. struct cnic_local *cp = dev->cnic_priv;
  1980. if (cp->ack_int)
  1981. cp->ack_int(dev);
  1982. cnic_doirq(dev);
  1983. return IRQ_HANDLED;
  1984. }
  1985. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1986. u16 index, u8 op, u8 update)
  1987. {
  1988. struct cnic_local *cp = dev->cnic_priv;
  1989. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1990. COMMAND_REG_INT_ACK);
  1991. struct igu_ack_register igu_ack;
  1992. igu_ack.status_block_index = index;
  1993. igu_ack.sb_id_and_flags =
  1994. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1995. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1996. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1997. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1998. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1999. }
  2000. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2001. u16 index, u8 op, u8 update)
  2002. {
  2003. struct igu_regular cmd_data;
  2004. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2005. cmd_data.sb_id_and_flags =
  2006. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2007. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2008. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2009. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2010. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2011. }
  2012. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2013. {
  2014. struct cnic_local *cp = dev->cnic_priv;
  2015. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2016. IGU_INT_DISABLE, 0);
  2017. }
  2018. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2019. {
  2020. struct cnic_local *cp = dev->cnic_priv;
  2021. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2022. IGU_INT_DISABLE, 0);
  2023. }
  2024. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2025. {
  2026. u32 last_status = *info->status_idx_ptr;
  2027. int kcqe_cnt;
  2028. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2029. service_kcqes(dev, kcqe_cnt);
  2030. /* Tell compiler that sblk fields can change. */
  2031. barrier();
  2032. if (last_status == *info->status_idx_ptr)
  2033. break;
  2034. last_status = *info->status_idx_ptr;
  2035. }
  2036. return last_status;
  2037. }
  2038. static void cnic_service_bnx2x_bh(unsigned long data)
  2039. {
  2040. struct cnic_dev *dev = (struct cnic_dev *) data;
  2041. struct cnic_local *cp = dev->cnic_priv;
  2042. u32 status_idx;
  2043. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2044. return;
  2045. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2046. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2047. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  2048. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2049. status_idx, IGU_INT_ENABLE, 1);
  2050. else
  2051. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2052. status_idx, IGU_INT_ENABLE, 1);
  2053. }
  2054. static int cnic_service_bnx2x(void *data, void *status_blk)
  2055. {
  2056. struct cnic_dev *dev = data;
  2057. struct cnic_local *cp = dev->cnic_priv;
  2058. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2059. cnic_doirq(dev);
  2060. cnic_chk_pkt_rings(cp);
  2061. return 0;
  2062. }
  2063. static void cnic_ulp_stop(struct cnic_dev *dev)
  2064. {
  2065. struct cnic_local *cp = dev->cnic_priv;
  2066. int if_type;
  2067. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2068. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2069. struct cnic_ulp_ops *ulp_ops;
  2070. mutex_lock(&cnic_lock);
  2071. ulp_ops = cp->ulp_ops[if_type];
  2072. if (!ulp_ops) {
  2073. mutex_unlock(&cnic_lock);
  2074. continue;
  2075. }
  2076. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2077. mutex_unlock(&cnic_lock);
  2078. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2079. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2080. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2081. }
  2082. }
  2083. static void cnic_ulp_start(struct cnic_dev *dev)
  2084. {
  2085. struct cnic_local *cp = dev->cnic_priv;
  2086. int if_type;
  2087. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2088. struct cnic_ulp_ops *ulp_ops;
  2089. mutex_lock(&cnic_lock);
  2090. ulp_ops = cp->ulp_ops[if_type];
  2091. if (!ulp_ops || !ulp_ops->cnic_start) {
  2092. mutex_unlock(&cnic_lock);
  2093. continue;
  2094. }
  2095. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2096. mutex_unlock(&cnic_lock);
  2097. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2098. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2099. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2100. }
  2101. }
  2102. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2103. {
  2104. struct cnic_dev *dev = data;
  2105. switch (info->cmd) {
  2106. case CNIC_CTL_STOP_CMD:
  2107. cnic_hold(dev);
  2108. cnic_ulp_stop(dev);
  2109. cnic_stop_hw(dev);
  2110. cnic_put(dev);
  2111. break;
  2112. case CNIC_CTL_START_CMD:
  2113. cnic_hold(dev);
  2114. if (!cnic_start_hw(dev))
  2115. cnic_ulp_start(dev);
  2116. cnic_put(dev);
  2117. break;
  2118. case CNIC_CTL_COMPLETION_CMD: {
  2119. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2120. u32 l5_cid;
  2121. struct cnic_local *cp = dev->cnic_priv;
  2122. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2123. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2124. ctx->wait_cond = 1;
  2125. wake_up(&ctx->waitq);
  2126. }
  2127. break;
  2128. }
  2129. default:
  2130. return -EINVAL;
  2131. }
  2132. return 0;
  2133. }
  2134. static void cnic_ulp_init(struct cnic_dev *dev)
  2135. {
  2136. int i;
  2137. struct cnic_local *cp = dev->cnic_priv;
  2138. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2139. struct cnic_ulp_ops *ulp_ops;
  2140. mutex_lock(&cnic_lock);
  2141. ulp_ops = cnic_ulp_tbl[i];
  2142. if (!ulp_ops || !ulp_ops->cnic_init) {
  2143. mutex_unlock(&cnic_lock);
  2144. continue;
  2145. }
  2146. ulp_get(ulp_ops);
  2147. mutex_unlock(&cnic_lock);
  2148. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2149. ulp_ops->cnic_init(dev);
  2150. ulp_put(ulp_ops);
  2151. }
  2152. }
  2153. static void cnic_ulp_exit(struct cnic_dev *dev)
  2154. {
  2155. int i;
  2156. struct cnic_local *cp = dev->cnic_priv;
  2157. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2158. struct cnic_ulp_ops *ulp_ops;
  2159. mutex_lock(&cnic_lock);
  2160. ulp_ops = cnic_ulp_tbl[i];
  2161. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2162. mutex_unlock(&cnic_lock);
  2163. continue;
  2164. }
  2165. ulp_get(ulp_ops);
  2166. mutex_unlock(&cnic_lock);
  2167. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2168. ulp_ops->cnic_exit(dev);
  2169. ulp_put(ulp_ops);
  2170. }
  2171. }
  2172. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2173. {
  2174. struct cnic_dev *dev = csk->dev;
  2175. struct l4_kwq_offload_pg *l4kwqe;
  2176. struct kwqe *wqes[1];
  2177. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2178. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2179. wqes[0] = (struct kwqe *) l4kwqe;
  2180. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2181. l4kwqe->flags =
  2182. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2183. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2184. l4kwqe->da0 = csk->ha[0];
  2185. l4kwqe->da1 = csk->ha[1];
  2186. l4kwqe->da2 = csk->ha[2];
  2187. l4kwqe->da3 = csk->ha[3];
  2188. l4kwqe->da4 = csk->ha[4];
  2189. l4kwqe->da5 = csk->ha[5];
  2190. l4kwqe->sa0 = dev->mac_addr[0];
  2191. l4kwqe->sa1 = dev->mac_addr[1];
  2192. l4kwqe->sa2 = dev->mac_addr[2];
  2193. l4kwqe->sa3 = dev->mac_addr[3];
  2194. l4kwqe->sa4 = dev->mac_addr[4];
  2195. l4kwqe->sa5 = dev->mac_addr[5];
  2196. l4kwqe->etype = ETH_P_IP;
  2197. l4kwqe->ipid_start = DEF_IPID_START;
  2198. l4kwqe->host_opaque = csk->l5_cid;
  2199. if (csk->vlan_id) {
  2200. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2201. l4kwqe->vlan_tag = csk->vlan_id;
  2202. l4kwqe->l2hdr_nbytes += 4;
  2203. }
  2204. return dev->submit_kwqes(dev, wqes, 1);
  2205. }
  2206. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2207. {
  2208. struct cnic_dev *dev = csk->dev;
  2209. struct l4_kwq_update_pg *l4kwqe;
  2210. struct kwqe *wqes[1];
  2211. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2212. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2213. wqes[0] = (struct kwqe *) l4kwqe;
  2214. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2215. l4kwqe->flags =
  2216. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2217. l4kwqe->pg_cid = csk->pg_cid;
  2218. l4kwqe->da0 = csk->ha[0];
  2219. l4kwqe->da1 = csk->ha[1];
  2220. l4kwqe->da2 = csk->ha[2];
  2221. l4kwqe->da3 = csk->ha[3];
  2222. l4kwqe->da4 = csk->ha[4];
  2223. l4kwqe->da5 = csk->ha[5];
  2224. l4kwqe->pg_host_opaque = csk->l5_cid;
  2225. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2226. return dev->submit_kwqes(dev, wqes, 1);
  2227. }
  2228. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2229. {
  2230. struct cnic_dev *dev = csk->dev;
  2231. struct l4_kwq_upload *l4kwqe;
  2232. struct kwqe *wqes[1];
  2233. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2234. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2235. wqes[0] = (struct kwqe *) l4kwqe;
  2236. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2237. l4kwqe->flags =
  2238. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2239. l4kwqe->cid = csk->pg_cid;
  2240. return dev->submit_kwqes(dev, wqes, 1);
  2241. }
  2242. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2243. {
  2244. struct cnic_dev *dev = csk->dev;
  2245. struct l4_kwq_connect_req1 *l4kwqe1;
  2246. struct l4_kwq_connect_req2 *l4kwqe2;
  2247. struct l4_kwq_connect_req3 *l4kwqe3;
  2248. struct kwqe *wqes[3];
  2249. u8 tcp_flags = 0;
  2250. int num_wqes = 2;
  2251. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2252. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2253. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2254. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2255. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2256. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2257. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2258. l4kwqe3->flags =
  2259. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2260. l4kwqe3->ka_timeout = csk->ka_timeout;
  2261. l4kwqe3->ka_interval = csk->ka_interval;
  2262. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2263. l4kwqe3->tos = csk->tos;
  2264. l4kwqe3->ttl = csk->ttl;
  2265. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2266. l4kwqe3->pmtu = csk->mtu;
  2267. l4kwqe3->rcv_buf = csk->rcv_buf;
  2268. l4kwqe3->snd_buf = csk->snd_buf;
  2269. l4kwqe3->seed = csk->seed;
  2270. wqes[0] = (struct kwqe *) l4kwqe1;
  2271. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2272. wqes[1] = (struct kwqe *) l4kwqe2;
  2273. wqes[2] = (struct kwqe *) l4kwqe3;
  2274. num_wqes = 3;
  2275. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2276. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2277. l4kwqe2->flags =
  2278. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2279. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2280. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2281. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2282. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2283. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2284. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2285. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2286. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2287. sizeof(struct tcphdr);
  2288. } else {
  2289. wqes[1] = (struct kwqe *) l4kwqe3;
  2290. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2291. sizeof(struct tcphdr);
  2292. }
  2293. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2294. l4kwqe1->flags =
  2295. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2296. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2297. l4kwqe1->cid = csk->cid;
  2298. l4kwqe1->pg_cid = csk->pg_cid;
  2299. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2300. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2301. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2302. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2303. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2304. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2305. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2306. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2307. if (csk->tcp_flags & SK_TCP_NAGLE)
  2308. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2309. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2310. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2311. if (csk->tcp_flags & SK_TCP_SACK)
  2312. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2313. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2314. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2315. l4kwqe1->tcp_flags = tcp_flags;
  2316. return dev->submit_kwqes(dev, wqes, num_wqes);
  2317. }
  2318. static int cnic_cm_close_req(struct cnic_sock *csk)
  2319. {
  2320. struct cnic_dev *dev = csk->dev;
  2321. struct l4_kwq_close_req *l4kwqe;
  2322. struct kwqe *wqes[1];
  2323. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2324. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2325. wqes[0] = (struct kwqe *) l4kwqe;
  2326. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2327. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2328. l4kwqe->cid = csk->cid;
  2329. return dev->submit_kwqes(dev, wqes, 1);
  2330. }
  2331. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2332. {
  2333. struct cnic_dev *dev = csk->dev;
  2334. struct l4_kwq_reset_req *l4kwqe;
  2335. struct kwqe *wqes[1];
  2336. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2337. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2338. wqes[0] = (struct kwqe *) l4kwqe;
  2339. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2340. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2341. l4kwqe->cid = csk->cid;
  2342. return dev->submit_kwqes(dev, wqes, 1);
  2343. }
  2344. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2345. u32 l5_cid, struct cnic_sock **csk, void *context)
  2346. {
  2347. struct cnic_local *cp = dev->cnic_priv;
  2348. struct cnic_sock *csk1;
  2349. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2350. return -EINVAL;
  2351. if (cp->ctx_tbl) {
  2352. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2353. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2354. return -EAGAIN;
  2355. }
  2356. csk1 = &cp->csk_tbl[l5_cid];
  2357. if (atomic_read(&csk1->ref_count))
  2358. return -EAGAIN;
  2359. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2360. return -EBUSY;
  2361. csk1->dev = dev;
  2362. csk1->cid = cid;
  2363. csk1->l5_cid = l5_cid;
  2364. csk1->ulp_type = ulp_type;
  2365. csk1->context = context;
  2366. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2367. csk1->ka_interval = DEF_KA_INTERVAL;
  2368. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2369. csk1->tos = DEF_TOS;
  2370. csk1->ttl = DEF_TTL;
  2371. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2372. csk1->rcv_buf = DEF_RCV_BUF;
  2373. csk1->snd_buf = DEF_SND_BUF;
  2374. csk1->seed = DEF_SEED;
  2375. *csk = csk1;
  2376. return 0;
  2377. }
  2378. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2379. {
  2380. if (csk->src_port) {
  2381. struct cnic_dev *dev = csk->dev;
  2382. struct cnic_local *cp = dev->cnic_priv;
  2383. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2384. csk->src_port = 0;
  2385. }
  2386. }
  2387. static void cnic_close_conn(struct cnic_sock *csk)
  2388. {
  2389. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2390. cnic_cm_upload_pg(csk);
  2391. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2392. }
  2393. cnic_cm_cleanup(csk);
  2394. }
  2395. static int cnic_cm_destroy(struct cnic_sock *csk)
  2396. {
  2397. if (!cnic_in_use(csk))
  2398. return -EINVAL;
  2399. csk_hold(csk);
  2400. clear_bit(SK_F_INUSE, &csk->flags);
  2401. smp_mb__after_clear_bit();
  2402. while (atomic_read(&csk->ref_count) != 1)
  2403. msleep(1);
  2404. cnic_cm_cleanup(csk);
  2405. csk->flags = 0;
  2406. csk_put(csk);
  2407. return 0;
  2408. }
  2409. static inline u16 cnic_get_vlan(struct net_device *dev,
  2410. struct net_device **vlan_dev)
  2411. {
  2412. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2413. *vlan_dev = vlan_dev_real_dev(dev);
  2414. return vlan_dev_vlan_id(dev);
  2415. }
  2416. *vlan_dev = dev;
  2417. return 0;
  2418. }
  2419. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2420. struct dst_entry **dst)
  2421. {
  2422. #if defined(CONFIG_INET)
  2423. struct flowi fl;
  2424. int err;
  2425. struct rtable *rt;
  2426. memset(&fl, 0, sizeof(fl));
  2427. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2428. err = ip_route_output_key(&init_net, &rt, &fl);
  2429. if (!err)
  2430. *dst = &rt->dst;
  2431. return err;
  2432. #else
  2433. return -ENETUNREACH;
  2434. #endif
  2435. }
  2436. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2437. struct dst_entry **dst)
  2438. {
  2439. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2440. struct flowi fl;
  2441. memset(&fl, 0, sizeof(fl));
  2442. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2443. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2444. fl.oif = dst_addr->sin6_scope_id;
  2445. *dst = ip6_route_output(&init_net, NULL, &fl);
  2446. if (*dst)
  2447. return 0;
  2448. #endif
  2449. return -ENETUNREACH;
  2450. }
  2451. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2452. int ulp_type)
  2453. {
  2454. struct cnic_dev *dev = NULL;
  2455. struct dst_entry *dst;
  2456. struct net_device *netdev = NULL;
  2457. int err = -ENETUNREACH;
  2458. if (dst_addr->sin_family == AF_INET)
  2459. err = cnic_get_v4_route(dst_addr, &dst);
  2460. else if (dst_addr->sin_family == AF_INET6) {
  2461. struct sockaddr_in6 *dst_addr6 =
  2462. (struct sockaddr_in6 *) dst_addr;
  2463. err = cnic_get_v6_route(dst_addr6, &dst);
  2464. } else
  2465. return NULL;
  2466. if (err)
  2467. return NULL;
  2468. if (!dst->dev)
  2469. goto done;
  2470. cnic_get_vlan(dst->dev, &netdev);
  2471. dev = cnic_from_netdev(netdev);
  2472. done:
  2473. dst_release(dst);
  2474. if (dev)
  2475. cnic_put(dev);
  2476. return dev;
  2477. }
  2478. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2479. {
  2480. struct cnic_dev *dev = csk->dev;
  2481. struct cnic_local *cp = dev->cnic_priv;
  2482. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2483. }
  2484. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2485. {
  2486. struct cnic_dev *dev = csk->dev;
  2487. struct cnic_local *cp = dev->cnic_priv;
  2488. int is_v6, rc = 0;
  2489. struct dst_entry *dst = NULL;
  2490. struct net_device *realdev;
  2491. __be16 local_port;
  2492. u32 port_id;
  2493. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2494. saddr->remote.v6.sin6_family == AF_INET6)
  2495. is_v6 = 1;
  2496. else if (saddr->local.v4.sin_family == AF_INET &&
  2497. saddr->remote.v4.sin_family == AF_INET)
  2498. is_v6 = 0;
  2499. else
  2500. return -EINVAL;
  2501. clear_bit(SK_F_IPV6, &csk->flags);
  2502. if (is_v6) {
  2503. set_bit(SK_F_IPV6, &csk->flags);
  2504. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2505. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2506. sizeof(struct in6_addr));
  2507. csk->dst_port = saddr->remote.v6.sin6_port;
  2508. local_port = saddr->local.v6.sin6_port;
  2509. } else {
  2510. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2511. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2512. csk->dst_port = saddr->remote.v4.sin_port;
  2513. local_port = saddr->local.v4.sin_port;
  2514. }
  2515. csk->vlan_id = 0;
  2516. csk->mtu = dev->netdev->mtu;
  2517. if (dst && dst->dev) {
  2518. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2519. if (realdev == dev->netdev) {
  2520. csk->vlan_id = vlan;
  2521. csk->mtu = dst_mtu(dst);
  2522. }
  2523. }
  2524. port_id = be16_to_cpu(local_port);
  2525. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2526. port_id < CNIC_LOCAL_PORT_MAX) {
  2527. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2528. port_id = 0;
  2529. } else
  2530. port_id = 0;
  2531. if (!port_id) {
  2532. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2533. if (port_id == -1) {
  2534. rc = -ENOMEM;
  2535. goto err_out;
  2536. }
  2537. local_port = cpu_to_be16(port_id);
  2538. }
  2539. csk->src_port = local_port;
  2540. err_out:
  2541. dst_release(dst);
  2542. return rc;
  2543. }
  2544. static void cnic_init_csk_state(struct cnic_sock *csk)
  2545. {
  2546. csk->state = 0;
  2547. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2548. clear_bit(SK_F_CLOSING, &csk->flags);
  2549. }
  2550. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2551. {
  2552. int err = 0;
  2553. if (!cnic_in_use(csk))
  2554. return -EINVAL;
  2555. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2556. return -EINVAL;
  2557. cnic_init_csk_state(csk);
  2558. err = cnic_get_route(csk, saddr);
  2559. if (err)
  2560. goto err_out;
  2561. err = cnic_resolve_addr(csk, saddr);
  2562. if (!err)
  2563. return 0;
  2564. err_out:
  2565. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2566. return err;
  2567. }
  2568. static int cnic_cm_abort(struct cnic_sock *csk)
  2569. {
  2570. struct cnic_local *cp = csk->dev->cnic_priv;
  2571. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2572. if (!cnic_in_use(csk))
  2573. return -EINVAL;
  2574. if (cnic_abort_prep(csk))
  2575. return cnic_cm_abort_req(csk);
  2576. /* Getting here means that we haven't started connect, or
  2577. * connect was not successful.
  2578. */
  2579. cp->close_conn(csk, opcode);
  2580. if (csk->state != opcode)
  2581. return -EALREADY;
  2582. return 0;
  2583. }
  2584. static int cnic_cm_close(struct cnic_sock *csk)
  2585. {
  2586. if (!cnic_in_use(csk))
  2587. return -EINVAL;
  2588. if (cnic_close_prep(csk)) {
  2589. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2590. return cnic_cm_close_req(csk);
  2591. } else {
  2592. return -EALREADY;
  2593. }
  2594. return 0;
  2595. }
  2596. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2597. u8 opcode)
  2598. {
  2599. struct cnic_ulp_ops *ulp_ops;
  2600. int ulp_type = csk->ulp_type;
  2601. rcu_read_lock();
  2602. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2603. if (ulp_ops) {
  2604. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2605. ulp_ops->cm_connect_complete(csk);
  2606. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2607. ulp_ops->cm_close_complete(csk);
  2608. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2609. ulp_ops->cm_remote_abort(csk);
  2610. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2611. ulp_ops->cm_abort_complete(csk);
  2612. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2613. ulp_ops->cm_remote_close(csk);
  2614. }
  2615. rcu_read_unlock();
  2616. }
  2617. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2618. {
  2619. if (cnic_offld_prep(csk)) {
  2620. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2621. cnic_cm_update_pg(csk);
  2622. else
  2623. cnic_cm_offload_pg(csk);
  2624. }
  2625. return 0;
  2626. }
  2627. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2628. {
  2629. struct cnic_local *cp = dev->cnic_priv;
  2630. u32 l5_cid = kcqe->pg_host_opaque;
  2631. u8 opcode = kcqe->op_code;
  2632. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2633. csk_hold(csk);
  2634. if (!cnic_in_use(csk))
  2635. goto done;
  2636. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2637. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2638. goto done;
  2639. }
  2640. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2641. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2642. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2643. cnic_cm_upcall(cp, csk,
  2644. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2645. goto done;
  2646. }
  2647. csk->pg_cid = kcqe->pg_cid;
  2648. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2649. cnic_cm_conn_req(csk);
  2650. done:
  2651. csk_put(csk);
  2652. }
  2653. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2654. {
  2655. struct cnic_local *cp = dev->cnic_priv;
  2656. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2657. u8 opcode = l4kcqe->op_code;
  2658. u32 l5_cid;
  2659. struct cnic_sock *csk;
  2660. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2661. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2662. cnic_cm_process_offld_pg(dev, l4kcqe);
  2663. return;
  2664. }
  2665. l5_cid = l4kcqe->conn_id;
  2666. if (opcode & 0x80)
  2667. l5_cid = l4kcqe->cid;
  2668. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2669. return;
  2670. csk = &cp->csk_tbl[l5_cid];
  2671. csk_hold(csk);
  2672. if (!cnic_in_use(csk)) {
  2673. csk_put(csk);
  2674. return;
  2675. }
  2676. switch (opcode) {
  2677. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2678. if (l4kcqe->status != 0) {
  2679. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2680. cnic_cm_upcall(cp, csk,
  2681. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2682. }
  2683. break;
  2684. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2685. if (l4kcqe->status == 0)
  2686. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2687. smp_mb__before_clear_bit();
  2688. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2689. cnic_cm_upcall(cp, csk, opcode);
  2690. break;
  2691. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2692. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2693. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2694. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2695. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2696. cp->close_conn(csk, opcode);
  2697. break;
  2698. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2699. cnic_cm_upcall(cp, csk, opcode);
  2700. break;
  2701. }
  2702. csk_put(csk);
  2703. }
  2704. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2705. {
  2706. struct cnic_dev *dev = data;
  2707. int i;
  2708. for (i = 0; i < num; i++)
  2709. cnic_cm_process_kcqe(dev, kcqe[i]);
  2710. }
  2711. static struct cnic_ulp_ops cm_ulp_ops = {
  2712. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2713. };
  2714. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2715. {
  2716. struct cnic_local *cp = dev->cnic_priv;
  2717. kfree(cp->csk_tbl);
  2718. cp->csk_tbl = NULL;
  2719. cnic_free_id_tbl(&cp->csk_port_tbl);
  2720. }
  2721. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2722. {
  2723. struct cnic_local *cp = dev->cnic_priv;
  2724. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2725. GFP_KERNEL);
  2726. if (!cp->csk_tbl)
  2727. return -ENOMEM;
  2728. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2729. CNIC_LOCAL_PORT_MIN)) {
  2730. cnic_cm_free_mem(dev);
  2731. return -ENOMEM;
  2732. }
  2733. return 0;
  2734. }
  2735. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2736. {
  2737. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  2738. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  2739. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  2740. csk->state = opcode;
  2741. }
  2742. /* 1. If event opcode matches the expected event in csk->state
  2743. * 2. If the expected event is CLOSE_COMP, we accept any event
  2744. * 3. If the expected event is 0, meaning the connection was never
  2745. * never established, we accept the opcode from cm_abort.
  2746. */
  2747. if (opcode == csk->state || csk->state == 0 ||
  2748. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  2749. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  2750. if (csk->state == 0)
  2751. csk->state = opcode;
  2752. return 1;
  2753. }
  2754. }
  2755. return 0;
  2756. }
  2757. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2758. {
  2759. struct cnic_dev *dev = csk->dev;
  2760. struct cnic_local *cp = dev->cnic_priv;
  2761. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  2762. cnic_cm_upcall(cp, csk, opcode);
  2763. return;
  2764. }
  2765. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2766. cnic_close_conn(csk);
  2767. csk->state = opcode;
  2768. cnic_cm_upcall(cp, csk, opcode);
  2769. }
  2770. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2771. {
  2772. }
  2773. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2774. {
  2775. u32 seed;
  2776. get_random_bytes(&seed, 4);
  2777. cnic_ctx_wr(dev, 45, 0, seed);
  2778. return 0;
  2779. }
  2780. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2781. {
  2782. struct cnic_dev *dev = csk->dev;
  2783. struct cnic_local *cp = dev->cnic_priv;
  2784. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2785. union l5cm_specific_data l5_data;
  2786. u32 cmd = 0;
  2787. int close_complete = 0;
  2788. switch (opcode) {
  2789. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2790. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2791. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2792. if (cnic_ready_to_close(csk, opcode)) {
  2793. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2794. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2795. else
  2796. close_complete = 1;
  2797. }
  2798. break;
  2799. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2800. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2801. break;
  2802. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2803. close_complete = 1;
  2804. break;
  2805. }
  2806. if (cmd) {
  2807. memset(&l5_data, 0, sizeof(l5_data));
  2808. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2809. &l5_data);
  2810. } else if (close_complete) {
  2811. ctx->timestamp = jiffies;
  2812. cnic_close_conn(csk);
  2813. cnic_cm_upcall(cp, csk, csk->state);
  2814. }
  2815. }
  2816. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2817. {
  2818. struct cnic_local *cp = dev->cnic_priv;
  2819. int i;
  2820. if (!cp->ctx_tbl)
  2821. return;
  2822. if (!netif_running(dev->netdev))
  2823. return;
  2824. for (i = 0; i < cp->max_cid_space; i++) {
  2825. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2826. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2827. msleep(10);
  2828. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2829. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2830. ctx->cid);
  2831. }
  2832. cancel_delayed_work(&cp->delete_task);
  2833. flush_workqueue(cnic_wq);
  2834. if (atomic_read(&cp->iscsi_conn) != 0)
  2835. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  2836. atomic_read(&cp->iscsi_conn));
  2837. }
  2838. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2839. {
  2840. struct cnic_local *cp = dev->cnic_priv;
  2841. u32 pfid = cp->pfid;
  2842. u32 port = CNIC_PORT(cp);
  2843. cnic_init_bnx2x_mac(dev);
  2844. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2845. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2846. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  2847. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2848. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  2849. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2850. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  2851. DEF_MAX_DA_COUNT);
  2852. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2853. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  2854. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2855. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  2856. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2857. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  2858. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2859. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  2860. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  2861. DEF_MAX_CWND);
  2862. return 0;
  2863. }
  2864. static void cnic_delete_task(struct work_struct *work)
  2865. {
  2866. struct cnic_local *cp;
  2867. struct cnic_dev *dev;
  2868. u32 i;
  2869. int need_resched = 0;
  2870. cp = container_of(work, struct cnic_local, delete_task.work);
  2871. dev = cp->dev;
  2872. for (i = 0; i < cp->max_cid_space; i++) {
  2873. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2874. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  2875. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2876. continue;
  2877. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  2878. need_resched = 1;
  2879. continue;
  2880. }
  2881. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2882. continue;
  2883. cnic_bnx2x_destroy_ramrod(dev, i);
  2884. cnic_free_bnx2x_conn_resc(dev, i);
  2885. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  2886. atomic_dec(&cp->iscsi_conn);
  2887. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  2888. }
  2889. if (need_resched)
  2890. queue_delayed_work(cnic_wq, &cp->delete_task,
  2891. msecs_to_jiffies(10));
  2892. }
  2893. static int cnic_cm_open(struct cnic_dev *dev)
  2894. {
  2895. struct cnic_local *cp = dev->cnic_priv;
  2896. int err;
  2897. err = cnic_cm_alloc_mem(dev);
  2898. if (err)
  2899. return err;
  2900. err = cp->start_cm(dev);
  2901. if (err)
  2902. goto err_out;
  2903. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  2904. dev->cm_create = cnic_cm_create;
  2905. dev->cm_destroy = cnic_cm_destroy;
  2906. dev->cm_connect = cnic_cm_connect;
  2907. dev->cm_abort = cnic_cm_abort;
  2908. dev->cm_close = cnic_cm_close;
  2909. dev->cm_select_dev = cnic_cm_select_dev;
  2910. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2911. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2912. return 0;
  2913. err_out:
  2914. cnic_cm_free_mem(dev);
  2915. return err;
  2916. }
  2917. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2918. {
  2919. struct cnic_local *cp = dev->cnic_priv;
  2920. int i;
  2921. cp->stop_cm(dev);
  2922. if (!cp->csk_tbl)
  2923. return 0;
  2924. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2925. struct cnic_sock *csk = &cp->csk_tbl[i];
  2926. clear_bit(SK_F_INUSE, &csk->flags);
  2927. cnic_cm_cleanup(csk);
  2928. }
  2929. cnic_cm_free_mem(dev);
  2930. return 0;
  2931. }
  2932. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2933. {
  2934. u32 cid_addr;
  2935. int i;
  2936. cid_addr = GET_CID_ADDR(cid);
  2937. for (i = 0; i < CTX_SIZE; i += 4)
  2938. cnic_ctx_wr(dev, cid_addr, i, 0);
  2939. }
  2940. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2941. {
  2942. struct cnic_local *cp = dev->cnic_priv;
  2943. int ret = 0, i;
  2944. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2945. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2946. return 0;
  2947. for (i = 0; i < cp->ctx_blks; i++) {
  2948. int j;
  2949. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2950. u32 val;
  2951. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2952. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2953. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2954. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2955. (u64) cp->ctx_arr[i].mapping >> 32);
  2956. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2957. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2958. for (j = 0; j < 10; j++) {
  2959. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2960. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2961. break;
  2962. udelay(5);
  2963. }
  2964. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2965. ret = -EBUSY;
  2966. break;
  2967. }
  2968. }
  2969. return ret;
  2970. }
  2971. static void cnic_free_irq(struct cnic_dev *dev)
  2972. {
  2973. struct cnic_local *cp = dev->cnic_priv;
  2974. struct cnic_eth_dev *ethdev = cp->ethdev;
  2975. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2976. cp->disable_int_sync(dev);
  2977. tasklet_kill(&cp->cnic_irq_task);
  2978. free_irq(ethdev->irq_arr[0].vector, dev);
  2979. }
  2980. }
  2981. static int cnic_request_irq(struct cnic_dev *dev)
  2982. {
  2983. struct cnic_local *cp = dev->cnic_priv;
  2984. struct cnic_eth_dev *ethdev = cp->ethdev;
  2985. int err;
  2986. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  2987. if (err)
  2988. tasklet_disable(&cp->cnic_irq_task);
  2989. return err;
  2990. }
  2991. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2992. {
  2993. struct cnic_local *cp = dev->cnic_priv;
  2994. struct cnic_eth_dev *ethdev = cp->ethdev;
  2995. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2996. int err, i = 0;
  2997. int sblk_num = cp->status_blk_num;
  2998. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2999. BNX2_HC_SB_CONFIG_1;
  3000. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3001. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3002. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3003. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3004. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3005. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3006. (unsigned long) dev);
  3007. err = cnic_request_irq(dev);
  3008. if (err)
  3009. return err;
  3010. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3011. i < 10) {
  3012. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3013. 1 << (11 + sblk_num));
  3014. udelay(10);
  3015. i++;
  3016. barrier();
  3017. }
  3018. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3019. cnic_free_irq(dev);
  3020. goto failed;
  3021. }
  3022. } else {
  3023. struct status_block *sblk = cp->status_blk.gen;
  3024. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3025. int i = 0;
  3026. while (sblk->status_completion_producer_index && i < 10) {
  3027. CNIC_WR(dev, BNX2_HC_COMMAND,
  3028. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3029. udelay(10);
  3030. i++;
  3031. barrier();
  3032. }
  3033. if (sblk->status_completion_producer_index)
  3034. goto failed;
  3035. }
  3036. return 0;
  3037. failed:
  3038. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3039. return -EBUSY;
  3040. }
  3041. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3042. {
  3043. struct cnic_local *cp = dev->cnic_priv;
  3044. struct cnic_eth_dev *ethdev = cp->ethdev;
  3045. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3046. return;
  3047. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3048. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3049. }
  3050. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3051. {
  3052. struct cnic_local *cp = dev->cnic_priv;
  3053. struct cnic_eth_dev *ethdev = cp->ethdev;
  3054. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3055. return;
  3056. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3057. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3058. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3059. synchronize_irq(ethdev->irq_arr[0].vector);
  3060. }
  3061. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3062. {
  3063. struct cnic_local *cp = dev->cnic_priv;
  3064. struct cnic_eth_dev *ethdev = cp->ethdev;
  3065. struct cnic_uio_dev *udev = cp->udev;
  3066. u32 cid_addr, tx_cid, sb_id;
  3067. u32 val, offset0, offset1, offset2, offset3;
  3068. int i;
  3069. struct tx_bd *txbd;
  3070. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3071. struct status_block *s_blk = cp->status_blk.gen;
  3072. sb_id = cp->status_blk_num;
  3073. tx_cid = 20;
  3074. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3075. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3076. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3077. tx_cid = TX_TSS_CID + sb_id - 1;
  3078. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3079. (TX_TSS_CID << 7));
  3080. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3081. }
  3082. cp->tx_cons = *cp->tx_cons_ptr;
  3083. cid_addr = GET_CID_ADDR(tx_cid);
  3084. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3085. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3086. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3087. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3088. offset0 = BNX2_L2CTX_TYPE_XI;
  3089. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3090. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3091. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3092. } else {
  3093. cnic_init_context(dev, tx_cid);
  3094. cnic_init_context(dev, tx_cid + 1);
  3095. offset0 = BNX2_L2CTX_TYPE;
  3096. offset1 = BNX2_L2CTX_CMD_TYPE;
  3097. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3098. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3099. }
  3100. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3101. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3102. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3103. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3104. txbd = (struct tx_bd *) udev->l2_ring;
  3105. buf_map = udev->l2_buf_map;
  3106. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3107. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3108. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3109. }
  3110. val = (u64) ring_map >> 32;
  3111. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3112. txbd->tx_bd_haddr_hi = val;
  3113. val = (u64) ring_map & 0xffffffff;
  3114. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3115. txbd->tx_bd_haddr_lo = val;
  3116. }
  3117. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3118. {
  3119. struct cnic_local *cp = dev->cnic_priv;
  3120. struct cnic_eth_dev *ethdev = cp->ethdev;
  3121. struct cnic_uio_dev *udev = cp->udev;
  3122. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3123. int i;
  3124. struct rx_bd *rxbd;
  3125. struct status_block *s_blk = cp->status_blk.gen;
  3126. dma_addr_t ring_map = udev->l2_ring_map;
  3127. sb_id = cp->status_blk_num;
  3128. cnic_init_context(dev, 2);
  3129. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3130. coal_reg = BNX2_HC_COMMAND;
  3131. coal_val = CNIC_RD(dev, coal_reg);
  3132. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3133. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3134. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3135. coal_reg = BNX2_HC_COALESCE_NOW;
  3136. coal_val = 1 << (11 + sb_id);
  3137. }
  3138. i = 0;
  3139. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3140. CNIC_WR(dev, coal_reg, coal_val);
  3141. udelay(10);
  3142. i++;
  3143. barrier();
  3144. }
  3145. cp->rx_cons = *cp->rx_cons_ptr;
  3146. cid_addr = GET_CID_ADDR(2);
  3147. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3148. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3149. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3150. if (sb_id == 0)
  3151. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3152. else
  3153. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3154. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3155. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3156. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3157. dma_addr_t buf_map;
  3158. int n = (i % cp->l2_rx_ring_size) + 1;
  3159. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3160. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3161. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3162. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3163. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3164. }
  3165. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3166. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3167. rxbd->rx_bd_haddr_hi = val;
  3168. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3169. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3170. rxbd->rx_bd_haddr_lo = val;
  3171. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3172. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3173. }
  3174. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3175. {
  3176. struct kwqe *wqes[1], l2kwqe;
  3177. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3178. wqes[0] = &l2kwqe;
  3179. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  3180. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3181. KWQE_OPCODE_SHIFT) | 2;
  3182. dev->submit_kwqes(dev, wqes, 1);
  3183. }
  3184. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3185. {
  3186. struct cnic_local *cp = dev->cnic_priv;
  3187. u32 val;
  3188. val = cp->func << 2;
  3189. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3190. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3191. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3192. dev->mac_addr[0] = (u8) (val >> 8);
  3193. dev->mac_addr[1] = (u8) val;
  3194. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3195. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3196. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3197. dev->mac_addr[2] = (u8) (val >> 24);
  3198. dev->mac_addr[3] = (u8) (val >> 16);
  3199. dev->mac_addr[4] = (u8) (val >> 8);
  3200. dev->mac_addr[5] = (u8) val;
  3201. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3202. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3203. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3204. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3205. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3206. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3207. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3208. }
  3209. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3210. {
  3211. struct cnic_local *cp = dev->cnic_priv;
  3212. struct cnic_eth_dev *ethdev = cp->ethdev;
  3213. struct status_block *sblk = cp->status_blk.gen;
  3214. u32 val, kcq_cid_addr, kwq_cid_addr;
  3215. int err;
  3216. cnic_set_bnx2_mac(dev);
  3217. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3218. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3219. if (BCM_PAGE_BITS > 12)
  3220. val |= (12 - 8) << 4;
  3221. else
  3222. val |= (BCM_PAGE_BITS - 8) << 4;
  3223. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3224. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3225. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3226. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3227. err = cnic_setup_5709_context(dev, 1);
  3228. if (err)
  3229. return err;
  3230. cnic_init_context(dev, KWQ_CID);
  3231. cnic_init_context(dev, KCQ_CID);
  3232. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3233. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3234. cp->max_kwq_idx = MAX_KWQ_IDX;
  3235. cp->kwq_prod_idx = 0;
  3236. cp->kwq_con_idx = 0;
  3237. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3238. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3239. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3240. else
  3241. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3242. /* Initialize the kernel work queue context. */
  3243. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3244. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3245. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3246. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3247. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3248. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3249. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3250. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3251. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3252. val = (u32) cp->kwq_info.pgtbl_map;
  3253. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3254. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3255. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3256. cp->kcq1.sw_prod_idx = 0;
  3257. cp->kcq1.hw_prod_idx_ptr =
  3258. (u16 *) &sblk->status_completion_producer_index;
  3259. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3260. /* Initialize the kernel complete queue context. */
  3261. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3262. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3263. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3264. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3265. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3266. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3267. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3268. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3269. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3270. val = (u32) cp->kcq1.dma.pgtbl_map;
  3271. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3272. cp->int_num = 0;
  3273. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3274. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3275. u32 sb_id = cp->status_blk_num;
  3276. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3277. cp->kcq1.hw_prod_idx_ptr =
  3278. (u16 *) &msblk->status_completion_producer_index;
  3279. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3280. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3281. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3282. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3283. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3284. }
  3285. /* Enable Commnad Scheduler notification when we write to the
  3286. * host producer index of the kernel contexts. */
  3287. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3288. /* Enable Command Scheduler notification when we write to either
  3289. * the Send Queue or Receive Queue producer indexes of the kernel
  3290. * bypass contexts. */
  3291. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3292. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3293. /* Notify COM when the driver post an application buffer. */
  3294. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3295. /* Set the CP and COM doorbells. These two processors polls the
  3296. * doorbell for a non zero value before running. This must be done
  3297. * after setting up the kernel queue contexts. */
  3298. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3299. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3300. cnic_init_bnx2_tx_ring(dev);
  3301. cnic_init_bnx2_rx_ring(dev);
  3302. err = cnic_init_bnx2_irq(dev);
  3303. if (err) {
  3304. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3305. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3306. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3307. return err;
  3308. }
  3309. return 0;
  3310. }
  3311. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3312. {
  3313. struct cnic_local *cp = dev->cnic_priv;
  3314. struct cnic_eth_dev *ethdev = cp->ethdev;
  3315. u32 start_offset = ethdev->ctx_tbl_offset;
  3316. int i;
  3317. for (i = 0; i < cp->ctx_blks; i++) {
  3318. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3319. dma_addr_t map = ctx->mapping;
  3320. if (cp->ctx_align) {
  3321. unsigned long mask = cp->ctx_align - 1;
  3322. map = (map + mask) & ~mask;
  3323. }
  3324. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3325. }
  3326. }
  3327. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3328. {
  3329. struct cnic_local *cp = dev->cnic_priv;
  3330. struct cnic_eth_dev *ethdev = cp->ethdev;
  3331. int err = 0;
  3332. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3333. (unsigned long) dev);
  3334. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3335. err = cnic_request_irq(dev);
  3336. return err;
  3337. }
  3338. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3339. u16 sb_id, u8 sb_index,
  3340. u8 disable)
  3341. {
  3342. u32 addr = BAR_CSTRORM_INTMEM +
  3343. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3344. offsetof(struct hc_status_block_data_e1x, index_data) +
  3345. sizeof(struct hc_index_data)*sb_index +
  3346. offsetof(struct hc_index_data, flags);
  3347. u16 flags = CNIC_RD16(dev, addr);
  3348. /* clear and set */
  3349. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3350. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3351. HC_INDEX_DATA_HC_ENABLED);
  3352. CNIC_WR16(dev, addr, flags);
  3353. }
  3354. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3355. {
  3356. struct cnic_local *cp = dev->cnic_priv;
  3357. u8 sb_id = cp->status_blk_num;
  3358. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3359. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3360. offsetof(struct hc_status_block_data_e1x, index_data) +
  3361. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3362. offsetof(struct hc_index_data, timeout), 64 / 12);
  3363. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3364. }
  3365. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3366. {
  3367. }
  3368. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3369. struct client_init_ramrod_data *data)
  3370. {
  3371. struct cnic_local *cp = dev->cnic_priv;
  3372. struct cnic_uio_dev *udev = cp->udev;
  3373. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3374. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3375. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3376. int port = CNIC_PORT(cp);
  3377. int i;
  3378. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3379. u32 val;
  3380. memset(txbd, 0, BCM_PAGE_SIZE);
  3381. buf_map = udev->l2_buf_map;
  3382. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3383. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3384. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3385. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3386. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3387. reg_bd->addr_hi = start_bd->addr_hi;
  3388. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3389. start_bd->nbytes = cpu_to_le16(0x10);
  3390. start_bd->nbd = cpu_to_le16(3);
  3391. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3392. start_bd->general_data = (UNICAST_ADDRESS <<
  3393. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3394. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3395. }
  3396. val = (u64) ring_map >> 32;
  3397. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3398. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3399. val = (u64) ring_map & 0xffffffff;
  3400. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3401. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3402. /* Other ramrod params */
  3403. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3404. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3405. /* reset xstorm per client statistics */
  3406. if (cli < MAX_STAT_COUNTER_ID) {
  3407. val = BAR_XSTRORM_INTMEM +
  3408. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3409. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3410. CNIC_WR(dev, val + i * 4, 0);
  3411. }
  3412. cp->tx_cons_ptr =
  3413. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3414. }
  3415. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3416. struct client_init_ramrod_data *data)
  3417. {
  3418. struct cnic_local *cp = dev->cnic_priv;
  3419. struct cnic_uio_dev *udev = cp->udev;
  3420. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3421. BCM_PAGE_SIZE);
  3422. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3423. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3424. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3425. int i;
  3426. int port = CNIC_PORT(cp);
  3427. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3428. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3429. u32 val;
  3430. dma_addr_t ring_map = udev->l2_ring_map;
  3431. /* General data */
  3432. data->general.client_id = cli;
  3433. data->general.statistics_en_flg = 1;
  3434. data->general.statistics_counter_id = cli;
  3435. data->general.activate_flg = 1;
  3436. data->general.sp_client_id = cli;
  3437. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3438. dma_addr_t buf_map;
  3439. int n = (i % cp->l2_rx_ring_size) + 1;
  3440. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3441. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3442. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3443. }
  3444. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3445. rxbd->addr_hi = cpu_to_le32(val);
  3446. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3447. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3448. rxbd->addr_lo = cpu_to_le32(val);
  3449. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3450. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3451. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3452. rxcqe->addr_hi = cpu_to_le32(val);
  3453. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3454. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3455. rxcqe->addr_lo = cpu_to_le32(val);
  3456. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3457. /* Other ramrod params */
  3458. data->rx.client_qzone_id = cl_qzone_id;
  3459. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3460. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3461. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3462. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3463. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3464. data->rx.outer_vlan_removal_enable_flg = 1;
  3465. /* reset tstorm and ustorm per client statistics */
  3466. if (cli < MAX_STAT_COUNTER_ID) {
  3467. val = BAR_TSTRORM_INTMEM +
  3468. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3469. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3470. CNIC_WR(dev, val + i * 4, 0);
  3471. val = BAR_USTRORM_INTMEM +
  3472. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3473. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3474. CNIC_WR(dev, val + i * 4, 0);
  3475. }
  3476. cp->rx_cons_ptr =
  3477. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3478. }
  3479. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3480. {
  3481. struct cnic_local *cp = dev->cnic_priv;
  3482. u32 base, base2, addr, val;
  3483. int port = CNIC_PORT(cp);
  3484. dev->max_iscsi_conn = 0;
  3485. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3486. if (base == 0)
  3487. return;
  3488. base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
  3489. MISC_REG_GENERIC_CR_0));
  3490. addr = BNX2X_SHMEM_ADDR(base,
  3491. dev_info.port_hw_config[port].iscsi_mac_upper);
  3492. val = CNIC_RD(dev, addr);
  3493. dev->mac_addr[0] = (u8) (val >> 8);
  3494. dev->mac_addr[1] = (u8) val;
  3495. addr = BNX2X_SHMEM_ADDR(base,
  3496. dev_info.port_hw_config[port].iscsi_mac_lower);
  3497. val = CNIC_RD(dev, addr);
  3498. dev->mac_addr[2] = (u8) (val >> 24);
  3499. dev->mac_addr[3] = (u8) (val >> 16);
  3500. dev->mac_addr[4] = (u8) (val >> 8);
  3501. dev->mac_addr[5] = (u8) val;
  3502. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3503. val = CNIC_RD(dev, addr);
  3504. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3505. u16 val16;
  3506. addr = BNX2X_SHMEM_ADDR(base,
  3507. drv_lic_key[port].max_iscsi_init_conn);
  3508. val16 = CNIC_RD16(dev, addr);
  3509. if (val16)
  3510. val16 ^= 0x1e1e;
  3511. dev->max_iscsi_conn = val16;
  3512. }
  3513. if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3514. int func = CNIC_FUNC(cp);
  3515. u32 mf_cfg_addr;
  3516. if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
  3517. mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
  3518. mf_cfg_addr));
  3519. else
  3520. mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  3521. addr = mf_cfg_addr +
  3522. offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
  3523. val = CNIC_RD(dev, addr);
  3524. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3525. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3526. addr = mf_cfg_addr +
  3527. offsetof(struct mf_cfg,
  3528. func_mf_config[func].config);
  3529. val = CNIC_RD(dev, addr);
  3530. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3531. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3532. dev->max_iscsi_conn = 0;
  3533. }
  3534. }
  3535. }
  3536. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3537. {
  3538. struct cnic_local *cp = dev->cnic_priv;
  3539. struct cnic_eth_dev *ethdev = cp->ethdev;
  3540. int func = CNIC_FUNC(cp), ret, i;
  3541. u32 pfid;
  3542. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3543. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3544. if (!(val & 1))
  3545. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3546. else
  3547. val = (val >> 1) & 1;
  3548. if (val)
  3549. cp->pfid = func >> 1;
  3550. else
  3551. cp->pfid = func & 0x6;
  3552. } else {
  3553. cp->pfid = func;
  3554. }
  3555. pfid = cp->pfid;
  3556. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3557. cp->iscsi_start_cid);
  3558. if (ret)
  3559. return -ENOMEM;
  3560. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3561. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3562. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3563. cp->kcq1.sw_prod_idx = 0;
  3564. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3565. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3566. cp->kcq1.hw_prod_idx_ptr =
  3567. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3568. cp->kcq1.status_idx_ptr =
  3569. &sb->sb.running_index[SM_RX_ID];
  3570. } else {
  3571. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3572. cp->kcq1.hw_prod_idx_ptr =
  3573. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3574. cp->kcq1.status_idx_ptr =
  3575. &sb->sb.running_index[SM_RX_ID];
  3576. }
  3577. cnic_get_bnx2x_iscsi_info(dev);
  3578. /* Only 1 EQ */
  3579. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3580. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3581. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3582. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3583. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3584. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3585. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3586. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3587. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3588. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3589. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3590. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3591. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3592. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  3593. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  3594. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3595. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  3596. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3597. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  3598. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3599. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  3600. HC_INDEX_ISCSI_EQ_CONS);
  3601. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3602. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3603. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  3604. cp->conn_buf_info.pgtbl[2 * i]);
  3605. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3606. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  3607. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3608. }
  3609. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3610. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  3611. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3612. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3613. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  3614. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3615. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3616. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  3617. cnic_setup_bnx2x_context(dev);
  3618. ret = cnic_init_bnx2x_irq(dev);
  3619. if (ret)
  3620. return ret;
  3621. return 0;
  3622. }
  3623. static void cnic_init_rings(struct cnic_dev *dev)
  3624. {
  3625. struct cnic_local *cp = dev->cnic_priv;
  3626. struct cnic_uio_dev *udev = cp->udev;
  3627. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3628. return;
  3629. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3630. cnic_init_bnx2_tx_ring(dev);
  3631. cnic_init_bnx2_rx_ring(dev);
  3632. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3633. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3634. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3635. u32 cl_qzone_id, type;
  3636. struct client_init_ramrod_data *data;
  3637. union l5cm_specific_data l5_data;
  3638. struct ustorm_eth_rx_producers rx_prods = {0};
  3639. u32 off, i;
  3640. rx_prods.bd_prod = 0;
  3641. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3642. barrier();
  3643. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3644. off = BAR_USTRORM_INTMEM +
  3645. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  3646. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  3647. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  3648. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3649. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3650. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3651. data = udev->l2_buf;
  3652. memset(data, 0, sizeof(*data));
  3653. cnic_init_bnx2x_tx_ring(dev, data);
  3654. cnic_init_bnx2x_rx_ring(dev, data);
  3655. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  3656. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  3657. type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3658. & SPE_HDR_CONN_TYPE;
  3659. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3660. SPE_HDR_FUNCTION_ID);
  3661. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3662. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3663. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3664. i = 0;
  3665. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3666. ++i < 10)
  3667. msleep(1);
  3668. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3669. netdev_err(dev->netdev,
  3670. "iSCSI CLIENT_SETUP did not complete\n");
  3671. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3672. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3673. }
  3674. }
  3675. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3676. {
  3677. struct cnic_local *cp = dev->cnic_priv;
  3678. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3679. return;
  3680. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3681. cnic_shutdown_bnx2_rx_ring(dev);
  3682. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3683. struct cnic_local *cp = dev->cnic_priv;
  3684. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3685. union l5cm_specific_data l5_data;
  3686. int i;
  3687. u32 type;
  3688. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3689. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3690. l5_data.phy_address.lo = cli;
  3691. l5_data.phy_address.hi = 0;
  3692. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3693. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3694. i = 0;
  3695. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3696. ++i < 10)
  3697. msleep(1);
  3698. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3699. netdev_err(dev->netdev,
  3700. "iSCSI CLIENT_HALT did not complete\n");
  3701. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3702. memset(&l5_data, 0, sizeof(l5_data));
  3703. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3704. & SPE_HDR_CONN_TYPE;
  3705. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3706. SPE_HDR_FUNCTION_ID);
  3707. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  3708. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3709. msleep(10);
  3710. }
  3711. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3712. }
  3713. static int cnic_register_netdev(struct cnic_dev *dev)
  3714. {
  3715. struct cnic_local *cp = dev->cnic_priv;
  3716. struct cnic_eth_dev *ethdev = cp->ethdev;
  3717. int err;
  3718. if (!ethdev)
  3719. return -ENODEV;
  3720. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3721. return 0;
  3722. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3723. if (err)
  3724. netdev_err(dev->netdev, "register_cnic failed\n");
  3725. return err;
  3726. }
  3727. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3728. {
  3729. struct cnic_local *cp = dev->cnic_priv;
  3730. struct cnic_eth_dev *ethdev = cp->ethdev;
  3731. if (!ethdev)
  3732. return;
  3733. ethdev->drv_unregister_cnic(dev->netdev);
  3734. }
  3735. static int cnic_start_hw(struct cnic_dev *dev)
  3736. {
  3737. struct cnic_local *cp = dev->cnic_priv;
  3738. struct cnic_eth_dev *ethdev = cp->ethdev;
  3739. int err;
  3740. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3741. return -EALREADY;
  3742. dev->regview = ethdev->io_base;
  3743. pci_dev_get(dev->pcidev);
  3744. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3745. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  3746. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3747. err = cp->alloc_resc(dev);
  3748. if (err) {
  3749. netdev_err(dev->netdev, "allocate resource failure\n");
  3750. goto err1;
  3751. }
  3752. err = cp->start_hw(dev);
  3753. if (err)
  3754. goto err1;
  3755. err = cnic_cm_open(dev);
  3756. if (err)
  3757. goto err1;
  3758. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3759. cp->enable_int(dev);
  3760. return 0;
  3761. err1:
  3762. cp->free_resc(dev);
  3763. pci_dev_put(dev->pcidev);
  3764. return err;
  3765. }
  3766. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3767. {
  3768. cnic_disable_bnx2_int_sync(dev);
  3769. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3770. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3771. cnic_init_context(dev, KWQ_CID);
  3772. cnic_init_context(dev, KCQ_CID);
  3773. cnic_setup_5709_context(dev, 0);
  3774. cnic_free_irq(dev);
  3775. cnic_free_resc(dev);
  3776. }
  3777. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3778. {
  3779. struct cnic_local *cp = dev->cnic_priv;
  3780. cnic_free_irq(dev);
  3781. *cp->kcq1.hw_prod_idx_ptr = 0;
  3782. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3783. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  3784. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  3785. cnic_free_resc(dev);
  3786. }
  3787. static void cnic_stop_hw(struct cnic_dev *dev)
  3788. {
  3789. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3790. struct cnic_local *cp = dev->cnic_priv;
  3791. int i = 0;
  3792. /* Need to wait for the ring shutdown event to complete
  3793. * before clearing the CNIC_UP flag.
  3794. */
  3795. while (cp->udev->uio_dev != -1 && i < 15) {
  3796. msleep(100);
  3797. i++;
  3798. }
  3799. cnic_shutdown_rings(dev);
  3800. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3801. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3802. synchronize_rcu();
  3803. cnic_cm_shutdown(dev);
  3804. cp->stop_hw(dev);
  3805. pci_dev_put(dev->pcidev);
  3806. }
  3807. }
  3808. static void cnic_free_dev(struct cnic_dev *dev)
  3809. {
  3810. int i = 0;
  3811. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3812. msleep(100);
  3813. i++;
  3814. }
  3815. if (atomic_read(&dev->ref_count) != 0)
  3816. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3817. netdev_info(dev->netdev, "Removed CNIC device\n");
  3818. dev_put(dev->netdev);
  3819. kfree(dev);
  3820. }
  3821. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3822. struct pci_dev *pdev)
  3823. {
  3824. struct cnic_dev *cdev;
  3825. struct cnic_local *cp;
  3826. int alloc_size;
  3827. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3828. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3829. if (cdev == NULL) {
  3830. netdev_err(dev, "allocate dev struct failure\n");
  3831. return NULL;
  3832. }
  3833. cdev->netdev = dev;
  3834. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3835. cdev->register_device = cnic_register_device;
  3836. cdev->unregister_device = cnic_unregister_device;
  3837. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3838. cp = cdev->cnic_priv;
  3839. cp->dev = cdev;
  3840. cp->l2_single_buf_size = 0x400;
  3841. cp->l2_rx_ring_size = 3;
  3842. spin_lock_init(&cp->cnic_ulp_lock);
  3843. netdev_info(dev, "Added CNIC device\n");
  3844. return cdev;
  3845. }
  3846. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3847. {
  3848. struct pci_dev *pdev;
  3849. struct cnic_dev *cdev;
  3850. struct cnic_local *cp;
  3851. struct cnic_eth_dev *ethdev = NULL;
  3852. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3853. probe = symbol_get(bnx2_cnic_probe);
  3854. if (probe) {
  3855. ethdev = (*probe)(dev);
  3856. symbol_put(bnx2_cnic_probe);
  3857. }
  3858. if (!ethdev)
  3859. return NULL;
  3860. pdev = ethdev->pdev;
  3861. if (!pdev)
  3862. return NULL;
  3863. dev_hold(dev);
  3864. pci_dev_get(pdev);
  3865. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3866. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3867. u8 rev;
  3868. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3869. if (rev < 0x10) {
  3870. pci_dev_put(pdev);
  3871. goto cnic_err;
  3872. }
  3873. }
  3874. pci_dev_put(pdev);
  3875. cdev = cnic_alloc_dev(dev, pdev);
  3876. if (cdev == NULL)
  3877. goto cnic_err;
  3878. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3879. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3880. cp = cdev->cnic_priv;
  3881. cp->ethdev = ethdev;
  3882. cdev->pcidev = pdev;
  3883. cp->chip_id = ethdev->chip_id;
  3884. cp->cnic_ops = &cnic_bnx2_ops;
  3885. cp->start_hw = cnic_start_bnx2_hw;
  3886. cp->stop_hw = cnic_stop_bnx2_hw;
  3887. cp->setup_pgtbl = cnic_setup_page_tbl;
  3888. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3889. cp->free_resc = cnic_free_resc;
  3890. cp->start_cm = cnic_cm_init_bnx2_hw;
  3891. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3892. cp->enable_int = cnic_enable_bnx2_int;
  3893. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3894. cp->close_conn = cnic_close_bnx2_conn;
  3895. cp->next_idx = cnic_bnx2_next_idx;
  3896. cp->hw_idx = cnic_bnx2_hw_idx;
  3897. return cdev;
  3898. cnic_err:
  3899. dev_put(dev);
  3900. return NULL;
  3901. }
  3902. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3903. {
  3904. struct pci_dev *pdev;
  3905. struct cnic_dev *cdev;
  3906. struct cnic_local *cp;
  3907. struct cnic_eth_dev *ethdev = NULL;
  3908. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3909. probe = symbol_get(bnx2x_cnic_probe);
  3910. if (probe) {
  3911. ethdev = (*probe)(dev);
  3912. symbol_put(bnx2x_cnic_probe);
  3913. }
  3914. if (!ethdev)
  3915. return NULL;
  3916. pdev = ethdev->pdev;
  3917. if (!pdev)
  3918. return NULL;
  3919. dev_hold(dev);
  3920. cdev = cnic_alloc_dev(dev, pdev);
  3921. if (cdev == NULL) {
  3922. dev_put(dev);
  3923. return NULL;
  3924. }
  3925. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3926. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3927. cp = cdev->cnic_priv;
  3928. cp->ethdev = ethdev;
  3929. cdev->pcidev = pdev;
  3930. cp->chip_id = ethdev->chip_id;
  3931. cp->cnic_ops = &cnic_bnx2x_ops;
  3932. cp->start_hw = cnic_start_bnx2x_hw;
  3933. cp->stop_hw = cnic_stop_bnx2x_hw;
  3934. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3935. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3936. cp->free_resc = cnic_free_resc;
  3937. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3938. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3939. cp->enable_int = cnic_enable_bnx2x_int;
  3940. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3941. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  3942. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  3943. else
  3944. cp->ack_int = cnic_ack_bnx2x_msix;
  3945. cp->close_conn = cnic_close_bnx2x_conn;
  3946. cp->next_idx = cnic_bnx2x_next_idx;
  3947. cp->hw_idx = cnic_bnx2x_hw_idx;
  3948. return cdev;
  3949. }
  3950. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3951. {
  3952. struct ethtool_drvinfo drvinfo;
  3953. struct cnic_dev *cdev = NULL;
  3954. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3955. memset(&drvinfo, 0, sizeof(drvinfo));
  3956. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3957. if (!strcmp(drvinfo.driver, "bnx2"))
  3958. cdev = init_bnx2_cnic(dev);
  3959. if (!strcmp(drvinfo.driver, "bnx2x"))
  3960. cdev = init_bnx2x_cnic(dev);
  3961. if (cdev) {
  3962. write_lock(&cnic_dev_lock);
  3963. list_add(&cdev->list, &cnic_dev_list);
  3964. write_unlock(&cnic_dev_lock);
  3965. }
  3966. }
  3967. return cdev;
  3968. }
  3969. /**
  3970. * netdev event handler
  3971. */
  3972. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3973. void *ptr)
  3974. {
  3975. struct net_device *netdev = ptr;
  3976. struct cnic_dev *dev;
  3977. int if_type;
  3978. int new_dev = 0;
  3979. dev = cnic_from_netdev(netdev);
  3980. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3981. /* Check for the hot-plug device */
  3982. dev = is_cnic_dev(netdev);
  3983. if (dev) {
  3984. new_dev = 1;
  3985. cnic_hold(dev);
  3986. }
  3987. }
  3988. if (dev) {
  3989. struct cnic_local *cp = dev->cnic_priv;
  3990. if (new_dev)
  3991. cnic_ulp_init(dev);
  3992. else if (event == NETDEV_UNREGISTER)
  3993. cnic_ulp_exit(dev);
  3994. if (event == NETDEV_UP) {
  3995. if (cnic_register_netdev(dev) != 0) {
  3996. cnic_put(dev);
  3997. goto done;
  3998. }
  3999. if (!cnic_start_hw(dev))
  4000. cnic_ulp_start(dev);
  4001. }
  4002. rcu_read_lock();
  4003. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4004. struct cnic_ulp_ops *ulp_ops;
  4005. void *ctx;
  4006. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4007. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4008. continue;
  4009. ctx = cp->ulp_handle[if_type];
  4010. ulp_ops->indicate_netevent(ctx, event);
  4011. }
  4012. rcu_read_unlock();
  4013. if (event == NETDEV_GOING_DOWN) {
  4014. cnic_ulp_stop(dev);
  4015. cnic_stop_hw(dev);
  4016. cnic_unregister_netdev(dev);
  4017. } else if (event == NETDEV_UNREGISTER) {
  4018. write_lock(&cnic_dev_lock);
  4019. list_del_init(&dev->list);
  4020. write_unlock(&cnic_dev_lock);
  4021. cnic_put(dev);
  4022. cnic_free_dev(dev);
  4023. goto done;
  4024. }
  4025. cnic_put(dev);
  4026. }
  4027. done:
  4028. return NOTIFY_DONE;
  4029. }
  4030. static struct notifier_block cnic_netdev_notifier = {
  4031. .notifier_call = cnic_netdev_event
  4032. };
  4033. static void cnic_release(void)
  4034. {
  4035. struct cnic_dev *dev;
  4036. struct cnic_uio_dev *udev;
  4037. while (!list_empty(&cnic_dev_list)) {
  4038. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4039. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4040. cnic_ulp_stop(dev);
  4041. cnic_stop_hw(dev);
  4042. }
  4043. cnic_ulp_exit(dev);
  4044. cnic_unregister_netdev(dev);
  4045. list_del_init(&dev->list);
  4046. cnic_free_dev(dev);
  4047. }
  4048. while (!list_empty(&cnic_udev_list)) {
  4049. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4050. list);
  4051. cnic_free_uio(udev);
  4052. }
  4053. }
  4054. static int __init cnic_init(void)
  4055. {
  4056. int rc = 0;
  4057. pr_info("%s", version);
  4058. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4059. if (rc) {
  4060. cnic_release();
  4061. return rc;
  4062. }
  4063. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4064. if (!cnic_wq) {
  4065. cnic_release();
  4066. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4067. return -ENOMEM;
  4068. }
  4069. return 0;
  4070. }
  4071. static void __exit cnic_exit(void)
  4072. {
  4073. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4074. cnic_release();
  4075. destroy_workqueue(cnic_wq);
  4076. }
  4077. module_init(cnic_init);
  4078. module_exit(cnic_exit);