intel_sdvo.c 90 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct intel_sdvo {
  61. struct intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. uint32_t sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * intel_sdvo_get_capabilities()
  72. */
  73. struct intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /*
  82. * Hotplug activation bits for this device
  83. */
  84. uint16_t hotplug_active;
  85. /**
  86. * This is used to select the color range of RBG outputs in HDMI mode.
  87. * It is only valid when using TMDS encoding and 8 bit per color mode.
  88. */
  89. uint32_t color_range;
  90. bool color_range_auto;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. bool rgb_quant_range_selectable;
  110. /**
  111. * This is set if we detect output of sdvo device as LVDS and
  112. * have a valid fixed mode to use with the panel.
  113. */
  114. bool is_lvds;
  115. /**
  116. * This is sdvo fixed pannel mode pointer
  117. */
  118. struct drm_display_mode *sdvo_lvds_fixed_mode;
  119. /* DDC bus used by this SDVO encoder */
  120. uint8_t ddc_bus;
  121. /*
  122. * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
  123. */
  124. uint8_t dtd_sdvo_flags;
  125. };
  126. struct intel_sdvo_connector {
  127. struct intel_connector base;
  128. /* Mark the type of connector */
  129. uint16_t output_flag;
  130. enum hdmi_force_audio force_audio;
  131. /* This contains all current supported TV format */
  132. u8 tv_format_supported[TV_FORMAT_NUM];
  133. int format_supported_num;
  134. struct drm_property *tv_format;
  135. /* add the property for the SDVO-TV */
  136. struct drm_property *left;
  137. struct drm_property *right;
  138. struct drm_property *top;
  139. struct drm_property *bottom;
  140. struct drm_property *hpos;
  141. struct drm_property *vpos;
  142. struct drm_property *contrast;
  143. struct drm_property *saturation;
  144. struct drm_property *hue;
  145. struct drm_property *sharpness;
  146. struct drm_property *flicker_filter;
  147. struct drm_property *flicker_filter_adaptive;
  148. struct drm_property *flicker_filter_2d;
  149. struct drm_property *tv_chroma_filter;
  150. struct drm_property *tv_luma_filter;
  151. struct drm_property *dot_crawl;
  152. /* add the property for the SDVO-TV/LVDS */
  153. struct drm_property *brightness;
  154. /* Add variable to record current setting for the above property */
  155. u32 left_margin, right_margin, top_margin, bottom_margin;
  156. /* this is to get the range of margin.*/
  157. u32 max_hscan, max_vscan;
  158. u32 max_hpos, cur_hpos;
  159. u32 max_vpos, cur_vpos;
  160. u32 cur_brightness, max_brightness;
  161. u32 cur_contrast, max_contrast;
  162. u32 cur_saturation, max_saturation;
  163. u32 cur_hue, max_hue;
  164. u32 cur_sharpness, max_sharpness;
  165. u32 cur_flicker_filter, max_flicker_filter;
  166. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  167. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  168. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  169. u32 cur_tv_luma_filter, max_tv_luma_filter;
  170. u32 cur_dot_crawl, max_dot_crawl;
  171. };
  172. static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
  173. {
  174. return container_of(encoder, struct intel_sdvo, base);
  175. }
  176. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  177. {
  178. return to_sdvo(intel_attached_encoder(connector));
  179. }
  180. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  181. {
  182. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  183. }
  184. static bool
  185. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  186. static bool
  187. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  188. struct intel_sdvo_connector *intel_sdvo_connector,
  189. int type);
  190. static bool
  191. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  192. struct intel_sdvo_connector *intel_sdvo_connector);
  193. /**
  194. * Writes the SDVOB or SDVOC with the given value, but always writes both
  195. * SDVOB and SDVOC to work around apparent hardware issues (according to
  196. * comments in the BIOS).
  197. */
  198. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  199. {
  200. struct drm_device *dev = intel_sdvo->base.base.dev;
  201. struct drm_i915_private *dev_priv = dev->dev_private;
  202. u32 bval = val, cval = val;
  203. int i;
  204. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  205. I915_WRITE(intel_sdvo->sdvo_reg, val);
  206. I915_READ(intel_sdvo->sdvo_reg);
  207. return;
  208. }
  209. if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
  210. cval = I915_READ(GEN3_SDVOC);
  211. else
  212. bval = I915_READ(GEN3_SDVOB);
  213. /*
  214. * Write the registers twice for luck. Sometimes,
  215. * writing them only once doesn't appear to 'stick'.
  216. * The BIOS does this too. Yay, magic
  217. */
  218. for (i = 0; i < 2; i++)
  219. {
  220. I915_WRITE(GEN3_SDVOB, bval);
  221. I915_READ(GEN3_SDVOB);
  222. I915_WRITE(GEN3_SDVOC, cval);
  223. I915_READ(GEN3_SDVOC);
  224. }
  225. }
  226. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  227. {
  228. struct i2c_msg msgs[] = {
  229. {
  230. .addr = intel_sdvo->slave_addr,
  231. .flags = 0,
  232. .len = 1,
  233. .buf = &addr,
  234. },
  235. {
  236. .addr = intel_sdvo->slave_addr,
  237. .flags = I2C_M_RD,
  238. .len = 1,
  239. .buf = ch,
  240. }
  241. };
  242. int ret;
  243. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  244. return true;
  245. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  246. return false;
  247. }
  248. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  249. /** Mapping of command numbers to names, for debug output */
  250. static const struct _sdvo_cmd_name {
  251. u8 cmd;
  252. const char *name;
  253. } sdvo_cmd_names[] = {
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  297. /* Add the op code for SDVO enhancements */
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  342. /* HDMI op code */
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  362. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  363. };
  364. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  365. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  366. const void *args, int args_len)
  367. {
  368. int i;
  369. DRM_DEBUG_KMS("%s: W: %02X ",
  370. SDVO_NAME(intel_sdvo), cmd);
  371. for (i = 0; i < args_len; i++)
  372. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  373. for (; i < 8; i++)
  374. DRM_LOG_KMS(" ");
  375. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  376. if (cmd == sdvo_cmd_names[i].cmd) {
  377. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  378. break;
  379. }
  380. }
  381. if (i == ARRAY_SIZE(sdvo_cmd_names))
  382. DRM_LOG_KMS("(%02X)", cmd);
  383. DRM_LOG_KMS("\n");
  384. }
  385. static const char *cmd_status_names[] = {
  386. "Power on",
  387. "Success",
  388. "Not supported",
  389. "Invalid arg",
  390. "Pending",
  391. "Target not specified",
  392. "Scaling not supported"
  393. };
  394. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  395. const void *args, int args_len)
  396. {
  397. u8 *buf, status;
  398. struct i2c_msg *msgs;
  399. int i, ret = true;
  400. /* Would be simpler to allocate both in one go ? */
  401. buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
  402. if (!buf)
  403. return false;
  404. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  405. if (!msgs) {
  406. kfree(buf);
  407. return false;
  408. }
  409. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  410. for (i = 0; i < args_len; i++) {
  411. msgs[i].addr = intel_sdvo->slave_addr;
  412. msgs[i].flags = 0;
  413. msgs[i].len = 2;
  414. msgs[i].buf = buf + 2 *i;
  415. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  416. buf[2*i + 1] = ((u8*)args)[i];
  417. }
  418. msgs[i].addr = intel_sdvo->slave_addr;
  419. msgs[i].flags = 0;
  420. msgs[i].len = 2;
  421. msgs[i].buf = buf + 2*i;
  422. buf[2*i + 0] = SDVO_I2C_OPCODE;
  423. buf[2*i + 1] = cmd;
  424. /* the following two are to read the response */
  425. status = SDVO_I2C_CMD_STATUS;
  426. msgs[i+1].addr = intel_sdvo->slave_addr;
  427. msgs[i+1].flags = 0;
  428. msgs[i+1].len = 1;
  429. msgs[i+1].buf = &status;
  430. msgs[i+2].addr = intel_sdvo->slave_addr;
  431. msgs[i+2].flags = I2C_M_RD;
  432. msgs[i+2].len = 1;
  433. msgs[i+2].buf = &status;
  434. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  435. if (ret < 0) {
  436. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  437. ret = false;
  438. goto out;
  439. }
  440. if (ret != i+3) {
  441. /* failure in I2C transfer */
  442. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  443. ret = false;
  444. }
  445. out:
  446. kfree(msgs);
  447. kfree(buf);
  448. return ret;
  449. }
  450. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  451. void *response, int response_len)
  452. {
  453. u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
  454. u8 status;
  455. int i;
  456. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  457. /*
  458. * The documentation states that all commands will be
  459. * processed within 15µs, and that we need only poll
  460. * the status byte a maximum of 3 times in order for the
  461. * command to be complete.
  462. *
  463. * Check 5 times in case the hardware failed to read the docs.
  464. *
  465. * Also beware that the first response by many devices is to
  466. * reply PENDING and stall for time. TVs are notorious for
  467. * requiring longer than specified to complete their replies.
  468. * Originally (in the DDX long ago), the delay was only ever 15ms
  469. * with an additional delay of 30ms applied for TVs added later after
  470. * many experiments. To accommodate both sets of delays, we do a
  471. * sequence of slow checks if the device is falling behind and fails
  472. * to reply within 5*15µs.
  473. */
  474. if (!intel_sdvo_read_byte(intel_sdvo,
  475. SDVO_I2C_CMD_STATUS,
  476. &status))
  477. goto log_fail;
  478. while (status == SDVO_CMD_STATUS_PENDING && --retry) {
  479. if (retry < 10)
  480. msleep(15);
  481. else
  482. udelay(15);
  483. if (!intel_sdvo_read_byte(intel_sdvo,
  484. SDVO_I2C_CMD_STATUS,
  485. &status))
  486. goto log_fail;
  487. }
  488. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  489. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  490. else
  491. DRM_LOG_KMS("(??? %d)", status);
  492. if (status != SDVO_CMD_STATUS_SUCCESS)
  493. goto log_fail;
  494. /* Read the command response */
  495. for (i = 0; i < response_len; i++) {
  496. if (!intel_sdvo_read_byte(intel_sdvo,
  497. SDVO_I2C_RETURN_0 + i,
  498. &((u8 *)response)[i]))
  499. goto log_fail;
  500. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  501. }
  502. DRM_LOG_KMS("\n");
  503. return true;
  504. log_fail:
  505. DRM_LOG_KMS("... failed\n");
  506. return false;
  507. }
  508. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  509. {
  510. if (mode->clock >= 100000)
  511. return 1;
  512. else if (mode->clock >= 50000)
  513. return 2;
  514. else
  515. return 4;
  516. }
  517. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  518. u8 ddc_bus)
  519. {
  520. /* This must be the immediately preceding write before the i2c xfer */
  521. return intel_sdvo_write_cmd(intel_sdvo,
  522. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  523. &ddc_bus, 1);
  524. }
  525. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  526. {
  527. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  528. return false;
  529. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  530. }
  531. static bool
  532. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  533. {
  534. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  535. return false;
  536. return intel_sdvo_read_response(intel_sdvo, value, len);
  537. }
  538. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  539. {
  540. struct intel_sdvo_set_target_input_args targets = {0};
  541. return intel_sdvo_set_value(intel_sdvo,
  542. SDVO_CMD_SET_TARGET_INPUT,
  543. &targets, sizeof(targets));
  544. }
  545. /**
  546. * Return whether each input is trained.
  547. *
  548. * This function is making an assumption about the layout of the response,
  549. * which should be checked against the docs.
  550. */
  551. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  552. {
  553. struct intel_sdvo_get_trained_inputs_response response;
  554. BUILD_BUG_ON(sizeof(response) != 1);
  555. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  556. &response, sizeof(response)))
  557. return false;
  558. *input_1 = response.input0_trained;
  559. *input_2 = response.input1_trained;
  560. return true;
  561. }
  562. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  563. u16 outputs)
  564. {
  565. return intel_sdvo_set_value(intel_sdvo,
  566. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  567. &outputs, sizeof(outputs));
  568. }
  569. static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
  570. u16 *outputs)
  571. {
  572. return intel_sdvo_get_value(intel_sdvo,
  573. SDVO_CMD_GET_ACTIVE_OUTPUTS,
  574. outputs, sizeof(*outputs));
  575. }
  576. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  577. int mode)
  578. {
  579. u8 state = SDVO_ENCODER_STATE_ON;
  580. switch (mode) {
  581. case DRM_MODE_DPMS_ON:
  582. state = SDVO_ENCODER_STATE_ON;
  583. break;
  584. case DRM_MODE_DPMS_STANDBY:
  585. state = SDVO_ENCODER_STATE_STANDBY;
  586. break;
  587. case DRM_MODE_DPMS_SUSPEND:
  588. state = SDVO_ENCODER_STATE_SUSPEND;
  589. break;
  590. case DRM_MODE_DPMS_OFF:
  591. state = SDVO_ENCODER_STATE_OFF;
  592. break;
  593. }
  594. return intel_sdvo_set_value(intel_sdvo,
  595. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  596. }
  597. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  598. int *clock_min,
  599. int *clock_max)
  600. {
  601. struct intel_sdvo_pixel_clock_range clocks;
  602. BUILD_BUG_ON(sizeof(clocks) != 4);
  603. if (!intel_sdvo_get_value(intel_sdvo,
  604. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  605. &clocks, sizeof(clocks)))
  606. return false;
  607. /* Convert the values from units of 10 kHz to kHz. */
  608. *clock_min = clocks.min * 10;
  609. *clock_max = clocks.max * 10;
  610. return true;
  611. }
  612. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  613. u16 outputs)
  614. {
  615. return intel_sdvo_set_value(intel_sdvo,
  616. SDVO_CMD_SET_TARGET_OUTPUT,
  617. &outputs, sizeof(outputs));
  618. }
  619. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  620. struct intel_sdvo_dtd *dtd)
  621. {
  622. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  623. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  624. }
  625. static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  626. struct intel_sdvo_dtd *dtd)
  627. {
  628. return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  629. intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  630. }
  631. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  632. struct intel_sdvo_dtd *dtd)
  633. {
  634. return intel_sdvo_set_timing(intel_sdvo,
  635. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  636. }
  637. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  638. struct intel_sdvo_dtd *dtd)
  639. {
  640. return intel_sdvo_set_timing(intel_sdvo,
  641. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  642. }
  643. static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
  644. struct intel_sdvo_dtd *dtd)
  645. {
  646. return intel_sdvo_get_timing(intel_sdvo,
  647. SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
  648. }
  649. static bool
  650. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  651. uint16_t clock,
  652. uint16_t width,
  653. uint16_t height)
  654. {
  655. struct intel_sdvo_preferred_input_timing_args args;
  656. memset(&args, 0, sizeof(args));
  657. args.clock = clock;
  658. args.width = width;
  659. args.height = height;
  660. args.interlace = 0;
  661. if (intel_sdvo->is_lvds &&
  662. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  663. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  664. args.scaled = 1;
  665. return intel_sdvo_set_value(intel_sdvo,
  666. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  667. &args, sizeof(args));
  668. }
  669. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  670. struct intel_sdvo_dtd *dtd)
  671. {
  672. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  673. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  674. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  675. &dtd->part1, sizeof(dtd->part1)) &&
  676. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  677. &dtd->part2, sizeof(dtd->part2));
  678. }
  679. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  680. {
  681. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  682. }
  683. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  684. const struct drm_display_mode *mode)
  685. {
  686. uint16_t width, height;
  687. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  688. uint16_t h_sync_offset, v_sync_offset;
  689. int mode_clock;
  690. width = mode->hdisplay;
  691. height = mode->vdisplay;
  692. /* do some mode translations */
  693. h_blank_len = mode->htotal - mode->hdisplay;
  694. h_sync_len = mode->hsync_end - mode->hsync_start;
  695. v_blank_len = mode->vtotal - mode->vdisplay;
  696. v_sync_len = mode->vsync_end - mode->vsync_start;
  697. h_sync_offset = mode->hsync_start - mode->hdisplay;
  698. v_sync_offset = mode->vsync_start - mode->vdisplay;
  699. mode_clock = mode->clock;
  700. mode_clock /= 10;
  701. dtd->part1.clock = mode_clock;
  702. dtd->part1.h_active = width & 0xff;
  703. dtd->part1.h_blank = h_blank_len & 0xff;
  704. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  705. ((h_blank_len >> 8) & 0xf);
  706. dtd->part1.v_active = height & 0xff;
  707. dtd->part1.v_blank = v_blank_len & 0xff;
  708. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  709. ((v_blank_len >> 8) & 0xf);
  710. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  711. dtd->part2.h_sync_width = h_sync_len & 0xff;
  712. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  713. (v_sync_len & 0xf);
  714. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  715. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  716. ((v_sync_len & 0x30) >> 4);
  717. dtd->part2.dtd_flags = 0x18;
  718. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  719. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  720. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  721. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  722. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  723. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  724. dtd->part2.sdvo_flags = 0;
  725. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  726. dtd->part2.reserved = 0;
  727. }
  728. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  729. const struct intel_sdvo_dtd *dtd)
  730. {
  731. mode->hdisplay = dtd->part1.h_active;
  732. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  733. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  734. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  735. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  736. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  737. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  738. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  739. mode->vdisplay = dtd->part1.v_active;
  740. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  741. mode->vsync_start = mode->vdisplay;
  742. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  743. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  744. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  745. mode->vsync_end = mode->vsync_start +
  746. (dtd->part2.v_sync_off_width & 0xf);
  747. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  748. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  749. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  750. mode->clock = dtd->part1.clock * 10;
  751. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  752. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  753. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  754. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  755. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  756. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  757. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  758. }
  759. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  760. {
  761. struct intel_sdvo_encode encode;
  762. BUILD_BUG_ON(sizeof(encode) != 2);
  763. return intel_sdvo_get_value(intel_sdvo,
  764. SDVO_CMD_GET_SUPP_ENCODE,
  765. &encode, sizeof(encode));
  766. }
  767. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  768. uint8_t mode)
  769. {
  770. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  771. }
  772. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  773. uint8_t mode)
  774. {
  775. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  776. }
  777. #if 0
  778. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  779. {
  780. int i, j;
  781. uint8_t set_buf_index[2];
  782. uint8_t av_split;
  783. uint8_t buf_size;
  784. uint8_t buf[48];
  785. uint8_t *pos;
  786. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  787. for (i = 0; i <= av_split; i++) {
  788. set_buf_index[0] = i; set_buf_index[1] = 0;
  789. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  790. set_buf_index, 2);
  791. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  792. intel_sdvo_read_response(encoder, &buf_size, 1);
  793. pos = buf;
  794. for (j = 0; j <= buf_size; j += 8) {
  795. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  796. NULL, 0);
  797. intel_sdvo_read_response(encoder, pos, 8);
  798. pos += 8;
  799. }
  800. }
  801. }
  802. #endif
  803. static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
  804. unsigned if_index, uint8_t tx_rate,
  805. uint8_t *data, unsigned length)
  806. {
  807. uint8_t set_buf_index[2] = { if_index, 0 };
  808. uint8_t hbuf_size, tmp[8];
  809. int i;
  810. if (!intel_sdvo_set_value(intel_sdvo,
  811. SDVO_CMD_SET_HBUF_INDEX,
  812. set_buf_index, 2))
  813. return false;
  814. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
  815. &hbuf_size, 1))
  816. return false;
  817. /* Buffer size is 0 based, hooray! */
  818. hbuf_size++;
  819. DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
  820. if_index, length, hbuf_size);
  821. for (i = 0; i < hbuf_size; i += 8) {
  822. memset(tmp, 0, 8);
  823. if (i < length)
  824. memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
  825. if (!intel_sdvo_set_value(intel_sdvo,
  826. SDVO_CMD_SET_HBUF_DATA,
  827. tmp, 8))
  828. return false;
  829. }
  830. return intel_sdvo_set_value(intel_sdvo,
  831. SDVO_CMD_SET_HBUF_TXRATE,
  832. &tx_rate, 1);
  833. }
  834. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
  835. const struct drm_display_mode *adjusted_mode)
  836. {
  837. struct dip_infoframe avi_if = {
  838. .type = DIP_TYPE_AVI,
  839. .ver = DIP_VERSION_AVI,
  840. .len = DIP_LEN_AVI,
  841. };
  842. uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
  843. struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
  844. if (intel_sdvo->rgb_quant_range_selectable) {
  845. if (intel_crtc->config.limited_color_range)
  846. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
  847. else
  848. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
  849. }
  850. avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
  851. intel_dip_infoframe_csum(&avi_if);
  852. /* sdvo spec says that the ecc is handled by the hw, and it looks like
  853. * we must not send the ecc field, either. */
  854. memcpy(sdvo_data, &avi_if, 3);
  855. sdvo_data[3] = avi_if.checksum;
  856. memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
  857. return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
  858. SDVO_HBUF_TX_VSYNC,
  859. sdvo_data, sizeof(sdvo_data));
  860. }
  861. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  862. {
  863. struct intel_sdvo_tv_format format;
  864. uint32_t format_map;
  865. format_map = 1 << intel_sdvo->tv_format_index;
  866. memset(&format, 0, sizeof(format));
  867. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  868. BUILD_BUG_ON(sizeof(format) != 6);
  869. return intel_sdvo_set_value(intel_sdvo,
  870. SDVO_CMD_SET_TV_FORMAT,
  871. &format, sizeof(format));
  872. }
  873. static bool
  874. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  875. const struct drm_display_mode *mode)
  876. {
  877. struct intel_sdvo_dtd output_dtd;
  878. if (!intel_sdvo_set_target_output(intel_sdvo,
  879. intel_sdvo->attached_output))
  880. return false;
  881. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  882. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  883. return false;
  884. return true;
  885. }
  886. /* Asks the sdvo controller for the preferred input mode given the output mode.
  887. * Unfortunately we have to set up the full output mode to do that. */
  888. static bool
  889. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  890. const struct drm_display_mode *mode,
  891. struct drm_display_mode *adjusted_mode)
  892. {
  893. struct intel_sdvo_dtd input_dtd;
  894. /* Reset the input timing to the screen. Assume always input 0. */
  895. if (!intel_sdvo_set_target_input(intel_sdvo))
  896. return false;
  897. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  898. mode->clock / 10,
  899. mode->hdisplay,
  900. mode->vdisplay))
  901. return false;
  902. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  903. &input_dtd))
  904. return false;
  905. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  906. intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
  907. return true;
  908. }
  909. static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
  910. {
  911. unsigned dotclock = pipe_config->adjusted_mode.clock;
  912. struct dpll *clock = &pipe_config->dpll;
  913. /* SDVO TV has fixed PLL values depend on its clock range,
  914. this mirrors vbios setting. */
  915. if (dotclock >= 100000 && dotclock < 140500) {
  916. clock->p1 = 2;
  917. clock->p2 = 10;
  918. clock->n = 3;
  919. clock->m1 = 16;
  920. clock->m2 = 8;
  921. } else if (dotclock >= 140500 && dotclock <= 200000) {
  922. clock->p1 = 1;
  923. clock->p2 = 10;
  924. clock->n = 6;
  925. clock->m1 = 12;
  926. clock->m2 = 8;
  927. } else {
  928. WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
  929. }
  930. pipe_config->clock_set = true;
  931. }
  932. static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
  933. struct intel_crtc_config *pipe_config)
  934. {
  935. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  936. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  937. struct drm_display_mode *mode = &pipe_config->requested_mode;
  938. DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
  939. pipe_config->pipe_bpp = 8*3;
  940. if (HAS_PCH_SPLIT(encoder->base.dev))
  941. pipe_config->has_pch_encoder = true;
  942. /* We need to construct preferred input timings based on our
  943. * output timings. To do that, we have to set the output
  944. * timings, even though this isn't really the right place in
  945. * the sequence to do it. Oh well.
  946. */
  947. if (intel_sdvo->is_tv) {
  948. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  949. return false;
  950. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  951. mode,
  952. adjusted_mode);
  953. pipe_config->sdvo_tv_clock = true;
  954. } else if (intel_sdvo->is_lvds) {
  955. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  956. intel_sdvo->sdvo_lvds_fixed_mode))
  957. return false;
  958. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  959. mode,
  960. adjusted_mode);
  961. }
  962. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  963. * SDVO device will factor out the multiplier during mode_set.
  964. */
  965. pipe_config->pixel_multiplier =
  966. intel_sdvo_get_pixel_multiplier(adjusted_mode);
  967. adjusted_mode->clock *= pipe_config->pixel_multiplier;
  968. if (intel_sdvo->color_range_auto) {
  969. /* See CEA-861-E - 5.1 Default Encoding Parameters */
  970. /* FIXME: This bit is only valid when using TMDS encoding and 8
  971. * bit per color mode. */
  972. if (intel_sdvo->has_hdmi_monitor &&
  973. drm_match_cea_mode(adjusted_mode) > 1)
  974. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  975. else
  976. intel_sdvo->color_range = 0;
  977. }
  978. if (intel_sdvo->color_range)
  979. pipe_config->limited_color_range = true;
  980. /* Clock computation needs to happen after pixel multiplier. */
  981. if (intel_sdvo->is_tv)
  982. i9xx_adjust_sdvo_tv_clock(pipe_config);
  983. return true;
  984. }
  985. static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
  986. {
  987. struct drm_device *dev = intel_encoder->base.dev;
  988. struct drm_i915_private *dev_priv = dev->dev_private;
  989. struct drm_crtc *crtc = intel_encoder->base.crtc;
  990. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  991. struct drm_display_mode *adjusted_mode =
  992. &intel_crtc->config.adjusted_mode;
  993. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  994. struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
  995. u32 sdvox;
  996. struct intel_sdvo_in_out_map in_out;
  997. struct intel_sdvo_dtd input_dtd, output_dtd;
  998. int rate;
  999. if (!mode)
  1000. return;
  1001. /* First, set the input mapping for the first input to our controlled
  1002. * output. This is only correct if we're a single-input device, in
  1003. * which case the first input is the output from the appropriate SDVO
  1004. * channel on the motherboard. In a two-input device, the first input
  1005. * will be SDVOB and the second SDVOC.
  1006. */
  1007. in_out.in0 = intel_sdvo->attached_output;
  1008. in_out.in1 = 0;
  1009. intel_sdvo_set_value(intel_sdvo,
  1010. SDVO_CMD_SET_IN_OUT_MAP,
  1011. &in_out, sizeof(in_out));
  1012. /* Set the output timings to the screen */
  1013. if (!intel_sdvo_set_target_output(intel_sdvo,
  1014. intel_sdvo->attached_output))
  1015. return;
  1016. /* lvds has a special fixed output timing. */
  1017. if (intel_sdvo->is_lvds)
  1018. intel_sdvo_get_dtd_from_mode(&output_dtd,
  1019. intel_sdvo->sdvo_lvds_fixed_mode);
  1020. else
  1021. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  1022. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  1023. DRM_INFO("Setting output timings on %s failed\n",
  1024. SDVO_NAME(intel_sdvo));
  1025. /* Set the input timing to the screen. Assume always input 0. */
  1026. if (!intel_sdvo_set_target_input(intel_sdvo))
  1027. return;
  1028. if (intel_sdvo->has_hdmi_monitor) {
  1029. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  1030. intel_sdvo_set_colorimetry(intel_sdvo,
  1031. SDVO_COLORIMETRY_RGB256);
  1032. intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
  1033. } else
  1034. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  1035. if (intel_sdvo->is_tv &&
  1036. !intel_sdvo_set_tv_format(intel_sdvo))
  1037. return;
  1038. /* We have tried to get input timing in mode_fixup, and filled into
  1039. * adjusted_mode.
  1040. */
  1041. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  1042. if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
  1043. input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
  1044. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  1045. DRM_INFO("Setting input timings on %s failed\n",
  1046. SDVO_NAME(intel_sdvo));
  1047. switch (intel_crtc->config.pixel_multiplier) {
  1048. default:
  1049. WARN(1, "unknown pixel mutlipler specified\n");
  1050. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  1051. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  1052. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  1053. }
  1054. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  1055. return;
  1056. /* Set the SDVO control regs. */
  1057. if (INTEL_INFO(dev)->gen >= 4) {
  1058. /* The real mode polarity is set by the SDVO commands, using
  1059. * struct intel_sdvo_dtd. */
  1060. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  1061. if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
  1062. sdvox |= intel_sdvo->color_range;
  1063. if (INTEL_INFO(dev)->gen < 5)
  1064. sdvox |= SDVO_BORDER_ENABLE;
  1065. } else {
  1066. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1067. switch (intel_sdvo->sdvo_reg) {
  1068. case GEN3_SDVOB:
  1069. sdvox &= SDVOB_PRESERVE_MASK;
  1070. break;
  1071. case GEN3_SDVOC:
  1072. sdvox &= SDVOC_PRESERVE_MASK;
  1073. break;
  1074. }
  1075. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1076. }
  1077. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  1078. sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
  1079. else
  1080. sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1081. if (intel_sdvo->has_hdmi_audio)
  1082. sdvox |= SDVO_AUDIO_ENABLE;
  1083. if (INTEL_INFO(dev)->gen >= 4) {
  1084. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1085. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1086. /* done in crtc_mode_set as it lives inside the dpll register */
  1087. } else {
  1088. sdvox |= (intel_crtc->config.pixel_multiplier - 1)
  1089. << SDVO_PORT_MULTIPLY_SHIFT;
  1090. }
  1091. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  1092. INTEL_INFO(dev)->gen < 5)
  1093. sdvox |= SDVO_STALL_SELECT;
  1094. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  1095. }
  1096. static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
  1097. {
  1098. struct intel_sdvo_connector *intel_sdvo_connector =
  1099. to_intel_sdvo_connector(&connector->base);
  1100. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
  1101. u16 active_outputs = 0;
  1102. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1103. if (active_outputs & intel_sdvo_connector->output_flag)
  1104. return true;
  1105. else
  1106. return false;
  1107. }
  1108. static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
  1109. enum pipe *pipe)
  1110. {
  1111. struct drm_device *dev = encoder->base.dev;
  1112. struct drm_i915_private *dev_priv = dev->dev_private;
  1113. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1114. u16 active_outputs = 0;
  1115. u32 tmp;
  1116. tmp = I915_READ(intel_sdvo->sdvo_reg);
  1117. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1118. if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
  1119. return false;
  1120. if (HAS_PCH_CPT(dev))
  1121. *pipe = PORT_TO_PIPE_CPT(tmp);
  1122. else
  1123. *pipe = PORT_TO_PIPE(tmp);
  1124. return true;
  1125. }
  1126. static void intel_sdvo_get_config(struct intel_encoder *encoder,
  1127. struct intel_crtc_config *pipe_config)
  1128. {
  1129. struct drm_device *dev = encoder->base.dev;
  1130. struct drm_i915_private *dev_priv = dev->dev_private;
  1131. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1132. struct intel_sdvo_dtd dtd;
  1133. int encoder_pixel_multiplier = 0;
  1134. u32 flags = 0, sdvox;
  1135. u8 val;
  1136. bool ret;
  1137. ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
  1138. if (!ret) {
  1139. /* Some sdvo encoders are not spec compliant and don't
  1140. * implement the mandatory get_timings function. */
  1141. DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
  1142. pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
  1143. } else {
  1144. if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  1145. flags |= DRM_MODE_FLAG_PHSYNC;
  1146. else
  1147. flags |= DRM_MODE_FLAG_NHSYNC;
  1148. if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  1149. flags |= DRM_MODE_FLAG_PVSYNC;
  1150. else
  1151. flags |= DRM_MODE_FLAG_NVSYNC;
  1152. }
  1153. pipe_config->adjusted_mode.flags |= flags;
  1154. /*
  1155. * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
  1156. * the sdvo port register, on all other platforms it is part of the dpll
  1157. * state. Since the general pipe state readout happens before the
  1158. * encoder->get_config we so already have a valid pixel multplier on all
  1159. * other platfroms.
  1160. */
  1161. if (IS_I915G(dev) || IS_I915GM(dev)) {
  1162. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1163. pipe_config->pixel_multiplier =
  1164. ((sdvox & SDVO_PORT_MULTIPLY_MASK)
  1165. >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
  1166. }
  1167. /* Cross check the port pixel multiplier with the sdvo encoder state. */
  1168. if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
  1169. &val, 1)) {
  1170. switch (val) {
  1171. case SDVO_CLOCK_RATE_MULT_1X:
  1172. encoder_pixel_multiplier = 1;
  1173. break;
  1174. case SDVO_CLOCK_RATE_MULT_2X:
  1175. encoder_pixel_multiplier = 2;
  1176. break;
  1177. case SDVO_CLOCK_RATE_MULT_4X:
  1178. encoder_pixel_multiplier = 4;
  1179. break;
  1180. }
  1181. }
  1182. WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
  1183. "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
  1184. pipe_config->pixel_multiplier, encoder_pixel_multiplier);
  1185. }
  1186. static void intel_disable_sdvo(struct intel_encoder *encoder)
  1187. {
  1188. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1189. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1190. u32 temp;
  1191. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1192. if (0)
  1193. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1194. DRM_MODE_DPMS_OFF);
  1195. temp = I915_READ(intel_sdvo->sdvo_reg);
  1196. if ((temp & SDVO_ENABLE) != 0) {
  1197. /* HW workaround for IBX, we need to move the port to
  1198. * transcoder A before disabling it. */
  1199. if (HAS_PCH_IBX(encoder->base.dev)) {
  1200. struct drm_crtc *crtc = encoder->base.crtc;
  1201. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1202. if (temp & SDVO_PIPE_B_SELECT) {
  1203. temp &= ~SDVO_PIPE_B_SELECT;
  1204. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1205. POSTING_READ(intel_sdvo->sdvo_reg);
  1206. /* Again we need to write this twice. */
  1207. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1208. POSTING_READ(intel_sdvo->sdvo_reg);
  1209. /* Transcoder selection bits only update
  1210. * effectively on vblank. */
  1211. if (crtc)
  1212. intel_wait_for_vblank(encoder->base.dev, pipe);
  1213. else
  1214. msleep(50);
  1215. }
  1216. }
  1217. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1218. }
  1219. }
  1220. static void intel_enable_sdvo(struct intel_encoder *encoder)
  1221. {
  1222. struct drm_device *dev = encoder->base.dev;
  1223. struct drm_i915_private *dev_priv = dev->dev_private;
  1224. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1225. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1226. u32 temp;
  1227. bool input1, input2;
  1228. int i;
  1229. u8 status;
  1230. temp = I915_READ(intel_sdvo->sdvo_reg);
  1231. if ((temp & SDVO_ENABLE) == 0) {
  1232. /* HW workaround for IBX, we need to move the port
  1233. * to transcoder A before disabling it, so restore it here. */
  1234. if (HAS_PCH_IBX(dev))
  1235. temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1236. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1237. }
  1238. for (i = 0; i < 2; i++)
  1239. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1240. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1241. /* Warn if the device reported failure to sync.
  1242. * A lot of SDVO devices fail to notify of sync, but it's
  1243. * a given it the status is a success, we succeeded.
  1244. */
  1245. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1246. DRM_DEBUG_KMS("First %s output reported failure to "
  1247. "sync\n", SDVO_NAME(intel_sdvo));
  1248. }
  1249. if (0)
  1250. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1251. DRM_MODE_DPMS_ON);
  1252. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1253. }
  1254. /* Special dpms function to support cloning between dvo/sdvo/crt. */
  1255. static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
  1256. {
  1257. struct drm_crtc *crtc;
  1258. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1259. /* dvo supports only 2 dpms states. */
  1260. if (mode != DRM_MODE_DPMS_ON)
  1261. mode = DRM_MODE_DPMS_OFF;
  1262. if (mode == connector->dpms)
  1263. return;
  1264. connector->dpms = mode;
  1265. /* Only need to change hw state when actually enabled */
  1266. crtc = intel_sdvo->base.base.crtc;
  1267. if (!crtc) {
  1268. intel_sdvo->base.connectors_active = false;
  1269. return;
  1270. }
  1271. /* We set active outputs manually below in case pipe dpms doesn't change
  1272. * due to cloning. */
  1273. if (mode != DRM_MODE_DPMS_ON) {
  1274. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1275. if (0)
  1276. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1277. intel_sdvo->base.connectors_active = false;
  1278. intel_crtc_update_dpms(crtc);
  1279. } else {
  1280. intel_sdvo->base.connectors_active = true;
  1281. intel_crtc_update_dpms(crtc);
  1282. if (0)
  1283. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1284. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1285. }
  1286. intel_modeset_check_state(connector->dev);
  1287. }
  1288. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1289. struct drm_display_mode *mode)
  1290. {
  1291. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1292. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1293. return MODE_NO_DBLESCAN;
  1294. if (intel_sdvo->pixel_clock_min > mode->clock)
  1295. return MODE_CLOCK_LOW;
  1296. if (intel_sdvo->pixel_clock_max < mode->clock)
  1297. return MODE_CLOCK_HIGH;
  1298. if (intel_sdvo->is_lvds) {
  1299. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1300. return MODE_PANEL;
  1301. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1302. return MODE_PANEL;
  1303. }
  1304. return MODE_OK;
  1305. }
  1306. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1307. {
  1308. BUILD_BUG_ON(sizeof(*caps) != 8);
  1309. if (!intel_sdvo_get_value(intel_sdvo,
  1310. SDVO_CMD_GET_DEVICE_CAPS,
  1311. caps, sizeof(*caps)))
  1312. return false;
  1313. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1314. " vendor_id: %d\n"
  1315. " device_id: %d\n"
  1316. " device_rev_id: %d\n"
  1317. " sdvo_version_major: %d\n"
  1318. " sdvo_version_minor: %d\n"
  1319. " sdvo_inputs_mask: %d\n"
  1320. " smooth_scaling: %d\n"
  1321. " sharp_scaling: %d\n"
  1322. " up_scaling: %d\n"
  1323. " down_scaling: %d\n"
  1324. " stall_support: %d\n"
  1325. " output_flags: %d\n",
  1326. caps->vendor_id,
  1327. caps->device_id,
  1328. caps->device_rev_id,
  1329. caps->sdvo_version_major,
  1330. caps->sdvo_version_minor,
  1331. caps->sdvo_inputs_mask,
  1332. caps->smooth_scaling,
  1333. caps->sharp_scaling,
  1334. caps->up_scaling,
  1335. caps->down_scaling,
  1336. caps->stall_support,
  1337. caps->output_flags);
  1338. return true;
  1339. }
  1340. static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
  1341. {
  1342. struct drm_device *dev = intel_sdvo->base.base.dev;
  1343. uint16_t hotplug;
  1344. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1345. * on the line. */
  1346. if (IS_I945G(dev) || IS_I945GM(dev))
  1347. return 0;
  1348. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1349. &hotplug, sizeof(hotplug)))
  1350. return 0;
  1351. return hotplug;
  1352. }
  1353. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1354. {
  1355. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1356. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
  1357. &intel_sdvo->hotplug_active, 2);
  1358. }
  1359. static bool
  1360. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1361. {
  1362. /* Is there more than one type of output? */
  1363. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1364. }
  1365. static struct edid *
  1366. intel_sdvo_get_edid(struct drm_connector *connector)
  1367. {
  1368. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1369. return drm_get_edid(connector, &sdvo->ddc);
  1370. }
  1371. /* Mac mini hack -- use the same DDC as the analog connector */
  1372. static struct edid *
  1373. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1374. {
  1375. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1376. return drm_get_edid(connector,
  1377. intel_gmbus_get_adapter(dev_priv,
  1378. dev_priv->vbt.crt_ddc_pin));
  1379. }
  1380. static enum drm_connector_status
  1381. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1382. {
  1383. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1384. enum drm_connector_status status;
  1385. struct edid *edid;
  1386. edid = intel_sdvo_get_edid(connector);
  1387. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1388. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1389. /*
  1390. * Don't use the 1 as the argument of DDC bus switch to get
  1391. * the EDID. It is used for SDVO SPD ROM.
  1392. */
  1393. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1394. intel_sdvo->ddc_bus = ddc;
  1395. edid = intel_sdvo_get_edid(connector);
  1396. if (edid)
  1397. break;
  1398. }
  1399. /*
  1400. * If we found the EDID on the other bus,
  1401. * assume that is the correct DDC bus.
  1402. */
  1403. if (edid == NULL)
  1404. intel_sdvo->ddc_bus = saved_ddc;
  1405. }
  1406. /*
  1407. * When there is no edid and no monitor is connected with VGA
  1408. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1409. */
  1410. if (edid == NULL)
  1411. edid = intel_sdvo_get_analog_edid(connector);
  1412. status = connector_status_unknown;
  1413. if (edid != NULL) {
  1414. /* DDC bus is shared, match EDID to connector type */
  1415. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1416. status = connector_status_connected;
  1417. if (intel_sdvo->is_hdmi) {
  1418. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1419. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1420. intel_sdvo->rgb_quant_range_selectable =
  1421. drm_rgb_quant_range_selectable(edid);
  1422. }
  1423. } else
  1424. status = connector_status_disconnected;
  1425. kfree(edid);
  1426. }
  1427. if (status == connector_status_connected) {
  1428. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1429. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1430. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1431. }
  1432. return status;
  1433. }
  1434. static bool
  1435. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1436. struct edid *edid)
  1437. {
  1438. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1439. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1440. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1441. connector_is_digital, monitor_is_digital);
  1442. return connector_is_digital == monitor_is_digital;
  1443. }
  1444. static enum drm_connector_status
  1445. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1446. {
  1447. uint16_t response;
  1448. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1449. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1450. enum drm_connector_status ret;
  1451. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1452. connector->base.id, drm_get_connector_name(connector));
  1453. if (!intel_sdvo_get_value(intel_sdvo,
  1454. SDVO_CMD_GET_ATTACHED_DISPLAYS,
  1455. &response, 2))
  1456. return connector_status_unknown;
  1457. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1458. response & 0xff, response >> 8,
  1459. intel_sdvo_connector->output_flag);
  1460. if (response == 0)
  1461. return connector_status_disconnected;
  1462. intel_sdvo->attached_output = response;
  1463. intel_sdvo->has_hdmi_monitor = false;
  1464. intel_sdvo->has_hdmi_audio = false;
  1465. intel_sdvo->rgb_quant_range_selectable = false;
  1466. if ((intel_sdvo_connector->output_flag & response) == 0)
  1467. ret = connector_status_disconnected;
  1468. else if (IS_TMDS(intel_sdvo_connector))
  1469. ret = intel_sdvo_tmds_sink_detect(connector);
  1470. else {
  1471. struct edid *edid;
  1472. /* if we have an edid check it matches the connection */
  1473. edid = intel_sdvo_get_edid(connector);
  1474. if (edid == NULL)
  1475. edid = intel_sdvo_get_analog_edid(connector);
  1476. if (edid != NULL) {
  1477. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1478. edid))
  1479. ret = connector_status_connected;
  1480. else
  1481. ret = connector_status_disconnected;
  1482. kfree(edid);
  1483. } else
  1484. ret = connector_status_connected;
  1485. }
  1486. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1487. if (ret == connector_status_connected) {
  1488. intel_sdvo->is_tv = false;
  1489. intel_sdvo->is_lvds = false;
  1490. if (response & SDVO_TV_MASK)
  1491. intel_sdvo->is_tv = true;
  1492. if (response & SDVO_LVDS_MASK)
  1493. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1494. }
  1495. return ret;
  1496. }
  1497. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1498. {
  1499. struct edid *edid;
  1500. /* set the bus switch and get the modes */
  1501. edid = intel_sdvo_get_edid(connector);
  1502. /*
  1503. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1504. * link between analog and digital outputs. So, if the regular SDVO
  1505. * DDC fails, check to see if the analog output is disconnected, in
  1506. * which case we'll look there for the digital DDC data.
  1507. */
  1508. if (edid == NULL)
  1509. edid = intel_sdvo_get_analog_edid(connector);
  1510. if (edid != NULL) {
  1511. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1512. edid)) {
  1513. drm_mode_connector_update_edid_property(connector, edid);
  1514. drm_add_edid_modes(connector, edid);
  1515. }
  1516. kfree(edid);
  1517. }
  1518. }
  1519. /*
  1520. * Set of SDVO TV modes.
  1521. * Note! This is in reply order (see loop in get_tv_modes).
  1522. * XXX: all 60Hz refresh?
  1523. */
  1524. static const struct drm_display_mode sdvo_tv_modes[] = {
  1525. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1526. 416, 0, 200, 201, 232, 233, 0,
  1527. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1528. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1529. 416, 0, 240, 241, 272, 273, 0,
  1530. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1531. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1532. 496, 0, 300, 301, 332, 333, 0,
  1533. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1534. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1535. 736, 0, 350, 351, 382, 383, 0,
  1536. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1537. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1538. 736, 0, 400, 401, 432, 433, 0,
  1539. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1540. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1541. 736, 0, 480, 481, 512, 513, 0,
  1542. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1543. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1544. 800, 0, 480, 481, 512, 513, 0,
  1545. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1546. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1547. 800, 0, 576, 577, 608, 609, 0,
  1548. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1549. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1550. 816, 0, 350, 351, 382, 383, 0,
  1551. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1552. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1553. 816, 0, 400, 401, 432, 433, 0,
  1554. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1555. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1556. 816, 0, 480, 481, 512, 513, 0,
  1557. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1558. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1559. 816, 0, 540, 541, 572, 573, 0,
  1560. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1561. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1562. 816, 0, 576, 577, 608, 609, 0,
  1563. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1564. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1565. 864, 0, 576, 577, 608, 609, 0,
  1566. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1567. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1568. 896, 0, 600, 601, 632, 633, 0,
  1569. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1570. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1571. 928, 0, 624, 625, 656, 657, 0,
  1572. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1573. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1574. 1016, 0, 766, 767, 798, 799, 0,
  1575. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1576. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1577. 1120, 0, 768, 769, 800, 801, 0,
  1578. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1579. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1580. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1581. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1582. };
  1583. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1584. {
  1585. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1586. struct intel_sdvo_sdtv_resolution_request tv_res;
  1587. uint32_t reply = 0, format_map = 0;
  1588. int i;
  1589. /* Read the list of supported input resolutions for the selected TV
  1590. * format.
  1591. */
  1592. format_map = 1 << intel_sdvo->tv_format_index;
  1593. memcpy(&tv_res, &format_map,
  1594. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1595. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1596. return;
  1597. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1598. if (!intel_sdvo_write_cmd(intel_sdvo,
  1599. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1600. &tv_res, sizeof(tv_res)))
  1601. return;
  1602. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1603. return;
  1604. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1605. if (reply & (1 << i)) {
  1606. struct drm_display_mode *nmode;
  1607. nmode = drm_mode_duplicate(connector->dev,
  1608. &sdvo_tv_modes[i]);
  1609. if (nmode)
  1610. drm_mode_probed_add(connector, nmode);
  1611. }
  1612. }
  1613. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1614. {
  1615. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1616. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1617. struct drm_display_mode *newmode;
  1618. /*
  1619. * Fetch modes from VBT. For SDVO prefer the VBT mode since some
  1620. * SDVO->LVDS transcoders can't cope with the EDID mode.
  1621. */
  1622. if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
  1623. newmode = drm_mode_duplicate(connector->dev,
  1624. dev_priv->vbt.sdvo_lvds_vbt_mode);
  1625. if (newmode != NULL) {
  1626. /* Guarantee the mode is preferred */
  1627. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1628. DRM_MODE_TYPE_DRIVER);
  1629. drm_mode_probed_add(connector, newmode);
  1630. }
  1631. }
  1632. /*
  1633. * Attempt to get the mode list from DDC.
  1634. * Assume that the preferred modes are
  1635. * arranged in priority order.
  1636. */
  1637. intel_ddc_get_modes(connector, &intel_sdvo->ddc);
  1638. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1639. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1640. intel_sdvo->sdvo_lvds_fixed_mode =
  1641. drm_mode_duplicate(connector->dev, newmode);
  1642. intel_sdvo->is_lvds = true;
  1643. break;
  1644. }
  1645. }
  1646. }
  1647. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1648. {
  1649. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1650. if (IS_TV(intel_sdvo_connector))
  1651. intel_sdvo_get_tv_modes(connector);
  1652. else if (IS_LVDS(intel_sdvo_connector))
  1653. intel_sdvo_get_lvds_modes(connector);
  1654. else
  1655. intel_sdvo_get_ddc_modes(connector);
  1656. return !list_empty(&connector->probed_modes);
  1657. }
  1658. static void
  1659. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1660. {
  1661. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1662. struct drm_device *dev = connector->dev;
  1663. if (intel_sdvo_connector->left)
  1664. drm_property_destroy(dev, intel_sdvo_connector->left);
  1665. if (intel_sdvo_connector->right)
  1666. drm_property_destroy(dev, intel_sdvo_connector->right);
  1667. if (intel_sdvo_connector->top)
  1668. drm_property_destroy(dev, intel_sdvo_connector->top);
  1669. if (intel_sdvo_connector->bottom)
  1670. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1671. if (intel_sdvo_connector->hpos)
  1672. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1673. if (intel_sdvo_connector->vpos)
  1674. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1675. if (intel_sdvo_connector->saturation)
  1676. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1677. if (intel_sdvo_connector->contrast)
  1678. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1679. if (intel_sdvo_connector->hue)
  1680. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1681. if (intel_sdvo_connector->sharpness)
  1682. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1683. if (intel_sdvo_connector->flicker_filter)
  1684. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1685. if (intel_sdvo_connector->flicker_filter_2d)
  1686. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1687. if (intel_sdvo_connector->flicker_filter_adaptive)
  1688. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1689. if (intel_sdvo_connector->tv_luma_filter)
  1690. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1691. if (intel_sdvo_connector->tv_chroma_filter)
  1692. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1693. if (intel_sdvo_connector->dot_crawl)
  1694. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1695. if (intel_sdvo_connector->brightness)
  1696. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1697. }
  1698. static void intel_sdvo_destroy(struct drm_connector *connector)
  1699. {
  1700. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1701. if (intel_sdvo_connector->tv_format)
  1702. drm_property_destroy(connector->dev,
  1703. intel_sdvo_connector->tv_format);
  1704. intel_sdvo_destroy_enhance_property(connector);
  1705. drm_sysfs_connector_remove(connector);
  1706. drm_connector_cleanup(connector);
  1707. kfree(intel_sdvo_connector);
  1708. }
  1709. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1710. {
  1711. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1712. struct edid *edid;
  1713. bool has_audio = false;
  1714. if (!intel_sdvo->is_hdmi)
  1715. return false;
  1716. edid = intel_sdvo_get_edid(connector);
  1717. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1718. has_audio = drm_detect_monitor_audio(edid);
  1719. kfree(edid);
  1720. return has_audio;
  1721. }
  1722. static int
  1723. intel_sdvo_set_property(struct drm_connector *connector,
  1724. struct drm_property *property,
  1725. uint64_t val)
  1726. {
  1727. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1728. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1729. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1730. uint16_t temp_value;
  1731. uint8_t cmd;
  1732. int ret;
  1733. ret = drm_object_property_set_value(&connector->base, property, val);
  1734. if (ret)
  1735. return ret;
  1736. if (property == dev_priv->force_audio_property) {
  1737. int i = val;
  1738. bool has_audio;
  1739. if (i == intel_sdvo_connector->force_audio)
  1740. return 0;
  1741. intel_sdvo_connector->force_audio = i;
  1742. if (i == HDMI_AUDIO_AUTO)
  1743. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1744. else
  1745. has_audio = (i == HDMI_AUDIO_ON);
  1746. if (has_audio == intel_sdvo->has_hdmi_audio)
  1747. return 0;
  1748. intel_sdvo->has_hdmi_audio = has_audio;
  1749. goto done;
  1750. }
  1751. if (property == dev_priv->broadcast_rgb_property) {
  1752. bool old_auto = intel_sdvo->color_range_auto;
  1753. uint32_t old_range = intel_sdvo->color_range;
  1754. switch (val) {
  1755. case INTEL_BROADCAST_RGB_AUTO:
  1756. intel_sdvo->color_range_auto = true;
  1757. break;
  1758. case INTEL_BROADCAST_RGB_FULL:
  1759. intel_sdvo->color_range_auto = false;
  1760. intel_sdvo->color_range = 0;
  1761. break;
  1762. case INTEL_BROADCAST_RGB_LIMITED:
  1763. intel_sdvo->color_range_auto = false;
  1764. /* FIXME: this bit is only valid when using TMDS
  1765. * encoding and 8 bit per color mode. */
  1766. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  1767. break;
  1768. default:
  1769. return -EINVAL;
  1770. }
  1771. if (old_auto == intel_sdvo->color_range_auto &&
  1772. old_range == intel_sdvo->color_range)
  1773. return 0;
  1774. goto done;
  1775. }
  1776. #define CHECK_PROPERTY(name, NAME) \
  1777. if (intel_sdvo_connector->name == property) { \
  1778. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1779. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1780. cmd = SDVO_CMD_SET_##NAME; \
  1781. intel_sdvo_connector->cur_##name = temp_value; \
  1782. goto set_value; \
  1783. }
  1784. if (property == intel_sdvo_connector->tv_format) {
  1785. if (val >= TV_FORMAT_NUM)
  1786. return -EINVAL;
  1787. if (intel_sdvo->tv_format_index ==
  1788. intel_sdvo_connector->tv_format_supported[val])
  1789. return 0;
  1790. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1791. goto done;
  1792. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1793. temp_value = val;
  1794. if (intel_sdvo_connector->left == property) {
  1795. drm_object_property_set_value(&connector->base,
  1796. intel_sdvo_connector->right, val);
  1797. if (intel_sdvo_connector->left_margin == temp_value)
  1798. return 0;
  1799. intel_sdvo_connector->left_margin = temp_value;
  1800. intel_sdvo_connector->right_margin = temp_value;
  1801. temp_value = intel_sdvo_connector->max_hscan -
  1802. intel_sdvo_connector->left_margin;
  1803. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1804. goto set_value;
  1805. } else if (intel_sdvo_connector->right == property) {
  1806. drm_object_property_set_value(&connector->base,
  1807. intel_sdvo_connector->left, val);
  1808. if (intel_sdvo_connector->right_margin == temp_value)
  1809. return 0;
  1810. intel_sdvo_connector->left_margin = temp_value;
  1811. intel_sdvo_connector->right_margin = temp_value;
  1812. temp_value = intel_sdvo_connector->max_hscan -
  1813. intel_sdvo_connector->left_margin;
  1814. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1815. goto set_value;
  1816. } else if (intel_sdvo_connector->top == property) {
  1817. drm_object_property_set_value(&connector->base,
  1818. intel_sdvo_connector->bottom, val);
  1819. if (intel_sdvo_connector->top_margin == temp_value)
  1820. return 0;
  1821. intel_sdvo_connector->top_margin = temp_value;
  1822. intel_sdvo_connector->bottom_margin = temp_value;
  1823. temp_value = intel_sdvo_connector->max_vscan -
  1824. intel_sdvo_connector->top_margin;
  1825. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1826. goto set_value;
  1827. } else if (intel_sdvo_connector->bottom == property) {
  1828. drm_object_property_set_value(&connector->base,
  1829. intel_sdvo_connector->top, val);
  1830. if (intel_sdvo_connector->bottom_margin == temp_value)
  1831. return 0;
  1832. intel_sdvo_connector->top_margin = temp_value;
  1833. intel_sdvo_connector->bottom_margin = temp_value;
  1834. temp_value = intel_sdvo_connector->max_vscan -
  1835. intel_sdvo_connector->top_margin;
  1836. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1837. goto set_value;
  1838. }
  1839. CHECK_PROPERTY(hpos, HPOS)
  1840. CHECK_PROPERTY(vpos, VPOS)
  1841. CHECK_PROPERTY(saturation, SATURATION)
  1842. CHECK_PROPERTY(contrast, CONTRAST)
  1843. CHECK_PROPERTY(hue, HUE)
  1844. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1845. CHECK_PROPERTY(sharpness, SHARPNESS)
  1846. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1847. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1848. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1849. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1850. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1851. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1852. }
  1853. return -EINVAL; /* unknown property */
  1854. set_value:
  1855. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1856. return -EIO;
  1857. done:
  1858. if (intel_sdvo->base.base.crtc)
  1859. intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
  1860. return 0;
  1861. #undef CHECK_PROPERTY
  1862. }
  1863. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1864. .dpms = intel_sdvo_dpms,
  1865. .detect = intel_sdvo_detect,
  1866. .fill_modes = drm_helper_probe_single_connector_modes,
  1867. .set_property = intel_sdvo_set_property,
  1868. .destroy = intel_sdvo_destroy,
  1869. };
  1870. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1871. .get_modes = intel_sdvo_get_modes,
  1872. .mode_valid = intel_sdvo_mode_valid,
  1873. .best_encoder = intel_best_encoder,
  1874. };
  1875. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1876. {
  1877. struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
  1878. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1879. drm_mode_destroy(encoder->dev,
  1880. intel_sdvo->sdvo_lvds_fixed_mode);
  1881. i2c_del_adapter(&intel_sdvo->ddc);
  1882. intel_encoder_destroy(encoder);
  1883. }
  1884. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1885. .destroy = intel_sdvo_enc_destroy,
  1886. };
  1887. static void
  1888. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1889. {
  1890. uint16_t mask = 0;
  1891. unsigned int num_bits;
  1892. /* Make a mask of outputs less than or equal to our own priority in the
  1893. * list.
  1894. */
  1895. switch (sdvo->controlled_output) {
  1896. case SDVO_OUTPUT_LVDS1:
  1897. mask |= SDVO_OUTPUT_LVDS1;
  1898. case SDVO_OUTPUT_LVDS0:
  1899. mask |= SDVO_OUTPUT_LVDS0;
  1900. case SDVO_OUTPUT_TMDS1:
  1901. mask |= SDVO_OUTPUT_TMDS1;
  1902. case SDVO_OUTPUT_TMDS0:
  1903. mask |= SDVO_OUTPUT_TMDS0;
  1904. case SDVO_OUTPUT_RGB1:
  1905. mask |= SDVO_OUTPUT_RGB1;
  1906. case SDVO_OUTPUT_RGB0:
  1907. mask |= SDVO_OUTPUT_RGB0;
  1908. break;
  1909. }
  1910. /* Count bits to find what number we are in the priority list. */
  1911. mask &= sdvo->caps.output_flags;
  1912. num_bits = hweight16(mask);
  1913. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1914. if (num_bits > 3)
  1915. num_bits = 3;
  1916. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1917. sdvo->ddc_bus = 1 << num_bits;
  1918. }
  1919. /**
  1920. * Choose the appropriate DDC bus for control bus switch command for this
  1921. * SDVO output based on the controlled output.
  1922. *
  1923. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1924. * outputs, then LVDS outputs.
  1925. */
  1926. static void
  1927. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1928. struct intel_sdvo *sdvo, u32 reg)
  1929. {
  1930. struct sdvo_device_mapping *mapping;
  1931. if (sdvo->is_sdvob)
  1932. mapping = &(dev_priv->sdvo_mappings[0]);
  1933. else
  1934. mapping = &(dev_priv->sdvo_mappings[1]);
  1935. if (mapping->initialized)
  1936. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1937. else
  1938. intel_sdvo_guess_ddc_bus(sdvo);
  1939. }
  1940. static void
  1941. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1942. struct intel_sdvo *sdvo, u32 reg)
  1943. {
  1944. struct sdvo_device_mapping *mapping;
  1945. u8 pin;
  1946. if (sdvo->is_sdvob)
  1947. mapping = &dev_priv->sdvo_mappings[0];
  1948. else
  1949. mapping = &dev_priv->sdvo_mappings[1];
  1950. if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
  1951. pin = mapping->i2c_pin;
  1952. else
  1953. pin = GMBUS_PORT_DPB;
  1954. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1955. /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
  1956. * our code totally fails once we start using gmbus. Hence fall back to
  1957. * bit banging for now. */
  1958. intel_gmbus_force_bit(sdvo->i2c, true);
  1959. }
  1960. /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
  1961. static void
  1962. intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
  1963. {
  1964. intel_gmbus_force_bit(sdvo->i2c, false);
  1965. }
  1966. static bool
  1967. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1968. {
  1969. return intel_sdvo_check_supp_encode(intel_sdvo);
  1970. }
  1971. static u8
  1972. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1973. {
  1974. struct drm_i915_private *dev_priv = dev->dev_private;
  1975. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1976. if (sdvo->is_sdvob) {
  1977. my_mapping = &dev_priv->sdvo_mappings[0];
  1978. other_mapping = &dev_priv->sdvo_mappings[1];
  1979. } else {
  1980. my_mapping = &dev_priv->sdvo_mappings[1];
  1981. other_mapping = &dev_priv->sdvo_mappings[0];
  1982. }
  1983. /* If the BIOS described our SDVO device, take advantage of it. */
  1984. if (my_mapping->slave_addr)
  1985. return my_mapping->slave_addr;
  1986. /* If the BIOS only described a different SDVO device, use the
  1987. * address that it isn't using.
  1988. */
  1989. if (other_mapping->slave_addr) {
  1990. if (other_mapping->slave_addr == 0x70)
  1991. return 0x72;
  1992. else
  1993. return 0x70;
  1994. }
  1995. /* No SDVO device info is found for another DVO port,
  1996. * so use mapping assumption we had before BIOS parsing.
  1997. */
  1998. if (sdvo->is_sdvob)
  1999. return 0x70;
  2000. else
  2001. return 0x72;
  2002. }
  2003. static void
  2004. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  2005. struct intel_sdvo *encoder)
  2006. {
  2007. drm_connector_init(encoder->base.base.dev,
  2008. &connector->base.base,
  2009. &intel_sdvo_connector_funcs,
  2010. connector->base.base.connector_type);
  2011. drm_connector_helper_add(&connector->base.base,
  2012. &intel_sdvo_connector_helper_funcs);
  2013. connector->base.base.interlace_allowed = 1;
  2014. connector->base.base.doublescan_allowed = 0;
  2015. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  2016. connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
  2017. intel_connector_attach_encoder(&connector->base, &encoder->base);
  2018. drm_sysfs_connector_add(&connector->base.base);
  2019. }
  2020. static void
  2021. intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
  2022. struct intel_sdvo_connector *connector)
  2023. {
  2024. struct drm_device *dev = connector->base.base.dev;
  2025. intel_attach_force_audio_property(&connector->base.base);
  2026. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
  2027. intel_attach_broadcast_rgb_property(&connector->base.base);
  2028. intel_sdvo->color_range_auto = true;
  2029. }
  2030. }
  2031. static bool
  2032. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  2033. {
  2034. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2035. struct drm_connector *connector;
  2036. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2037. struct intel_connector *intel_connector;
  2038. struct intel_sdvo_connector *intel_sdvo_connector;
  2039. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2040. if (!intel_sdvo_connector)
  2041. return false;
  2042. if (device == 0) {
  2043. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  2044. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  2045. } else if (device == 1) {
  2046. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  2047. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  2048. }
  2049. intel_connector = &intel_sdvo_connector->base;
  2050. connector = &intel_connector->base;
  2051. if (intel_sdvo_get_hotplug_support(intel_sdvo) &
  2052. intel_sdvo_connector->output_flag) {
  2053. intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
  2054. /* Some SDVO devices have one-shot hotplug interrupts.
  2055. * Ensure that they get re-enabled when an interrupt happens.
  2056. */
  2057. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  2058. intel_sdvo_enable_hotplug(intel_encoder);
  2059. } else {
  2060. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  2061. }
  2062. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  2063. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  2064. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  2065. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  2066. intel_sdvo->is_hdmi = true;
  2067. }
  2068. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2069. if (intel_sdvo->is_hdmi)
  2070. intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
  2071. return true;
  2072. }
  2073. static bool
  2074. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  2075. {
  2076. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2077. struct drm_connector *connector;
  2078. struct intel_connector *intel_connector;
  2079. struct intel_sdvo_connector *intel_sdvo_connector;
  2080. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2081. if (!intel_sdvo_connector)
  2082. return false;
  2083. intel_connector = &intel_sdvo_connector->base;
  2084. connector = &intel_connector->base;
  2085. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  2086. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  2087. intel_sdvo->controlled_output |= type;
  2088. intel_sdvo_connector->output_flag = type;
  2089. intel_sdvo->is_tv = true;
  2090. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2091. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  2092. goto err;
  2093. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2094. goto err;
  2095. return true;
  2096. err:
  2097. intel_sdvo_destroy(connector);
  2098. return false;
  2099. }
  2100. static bool
  2101. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  2102. {
  2103. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2104. struct drm_connector *connector;
  2105. struct intel_connector *intel_connector;
  2106. struct intel_sdvo_connector *intel_sdvo_connector;
  2107. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2108. if (!intel_sdvo_connector)
  2109. return false;
  2110. intel_connector = &intel_sdvo_connector->base;
  2111. connector = &intel_connector->base;
  2112. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  2113. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  2114. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  2115. if (device == 0) {
  2116. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  2117. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  2118. } else if (device == 1) {
  2119. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  2120. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  2121. }
  2122. intel_sdvo_connector_init(intel_sdvo_connector,
  2123. intel_sdvo);
  2124. return true;
  2125. }
  2126. static bool
  2127. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  2128. {
  2129. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2130. struct drm_connector *connector;
  2131. struct intel_connector *intel_connector;
  2132. struct intel_sdvo_connector *intel_sdvo_connector;
  2133. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2134. if (!intel_sdvo_connector)
  2135. return false;
  2136. intel_connector = &intel_sdvo_connector->base;
  2137. connector = &intel_connector->base;
  2138. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  2139. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  2140. if (device == 0) {
  2141. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  2142. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  2143. } else if (device == 1) {
  2144. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  2145. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  2146. }
  2147. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2148. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2149. goto err;
  2150. return true;
  2151. err:
  2152. intel_sdvo_destroy(connector);
  2153. return false;
  2154. }
  2155. static bool
  2156. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  2157. {
  2158. intel_sdvo->is_tv = false;
  2159. intel_sdvo->is_lvds = false;
  2160. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  2161. if (flags & SDVO_OUTPUT_TMDS0)
  2162. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  2163. return false;
  2164. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  2165. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  2166. return false;
  2167. /* TV has no XXX1 function block */
  2168. if (flags & SDVO_OUTPUT_SVID0)
  2169. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  2170. return false;
  2171. if (flags & SDVO_OUTPUT_CVBS0)
  2172. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  2173. return false;
  2174. if (flags & SDVO_OUTPUT_YPRPB0)
  2175. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  2176. return false;
  2177. if (flags & SDVO_OUTPUT_RGB0)
  2178. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  2179. return false;
  2180. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  2181. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  2182. return false;
  2183. if (flags & SDVO_OUTPUT_LVDS0)
  2184. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  2185. return false;
  2186. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  2187. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  2188. return false;
  2189. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  2190. unsigned char bytes[2];
  2191. intel_sdvo->controlled_output = 0;
  2192. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  2193. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  2194. SDVO_NAME(intel_sdvo),
  2195. bytes[0], bytes[1]);
  2196. return false;
  2197. }
  2198. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2199. return true;
  2200. }
  2201. static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
  2202. {
  2203. struct drm_device *dev = intel_sdvo->base.base.dev;
  2204. struct drm_connector *connector, *tmp;
  2205. list_for_each_entry_safe(connector, tmp,
  2206. &dev->mode_config.connector_list, head) {
  2207. if (intel_attached_encoder(connector) == &intel_sdvo->base)
  2208. intel_sdvo_destroy(connector);
  2209. }
  2210. }
  2211. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  2212. struct intel_sdvo_connector *intel_sdvo_connector,
  2213. int type)
  2214. {
  2215. struct drm_device *dev = intel_sdvo->base.base.dev;
  2216. struct intel_sdvo_tv_format format;
  2217. uint32_t format_map, i;
  2218. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  2219. return false;
  2220. BUILD_BUG_ON(sizeof(format) != 6);
  2221. if (!intel_sdvo_get_value(intel_sdvo,
  2222. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  2223. &format, sizeof(format)))
  2224. return false;
  2225. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  2226. if (format_map == 0)
  2227. return false;
  2228. intel_sdvo_connector->format_supported_num = 0;
  2229. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  2230. if (format_map & (1 << i))
  2231. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  2232. intel_sdvo_connector->tv_format =
  2233. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  2234. "mode", intel_sdvo_connector->format_supported_num);
  2235. if (!intel_sdvo_connector->tv_format)
  2236. return false;
  2237. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  2238. drm_property_add_enum(
  2239. intel_sdvo_connector->tv_format, i,
  2240. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  2241. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  2242. drm_object_attach_property(&intel_sdvo_connector->base.base.base,
  2243. intel_sdvo_connector->tv_format, 0);
  2244. return true;
  2245. }
  2246. #define ENHANCEMENT(name, NAME) do { \
  2247. if (enhancements.name) { \
  2248. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  2249. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  2250. return false; \
  2251. intel_sdvo_connector->max_##name = data_value[0]; \
  2252. intel_sdvo_connector->cur_##name = response; \
  2253. intel_sdvo_connector->name = \
  2254. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  2255. if (!intel_sdvo_connector->name) return false; \
  2256. drm_object_attach_property(&connector->base, \
  2257. intel_sdvo_connector->name, \
  2258. intel_sdvo_connector->cur_##name); \
  2259. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  2260. data_value[0], data_value[1], response); \
  2261. } \
  2262. } while (0)
  2263. static bool
  2264. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  2265. struct intel_sdvo_connector *intel_sdvo_connector,
  2266. struct intel_sdvo_enhancements_reply enhancements)
  2267. {
  2268. struct drm_device *dev = intel_sdvo->base.base.dev;
  2269. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2270. uint16_t response, data_value[2];
  2271. /* when horizontal overscan is supported, Add the left/right property */
  2272. if (enhancements.overscan_h) {
  2273. if (!intel_sdvo_get_value(intel_sdvo,
  2274. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2275. &data_value, 4))
  2276. return false;
  2277. if (!intel_sdvo_get_value(intel_sdvo,
  2278. SDVO_CMD_GET_OVERSCAN_H,
  2279. &response, 2))
  2280. return false;
  2281. intel_sdvo_connector->max_hscan = data_value[0];
  2282. intel_sdvo_connector->left_margin = data_value[0] - response;
  2283. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2284. intel_sdvo_connector->left =
  2285. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2286. if (!intel_sdvo_connector->left)
  2287. return false;
  2288. drm_object_attach_property(&connector->base,
  2289. intel_sdvo_connector->left,
  2290. intel_sdvo_connector->left_margin);
  2291. intel_sdvo_connector->right =
  2292. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2293. if (!intel_sdvo_connector->right)
  2294. return false;
  2295. drm_object_attach_property(&connector->base,
  2296. intel_sdvo_connector->right,
  2297. intel_sdvo_connector->right_margin);
  2298. DRM_DEBUG_KMS("h_overscan: max %d, "
  2299. "default %d, current %d\n",
  2300. data_value[0], data_value[1], response);
  2301. }
  2302. if (enhancements.overscan_v) {
  2303. if (!intel_sdvo_get_value(intel_sdvo,
  2304. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2305. &data_value, 4))
  2306. return false;
  2307. if (!intel_sdvo_get_value(intel_sdvo,
  2308. SDVO_CMD_GET_OVERSCAN_V,
  2309. &response, 2))
  2310. return false;
  2311. intel_sdvo_connector->max_vscan = data_value[0];
  2312. intel_sdvo_connector->top_margin = data_value[0] - response;
  2313. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2314. intel_sdvo_connector->top =
  2315. drm_property_create_range(dev, 0,
  2316. "top_margin", 0, data_value[0]);
  2317. if (!intel_sdvo_connector->top)
  2318. return false;
  2319. drm_object_attach_property(&connector->base,
  2320. intel_sdvo_connector->top,
  2321. intel_sdvo_connector->top_margin);
  2322. intel_sdvo_connector->bottom =
  2323. drm_property_create_range(dev, 0,
  2324. "bottom_margin", 0, data_value[0]);
  2325. if (!intel_sdvo_connector->bottom)
  2326. return false;
  2327. drm_object_attach_property(&connector->base,
  2328. intel_sdvo_connector->bottom,
  2329. intel_sdvo_connector->bottom_margin);
  2330. DRM_DEBUG_KMS("v_overscan: max %d, "
  2331. "default %d, current %d\n",
  2332. data_value[0], data_value[1], response);
  2333. }
  2334. ENHANCEMENT(hpos, HPOS);
  2335. ENHANCEMENT(vpos, VPOS);
  2336. ENHANCEMENT(saturation, SATURATION);
  2337. ENHANCEMENT(contrast, CONTRAST);
  2338. ENHANCEMENT(hue, HUE);
  2339. ENHANCEMENT(sharpness, SHARPNESS);
  2340. ENHANCEMENT(brightness, BRIGHTNESS);
  2341. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2342. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2343. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2344. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2345. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2346. if (enhancements.dot_crawl) {
  2347. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2348. return false;
  2349. intel_sdvo_connector->max_dot_crawl = 1;
  2350. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2351. intel_sdvo_connector->dot_crawl =
  2352. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2353. if (!intel_sdvo_connector->dot_crawl)
  2354. return false;
  2355. drm_object_attach_property(&connector->base,
  2356. intel_sdvo_connector->dot_crawl,
  2357. intel_sdvo_connector->cur_dot_crawl);
  2358. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2359. }
  2360. return true;
  2361. }
  2362. static bool
  2363. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2364. struct intel_sdvo_connector *intel_sdvo_connector,
  2365. struct intel_sdvo_enhancements_reply enhancements)
  2366. {
  2367. struct drm_device *dev = intel_sdvo->base.base.dev;
  2368. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2369. uint16_t response, data_value[2];
  2370. ENHANCEMENT(brightness, BRIGHTNESS);
  2371. return true;
  2372. }
  2373. #undef ENHANCEMENT
  2374. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2375. struct intel_sdvo_connector *intel_sdvo_connector)
  2376. {
  2377. union {
  2378. struct intel_sdvo_enhancements_reply reply;
  2379. uint16_t response;
  2380. } enhancements;
  2381. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2382. enhancements.response = 0;
  2383. intel_sdvo_get_value(intel_sdvo,
  2384. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2385. &enhancements, sizeof(enhancements));
  2386. if (enhancements.response == 0) {
  2387. DRM_DEBUG_KMS("No enhancement is supported\n");
  2388. return true;
  2389. }
  2390. if (IS_TV(intel_sdvo_connector))
  2391. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2392. else if (IS_LVDS(intel_sdvo_connector))
  2393. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2394. else
  2395. return true;
  2396. }
  2397. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2398. struct i2c_msg *msgs,
  2399. int num)
  2400. {
  2401. struct intel_sdvo *sdvo = adapter->algo_data;
  2402. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2403. return -EIO;
  2404. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2405. }
  2406. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2407. {
  2408. struct intel_sdvo *sdvo = adapter->algo_data;
  2409. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2410. }
  2411. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2412. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2413. .functionality = intel_sdvo_ddc_proxy_func
  2414. };
  2415. static bool
  2416. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2417. struct drm_device *dev)
  2418. {
  2419. sdvo->ddc.owner = THIS_MODULE;
  2420. sdvo->ddc.class = I2C_CLASS_DDC;
  2421. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2422. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2423. sdvo->ddc.algo_data = sdvo;
  2424. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2425. return i2c_add_adapter(&sdvo->ddc) == 0;
  2426. }
  2427. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2428. {
  2429. struct drm_i915_private *dev_priv = dev->dev_private;
  2430. struct intel_encoder *intel_encoder;
  2431. struct intel_sdvo *intel_sdvo;
  2432. int i;
  2433. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2434. if (!intel_sdvo)
  2435. return false;
  2436. intel_sdvo->sdvo_reg = sdvo_reg;
  2437. intel_sdvo->is_sdvob = is_sdvob;
  2438. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2439. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2440. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
  2441. goto err_i2c_bus;
  2442. /* encoder type will be decided later */
  2443. intel_encoder = &intel_sdvo->base;
  2444. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2445. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2446. /* Read the regs to test if we can talk to the device */
  2447. for (i = 0; i < 0x40; i++) {
  2448. u8 byte;
  2449. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2450. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2451. SDVO_NAME(intel_sdvo));
  2452. goto err;
  2453. }
  2454. }
  2455. intel_encoder->compute_config = intel_sdvo_compute_config;
  2456. intel_encoder->disable = intel_disable_sdvo;
  2457. intel_encoder->mode_set = intel_sdvo_mode_set;
  2458. intel_encoder->enable = intel_enable_sdvo;
  2459. intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
  2460. intel_encoder->get_config = intel_sdvo_get_config;
  2461. /* In default case sdvo lvds is false */
  2462. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2463. goto err;
  2464. if (intel_sdvo_output_setup(intel_sdvo,
  2465. intel_sdvo->caps.output_flags) != true) {
  2466. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2467. SDVO_NAME(intel_sdvo));
  2468. /* Output_setup can leave behind connectors! */
  2469. goto err_output;
  2470. }
  2471. /* Only enable the hotplug irq if we need it, to work around noisy
  2472. * hotplug lines.
  2473. */
  2474. if (intel_sdvo->hotplug_active) {
  2475. intel_encoder->hpd_pin =
  2476. intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
  2477. }
  2478. /*
  2479. * Cloning SDVO with anything is often impossible, since the SDVO
  2480. * encoder can request a special input timing mode. And even if that's
  2481. * not the case we have evidence that cloning a plain unscaled mode with
  2482. * VGA doesn't really work. Furthermore the cloning flags are way too
  2483. * simplistic anyway to express such constraints, so just give up on
  2484. * cloning for SDVO encoders.
  2485. */
  2486. intel_sdvo->base.cloneable = false;
  2487. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2488. /* Set the input timing to the screen. Assume always input 0. */
  2489. if (!intel_sdvo_set_target_input(intel_sdvo))
  2490. goto err_output;
  2491. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2492. &intel_sdvo->pixel_clock_min,
  2493. &intel_sdvo->pixel_clock_max))
  2494. goto err_output;
  2495. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2496. "clock range %dMHz - %dMHz, "
  2497. "input 1: %c, input 2: %c, "
  2498. "output 1: %c, output 2: %c\n",
  2499. SDVO_NAME(intel_sdvo),
  2500. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2501. intel_sdvo->caps.device_rev_id,
  2502. intel_sdvo->pixel_clock_min / 1000,
  2503. intel_sdvo->pixel_clock_max / 1000,
  2504. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2505. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2506. /* check currently supported outputs */
  2507. intel_sdvo->caps.output_flags &
  2508. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2509. intel_sdvo->caps.output_flags &
  2510. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2511. return true;
  2512. err_output:
  2513. intel_sdvo_output_cleanup(intel_sdvo);
  2514. err:
  2515. drm_encoder_cleanup(&intel_encoder->base);
  2516. i2c_del_adapter(&intel_sdvo->ddc);
  2517. err_i2c_bus:
  2518. intel_sdvo_unselect_i2c_bus(intel_sdvo);
  2519. kfree(intel_sdvo);
  2520. return false;
  2521. }