tegra114.dtsi 3.1 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra114";
  4. interrupt-parent = <&gic>;
  5. gic: interrupt-controller {
  6. compatible = "arm,cortex-a15-gic";
  7. #interrupt-cells = <3>;
  8. interrupt-controller;
  9. reg = <0x50041000 0x1000>,
  10. <0x50042000 0x1000>,
  11. <0x50044000 0x2000>,
  12. <0x50046000 0x2000>;
  13. interrupts = <1 9 0xf04>;
  14. };
  15. timer@60005000 {
  16. compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
  17. reg = <0x60005000 0x400>;
  18. interrupts = <0 0 0x04
  19. 0 1 0x04
  20. 0 41 0x04
  21. 0 42 0x04
  22. 0 121 0x04
  23. 0 122 0x04>;
  24. };
  25. tegra_car: clock {
  26. compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
  27. reg = <0x60006000 0x1000>;
  28. #clock-cells = <1>;
  29. };
  30. ahb: ahb {
  31. compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
  32. reg = <0x6000c004 0x14c>;
  33. };
  34. gpio: gpio {
  35. compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
  36. reg = <0x6000d000 0x1000>;
  37. interrupts = <0 32 0x04
  38. 0 33 0x04
  39. 0 34 0x04
  40. 0 35 0x04
  41. 0 55 0x04
  42. 0 87 0x04
  43. 0 89 0x04
  44. 0 125 0x04>;
  45. #gpio-cells = <2>;
  46. gpio-controller;
  47. #interrupt-cells = <2>;
  48. interrupt-controller;
  49. };
  50. pinmux: pinmux {
  51. compatible = "nvidia,tegra114-pinmux";
  52. reg = <0x70000868 0x148 /* Pad control registers */
  53. 0x70003000 0x40c>; /* Mux registers */
  54. };
  55. serial@70006000 {
  56. compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  57. reg = <0x70006000 0x40>;
  58. reg-shift = <2>;
  59. interrupts = <0 36 0x04>;
  60. status = "disabled";
  61. };
  62. serial@70006040 {
  63. compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  64. reg = <0x70006040 0x40>;
  65. reg-shift = <2>;
  66. interrupts = <0 37 0x04>;
  67. status = "disabled";
  68. };
  69. serial@70006200 {
  70. compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  71. reg = <0x70006200 0x100>;
  72. reg-shift = <2>;
  73. interrupts = <0 46 0x04>;
  74. status = "disabled";
  75. };
  76. serial@70006300 {
  77. compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  78. reg = <0x70006300 0x100>;
  79. reg-shift = <2>;
  80. interrupts = <0 90 0x04>;
  81. status = "disabled";
  82. };
  83. rtc {
  84. compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
  85. reg = <0x7000e000 0x100>;
  86. interrupts = <0 2 0x04>;
  87. };
  88. pmc {
  89. compatible = "nvidia,tegra114-pmc";
  90. reg = <0x7000e400 0x400>;
  91. clocks = <&tegra_car 261>, <&clk32k_in>;
  92. clock-names = "pclk", "clk32k_in";
  93. };
  94. iommu {
  95. compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
  96. reg = <0x7000f010 0x02c
  97. 0x7000f1f0 0x010
  98. 0x7000f228 0x074>;
  99. nvidia,#asids = <4>;
  100. dma-window = <0 0x40000000>;
  101. nvidia,swgroups = <0x18659fe>;
  102. nvidia,ahb = <&ahb>;
  103. };
  104. cpus {
  105. #address-cells = <1>;
  106. #size-cells = <0>;
  107. cpu@0 {
  108. device_type = "cpu";
  109. compatible = "arm,cortex-a15";
  110. reg = <0>;
  111. };
  112. cpu@1 {
  113. device_type = "cpu";
  114. compatible = "arm,cortex-a15";
  115. reg = <1>;
  116. };
  117. cpu@2 {
  118. device_type = "cpu";
  119. compatible = "arm,cortex-a15";
  120. reg = <2>;
  121. };
  122. cpu@3 {
  123. device_type = "cpu";
  124. compatible = "arm,cortex-a15";
  125. reg = <3>;
  126. };
  127. };
  128. timer {
  129. compatible = "arm,armv7-timer";
  130. interrupts = <1 13 0xf08>,
  131. <1 14 0xf08>,
  132. <1 11 0xf08>,
  133. <1 10 0xf08>;
  134. };
  135. };