debug.h 4.6 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef DEBUG_H
  17. #define DEBUG_H
  18. #include "hw.h"
  19. struct ath_txq;
  20. struct ath_buf;
  21. #ifdef CONFIG_ATH9K_DEBUG
  22. #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  23. #else
  24. #define TX_STAT_INC(q, c) do { } while (0)
  25. #endif
  26. #ifdef CONFIG_ATH9K_DEBUG
  27. /**
  28. * struct ath_interrupt_stats - Contains statistics about interrupts
  29. * @total: Total no. of interrupts generated so far
  30. * @rxok: RX with no errors
  31. * @rxeol: RX with no more RXDESC available
  32. * @rxorn: RX FIFO overrun
  33. * @txok: TX completed at the requested rate
  34. * @txurn: TX FIFO underrun
  35. * @mib: MIB regs reaching its threshold
  36. * @rxphyerr: RX with phy errors
  37. * @rx_keycache_miss: RX with key cache misses
  38. * @swba: Software Beacon Alert
  39. * @bmiss: Beacon Miss
  40. * @bnr: Beacon Not Ready
  41. * @cst: Carrier Sense TImeout
  42. * @gtt: Global TX Timeout
  43. * @tim: RX beacon TIM occurrence
  44. * @cabend: RX End of CAB traffic
  45. * @dtimsync: DTIM sync lossage
  46. * @dtim: RX Beacon with DTIM
  47. */
  48. struct ath_interrupt_stats {
  49. u32 total;
  50. u32 rxok;
  51. u32 rxeol;
  52. u32 rxorn;
  53. u32 txok;
  54. u32 txeol;
  55. u32 txurn;
  56. u32 mib;
  57. u32 rxphyerr;
  58. u32 rx_keycache_miss;
  59. u32 swba;
  60. u32 bmiss;
  61. u32 bnr;
  62. u32 cst;
  63. u32 gtt;
  64. u32 tim;
  65. u32 cabend;
  66. u32 dtimsync;
  67. u32 dtim;
  68. };
  69. struct ath_rc_stats {
  70. u32 success;
  71. u32 retries;
  72. u32 xretries;
  73. u8 per;
  74. };
  75. /**
  76. * struct ath_tx_stats - Statistics about TX
  77. * @queued: Total MPDUs (non-aggr) queued
  78. * @completed: Total MPDUs (non-aggr) completed
  79. * @a_aggr: Total no. of aggregates queued
  80. * @a_queued: Total AMPDUs queued
  81. * @a_completed: Total AMPDUs completed
  82. * @a_retries: No. of AMPDUs retried (SW)
  83. * @a_xretries: No. of AMPDUs dropped due to xretries
  84. * @fifo_underrun: FIFO underrun occurrences
  85. Valid only for:
  86. - non-aggregate condition.
  87. - first packet of aggregate.
  88. * @xtxop: No. of frames filtered because of TXOP limit
  89. * @timer_exp: Transmit timer expiry
  90. * @desc_cfg_err: Descriptor configuration errors
  91. * @data_urn: TX data underrun errors
  92. * @delim_urn: TX delimiter underrun errors
  93. */
  94. struct ath_tx_stats {
  95. u32 queued;
  96. u32 completed;
  97. u32 a_aggr;
  98. u32 a_queued;
  99. u32 a_completed;
  100. u32 a_retries;
  101. u32 a_xretries;
  102. u32 fifo_underrun;
  103. u32 xtxop;
  104. u32 timer_exp;
  105. u32 desc_cfg_err;
  106. u32 data_underrun;
  107. u32 delim_underrun;
  108. };
  109. struct ath_stats {
  110. struct ath_interrupt_stats istats;
  111. struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
  112. struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
  113. };
  114. struct ath9k_debug {
  115. struct dentry *debugfs_phy;
  116. struct dentry *debugfs_debug;
  117. struct dentry *debugfs_dma;
  118. struct dentry *debugfs_interrupt;
  119. struct dentry *debugfs_rcstat;
  120. struct dentry *debugfs_wiphy;
  121. struct dentry *debugfs_xmit;
  122. struct ath_stats stats;
  123. };
  124. int ath9k_init_debug(struct ath_hw *ah);
  125. void ath9k_exit_debug(struct ath_hw *ah);
  126. int ath9k_debug_create_root(void);
  127. void ath9k_debug_remove_root(void);
  128. void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
  129. void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb);
  130. void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
  131. struct ath_buf *bf);
  132. void ath_debug_stat_retries(struct ath_softc *sc, int rix,
  133. int xretries, int retries, u8 per);
  134. #else
  135. static inline int ath9k_init_debug(struct ath_hw *ah)
  136. {
  137. return 0;
  138. }
  139. static inline void ath9k_exit_debug(struct ath_hw *ah)
  140. {
  141. }
  142. static inline int ath9k_debug_create_root(void)
  143. {
  144. return 0;
  145. }
  146. static inline void ath9k_debug_remove_root(void)
  147. {
  148. }
  149. static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
  150. enum ath9k_int status)
  151. {
  152. }
  153. static inline void ath_debug_stat_rc(struct ath_softc *sc,
  154. struct sk_buff *skb)
  155. {
  156. }
  157. static inline void ath_debug_stat_tx(struct ath_softc *sc,
  158. struct ath_txq *txq,
  159. struct ath_buf *bf)
  160. {
  161. }
  162. static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
  163. int xretries, int retries, u8 per)
  164. {
  165. }
  166. #endif /* CONFIG_ATH9K_DEBUG */
  167. #endif /* DEBUG_H */