be_main.c 150 KB

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  1. /**
  2. * Copyright (C) 2005 - 2013 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
  145. DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
  146. DEVICE_ATTR(beiscsi_active_cid_count, S_IRUGO, beiscsi_active_cid_disp, NULL);
  147. struct device_attribute *beiscsi_attrs[] = {
  148. &dev_attr_beiscsi_log_enable,
  149. &dev_attr_beiscsi_drvr_ver,
  150. &dev_attr_beiscsi_adapter_family,
  151. &dev_attr_beiscsi_fw_ver,
  152. &dev_attr_beiscsi_active_cid_count,
  153. NULL,
  154. };
  155. static char const *cqe_desc[] = {
  156. "RESERVED_DESC",
  157. "SOL_CMD_COMPLETE",
  158. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  159. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  160. "CXN_KILLED_BURST_LEN_MISMATCH",
  161. "CXN_KILLED_AHS_RCVD",
  162. "CXN_KILLED_HDR_DIGEST_ERR",
  163. "CXN_KILLED_UNKNOWN_HDR",
  164. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  165. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  166. "CXN_KILLED_RST_RCVD",
  167. "CXN_KILLED_TIMED_OUT",
  168. "CXN_KILLED_RST_SENT",
  169. "CXN_KILLED_FIN_RCVD",
  170. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  171. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  172. "CXN_KILLED_OVER_RUN_RESIDUAL",
  173. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  174. "CMD_KILLED_INVALID_STATSN_RCVD",
  175. "CMD_KILLED_INVALID_R2T_RCVD",
  176. "CMD_CXN_KILLED_LUN_INVALID",
  177. "CMD_CXN_KILLED_ICD_INVALID",
  178. "CMD_CXN_KILLED_ITT_INVALID",
  179. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  180. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  181. "CXN_INVALIDATE_NOTIFY",
  182. "CXN_INVALIDATE_INDEX_NOTIFY",
  183. "CMD_INVALIDATED_NOTIFY",
  184. "UNSOL_HDR_NOTIFY",
  185. "UNSOL_DATA_NOTIFY",
  186. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  187. "DRIVERMSG_NOTIFY",
  188. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  189. "SOL_CMD_KILLED_DIF_ERR",
  190. "CXN_KILLED_SYN_RCVD",
  191. "CXN_KILLED_IMM_DATA_RCVD"
  192. };
  193. static int beiscsi_slave_configure(struct scsi_device *sdev)
  194. {
  195. blk_queue_max_segment_size(sdev->request_queue, 65536);
  196. return 0;
  197. }
  198. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  199. {
  200. struct iscsi_cls_session *cls_session;
  201. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  202. struct beiscsi_io_task *aborted_io_task;
  203. struct iscsi_conn *conn;
  204. struct beiscsi_conn *beiscsi_conn;
  205. struct beiscsi_hba *phba;
  206. struct iscsi_session *session;
  207. struct invalidate_command_table *inv_tbl;
  208. struct be_dma_mem nonemb_cmd;
  209. unsigned int cid, tag, num_invalidate;
  210. cls_session = starget_to_session(scsi_target(sc->device));
  211. session = cls_session->dd_data;
  212. spin_lock_bh(&session->lock);
  213. if (!aborted_task || !aborted_task->sc) {
  214. /* we raced */
  215. spin_unlock_bh(&session->lock);
  216. return SUCCESS;
  217. }
  218. aborted_io_task = aborted_task->dd_data;
  219. if (!aborted_io_task->scsi_cmnd) {
  220. /* raced or invalid command */
  221. spin_unlock_bh(&session->lock);
  222. return SUCCESS;
  223. }
  224. spin_unlock_bh(&session->lock);
  225. conn = aborted_task->conn;
  226. beiscsi_conn = conn->dd_data;
  227. phba = beiscsi_conn->phba;
  228. /* invalidate iocb */
  229. cid = beiscsi_conn->beiscsi_conn_cid;
  230. inv_tbl = phba->inv_tbl;
  231. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  232. inv_tbl->cid = cid;
  233. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  234. num_invalidate = 1;
  235. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  236. sizeof(struct invalidate_commands_params_in),
  237. &nonemb_cmd.dma);
  238. if (nonemb_cmd.va == NULL) {
  239. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  240. "BM_%d : Failed to allocate memory for"
  241. "mgmt_invalidate_icds\n");
  242. return FAILED;
  243. }
  244. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  245. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  246. cid, &nonemb_cmd);
  247. if (!tag) {
  248. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  249. "BM_%d : mgmt_invalidate_icds could not be"
  250. "submitted\n");
  251. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  252. nonemb_cmd.va, nonemb_cmd.dma);
  253. return FAILED;
  254. }
  255. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  256. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  257. nonemb_cmd.va, nonemb_cmd.dma);
  258. return iscsi_eh_abort(sc);
  259. }
  260. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  261. {
  262. struct iscsi_task *abrt_task;
  263. struct beiscsi_io_task *abrt_io_task;
  264. struct iscsi_conn *conn;
  265. struct beiscsi_conn *beiscsi_conn;
  266. struct beiscsi_hba *phba;
  267. struct iscsi_session *session;
  268. struct iscsi_cls_session *cls_session;
  269. struct invalidate_command_table *inv_tbl;
  270. struct be_dma_mem nonemb_cmd;
  271. unsigned int cid, tag, i, num_invalidate;
  272. /* invalidate iocbs */
  273. cls_session = starget_to_session(scsi_target(sc->device));
  274. session = cls_session->dd_data;
  275. spin_lock_bh(&session->lock);
  276. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  277. spin_unlock_bh(&session->lock);
  278. return FAILED;
  279. }
  280. conn = session->leadconn;
  281. beiscsi_conn = conn->dd_data;
  282. phba = beiscsi_conn->phba;
  283. cid = beiscsi_conn->beiscsi_conn_cid;
  284. inv_tbl = phba->inv_tbl;
  285. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  286. num_invalidate = 0;
  287. for (i = 0; i < conn->session->cmds_max; i++) {
  288. abrt_task = conn->session->cmds[i];
  289. abrt_io_task = abrt_task->dd_data;
  290. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  291. continue;
  292. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  293. continue;
  294. inv_tbl->cid = cid;
  295. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  296. num_invalidate++;
  297. inv_tbl++;
  298. }
  299. spin_unlock_bh(&session->lock);
  300. inv_tbl = phba->inv_tbl;
  301. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  302. sizeof(struct invalidate_commands_params_in),
  303. &nonemb_cmd.dma);
  304. if (nonemb_cmd.va == NULL) {
  305. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  306. "BM_%d : Failed to allocate memory for"
  307. "mgmt_invalidate_icds\n");
  308. return FAILED;
  309. }
  310. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  311. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  312. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  313. cid, &nonemb_cmd);
  314. if (!tag) {
  315. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  316. "BM_%d : mgmt_invalidate_icds could not be"
  317. " submitted\n");
  318. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  319. nonemb_cmd.va, nonemb_cmd.dma);
  320. return FAILED;
  321. }
  322. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  323. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  324. nonemb_cmd.va, nonemb_cmd.dma);
  325. return iscsi_eh_device_reset(sc);
  326. }
  327. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  328. {
  329. struct beiscsi_hba *phba = data;
  330. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  331. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  332. char *str = buf;
  333. int rc;
  334. switch (type) {
  335. case ISCSI_BOOT_TGT_NAME:
  336. rc = sprintf(buf, "%.*s\n",
  337. (int)strlen(boot_sess->target_name),
  338. (char *)&boot_sess->target_name);
  339. break;
  340. case ISCSI_BOOT_TGT_IP_ADDR:
  341. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  342. rc = sprintf(buf, "%pI4\n",
  343. (char *)&boot_conn->dest_ipaddr.addr);
  344. else
  345. rc = sprintf(str, "%pI6\n",
  346. (char *)&boot_conn->dest_ipaddr.addr);
  347. break;
  348. case ISCSI_BOOT_TGT_PORT:
  349. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  350. break;
  351. case ISCSI_BOOT_TGT_CHAP_NAME:
  352. rc = sprintf(str, "%.*s\n",
  353. boot_conn->negotiated_login_options.auth_data.chap.
  354. target_chap_name_length,
  355. (char *)&boot_conn->negotiated_login_options.
  356. auth_data.chap.target_chap_name);
  357. break;
  358. case ISCSI_BOOT_TGT_CHAP_SECRET:
  359. rc = sprintf(str, "%.*s\n",
  360. boot_conn->negotiated_login_options.auth_data.chap.
  361. target_secret_length,
  362. (char *)&boot_conn->negotiated_login_options.
  363. auth_data.chap.target_secret);
  364. break;
  365. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  366. rc = sprintf(str, "%.*s\n",
  367. boot_conn->negotiated_login_options.auth_data.chap.
  368. intr_chap_name_length,
  369. (char *)&boot_conn->negotiated_login_options.
  370. auth_data.chap.intr_chap_name);
  371. break;
  372. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  373. rc = sprintf(str, "%.*s\n",
  374. boot_conn->negotiated_login_options.auth_data.chap.
  375. intr_secret_length,
  376. (char *)&boot_conn->negotiated_login_options.
  377. auth_data.chap.intr_secret);
  378. break;
  379. case ISCSI_BOOT_TGT_FLAGS:
  380. rc = sprintf(str, "2\n");
  381. break;
  382. case ISCSI_BOOT_TGT_NIC_ASSOC:
  383. rc = sprintf(str, "0\n");
  384. break;
  385. default:
  386. rc = -ENOSYS;
  387. break;
  388. }
  389. return rc;
  390. }
  391. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  392. {
  393. struct beiscsi_hba *phba = data;
  394. char *str = buf;
  395. int rc;
  396. switch (type) {
  397. case ISCSI_BOOT_INI_INITIATOR_NAME:
  398. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  399. break;
  400. default:
  401. rc = -ENOSYS;
  402. break;
  403. }
  404. return rc;
  405. }
  406. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  407. {
  408. struct beiscsi_hba *phba = data;
  409. char *str = buf;
  410. int rc;
  411. switch (type) {
  412. case ISCSI_BOOT_ETH_FLAGS:
  413. rc = sprintf(str, "2\n");
  414. break;
  415. case ISCSI_BOOT_ETH_INDEX:
  416. rc = sprintf(str, "0\n");
  417. break;
  418. case ISCSI_BOOT_ETH_MAC:
  419. rc = beiscsi_get_macaddr(str, phba);
  420. break;
  421. default:
  422. rc = -ENOSYS;
  423. break;
  424. }
  425. return rc;
  426. }
  427. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  428. {
  429. umode_t rc;
  430. switch (type) {
  431. case ISCSI_BOOT_TGT_NAME:
  432. case ISCSI_BOOT_TGT_IP_ADDR:
  433. case ISCSI_BOOT_TGT_PORT:
  434. case ISCSI_BOOT_TGT_CHAP_NAME:
  435. case ISCSI_BOOT_TGT_CHAP_SECRET:
  436. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_NIC_ASSOC:
  439. case ISCSI_BOOT_TGT_FLAGS:
  440. rc = S_IRUGO;
  441. break;
  442. default:
  443. rc = 0;
  444. break;
  445. }
  446. return rc;
  447. }
  448. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  449. {
  450. umode_t rc;
  451. switch (type) {
  452. case ISCSI_BOOT_INI_INITIATOR_NAME:
  453. rc = S_IRUGO;
  454. break;
  455. default:
  456. rc = 0;
  457. break;
  458. }
  459. return rc;
  460. }
  461. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  462. {
  463. umode_t rc;
  464. switch (type) {
  465. case ISCSI_BOOT_ETH_FLAGS:
  466. case ISCSI_BOOT_ETH_MAC:
  467. case ISCSI_BOOT_ETH_INDEX:
  468. rc = S_IRUGO;
  469. break;
  470. default:
  471. rc = 0;
  472. break;
  473. }
  474. return rc;
  475. }
  476. /*------------------- PCI Driver operations and data ----------------- */
  477. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  478. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  479. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  480. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  483. { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
  484. { 0 }
  485. };
  486. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  487. static struct scsi_host_template beiscsi_sht = {
  488. .module = THIS_MODULE,
  489. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  490. .proc_name = DRV_NAME,
  491. .queuecommand = iscsi_queuecommand,
  492. .change_queue_depth = iscsi_change_queue_depth,
  493. .slave_configure = beiscsi_slave_configure,
  494. .target_alloc = iscsi_target_alloc,
  495. .eh_abort_handler = beiscsi_eh_abort,
  496. .eh_device_reset_handler = beiscsi_eh_device_reset,
  497. .eh_target_reset_handler = iscsi_eh_session_reset,
  498. .shost_attrs = beiscsi_attrs,
  499. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  500. .can_queue = BE2_IO_DEPTH,
  501. .this_id = -1,
  502. .max_sectors = BEISCSI_MAX_SECTORS,
  503. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  504. .use_clustering = ENABLE_CLUSTERING,
  505. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  506. };
  507. static struct scsi_transport_template *beiscsi_scsi_transport;
  508. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  509. {
  510. struct beiscsi_hba *phba;
  511. struct Scsi_Host *shost;
  512. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  513. if (!shost) {
  514. dev_err(&pcidev->dev,
  515. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  516. return NULL;
  517. }
  518. shost->dma_boundary = pcidev->dma_mask;
  519. shost->max_id = BE2_MAX_SESSIONS;
  520. shost->max_channel = 0;
  521. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  522. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  523. shost->transportt = beiscsi_scsi_transport;
  524. phba = iscsi_host_priv(shost);
  525. memset(phba, 0, sizeof(*phba));
  526. phba->shost = shost;
  527. phba->pcidev = pci_dev_get(pcidev);
  528. pci_set_drvdata(pcidev, phba);
  529. phba->interface_handle = 0xFFFFFFFF;
  530. if (iscsi_host_add(shost, &phba->pcidev->dev))
  531. goto free_devices;
  532. return phba;
  533. free_devices:
  534. pci_dev_put(phba->pcidev);
  535. iscsi_host_free(phba->shost);
  536. return NULL;
  537. }
  538. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  539. {
  540. if (phba->csr_va) {
  541. iounmap(phba->csr_va);
  542. phba->csr_va = NULL;
  543. }
  544. if (phba->db_va) {
  545. iounmap(phba->db_va);
  546. phba->db_va = NULL;
  547. }
  548. if (phba->pci_va) {
  549. iounmap(phba->pci_va);
  550. phba->pci_va = NULL;
  551. }
  552. }
  553. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  554. struct pci_dev *pcidev)
  555. {
  556. u8 __iomem *addr;
  557. int pcicfg_reg;
  558. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  559. pci_resource_len(pcidev, 2));
  560. if (addr == NULL)
  561. return -ENOMEM;
  562. phba->ctrl.csr = addr;
  563. phba->csr_va = addr;
  564. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  565. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  566. if (addr == NULL)
  567. goto pci_map_err;
  568. phba->ctrl.db = addr;
  569. phba->db_va = addr;
  570. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  571. if (phba->generation == BE_GEN2)
  572. pcicfg_reg = 1;
  573. else
  574. pcicfg_reg = 0;
  575. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  576. pci_resource_len(pcidev, pcicfg_reg));
  577. if (addr == NULL)
  578. goto pci_map_err;
  579. phba->ctrl.pcicfg = addr;
  580. phba->pci_va = addr;
  581. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  582. return 0;
  583. pci_map_err:
  584. beiscsi_unmap_pci_function(phba);
  585. return -ENOMEM;
  586. }
  587. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  588. {
  589. int ret;
  590. ret = pci_enable_device(pcidev);
  591. if (ret) {
  592. dev_err(&pcidev->dev,
  593. "beiscsi_enable_pci - enable device failed\n");
  594. return ret;
  595. }
  596. pci_set_master(pcidev);
  597. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  598. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  599. if (ret) {
  600. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  601. pci_disable_device(pcidev);
  602. return ret;
  603. }
  604. }
  605. return 0;
  606. }
  607. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  608. {
  609. struct be_ctrl_info *ctrl = &phba->ctrl;
  610. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  611. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  612. int status = 0;
  613. ctrl->pdev = pdev;
  614. status = beiscsi_map_pci_bars(phba, pdev);
  615. if (status)
  616. return status;
  617. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  618. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  619. mbox_mem_alloc->size,
  620. &mbox_mem_alloc->dma);
  621. if (!mbox_mem_alloc->va) {
  622. beiscsi_unmap_pci_function(phba);
  623. return -ENOMEM;
  624. }
  625. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  626. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  627. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  628. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  629. spin_lock_init(&ctrl->mbox_lock);
  630. spin_lock_init(&phba->ctrl.mcc_lock);
  631. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  632. return status;
  633. }
  634. /**
  635. * beiscsi_get_params()- Set the config paramters
  636. * @phba: ptr device priv structure
  637. **/
  638. static void beiscsi_get_params(struct beiscsi_hba *phba)
  639. {
  640. uint32_t total_cid_count = 0;
  641. uint32_t total_icd_count = 0;
  642. uint8_t ulp_num = 0;
  643. total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
  644. BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
  645. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
  646. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  647. total_icd_count = phba->fw_config.
  648. iscsi_icd_count[ulp_num];
  649. break;
  650. }
  651. phba->params.ios_per_ctrl = (total_icd_count -
  652. (total_cid_count +
  653. BE2_TMFS + BE2_NOPOUT_REQ));
  654. phba->params.cxns_per_ctrl = total_cid_count;
  655. phba->params.asyncpdus_per_ctrl = total_cid_count;
  656. phba->params.icds_per_ctrl = total_icd_count;
  657. phba->params.num_sge_per_io = BE2_SGE;
  658. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  659. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  660. phba->params.eq_timer = 64;
  661. phba->params.num_eq_entries = 1024;
  662. phba->params.num_cq_entries = 1024;
  663. phba->params.wrbs_per_cxn = 256;
  664. }
  665. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  666. unsigned int id, unsigned int clr_interrupt,
  667. unsigned int num_processed,
  668. unsigned char rearm, unsigned char event)
  669. {
  670. u32 val = 0;
  671. val |= id & DB_EQ_RING_ID_MASK;
  672. if (rearm)
  673. val |= 1 << DB_EQ_REARM_SHIFT;
  674. if (clr_interrupt)
  675. val |= 1 << DB_EQ_CLR_SHIFT;
  676. if (event)
  677. val |= 1 << DB_EQ_EVNT_SHIFT;
  678. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  679. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  680. }
  681. /**
  682. * be_isr_mcc - The isr routine of the driver.
  683. * @irq: Not used
  684. * @dev_id: Pointer to host adapter structure
  685. */
  686. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  687. {
  688. struct beiscsi_hba *phba;
  689. struct be_eq_entry *eqe = NULL;
  690. struct be_queue_info *eq;
  691. struct be_queue_info *mcc;
  692. unsigned int num_eq_processed;
  693. struct be_eq_obj *pbe_eq;
  694. unsigned long flags;
  695. pbe_eq = dev_id;
  696. eq = &pbe_eq->q;
  697. phba = pbe_eq->phba;
  698. mcc = &phba->ctrl.mcc_obj.cq;
  699. eqe = queue_tail_node(eq);
  700. num_eq_processed = 0;
  701. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  702. & EQE_VALID_MASK) {
  703. if (((eqe->dw[offsetof(struct amap_eq_entry,
  704. resource_id) / 32] &
  705. EQE_RESID_MASK) >> 16) == mcc->id) {
  706. spin_lock_irqsave(&phba->isr_lock, flags);
  707. pbe_eq->todo_mcc_cq = true;
  708. spin_unlock_irqrestore(&phba->isr_lock, flags);
  709. }
  710. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  711. queue_tail_inc(eq);
  712. eqe = queue_tail_node(eq);
  713. num_eq_processed++;
  714. }
  715. if (pbe_eq->todo_mcc_cq)
  716. queue_work(phba->wq, &pbe_eq->work_cqs);
  717. if (num_eq_processed)
  718. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  719. return IRQ_HANDLED;
  720. }
  721. /**
  722. * be_isr_msix - The isr routine of the driver.
  723. * @irq: Not used
  724. * @dev_id: Pointer to host adapter structure
  725. */
  726. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  727. {
  728. struct beiscsi_hba *phba;
  729. struct be_eq_entry *eqe = NULL;
  730. struct be_queue_info *eq;
  731. struct be_queue_info *cq;
  732. unsigned int num_eq_processed;
  733. struct be_eq_obj *pbe_eq;
  734. unsigned long flags;
  735. pbe_eq = dev_id;
  736. eq = &pbe_eq->q;
  737. cq = pbe_eq->cq;
  738. eqe = queue_tail_node(eq);
  739. phba = pbe_eq->phba;
  740. num_eq_processed = 0;
  741. if (blk_iopoll_enabled) {
  742. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  743. & EQE_VALID_MASK) {
  744. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  745. blk_iopoll_sched(&pbe_eq->iopoll);
  746. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  747. queue_tail_inc(eq);
  748. eqe = queue_tail_node(eq);
  749. num_eq_processed++;
  750. }
  751. } else {
  752. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  753. & EQE_VALID_MASK) {
  754. spin_lock_irqsave(&phba->isr_lock, flags);
  755. pbe_eq->todo_cq = true;
  756. spin_unlock_irqrestore(&phba->isr_lock, flags);
  757. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  758. queue_tail_inc(eq);
  759. eqe = queue_tail_node(eq);
  760. num_eq_processed++;
  761. }
  762. if (pbe_eq->todo_cq)
  763. queue_work(phba->wq, &pbe_eq->work_cqs);
  764. }
  765. if (num_eq_processed)
  766. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  767. return IRQ_HANDLED;
  768. }
  769. /**
  770. * be_isr - The isr routine of the driver.
  771. * @irq: Not used
  772. * @dev_id: Pointer to host adapter structure
  773. */
  774. static irqreturn_t be_isr(int irq, void *dev_id)
  775. {
  776. struct beiscsi_hba *phba;
  777. struct hwi_controller *phwi_ctrlr;
  778. struct hwi_context_memory *phwi_context;
  779. struct be_eq_entry *eqe = NULL;
  780. struct be_queue_info *eq;
  781. struct be_queue_info *cq;
  782. struct be_queue_info *mcc;
  783. unsigned long flags, index;
  784. unsigned int num_mcceq_processed, num_ioeq_processed;
  785. struct be_ctrl_info *ctrl;
  786. struct be_eq_obj *pbe_eq;
  787. int isr;
  788. phba = dev_id;
  789. ctrl = &phba->ctrl;
  790. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  791. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  792. if (!isr)
  793. return IRQ_NONE;
  794. phwi_ctrlr = phba->phwi_ctrlr;
  795. phwi_context = phwi_ctrlr->phwi_ctxt;
  796. pbe_eq = &phwi_context->be_eq[0];
  797. eq = &phwi_context->be_eq[0].q;
  798. mcc = &phba->ctrl.mcc_obj.cq;
  799. index = 0;
  800. eqe = queue_tail_node(eq);
  801. num_ioeq_processed = 0;
  802. num_mcceq_processed = 0;
  803. if (blk_iopoll_enabled) {
  804. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  805. & EQE_VALID_MASK) {
  806. if (((eqe->dw[offsetof(struct amap_eq_entry,
  807. resource_id) / 32] &
  808. EQE_RESID_MASK) >> 16) == mcc->id) {
  809. spin_lock_irqsave(&phba->isr_lock, flags);
  810. pbe_eq->todo_mcc_cq = true;
  811. spin_unlock_irqrestore(&phba->isr_lock, flags);
  812. num_mcceq_processed++;
  813. } else {
  814. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  815. blk_iopoll_sched(&pbe_eq->iopoll);
  816. num_ioeq_processed++;
  817. }
  818. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  819. queue_tail_inc(eq);
  820. eqe = queue_tail_node(eq);
  821. }
  822. if (num_ioeq_processed || num_mcceq_processed) {
  823. if (pbe_eq->todo_mcc_cq)
  824. queue_work(phba->wq, &pbe_eq->work_cqs);
  825. if ((num_mcceq_processed) && (!num_ioeq_processed))
  826. hwi_ring_eq_db(phba, eq->id, 0,
  827. (num_ioeq_processed +
  828. num_mcceq_processed) , 1, 1);
  829. else
  830. hwi_ring_eq_db(phba, eq->id, 0,
  831. (num_ioeq_processed +
  832. num_mcceq_processed), 0, 1);
  833. return IRQ_HANDLED;
  834. } else
  835. return IRQ_NONE;
  836. } else {
  837. cq = &phwi_context->be_cq[0];
  838. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  839. & EQE_VALID_MASK) {
  840. if (((eqe->dw[offsetof(struct amap_eq_entry,
  841. resource_id) / 32] &
  842. EQE_RESID_MASK) >> 16) != cq->id) {
  843. spin_lock_irqsave(&phba->isr_lock, flags);
  844. pbe_eq->todo_mcc_cq = true;
  845. spin_unlock_irqrestore(&phba->isr_lock, flags);
  846. } else {
  847. spin_lock_irqsave(&phba->isr_lock, flags);
  848. pbe_eq->todo_cq = true;
  849. spin_unlock_irqrestore(&phba->isr_lock, flags);
  850. }
  851. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  852. queue_tail_inc(eq);
  853. eqe = queue_tail_node(eq);
  854. num_ioeq_processed++;
  855. }
  856. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  857. queue_work(phba->wq, &pbe_eq->work_cqs);
  858. if (num_ioeq_processed) {
  859. hwi_ring_eq_db(phba, eq->id, 0,
  860. num_ioeq_processed, 1, 1);
  861. return IRQ_HANDLED;
  862. } else
  863. return IRQ_NONE;
  864. }
  865. }
  866. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  867. {
  868. struct pci_dev *pcidev = phba->pcidev;
  869. struct hwi_controller *phwi_ctrlr;
  870. struct hwi_context_memory *phwi_context;
  871. int ret, msix_vec, i, j;
  872. phwi_ctrlr = phba->phwi_ctrlr;
  873. phwi_context = phwi_ctrlr->phwi_ctxt;
  874. if (phba->msix_enabled) {
  875. for (i = 0; i < phba->num_cpus; i++) {
  876. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  877. GFP_KERNEL);
  878. if (!phba->msi_name[i]) {
  879. ret = -ENOMEM;
  880. goto free_msix_irqs;
  881. }
  882. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  883. phba->shost->host_no, i);
  884. msix_vec = phba->msix_entries[i].vector;
  885. ret = request_irq(msix_vec, be_isr_msix, 0,
  886. phba->msi_name[i],
  887. &phwi_context->be_eq[i]);
  888. if (ret) {
  889. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  890. "BM_%d : beiscsi_init_irqs-Failed to"
  891. "register msix for i = %d\n",
  892. i);
  893. kfree(phba->msi_name[i]);
  894. goto free_msix_irqs;
  895. }
  896. }
  897. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  898. if (!phba->msi_name[i]) {
  899. ret = -ENOMEM;
  900. goto free_msix_irqs;
  901. }
  902. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  903. phba->shost->host_no);
  904. msix_vec = phba->msix_entries[i].vector;
  905. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  906. &phwi_context->be_eq[i]);
  907. if (ret) {
  908. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  909. "BM_%d : beiscsi_init_irqs-"
  910. "Failed to register beiscsi_msix_mcc\n");
  911. kfree(phba->msi_name[i]);
  912. goto free_msix_irqs;
  913. }
  914. } else {
  915. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  916. "beiscsi", phba);
  917. if (ret) {
  918. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  919. "BM_%d : beiscsi_init_irqs-"
  920. "Failed to register irq\\n");
  921. return ret;
  922. }
  923. }
  924. return 0;
  925. free_msix_irqs:
  926. for (j = i - 1; j >= 0; j--) {
  927. kfree(phba->msi_name[j]);
  928. msix_vec = phba->msix_entries[j].vector;
  929. free_irq(msix_vec, &phwi_context->be_eq[j]);
  930. }
  931. return ret;
  932. }
  933. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  934. unsigned int id, unsigned int num_processed,
  935. unsigned char rearm, unsigned char event)
  936. {
  937. u32 val = 0;
  938. val |= id & DB_CQ_RING_ID_MASK;
  939. if (rearm)
  940. val |= 1 << DB_CQ_REARM_SHIFT;
  941. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  942. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  943. }
  944. static unsigned int
  945. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  946. struct beiscsi_hba *phba,
  947. struct pdu_base *ppdu,
  948. unsigned long pdu_len,
  949. void *pbuffer, unsigned long buf_len)
  950. {
  951. struct iscsi_conn *conn = beiscsi_conn->conn;
  952. struct iscsi_session *session = conn->session;
  953. struct iscsi_task *task;
  954. struct beiscsi_io_task *io_task;
  955. struct iscsi_hdr *login_hdr;
  956. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  957. PDUBASE_OPCODE_MASK) {
  958. case ISCSI_OP_NOOP_IN:
  959. pbuffer = NULL;
  960. buf_len = 0;
  961. break;
  962. case ISCSI_OP_ASYNC_EVENT:
  963. break;
  964. case ISCSI_OP_REJECT:
  965. WARN_ON(!pbuffer);
  966. WARN_ON(!(buf_len == 48));
  967. beiscsi_log(phba, KERN_ERR,
  968. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  969. "BM_%d : In ISCSI_OP_REJECT\n");
  970. break;
  971. case ISCSI_OP_LOGIN_RSP:
  972. case ISCSI_OP_TEXT_RSP:
  973. task = conn->login_task;
  974. io_task = task->dd_data;
  975. login_hdr = (struct iscsi_hdr *)ppdu;
  976. login_hdr->itt = io_task->libiscsi_itt;
  977. break;
  978. default:
  979. beiscsi_log(phba, KERN_WARNING,
  980. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  981. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  982. (ppdu->
  983. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  984. & PDUBASE_OPCODE_MASK));
  985. return 1;
  986. }
  987. spin_lock_bh(&session->lock);
  988. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  989. spin_unlock_bh(&session->lock);
  990. return 0;
  991. }
  992. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  993. {
  994. struct sgl_handle *psgl_handle;
  995. if (phba->io_sgl_hndl_avbl) {
  996. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  997. "BM_%d : In alloc_io_sgl_handle,"
  998. " io_sgl_alloc_index=%d\n",
  999. phba->io_sgl_alloc_index);
  1000. psgl_handle = phba->io_sgl_hndl_base[phba->
  1001. io_sgl_alloc_index];
  1002. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  1003. phba->io_sgl_hndl_avbl--;
  1004. if (phba->io_sgl_alloc_index == (phba->params.
  1005. ios_per_ctrl - 1))
  1006. phba->io_sgl_alloc_index = 0;
  1007. else
  1008. phba->io_sgl_alloc_index++;
  1009. } else
  1010. psgl_handle = NULL;
  1011. return psgl_handle;
  1012. }
  1013. static void
  1014. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1015. {
  1016. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1017. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1018. phba->io_sgl_free_index);
  1019. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1020. /*
  1021. * this can happen if clean_task is called on a task that
  1022. * failed in xmit_task or alloc_pdu.
  1023. */
  1024. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1025. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1026. "value there=%p\n", phba->io_sgl_free_index,
  1027. phba->io_sgl_hndl_base
  1028. [phba->io_sgl_free_index]);
  1029. return;
  1030. }
  1031. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1032. phba->io_sgl_hndl_avbl++;
  1033. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1034. phba->io_sgl_free_index = 0;
  1035. else
  1036. phba->io_sgl_free_index++;
  1037. }
  1038. /**
  1039. * alloc_wrb_handle - To allocate a wrb handle
  1040. * @phba: The hba pointer
  1041. * @cid: The cid to use for allocation
  1042. *
  1043. * This happens under session_lock until submission to chip
  1044. */
  1045. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1046. {
  1047. struct hwi_wrb_context *pwrb_context;
  1048. struct hwi_controller *phwi_ctrlr;
  1049. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1050. uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
  1051. phwi_ctrlr = phba->phwi_ctrlr;
  1052. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1053. if (pwrb_context->wrb_handles_available >= 2) {
  1054. pwrb_handle = pwrb_context->pwrb_handle_base[
  1055. pwrb_context->alloc_index];
  1056. pwrb_context->wrb_handles_available--;
  1057. if (pwrb_context->alloc_index ==
  1058. (phba->params.wrbs_per_cxn - 1))
  1059. pwrb_context->alloc_index = 0;
  1060. else
  1061. pwrb_context->alloc_index++;
  1062. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1063. pwrb_context->alloc_index];
  1064. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1065. } else
  1066. pwrb_handle = NULL;
  1067. return pwrb_handle;
  1068. }
  1069. /**
  1070. * free_wrb_handle - To free the wrb handle back to pool
  1071. * @phba: The hba pointer
  1072. * @pwrb_context: The context to free from
  1073. * @pwrb_handle: The wrb_handle to free
  1074. *
  1075. * This happens under session_lock until submission to chip
  1076. */
  1077. static void
  1078. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1079. struct wrb_handle *pwrb_handle)
  1080. {
  1081. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1082. pwrb_context->wrb_handles_available++;
  1083. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1084. pwrb_context->free_index = 0;
  1085. else
  1086. pwrb_context->free_index++;
  1087. beiscsi_log(phba, KERN_INFO,
  1088. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1089. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1090. "wrb_handles_available=%d\n",
  1091. pwrb_handle, pwrb_context->free_index,
  1092. pwrb_context->wrb_handles_available);
  1093. }
  1094. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1095. {
  1096. struct sgl_handle *psgl_handle;
  1097. if (phba->eh_sgl_hndl_avbl) {
  1098. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1099. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1100. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1101. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1102. phba->eh_sgl_alloc_index,
  1103. phba->eh_sgl_alloc_index);
  1104. phba->eh_sgl_hndl_avbl--;
  1105. if (phba->eh_sgl_alloc_index ==
  1106. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1107. 1))
  1108. phba->eh_sgl_alloc_index = 0;
  1109. else
  1110. phba->eh_sgl_alloc_index++;
  1111. } else
  1112. psgl_handle = NULL;
  1113. return psgl_handle;
  1114. }
  1115. void
  1116. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1117. {
  1118. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1119. "BM_%d : In free_mgmt_sgl_handle,"
  1120. "eh_sgl_free_index=%d\n",
  1121. phba->eh_sgl_free_index);
  1122. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1123. /*
  1124. * this can happen if clean_task is called on a task that
  1125. * failed in xmit_task or alloc_pdu.
  1126. */
  1127. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1128. "BM_%d : Double Free in eh SGL ,"
  1129. "eh_sgl_free_index=%d\n",
  1130. phba->eh_sgl_free_index);
  1131. return;
  1132. }
  1133. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1134. phba->eh_sgl_hndl_avbl++;
  1135. if (phba->eh_sgl_free_index ==
  1136. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1137. phba->eh_sgl_free_index = 0;
  1138. else
  1139. phba->eh_sgl_free_index++;
  1140. }
  1141. static void
  1142. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1143. struct iscsi_task *task,
  1144. struct common_sol_cqe *csol_cqe)
  1145. {
  1146. struct beiscsi_io_task *io_task = task->dd_data;
  1147. struct be_status_bhs *sts_bhs =
  1148. (struct be_status_bhs *)io_task->cmd_bhs;
  1149. struct iscsi_conn *conn = beiscsi_conn->conn;
  1150. unsigned char *sense;
  1151. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1152. u8 rsp, status, flags;
  1153. exp_cmdsn = csol_cqe->exp_cmdsn;
  1154. max_cmdsn = (csol_cqe->exp_cmdsn +
  1155. csol_cqe->cmd_wnd - 1);
  1156. rsp = csol_cqe->i_resp;
  1157. status = csol_cqe->i_sts;
  1158. flags = csol_cqe->i_flags;
  1159. resid = csol_cqe->res_cnt;
  1160. if (!task->sc) {
  1161. if (io_task->scsi_cmnd)
  1162. scsi_dma_unmap(io_task->scsi_cmnd);
  1163. return;
  1164. }
  1165. task->sc->result = (DID_OK << 16) | status;
  1166. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1167. task->sc->result = DID_ERROR << 16;
  1168. goto unmap;
  1169. }
  1170. /* bidi not initially supported */
  1171. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1172. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1173. task->sc->result = DID_ERROR << 16;
  1174. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1175. scsi_set_resid(task->sc, resid);
  1176. if (!status && (scsi_bufflen(task->sc) - resid <
  1177. task->sc->underflow))
  1178. task->sc->result = DID_ERROR << 16;
  1179. }
  1180. }
  1181. if (status == SAM_STAT_CHECK_CONDITION) {
  1182. u16 sense_len;
  1183. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1184. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1185. sense_len = be16_to_cpu(*slen);
  1186. memcpy(task->sc->sense_buffer, sense,
  1187. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1188. }
  1189. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
  1190. conn->rxdata_octets += resid;
  1191. unmap:
  1192. scsi_dma_unmap(io_task->scsi_cmnd);
  1193. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1194. }
  1195. static void
  1196. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1197. struct iscsi_task *task,
  1198. struct common_sol_cqe *csol_cqe)
  1199. {
  1200. struct iscsi_logout_rsp *hdr;
  1201. struct beiscsi_io_task *io_task = task->dd_data;
  1202. struct iscsi_conn *conn = beiscsi_conn->conn;
  1203. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1204. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1205. hdr->t2wait = 5;
  1206. hdr->t2retain = 0;
  1207. hdr->flags = csol_cqe->i_flags;
  1208. hdr->response = csol_cqe->i_resp;
  1209. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1210. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1211. csol_cqe->cmd_wnd - 1);
  1212. hdr->dlength[0] = 0;
  1213. hdr->dlength[1] = 0;
  1214. hdr->dlength[2] = 0;
  1215. hdr->hlength = 0;
  1216. hdr->itt = io_task->libiscsi_itt;
  1217. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1218. }
  1219. static void
  1220. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1221. struct iscsi_task *task,
  1222. struct common_sol_cqe *csol_cqe)
  1223. {
  1224. struct iscsi_tm_rsp *hdr;
  1225. struct iscsi_conn *conn = beiscsi_conn->conn;
  1226. struct beiscsi_io_task *io_task = task->dd_data;
  1227. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1228. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1229. hdr->flags = csol_cqe->i_flags;
  1230. hdr->response = csol_cqe->i_resp;
  1231. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1232. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1233. csol_cqe->cmd_wnd - 1);
  1234. hdr->itt = io_task->libiscsi_itt;
  1235. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1236. }
  1237. static void
  1238. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1239. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1240. {
  1241. struct hwi_wrb_context *pwrb_context;
  1242. struct wrb_handle *pwrb_handle = NULL;
  1243. struct hwi_controller *phwi_ctrlr;
  1244. struct iscsi_task *task;
  1245. struct beiscsi_io_task *io_task;
  1246. uint16_t wrb_index, cid, cri_index;
  1247. phwi_ctrlr = phba->phwi_ctrlr;
  1248. if (is_chip_be2_be3r(phba)) {
  1249. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1250. wrb_idx, psol);
  1251. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1252. cid, psol);
  1253. } else {
  1254. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1255. wrb_idx, psol);
  1256. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1257. cid, psol);
  1258. }
  1259. cri_index = BE_GET_CRI_FROM_CID(cid);
  1260. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1261. pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
  1262. task = pwrb_handle->pio_handle;
  1263. io_task = task->dd_data;
  1264. memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb));
  1265. iscsi_put_task(task);
  1266. }
  1267. static void
  1268. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1269. struct iscsi_task *task,
  1270. struct common_sol_cqe *csol_cqe)
  1271. {
  1272. struct iscsi_nopin *hdr;
  1273. struct iscsi_conn *conn = beiscsi_conn->conn;
  1274. struct beiscsi_io_task *io_task = task->dd_data;
  1275. hdr = (struct iscsi_nopin *)task->hdr;
  1276. hdr->flags = csol_cqe->i_flags;
  1277. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1278. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1279. csol_cqe->cmd_wnd - 1);
  1280. hdr->opcode = ISCSI_OP_NOOP_IN;
  1281. hdr->itt = io_task->libiscsi_itt;
  1282. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1283. }
  1284. static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
  1285. struct sol_cqe *psol,
  1286. struct common_sol_cqe *csol_cqe)
  1287. {
  1288. if (is_chip_be2_be3r(phba)) {
  1289. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
  1290. i_exp_cmd_sn, psol);
  1291. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
  1292. i_res_cnt, psol);
  1293. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1294. i_cmd_wnd, psol);
  1295. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
  1296. wrb_index, psol);
  1297. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
  1298. cid, psol);
  1299. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1300. hw_sts, psol);
  1301. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
  1302. i_resp, psol);
  1303. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1304. i_sts, psol);
  1305. csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
  1306. i_flags, psol);
  1307. } else {
  1308. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1309. i_exp_cmd_sn, psol);
  1310. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1311. i_res_cnt, psol);
  1312. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1313. wrb_index, psol);
  1314. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1315. cid, psol);
  1316. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1317. hw_sts, psol);
  1318. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1319. i_cmd_wnd, psol);
  1320. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1321. cmd_cmpl, psol))
  1322. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1323. i_sts, psol);
  1324. else
  1325. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1326. i_sts, psol);
  1327. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1328. u, psol))
  1329. csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
  1330. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1331. o, psol))
  1332. csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
  1333. }
  1334. }
  1335. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1336. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1337. {
  1338. struct hwi_wrb_context *pwrb_context;
  1339. struct wrb_handle *pwrb_handle;
  1340. struct iscsi_wrb *pwrb = NULL;
  1341. struct hwi_controller *phwi_ctrlr;
  1342. struct iscsi_task *task;
  1343. unsigned int type;
  1344. struct iscsi_conn *conn = beiscsi_conn->conn;
  1345. struct iscsi_session *session = conn->session;
  1346. struct common_sol_cqe csol_cqe = {0};
  1347. uint16_t cri_index = 0;
  1348. phwi_ctrlr = phba->phwi_ctrlr;
  1349. /* Copy the elements to a common structure */
  1350. adapter_get_sol_cqe(phba, psol, &csol_cqe);
  1351. cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
  1352. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1353. pwrb_handle = pwrb_context->pwrb_handle_basestd[
  1354. csol_cqe.wrb_index];
  1355. task = pwrb_handle->pio_handle;
  1356. pwrb = pwrb_handle->pwrb;
  1357. type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
  1358. spin_lock_bh(&session->lock);
  1359. switch (type) {
  1360. case HWH_TYPE_IO:
  1361. case HWH_TYPE_IO_RD:
  1362. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1363. ISCSI_OP_NOOP_OUT)
  1364. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1365. else
  1366. be_complete_io(beiscsi_conn, task, &csol_cqe);
  1367. break;
  1368. case HWH_TYPE_LOGOUT:
  1369. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1370. be_complete_logout(beiscsi_conn, task, &csol_cqe);
  1371. else
  1372. be_complete_tmf(beiscsi_conn, task, &csol_cqe);
  1373. break;
  1374. case HWH_TYPE_LOGIN:
  1375. beiscsi_log(phba, KERN_ERR,
  1376. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1377. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1378. " hwi_complete_cmd- Solicited path\n");
  1379. break;
  1380. case HWH_TYPE_NOP:
  1381. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1382. break;
  1383. default:
  1384. beiscsi_log(phba, KERN_WARNING,
  1385. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1386. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1387. "wrb_index 0x%x CID 0x%x\n", type,
  1388. csol_cqe.wrb_index,
  1389. csol_cqe.cid);
  1390. break;
  1391. }
  1392. spin_unlock_bh(&session->lock);
  1393. }
  1394. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1395. *pasync_ctx, unsigned int is_header,
  1396. unsigned int host_write_ptr)
  1397. {
  1398. if (is_header)
  1399. return &pasync_ctx->async_entry[host_write_ptr].
  1400. header_busy_list;
  1401. else
  1402. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1403. }
  1404. static struct async_pdu_handle *
  1405. hwi_get_async_handle(struct beiscsi_hba *phba,
  1406. struct beiscsi_conn *beiscsi_conn,
  1407. struct hwi_async_pdu_context *pasync_ctx,
  1408. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1409. {
  1410. struct be_bus_address phys_addr;
  1411. struct list_head *pbusy_list;
  1412. struct async_pdu_handle *pasync_handle = NULL;
  1413. unsigned char is_header = 0;
  1414. unsigned int index, dpl;
  1415. if (is_chip_be2_be3r(phba)) {
  1416. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1417. dpl, pdpdu_cqe);
  1418. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1419. index, pdpdu_cqe);
  1420. } else {
  1421. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1422. dpl, pdpdu_cqe);
  1423. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1424. index, pdpdu_cqe);
  1425. }
  1426. phys_addr.u.a32.address_lo =
  1427. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1428. db_addr_lo) / 32] - dpl);
  1429. phys_addr.u.a32.address_hi =
  1430. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1431. db_addr_hi) / 32];
  1432. phys_addr.u.a64.address =
  1433. *((unsigned long long *)(&phys_addr.u.a64.address));
  1434. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1435. & PDUCQE_CODE_MASK) {
  1436. case UNSOL_HDR_NOTIFY:
  1437. is_header = 1;
  1438. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1439. is_header, index);
  1440. break;
  1441. case UNSOL_DATA_NOTIFY:
  1442. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1443. is_header, index);
  1444. break;
  1445. default:
  1446. pbusy_list = NULL;
  1447. beiscsi_log(phba, KERN_WARNING,
  1448. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1449. "BM_%d : Unexpected code=%d\n",
  1450. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1451. code) / 32] & PDUCQE_CODE_MASK);
  1452. return NULL;
  1453. }
  1454. WARN_ON(list_empty(pbusy_list));
  1455. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1456. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1457. break;
  1458. }
  1459. WARN_ON(!pasync_handle);
  1460. pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID(
  1461. beiscsi_conn->beiscsi_conn_cid);
  1462. pasync_handle->is_header = is_header;
  1463. pasync_handle->buffer_len = dpl;
  1464. *pcq_index = index;
  1465. return pasync_handle;
  1466. }
  1467. static unsigned int
  1468. hwi_update_async_writables(struct beiscsi_hba *phba,
  1469. struct hwi_async_pdu_context *pasync_ctx,
  1470. unsigned int is_header, unsigned int cq_index)
  1471. {
  1472. struct list_head *pbusy_list;
  1473. struct async_pdu_handle *pasync_handle;
  1474. unsigned int num_entries, writables = 0;
  1475. unsigned int *pep_read_ptr, *pwritables;
  1476. num_entries = pasync_ctx->num_entries;
  1477. if (is_header) {
  1478. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1479. pwritables = &pasync_ctx->async_header.writables;
  1480. } else {
  1481. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1482. pwritables = &pasync_ctx->async_data.writables;
  1483. }
  1484. while ((*pep_read_ptr) != cq_index) {
  1485. (*pep_read_ptr)++;
  1486. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1487. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1488. *pep_read_ptr);
  1489. if (writables == 0)
  1490. WARN_ON(list_empty(pbusy_list));
  1491. if (!list_empty(pbusy_list)) {
  1492. pasync_handle = list_entry(pbusy_list->next,
  1493. struct async_pdu_handle,
  1494. link);
  1495. WARN_ON(!pasync_handle);
  1496. pasync_handle->consumed = 1;
  1497. }
  1498. writables++;
  1499. }
  1500. if (!writables) {
  1501. beiscsi_log(phba, KERN_ERR,
  1502. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1503. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1504. cq_index);
  1505. WARN_ON(1);
  1506. }
  1507. *pwritables = *pwritables + writables;
  1508. return 0;
  1509. }
  1510. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1511. struct hwi_async_pdu_context *pasync_ctx,
  1512. unsigned int cri)
  1513. {
  1514. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1515. struct list_head *plist;
  1516. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1517. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1518. list_del(&pasync_handle->link);
  1519. if (pasync_handle->is_header) {
  1520. list_add_tail(&pasync_handle->link,
  1521. &pasync_ctx->async_header.free_list);
  1522. pasync_ctx->async_header.free_entries++;
  1523. } else {
  1524. list_add_tail(&pasync_handle->link,
  1525. &pasync_ctx->async_data.free_list);
  1526. pasync_ctx->async_data.free_entries++;
  1527. }
  1528. }
  1529. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1530. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1531. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1532. }
  1533. static struct phys_addr *
  1534. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1535. unsigned int is_header, unsigned int host_write_ptr)
  1536. {
  1537. struct phys_addr *pasync_sge = NULL;
  1538. if (is_header)
  1539. pasync_sge = pasync_ctx->async_header.ring_base;
  1540. else
  1541. pasync_sge = pasync_ctx->async_data.ring_base;
  1542. return pasync_sge + host_write_ptr;
  1543. }
  1544. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1545. unsigned int is_header, uint8_t ulp_num)
  1546. {
  1547. struct hwi_controller *phwi_ctrlr;
  1548. struct hwi_async_pdu_context *pasync_ctx;
  1549. struct async_pdu_handle *pasync_handle;
  1550. struct list_head *pfree_link, *pbusy_list;
  1551. struct phys_addr *pasync_sge;
  1552. unsigned int ring_id, num_entries;
  1553. unsigned int host_write_num, doorbell_offset;
  1554. unsigned int writables;
  1555. unsigned int i = 0;
  1556. u32 doorbell = 0;
  1557. phwi_ctrlr = phba->phwi_ctrlr;
  1558. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
  1559. num_entries = pasync_ctx->num_entries;
  1560. if (is_header) {
  1561. writables = min(pasync_ctx->async_header.writables,
  1562. pasync_ctx->async_header.free_entries);
  1563. pfree_link = pasync_ctx->async_header.free_list.next;
  1564. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1565. ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id;
  1566. doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num].
  1567. doorbell_offset;
  1568. } else {
  1569. writables = min(pasync_ctx->async_data.writables,
  1570. pasync_ctx->async_data.free_entries);
  1571. pfree_link = pasync_ctx->async_data.free_list.next;
  1572. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1573. ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id;
  1574. doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num].
  1575. doorbell_offset;
  1576. }
  1577. writables = (writables / 8) * 8;
  1578. if (writables) {
  1579. for (i = 0; i < writables; i++) {
  1580. pbusy_list =
  1581. hwi_get_async_busy_list(pasync_ctx, is_header,
  1582. host_write_num);
  1583. pasync_handle =
  1584. list_entry(pfree_link, struct async_pdu_handle,
  1585. link);
  1586. WARN_ON(!pasync_handle);
  1587. pasync_handle->consumed = 0;
  1588. pfree_link = pfree_link->next;
  1589. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1590. is_header, host_write_num);
  1591. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1592. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1593. list_move(&pasync_handle->link, pbusy_list);
  1594. host_write_num++;
  1595. host_write_num = host_write_num % num_entries;
  1596. }
  1597. if (is_header) {
  1598. pasync_ctx->async_header.host_write_ptr =
  1599. host_write_num;
  1600. pasync_ctx->async_header.free_entries -= writables;
  1601. pasync_ctx->async_header.writables -= writables;
  1602. pasync_ctx->async_header.busy_entries += writables;
  1603. } else {
  1604. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1605. pasync_ctx->async_data.free_entries -= writables;
  1606. pasync_ctx->async_data.writables -= writables;
  1607. pasync_ctx->async_data.busy_entries += writables;
  1608. }
  1609. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1610. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1611. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1612. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1613. << DB_DEF_PDU_CQPROC_SHIFT;
  1614. iowrite32(doorbell, phba->db_va + doorbell_offset);
  1615. }
  1616. }
  1617. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1618. struct beiscsi_conn *beiscsi_conn,
  1619. struct i_t_dpdu_cqe *pdpdu_cqe)
  1620. {
  1621. struct hwi_controller *phwi_ctrlr;
  1622. struct hwi_async_pdu_context *pasync_ctx;
  1623. struct async_pdu_handle *pasync_handle = NULL;
  1624. unsigned int cq_index = -1;
  1625. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  1626. beiscsi_conn->beiscsi_conn_cid);
  1627. phwi_ctrlr = phba->phwi_ctrlr;
  1628. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
  1629. BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
  1630. cri_index));
  1631. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1632. pdpdu_cqe, &cq_index);
  1633. BUG_ON(pasync_handle->is_header != 0);
  1634. if (pasync_handle->consumed == 0)
  1635. hwi_update_async_writables(phba, pasync_ctx,
  1636. pasync_handle->is_header, cq_index);
  1637. hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri);
  1638. hwi_post_async_buffers(phba, pasync_handle->is_header,
  1639. BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
  1640. cri_index));
  1641. }
  1642. static unsigned int
  1643. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1644. struct beiscsi_hba *phba,
  1645. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1646. {
  1647. struct list_head *plist;
  1648. struct async_pdu_handle *pasync_handle;
  1649. void *phdr = NULL;
  1650. unsigned int hdr_len = 0, buf_len = 0;
  1651. unsigned int status, index = 0, offset = 0;
  1652. void *pfirst_buffer = NULL;
  1653. unsigned int num_buf = 0;
  1654. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1655. list_for_each_entry(pasync_handle, plist, link) {
  1656. if (index == 0) {
  1657. phdr = pasync_handle->pbuffer;
  1658. hdr_len = pasync_handle->buffer_len;
  1659. } else {
  1660. buf_len = pasync_handle->buffer_len;
  1661. if (!num_buf) {
  1662. pfirst_buffer = pasync_handle->pbuffer;
  1663. num_buf++;
  1664. }
  1665. memcpy(pfirst_buffer + offset,
  1666. pasync_handle->pbuffer, buf_len);
  1667. offset += buf_len;
  1668. }
  1669. index++;
  1670. }
  1671. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1672. phdr, hdr_len, pfirst_buffer,
  1673. offset);
  1674. hwi_free_async_msg(phba, pasync_ctx, cri);
  1675. return 0;
  1676. }
  1677. static unsigned int
  1678. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1679. struct beiscsi_hba *phba,
  1680. struct async_pdu_handle *pasync_handle)
  1681. {
  1682. struct hwi_async_pdu_context *pasync_ctx;
  1683. struct hwi_controller *phwi_ctrlr;
  1684. unsigned int bytes_needed = 0, status = 0;
  1685. unsigned short cri = pasync_handle->cri;
  1686. struct pdu_base *ppdu;
  1687. phwi_ctrlr = phba->phwi_ctrlr;
  1688. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
  1689. BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
  1690. BE_GET_CRI_FROM_CID(beiscsi_conn->
  1691. beiscsi_conn_cid)));
  1692. list_del(&pasync_handle->link);
  1693. if (pasync_handle->is_header) {
  1694. pasync_ctx->async_header.busy_entries--;
  1695. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1696. hwi_free_async_msg(phba, pasync_ctx, cri);
  1697. BUG();
  1698. }
  1699. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1700. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1701. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1702. (unsigned short)pasync_handle->buffer_len;
  1703. list_add_tail(&pasync_handle->link,
  1704. &pasync_ctx->async_entry[cri].wait_queue.list);
  1705. ppdu = pasync_handle->pbuffer;
  1706. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1707. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1708. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1709. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1710. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1711. if (status == 0) {
  1712. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1713. bytes_needed;
  1714. if (bytes_needed == 0)
  1715. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1716. pasync_ctx, cri);
  1717. }
  1718. } else {
  1719. pasync_ctx->async_data.busy_entries--;
  1720. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1721. list_add_tail(&pasync_handle->link,
  1722. &pasync_ctx->async_entry[cri].wait_queue.
  1723. list);
  1724. pasync_ctx->async_entry[cri].wait_queue.
  1725. bytes_received +=
  1726. (unsigned short)pasync_handle->buffer_len;
  1727. if (pasync_ctx->async_entry[cri].wait_queue.
  1728. bytes_received >=
  1729. pasync_ctx->async_entry[cri].wait_queue.
  1730. bytes_needed)
  1731. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1732. pasync_ctx, cri);
  1733. }
  1734. }
  1735. return status;
  1736. }
  1737. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1738. struct beiscsi_hba *phba,
  1739. struct i_t_dpdu_cqe *pdpdu_cqe)
  1740. {
  1741. struct hwi_controller *phwi_ctrlr;
  1742. struct hwi_async_pdu_context *pasync_ctx;
  1743. struct async_pdu_handle *pasync_handle = NULL;
  1744. unsigned int cq_index = -1;
  1745. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  1746. beiscsi_conn->beiscsi_conn_cid);
  1747. phwi_ctrlr = phba->phwi_ctrlr;
  1748. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
  1749. BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
  1750. cri_index));
  1751. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1752. pdpdu_cqe, &cq_index);
  1753. if (pasync_handle->consumed == 0)
  1754. hwi_update_async_writables(phba, pasync_ctx,
  1755. pasync_handle->is_header, cq_index);
  1756. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1757. hwi_post_async_buffers(phba, pasync_handle->is_header,
  1758. BEISCSI_GET_ULP_FROM_CRI(
  1759. phwi_ctrlr, cri_index));
  1760. }
  1761. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1762. {
  1763. struct be_queue_info *mcc_cq;
  1764. struct be_mcc_compl *mcc_compl;
  1765. unsigned int num_processed = 0;
  1766. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1767. mcc_compl = queue_tail_node(mcc_cq);
  1768. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1769. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1770. if (num_processed >= 32) {
  1771. hwi_ring_cq_db(phba, mcc_cq->id,
  1772. num_processed, 0, 0);
  1773. num_processed = 0;
  1774. }
  1775. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1776. /* Interpret flags as an async trailer */
  1777. if (is_link_state_evt(mcc_compl->flags))
  1778. /* Interpret compl as a async link evt */
  1779. beiscsi_async_link_state_process(phba,
  1780. (struct be_async_event_link_state *) mcc_compl);
  1781. else
  1782. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1783. "BM_%d : Unsupported Async Event, flags"
  1784. " = 0x%08x\n",
  1785. mcc_compl->flags);
  1786. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1787. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1788. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1789. }
  1790. mcc_compl->flags = 0;
  1791. queue_tail_inc(mcc_cq);
  1792. mcc_compl = queue_tail_node(mcc_cq);
  1793. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1794. num_processed++;
  1795. }
  1796. if (num_processed > 0)
  1797. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1798. }
  1799. /**
  1800. * beiscsi_process_cq()- Process the Completion Queue
  1801. * @pbe_eq: Event Q on which the Completion has come
  1802. *
  1803. * return
  1804. * Number of Completion Entries processed.
  1805. **/
  1806. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1807. {
  1808. struct be_queue_info *cq;
  1809. struct sol_cqe *sol;
  1810. struct dmsg_cqe *dmsg;
  1811. unsigned int num_processed = 0;
  1812. unsigned int tot_nump = 0;
  1813. unsigned short code = 0, cid = 0;
  1814. uint16_t cri_index = 0;
  1815. struct beiscsi_conn *beiscsi_conn;
  1816. struct beiscsi_endpoint *beiscsi_ep;
  1817. struct iscsi_endpoint *ep;
  1818. struct beiscsi_hba *phba;
  1819. cq = pbe_eq->cq;
  1820. sol = queue_tail_node(cq);
  1821. phba = pbe_eq->phba;
  1822. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1823. CQE_VALID_MASK) {
  1824. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1825. code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
  1826. 32] & CQE_CODE_MASK);
  1827. /* Get the CID */
  1828. if (is_chip_be2_be3r(phba)) {
  1829. cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
  1830. } else {
  1831. if ((code == DRIVERMSG_NOTIFY) ||
  1832. (code == UNSOL_HDR_NOTIFY) ||
  1833. (code == UNSOL_DATA_NOTIFY))
  1834. cid = AMAP_GET_BITS(
  1835. struct amap_i_t_dpdu_cqe_v2,
  1836. cid, sol);
  1837. else
  1838. cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1839. cid, sol);
  1840. }
  1841. cri_index = BE_GET_CRI_FROM_CID(cid);
  1842. ep = phba->ep_array[cri_index];
  1843. beiscsi_ep = ep->dd_data;
  1844. beiscsi_conn = beiscsi_ep->conn;
  1845. if (num_processed >= 32) {
  1846. hwi_ring_cq_db(phba, cq->id,
  1847. num_processed, 0, 0);
  1848. tot_nump += num_processed;
  1849. num_processed = 0;
  1850. }
  1851. switch (code) {
  1852. case SOL_CMD_COMPLETE:
  1853. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1854. break;
  1855. case DRIVERMSG_NOTIFY:
  1856. beiscsi_log(phba, KERN_INFO,
  1857. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1858. "BM_%d : Received %s[%d] on CID : %d\n",
  1859. cqe_desc[code], code, cid);
  1860. dmsg = (struct dmsg_cqe *)sol;
  1861. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1862. break;
  1863. case UNSOL_HDR_NOTIFY:
  1864. beiscsi_log(phba, KERN_INFO,
  1865. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1866. "BM_%d : Received %s[%d] on CID : %d\n",
  1867. cqe_desc[code], code, cid);
  1868. spin_lock_bh(&phba->async_pdu_lock);
  1869. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1870. (struct i_t_dpdu_cqe *)sol);
  1871. spin_unlock_bh(&phba->async_pdu_lock);
  1872. break;
  1873. case UNSOL_DATA_NOTIFY:
  1874. beiscsi_log(phba, KERN_INFO,
  1875. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1876. "BM_%d : Received %s[%d] on CID : %d\n",
  1877. cqe_desc[code], code, cid);
  1878. spin_lock_bh(&phba->async_pdu_lock);
  1879. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1880. (struct i_t_dpdu_cqe *)sol);
  1881. spin_unlock_bh(&phba->async_pdu_lock);
  1882. break;
  1883. case CXN_INVALIDATE_INDEX_NOTIFY:
  1884. case CMD_INVALIDATED_NOTIFY:
  1885. case CXN_INVALIDATE_NOTIFY:
  1886. beiscsi_log(phba, KERN_ERR,
  1887. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1888. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1889. cqe_desc[code], code, cid);
  1890. break;
  1891. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1892. case CMD_KILLED_INVALID_STATSN_RCVD:
  1893. case CMD_KILLED_INVALID_R2T_RCVD:
  1894. case CMD_CXN_KILLED_LUN_INVALID:
  1895. case CMD_CXN_KILLED_ICD_INVALID:
  1896. case CMD_CXN_KILLED_ITT_INVALID:
  1897. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1898. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1899. beiscsi_log(phba, KERN_ERR,
  1900. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1901. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1902. cqe_desc[code], code, cid);
  1903. break;
  1904. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1905. beiscsi_log(phba, KERN_ERR,
  1906. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1907. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1908. cqe_desc[code], code, cid);
  1909. spin_lock_bh(&phba->async_pdu_lock);
  1910. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1911. (struct i_t_dpdu_cqe *) sol);
  1912. spin_unlock_bh(&phba->async_pdu_lock);
  1913. break;
  1914. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1915. case CXN_KILLED_BURST_LEN_MISMATCH:
  1916. case CXN_KILLED_AHS_RCVD:
  1917. case CXN_KILLED_HDR_DIGEST_ERR:
  1918. case CXN_KILLED_UNKNOWN_HDR:
  1919. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1920. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1921. case CXN_KILLED_TIMED_OUT:
  1922. case CXN_KILLED_FIN_RCVD:
  1923. case CXN_KILLED_RST_SENT:
  1924. case CXN_KILLED_RST_RCVD:
  1925. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1926. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1927. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1928. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1929. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1930. beiscsi_log(phba, KERN_ERR,
  1931. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1932. "BM_%d : Event %s[%d] received on CID : %d\n",
  1933. cqe_desc[code], code, cid);
  1934. if (beiscsi_conn)
  1935. iscsi_conn_failure(beiscsi_conn->conn,
  1936. ISCSI_ERR_CONN_FAILED);
  1937. break;
  1938. default:
  1939. beiscsi_log(phba, KERN_ERR,
  1940. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1941. "BM_%d : Invalid CQE Event Received Code : %d"
  1942. "CID 0x%x...\n",
  1943. code, cid);
  1944. break;
  1945. }
  1946. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1947. queue_tail_inc(cq);
  1948. sol = queue_tail_node(cq);
  1949. num_processed++;
  1950. }
  1951. if (num_processed > 0) {
  1952. tot_nump += num_processed;
  1953. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1954. }
  1955. return tot_nump;
  1956. }
  1957. void beiscsi_process_all_cqs(struct work_struct *work)
  1958. {
  1959. unsigned long flags;
  1960. struct hwi_controller *phwi_ctrlr;
  1961. struct hwi_context_memory *phwi_context;
  1962. struct beiscsi_hba *phba;
  1963. struct be_eq_obj *pbe_eq =
  1964. container_of(work, struct be_eq_obj, work_cqs);
  1965. phba = pbe_eq->phba;
  1966. phwi_ctrlr = phba->phwi_ctrlr;
  1967. phwi_context = phwi_ctrlr->phwi_ctxt;
  1968. if (pbe_eq->todo_mcc_cq) {
  1969. spin_lock_irqsave(&phba->isr_lock, flags);
  1970. pbe_eq->todo_mcc_cq = false;
  1971. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1972. beiscsi_process_mcc_isr(phba);
  1973. }
  1974. if (pbe_eq->todo_cq) {
  1975. spin_lock_irqsave(&phba->isr_lock, flags);
  1976. pbe_eq->todo_cq = false;
  1977. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1978. beiscsi_process_cq(pbe_eq);
  1979. }
  1980. /* rearm EQ for further interrupts */
  1981. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1982. }
  1983. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1984. {
  1985. unsigned int ret;
  1986. struct beiscsi_hba *phba;
  1987. struct be_eq_obj *pbe_eq;
  1988. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1989. ret = beiscsi_process_cq(pbe_eq);
  1990. if (ret < budget) {
  1991. phba = pbe_eq->phba;
  1992. blk_iopoll_complete(iop);
  1993. beiscsi_log(phba, KERN_INFO,
  1994. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1995. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1996. pbe_eq->q.id);
  1997. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1998. }
  1999. return ret;
  2000. }
  2001. static void
  2002. hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2003. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2004. {
  2005. struct iscsi_sge *psgl;
  2006. unsigned int sg_len, index;
  2007. unsigned int sge_len = 0;
  2008. unsigned long long addr;
  2009. struct scatterlist *l_sg;
  2010. unsigned int offset;
  2011. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
  2012. io_task->bhs_pa.u.a32.address_lo);
  2013. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
  2014. io_task->bhs_pa.u.a32.address_hi);
  2015. l_sg = sg;
  2016. for (index = 0; (index < num_sg) && (index < 2); index++,
  2017. sg = sg_next(sg)) {
  2018. if (index == 0) {
  2019. sg_len = sg_dma_len(sg);
  2020. addr = (u64) sg_dma_address(sg);
  2021. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2022. sge0_addr_lo, pwrb,
  2023. lower_32_bits(addr));
  2024. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2025. sge0_addr_hi, pwrb,
  2026. upper_32_bits(addr));
  2027. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2028. sge0_len, pwrb,
  2029. sg_len);
  2030. sge_len = sg_len;
  2031. } else {
  2032. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
  2033. pwrb, sge_len);
  2034. sg_len = sg_dma_len(sg);
  2035. addr = (u64) sg_dma_address(sg);
  2036. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2037. sge1_addr_lo, pwrb,
  2038. lower_32_bits(addr));
  2039. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2040. sge1_addr_hi, pwrb,
  2041. upper_32_bits(addr));
  2042. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2043. sge1_len, pwrb,
  2044. sg_len);
  2045. }
  2046. }
  2047. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2048. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2049. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2050. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2051. io_task->bhs_pa.u.a32.address_hi);
  2052. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2053. io_task->bhs_pa.u.a32.address_lo);
  2054. if (num_sg == 1) {
  2055. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2056. 1);
  2057. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2058. 0);
  2059. } else if (num_sg == 2) {
  2060. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2061. 0);
  2062. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2063. 1);
  2064. } else {
  2065. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2066. 0);
  2067. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2068. 0);
  2069. }
  2070. sg = l_sg;
  2071. psgl++;
  2072. psgl++;
  2073. offset = 0;
  2074. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2075. sg_len = sg_dma_len(sg);
  2076. addr = (u64) sg_dma_address(sg);
  2077. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2078. lower_32_bits(addr));
  2079. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2080. upper_32_bits(addr));
  2081. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2082. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2083. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2084. offset += sg_len;
  2085. }
  2086. psgl--;
  2087. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2088. }
  2089. static void
  2090. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2091. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2092. {
  2093. struct iscsi_sge *psgl;
  2094. unsigned int sg_len, index;
  2095. unsigned int sge_len = 0;
  2096. unsigned long long addr;
  2097. struct scatterlist *l_sg;
  2098. unsigned int offset;
  2099. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2100. io_task->bhs_pa.u.a32.address_lo);
  2101. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2102. io_task->bhs_pa.u.a32.address_hi);
  2103. l_sg = sg;
  2104. for (index = 0; (index < num_sg) && (index < 2); index++,
  2105. sg = sg_next(sg)) {
  2106. if (index == 0) {
  2107. sg_len = sg_dma_len(sg);
  2108. addr = (u64) sg_dma_address(sg);
  2109. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2110. ((u32)(addr & 0xFFFFFFFF)));
  2111. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2112. ((u32)(addr >> 32)));
  2113. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2114. sg_len);
  2115. sge_len = sg_len;
  2116. } else {
  2117. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  2118. pwrb, sge_len);
  2119. sg_len = sg_dma_len(sg);
  2120. addr = (u64) sg_dma_address(sg);
  2121. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  2122. ((u32)(addr & 0xFFFFFFFF)));
  2123. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  2124. ((u32)(addr >> 32)));
  2125. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  2126. sg_len);
  2127. }
  2128. }
  2129. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2130. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2131. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2132. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2133. io_task->bhs_pa.u.a32.address_hi);
  2134. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2135. io_task->bhs_pa.u.a32.address_lo);
  2136. if (num_sg == 1) {
  2137. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2138. 1);
  2139. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2140. 0);
  2141. } else if (num_sg == 2) {
  2142. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2143. 0);
  2144. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2145. 1);
  2146. } else {
  2147. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2148. 0);
  2149. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2150. 0);
  2151. }
  2152. sg = l_sg;
  2153. psgl++;
  2154. psgl++;
  2155. offset = 0;
  2156. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2157. sg_len = sg_dma_len(sg);
  2158. addr = (u64) sg_dma_address(sg);
  2159. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2160. (addr & 0xFFFFFFFF));
  2161. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2162. (addr >> 32));
  2163. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2164. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2165. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2166. offset += sg_len;
  2167. }
  2168. psgl--;
  2169. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2170. }
  2171. /**
  2172. * hwi_write_buffer()- Populate the WRB with task info
  2173. * @pwrb: ptr to the WRB entry
  2174. * @task: iscsi task which is to be executed
  2175. **/
  2176. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2177. {
  2178. struct iscsi_sge *psgl;
  2179. struct beiscsi_io_task *io_task = task->dd_data;
  2180. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2181. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2182. uint8_t dsp_value = 0;
  2183. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2184. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2185. io_task->bhs_pa.u.a32.address_lo);
  2186. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2187. io_task->bhs_pa.u.a32.address_hi);
  2188. if (task->data) {
  2189. /* Check for the data_count */
  2190. dsp_value = (task->data_count) ? 1 : 0;
  2191. if (is_chip_be2_be3r(phba))
  2192. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
  2193. pwrb, dsp_value);
  2194. else
  2195. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
  2196. pwrb, dsp_value);
  2197. /* Map addr only if there is data_count */
  2198. if (dsp_value) {
  2199. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2200. task->data,
  2201. task->data_count,
  2202. PCI_DMA_TODEVICE);
  2203. io_task->mtask_data_count = task->data_count;
  2204. } else
  2205. io_task->mtask_addr = 0;
  2206. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2207. lower_32_bits(io_task->mtask_addr));
  2208. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2209. upper_32_bits(io_task->mtask_addr));
  2210. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2211. task->data_count);
  2212. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2213. } else {
  2214. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2215. io_task->mtask_addr = 0;
  2216. }
  2217. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2218. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2219. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2220. io_task->bhs_pa.u.a32.address_hi);
  2221. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2222. io_task->bhs_pa.u.a32.address_lo);
  2223. if (task->data) {
  2224. psgl++;
  2225. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2226. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2227. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2228. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2229. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2230. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2231. psgl++;
  2232. if (task->data) {
  2233. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2234. lower_32_bits(io_task->mtask_addr));
  2235. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2236. upper_32_bits(io_task->mtask_addr));
  2237. }
  2238. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2239. }
  2240. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2241. }
  2242. /**
  2243. * beiscsi_find_mem_req()- Find mem needed
  2244. * @phba: ptr to HBA struct
  2245. **/
  2246. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2247. {
  2248. uint8_t mem_descr_index, ulp_num;
  2249. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2250. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2251. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2252. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2253. sizeof(struct sol_cqe));
  2254. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2255. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2256. BE_ISCSI_PDU_HEADER_SIZE;
  2257. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2258. sizeof(struct hwi_context_memory);
  2259. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2260. * (phba->params.wrbs_per_cxn)
  2261. * phba->params.cxns_per_ctrl;
  2262. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2263. (phba->params.wrbs_per_cxn);
  2264. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2265. phba->params.cxns_per_ctrl);
  2266. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2267. phba->params.icds_per_ctrl;
  2268. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2269. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2270. phba->mem_req[HWI_MEM_TEMPLATE_HDR] = phba->params.cxns_per_ctrl *
  2271. BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
  2272. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  2273. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  2274. num_async_pdu_buf_sgl_pages =
  2275. PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
  2276. phba, ulp_num) *
  2277. sizeof(struct phys_addr));
  2278. num_async_pdu_buf_pages =
  2279. PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
  2280. phba, ulp_num) *
  2281. phba->params.defpdu_hdr_sz);
  2282. num_async_pdu_data_pages =
  2283. PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
  2284. phba, ulp_num) *
  2285. phba->params.defpdu_data_sz);
  2286. num_async_pdu_data_sgl_pages =
  2287. PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
  2288. phba, ulp_num) *
  2289. sizeof(struct phys_addr));
  2290. mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
  2291. (ulp_num * MEM_DESCR_OFFSET));
  2292. phba->mem_req[mem_descr_index] =
  2293. num_async_pdu_buf_pages *
  2294. PAGE_SIZE;
  2295. mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 +
  2296. (ulp_num * MEM_DESCR_OFFSET));
  2297. phba->mem_req[mem_descr_index] =
  2298. num_async_pdu_data_pages *
  2299. PAGE_SIZE;
  2300. mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 +
  2301. (ulp_num * MEM_DESCR_OFFSET));
  2302. phba->mem_req[mem_descr_index] =
  2303. num_async_pdu_buf_sgl_pages *
  2304. PAGE_SIZE;
  2305. mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 +
  2306. (ulp_num * MEM_DESCR_OFFSET));
  2307. phba->mem_req[mem_descr_index] =
  2308. num_async_pdu_data_sgl_pages *
  2309. PAGE_SIZE;
  2310. mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
  2311. (ulp_num * MEM_DESCR_OFFSET));
  2312. phba->mem_req[mem_descr_index] =
  2313. BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  2314. sizeof(struct async_pdu_handle);
  2315. mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
  2316. (ulp_num * MEM_DESCR_OFFSET));
  2317. phba->mem_req[mem_descr_index] =
  2318. BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  2319. sizeof(struct async_pdu_handle);
  2320. mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
  2321. (ulp_num * MEM_DESCR_OFFSET));
  2322. phba->mem_req[mem_descr_index] =
  2323. sizeof(struct hwi_async_pdu_context) +
  2324. (BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  2325. sizeof(struct hwi_async_entry));
  2326. }
  2327. }
  2328. }
  2329. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2330. {
  2331. dma_addr_t bus_add;
  2332. struct hwi_controller *phwi_ctrlr;
  2333. struct be_mem_descriptor *mem_descr;
  2334. struct mem_array *mem_arr, *mem_arr_orig;
  2335. unsigned int i, j, alloc_size, curr_alloc_size;
  2336. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2337. if (!phba->phwi_ctrlr)
  2338. return -ENOMEM;
  2339. /* Allocate memory for wrb_context */
  2340. phwi_ctrlr = phba->phwi_ctrlr;
  2341. phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
  2342. phba->params.cxns_per_ctrl,
  2343. GFP_KERNEL);
  2344. if (!phwi_ctrlr->wrb_context)
  2345. return -ENOMEM;
  2346. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2347. GFP_KERNEL);
  2348. if (!phba->init_mem) {
  2349. kfree(phwi_ctrlr->wrb_context);
  2350. kfree(phba->phwi_ctrlr);
  2351. return -ENOMEM;
  2352. }
  2353. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2354. GFP_KERNEL);
  2355. if (!mem_arr_orig) {
  2356. kfree(phba->init_mem);
  2357. kfree(phwi_ctrlr->wrb_context);
  2358. kfree(phba->phwi_ctrlr);
  2359. return -ENOMEM;
  2360. }
  2361. mem_descr = phba->init_mem;
  2362. for (i = 0; i < SE_MEM_MAX; i++) {
  2363. if (!phba->mem_req[i]) {
  2364. mem_descr->mem_array = NULL;
  2365. mem_descr++;
  2366. continue;
  2367. }
  2368. j = 0;
  2369. mem_arr = mem_arr_orig;
  2370. alloc_size = phba->mem_req[i];
  2371. memset(mem_arr, 0, sizeof(struct mem_array) *
  2372. BEISCSI_MAX_FRAGS_INIT);
  2373. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2374. do {
  2375. mem_arr->virtual_address = pci_alloc_consistent(
  2376. phba->pcidev,
  2377. curr_alloc_size,
  2378. &bus_add);
  2379. if (!mem_arr->virtual_address) {
  2380. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2381. goto free_mem;
  2382. if (curr_alloc_size -
  2383. rounddown_pow_of_two(curr_alloc_size))
  2384. curr_alloc_size = rounddown_pow_of_two
  2385. (curr_alloc_size);
  2386. else
  2387. curr_alloc_size = curr_alloc_size / 2;
  2388. } else {
  2389. mem_arr->bus_address.u.
  2390. a64.address = (__u64) bus_add;
  2391. mem_arr->size = curr_alloc_size;
  2392. alloc_size -= curr_alloc_size;
  2393. curr_alloc_size = min(be_max_phys_size *
  2394. 1024, alloc_size);
  2395. j++;
  2396. mem_arr++;
  2397. }
  2398. } while (alloc_size);
  2399. mem_descr->num_elements = j;
  2400. mem_descr->size_in_bytes = phba->mem_req[i];
  2401. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2402. GFP_KERNEL);
  2403. if (!mem_descr->mem_array)
  2404. goto free_mem;
  2405. memcpy(mem_descr->mem_array, mem_arr_orig,
  2406. sizeof(struct mem_array) * j);
  2407. mem_descr++;
  2408. }
  2409. kfree(mem_arr_orig);
  2410. return 0;
  2411. free_mem:
  2412. mem_descr->num_elements = j;
  2413. while ((i) || (j)) {
  2414. for (j = mem_descr->num_elements; j > 0; j--) {
  2415. pci_free_consistent(phba->pcidev,
  2416. mem_descr->mem_array[j - 1].size,
  2417. mem_descr->mem_array[j - 1].
  2418. virtual_address,
  2419. (unsigned long)mem_descr->
  2420. mem_array[j - 1].
  2421. bus_address.u.a64.address);
  2422. }
  2423. if (i) {
  2424. i--;
  2425. kfree(mem_descr->mem_array);
  2426. mem_descr--;
  2427. }
  2428. }
  2429. kfree(mem_arr_orig);
  2430. kfree(phba->init_mem);
  2431. kfree(phba->phwi_ctrlr->wrb_context);
  2432. kfree(phba->phwi_ctrlr);
  2433. return -ENOMEM;
  2434. }
  2435. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2436. {
  2437. beiscsi_find_mem_req(phba);
  2438. return beiscsi_alloc_mem(phba);
  2439. }
  2440. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2441. {
  2442. struct pdu_data_out *pdata_out;
  2443. struct pdu_nop_out *pnop_out;
  2444. struct be_mem_descriptor *mem_descr;
  2445. mem_descr = phba->init_mem;
  2446. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2447. pdata_out =
  2448. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2449. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2450. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2451. IIOC_SCSI_DATA);
  2452. pnop_out =
  2453. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2454. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2455. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2456. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2457. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2458. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2459. }
  2460. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2461. {
  2462. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2463. struct hwi_context_memory *phwi_ctxt;
  2464. struct wrb_handle *pwrb_handle = NULL;
  2465. struct hwi_controller *phwi_ctrlr;
  2466. struct hwi_wrb_context *pwrb_context;
  2467. struct iscsi_wrb *pwrb = NULL;
  2468. unsigned int num_cxn_wrbh = 0;
  2469. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2470. mem_descr_wrbh = phba->init_mem;
  2471. mem_descr_wrbh += HWI_MEM_WRBH;
  2472. mem_descr_wrb = phba->init_mem;
  2473. mem_descr_wrb += HWI_MEM_WRB;
  2474. phwi_ctrlr = phba->phwi_ctrlr;
  2475. /* Allocate memory for WRBQ */
  2476. phwi_ctxt = phwi_ctrlr->phwi_ctxt;
  2477. phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
  2478. phba->params.cxns_per_ctrl,
  2479. GFP_KERNEL);
  2480. if (!phwi_ctxt->be_wrbq) {
  2481. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2482. "BM_%d : WRBQ Mem Alloc Failed\n");
  2483. return -ENOMEM;
  2484. }
  2485. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  2486. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2487. pwrb_context->pwrb_handle_base =
  2488. kzalloc(sizeof(struct wrb_handle *) *
  2489. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2490. if (!pwrb_context->pwrb_handle_base) {
  2491. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2492. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2493. goto init_wrb_hndl_failed;
  2494. }
  2495. pwrb_context->pwrb_handle_basestd =
  2496. kzalloc(sizeof(struct wrb_handle *) *
  2497. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2498. if (!pwrb_context->pwrb_handle_basestd) {
  2499. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2500. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2501. goto init_wrb_hndl_failed;
  2502. }
  2503. if (!num_cxn_wrbh) {
  2504. pwrb_handle =
  2505. mem_descr_wrbh->mem_array[idx].virtual_address;
  2506. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2507. ((sizeof(struct wrb_handle)) *
  2508. phba->params.wrbs_per_cxn));
  2509. idx++;
  2510. }
  2511. pwrb_context->alloc_index = 0;
  2512. pwrb_context->wrb_handles_available = 0;
  2513. pwrb_context->free_index = 0;
  2514. if (num_cxn_wrbh) {
  2515. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2516. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2517. pwrb_context->pwrb_handle_basestd[j] =
  2518. pwrb_handle;
  2519. pwrb_context->wrb_handles_available++;
  2520. pwrb_handle->wrb_index = j;
  2521. pwrb_handle++;
  2522. }
  2523. num_cxn_wrbh--;
  2524. }
  2525. }
  2526. idx = 0;
  2527. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  2528. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2529. if (!num_cxn_wrb) {
  2530. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2531. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2532. ((sizeof(struct iscsi_wrb) *
  2533. phba->params.wrbs_per_cxn));
  2534. idx++;
  2535. }
  2536. if (num_cxn_wrb) {
  2537. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2538. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2539. pwrb_handle->pwrb = pwrb;
  2540. pwrb++;
  2541. }
  2542. num_cxn_wrb--;
  2543. }
  2544. }
  2545. return 0;
  2546. init_wrb_hndl_failed:
  2547. for (j = index; j > 0; j--) {
  2548. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2549. kfree(pwrb_context->pwrb_handle_base);
  2550. kfree(pwrb_context->pwrb_handle_basestd);
  2551. }
  2552. return -ENOMEM;
  2553. }
  2554. static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2555. {
  2556. uint8_t ulp_num;
  2557. struct hwi_controller *phwi_ctrlr;
  2558. struct hba_parameters *p = &phba->params;
  2559. struct hwi_async_pdu_context *pasync_ctx;
  2560. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2561. unsigned int index, idx, num_per_mem, num_async_data;
  2562. struct be_mem_descriptor *mem_descr;
  2563. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  2564. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  2565. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2566. mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
  2567. (ulp_num * MEM_DESCR_OFFSET));
  2568. phwi_ctrlr = phba->phwi_ctrlr;
  2569. phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] =
  2570. (struct hwi_async_pdu_context *)
  2571. mem_descr->mem_array[0].virtual_address;
  2572. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
  2573. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2574. pasync_ctx->async_entry =
  2575. (struct hwi_async_entry *)
  2576. ((long unsigned int)pasync_ctx +
  2577. sizeof(struct hwi_async_pdu_context));
  2578. pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba,
  2579. ulp_num);
  2580. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2581. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2582. mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
  2583. (ulp_num * MEM_DESCR_OFFSET);
  2584. if (mem_descr->mem_array[0].virtual_address) {
  2585. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2586. "BM_%d : hwi_init_async_pdu_ctx"
  2587. " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n",
  2588. ulp_num,
  2589. mem_descr->mem_array[0].
  2590. virtual_address);
  2591. } else
  2592. beiscsi_log(phba, KERN_WARNING,
  2593. BEISCSI_LOG_INIT,
  2594. "BM_%d : No Virtual address for ULP : %d\n",
  2595. ulp_num);
  2596. pasync_ctx->async_header.va_base =
  2597. mem_descr->mem_array[0].virtual_address;
  2598. pasync_ctx->async_header.pa_base.u.a64.address =
  2599. mem_descr->mem_array[0].
  2600. bus_address.u.a64.address;
  2601. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2602. mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
  2603. (ulp_num * MEM_DESCR_OFFSET);
  2604. if (mem_descr->mem_array[0].virtual_address) {
  2605. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2606. "BM_%d : hwi_init_async_pdu_ctx"
  2607. " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n",
  2608. ulp_num,
  2609. mem_descr->mem_array[0].
  2610. virtual_address);
  2611. } else
  2612. beiscsi_log(phba, KERN_WARNING,
  2613. BEISCSI_LOG_INIT,
  2614. "BM_%d : No Virtual address for ULP : %d\n",
  2615. ulp_num);
  2616. pasync_ctx->async_header.ring_base =
  2617. mem_descr->mem_array[0].virtual_address;
  2618. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2619. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
  2620. (ulp_num * MEM_DESCR_OFFSET);
  2621. if (mem_descr->mem_array[0].virtual_address) {
  2622. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2623. "BM_%d : hwi_init_async_pdu_ctx"
  2624. " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n",
  2625. ulp_num,
  2626. mem_descr->mem_array[0].
  2627. virtual_address);
  2628. } else
  2629. beiscsi_log(phba, KERN_WARNING,
  2630. BEISCSI_LOG_INIT,
  2631. "BM_%d : No Virtual address for ULP : %d\n",
  2632. ulp_num);
  2633. pasync_ctx->async_header.handle_base =
  2634. mem_descr->mem_array[0].virtual_address;
  2635. pasync_ctx->async_header.writables = 0;
  2636. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2637. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2638. mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
  2639. (ulp_num * MEM_DESCR_OFFSET);
  2640. if (mem_descr->mem_array[0].virtual_address) {
  2641. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2642. "BM_%d : hwi_init_async_pdu_ctx"
  2643. " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n",
  2644. ulp_num,
  2645. mem_descr->mem_array[0].
  2646. virtual_address);
  2647. } else
  2648. beiscsi_log(phba, KERN_WARNING,
  2649. BEISCSI_LOG_INIT,
  2650. "BM_%d : No Virtual address for ULP : %d\n",
  2651. ulp_num);
  2652. pasync_ctx->async_data.ring_base =
  2653. mem_descr->mem_array[0].virtual_address;
  2654. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2655. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
  2656. (ulp_num * MEM_DESCR_OFFSET);
  2657. if (!mem_descr->mem_array[0].virtual_address)
  2658. beiscsi_log(phba, KERN_WARNING,
  2659. BEISCSI_LOG_INIT,
  2660. "BM_%d : No Virtual address for ULP : %d\n",
  2661. ulp_num);
  2662. pasync_ctx->async_data.handle_base =
  2663. mem_descr->mem_array[0].virtual_address;
  2664. pasync_ctx->async_data.writables = 0;
  2665. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2666. pasync_header_h =
  2667. (struct async_pdu_handle *)
  2668. pasync_ctx->async_header.handle_base;
  2669. pasync_data_h =
  2670. (struct async_pdu_handle *)
  2671. pasync_ctx->async_data.handle_base;
  2672. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2673. mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 +
  2674. (ulp_num * MEM_DESCR_OFFSET);
  2675. if (mem_descr->mem_array[0].virtual_address) {
  2676. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2677. "BM_%d : hwi_init_async_pdu_ctx"
  2678. " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n",
  2679. ulp_num,
  2680. mem_descr->mem_array[0].
  2681. virtual_address);
  2682. } else
  2683. beiscsi_log(phba, KERN_WARNING,
  2684. BEISCSI_LOG_INIT,
  2685. "BM_%d : No Virtual address for ULP : %d\n",
  2686. ulp_num);
  2687. idx = 0;
  2688. pasync_ctx->async_data.va_base =
  2689. mem_descr->mem_array[idx].virtual_address;
  2690. pasync_ctx->async_data.pa_base.u.a64.address =
  2691. mem_descr->mem_array[idx].
  2692. bus_address.u.a64.address;
  2693. num_async_data = ((mem_descr->mem_array[idx].size) /
  2694. phba->params.defpdu_data_sz);
  2695. num_per_mem = 0;
  2696. for (index = 0; index < BEISCSI_GET_CID_COUNT
  2697. (phba, ulp_num); index++) {
  2698. pasync_header_h->cri = -1;
  2699. pasync_header_h->index = (char)index;
  2700. INIT_LIST_HEAD(&pasync_header_h->link);
  2701. pasync_header_h->pbuffer =
  2702. (void *)((unsigned long)
  2703. (pasync_ctx->
  2704. async_header.va_base) +
  2705. (p->defpdu_hdr_sz * index));
  2706. pasync_header_h->pa.u.a64.address =
  2707. pasync_ctx->async_header.pa_base.u.a64.
  2708. address + (p->defpdu_hdr_sz * index);
  2709. list_add_tail(&pasync_header_h->link,
  2710. &pasync_ctx->async_header.
  2711. free_list);
  2712. pasync_header_h++;
  2713. pasync_ctx->async_header.free_entries++;
  2714. pasync_ctx->async_header.writables++;
  2715. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2716. wait_queue.list);
  2717. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2718. header_busy_list);
  2719. pasync_data_h->cri = -1;
  2720. pasync_data_h->index = (char)index;
  2721. INIT_LIST_HEAD(&pasync_data_h->link);
  2722. if (!num_async_data) {
  2723. num_per_mem = 0;
  2724. idx++;
  2725. pasync_ctx->async_data.va_base =
  2726. mem_descr->mem_array[idx].
  2727. virtual_address;
  2728. pasync_ctx->async_data.pa_base.u.
  2729. a64.address =
  2730. mem_descr->mem_array[idx].
  2731. bus_address.u.a64.address;
  2732. num_async_data =
  2733. ((mem_descr->mem_array[idx].
  2734. size) /
  2735. phba->params.defpdu_data_sz);
  2736. }
  2737. pasync_data_h->pbuffer =
  2738. (void *)((unsigned long)
  2739. (pasync_ctx->async_data.va_base) +
  2740. (p->defpdu_data_sz * num_per_mem));
  2741. pasync_data_h->pa.u.a64.address =
  2742. pasync_ctx->async_data.pa_base.u.a64.
  2743. address + (p->defpdu_data_sz *
  2744. num_per_mem);
  2745. num_per_mem++;
  2746. num_async_data--;
  2747. list_add_tail(&pasync_data_h->link,
  2748. &pasync_ctx->async_data.
  2749. free_list);
  2750. pasync_data_h++;
  2751. pasync_ctx->async_data.free_entries++;
  2752. pasync_ctx->async_data.writables++;
  2753. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2754. data_busy_list);
  2755. }
  2756. pasync_ctx->async_header.host_write_ptr = 0;
  2757. pasync_ctx->async_header.ep_read_ptr = -1;
  2758. pasync_ctx->async_data.host_write_ptr = 0;
  2759. pasync_ctx->async_data.ep_read_ptr = -1;
  2760. }
  2761. }
  2762. return 0;
  2763. }
  2764. static int
  2765. be_sgl_create_contiguous(void *virtual_address,
  2766. u64 physical_address, u32 length,
  2767. struct be_dma_mem *sgl)
  2768. {
  2769. WARN_ON(!virtual_address);
  2770. WARN_ON(!physical_address);
  2771. WARN_ON(!length > 0);
  2772. WARN_ON(!sgl);
  2773. sgl->va = virtual_address;
  2774. sgl->dma = (unsigned long)physical_address;
  2775. sgl->size = length;
  2776. return 0;
  2777. }
  2778. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2779. {
  2780. memset(sgl, 0, sizeof(*sgl));
  2781. }
  2782. static void
  2783. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2784. struct mem_array *pmem, struct be_dma_mem *sgl)
  2785. {
  2786. if (sgl->va)
  2787. be_sgl_destroy_contiguous(sgl);
  2788. be_sgl_create_contiguous(pmem->virtual_address,
  2789. pmem->bus_address.u.a64.address,
  2790. pmem->size, sgl);
  2791. }
  2792. static void
  2793. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2794. struct mem_array *pmem, struct be_dma_mem *sgl)
  2795. {
  2796. if (sgl->va)
  2797. be_sgl_destroy_contiguous(sgl);
  2798. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2799. pmem->bus_address.u.a64.address,
  2800. pmem->size, sgl);
  2801. }
  2802. static int be_fill_queue(struct be_queue_info *q,
  2803. u16 len, u16 entry_size, void *vaddress)
  2804. {
  2805. struct be_dma_mem *mem = &q->dma_mem;
  2806. memset(q, 0, sizeof(*q));
  2807. q->len = len;
  2808. q->entry_size = entry_size;
  2809. mem->size = len * entry_size;
  2810. mem->va = vaddress;
  2811. if (!mem->va)
  2812. return -ENOMEM;
  2813. memset(mem->va, 0, mem->size);
  2814. return 0;
  2815. }
  2816. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2817. struct hwi_context_memory *phwi_context)
  2818. {
  2819. unsigned int i, num_eq_pages;
  2820. int ret = 0, eq_for_mcc;
  2821. struct be_queue_info *eq;
  2822. struct be_dma_mem *mem;
  2823. void *eq_vaddress;
  2824. dma_addr_t paddr;
  2825. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2826. sizeof(struct be_eq_entry));
  2827. if (phba->msix_enabled)
  2828. eq_for_mcc = 1;
  2829. else
  2830. eq_for_mcc = 0;
  2831. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2832. eq = &phwi_context->be_eq[i].q;
  2833. mem = &eq->dma_mem;
  2834. phwi_context->be_eq[i].phba = phba;
  2835. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2836. num_eq_pages * PAGE_SIZE,
  2837. &paddr);
  2838. if (!eq_vaddress)
  2839. goto create_eq_error;
  2840. mem->va = eq_vaddress;
  2841. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2842. sizeof(struct be_eq_entry), eq_vaddress);
  2843. if (ret) {
  2844. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2845. "BM_%d : be_fill_queue Failed for EQ\n");
  2846. goto create_eq_error;
  2847. }
  2848. mem->dma = paddr;
  2849. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2850. phwi_context->cur_eqd);
  2851. if (ret) {
  2852. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2853. "BM_%d : beiscsi_cmd_eq_create"
  2854. "Failed for EQ\n");
  2855. goto create_eq_error;
  2856. }
  2857. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2858. "BM_%d : eqid = %d\n",
  2859. phwi_context->be_eq[i].q.id);
  2860. }
  2861. return 0;
  2862. create_eq_error:
  2863. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2864. eq = &phwi_context->be_eq[i].q;
  2865. mem = &eq->dma_mem;
  2866. if (mem->va)
  2867. pci_free_consistent(phba->pcidev, num_eq_pages
  2868. * PAGE_SIZE,
  2869. mem->va, mem->dma);
  2870. }
  2871. return ret;
  2872. }
  2873. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2874. struct hwi_context_memory *phwi_context)
  2875. {
  2876. unsigned int i, num_cq_pages;
  2877. int ret = 0;
  2878. struct be_queue_info *cq, *eq;
  2879. struct be_dma_mem *mem;
  2880. struct be_eq_obj *pbe_eq;
  2881. void *cq_vaddress;
  2882. dma_addr_t paddr;
  2883. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2884. sizeof(struct sol_cqe));
  2885. for (i = 0; i < phba->num_cpus; i++) {
  2886. cq = &phwi_context->be_cq[i];
  2887. eq = &phwi_context->be_eq[i].q;
  2888. pbe_eq = &phwi_context->be_eq[i];
  2889. pbe_eq->cq = cq;
  2890. pbe_eq->phba = phba;
  2891. mem = &cq->dma_mem;
  2892. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2893. num_cq_pages * PAGE_SIZE,
  2894. &paddr);
  2895. if (!cq_vaddress)
  2896. goto create_cq_error;
  2897. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2898. sizeof(struct sol_cqe), cq_vaddress);
  2899. if (ret) {
  2900. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2901. "BM_%d : be_fill_queue Failed "
  2902. "for ISCSI CQ\n");
  2903. goto create_cq_error;
  2904. }
  2905. mem->dma = paddr;
  2906. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2907. false, 0);
  2908. if (ret) {
  2909. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2910. "BM_%d : beiscsi_cmd_eq_create"
  2911. "Failed for ISCSI CQ\n");
  2912. goto create_cq_error;
  2913. }
  2914. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2915. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2916. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2917. }
  2918. return 0;
  2919. create_cq_error:
  2920. for (i = 0; i < phba->num_cpus; i++) {
  2921. cq = &phwi_context->be_cq[i];
  2922. mem = &cq->dma_mem;
  2923. if (mem->va)
  2924. pci_free_consistent(phba->pcidev, num_cq_pages
  2925. * PAGE_SIZE,
  2926. mem->va, mem->dma);
  2927. }
  2928. return ret;
  2929. }
  2930. static int
  2931. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2932. struct hwi_context_memory *phwi_context,
  2933. struct hwi_controller *phwi_ctrlr,
  2934. unsigned int def_pdu_ring_sz, uint8_t ulp_num)
  2935. {
  2936. unsigned int idx;
  2937. int ret;
  2938. struct be_queue_info *dq, *cq;
  2939. struct be_dma_mem *mem;
  2940. struct be_mem_descriptor *mem_descr;
  2941. void *dq_vaddress;
  2942. idx = 0;
  2943. dq = &phwi_context->be_def_hdrq[ulp_num];
  2944. cq = &phwi_context->be_cq[0];
  2945. mem = &dq->dma_mem;
  2946. mem_descr = phba->init_mem;
  2947. mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
  2948. (ulp_num * MEM_DESCR_OFFSET);
  2949. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2950. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2951. sizeof(struct phys_addr),
  2952. sizeof(struct phys_addr), dq_vaddress);
  2953. if (ret) {
  2954. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2955. "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n",
  2956. ulp_num);
  2957. return ret;
  2958. }
  2959. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2960. bus_address.u.a64.address;
  2961. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2962. def_pdu_ring_sz,
  2963. phba->params.defpdu_hdr_sz,
  2964. BEISCSI_DEFQ_HDR, ulp_num);
  2965. if (ret) {
  2966. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2967. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n",
  2968. ulp_num);
  2969. return ret;
  2970. }
  2971. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2972. "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n",
  2973. ulp_num,
  2974. phwi_context->be_def_hdrq[ulp_num].id);
  2975. hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num);
  2976. return 0;
  2977. }
  2978. static int
  2979. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2980. struct hwi_context_memory *phwi_context,
  2981. struct hwi_controller *phwi_ctrlr,
  2982. unsigned int def_pdu_ring_sz, uint8_t ulp_num)
  2983. {
  2984. unsigned int idx;
  2985. int ret;
  2986. struct be_queue_info *dataq, *cq;
  2987. struct be_dma_mem *mem;
  2988. struct be_mem_descriptor *mem_descr;
  2989. void *dq_vaddress;
  2990. idx = 0;
  2991. dataq = &phwi_context->be_def_dataq[ulp_num];
  2992. cq = &phwi_context->be_cq[0];
  2993. mem = &dataq->dma_mem;
  2994. mem_descr = phba->init_mem;
  2995. mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
  2996. (ulp_num * MEM_DESCR_OFFSET);
  2997. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2998. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2999. sizeof(struct phys_addr),
  3000. sizeof(struct phys_addr), dq_vaddress);
  3001. if (ret) {
  3002. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3003. "BM_%d : be_fill_queue Failed for DEF PDU "
  3004. "DATA on ULP : %d\n",
  3005. ulp_num);
  3006. return ret;
  3007. }
  3008. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  3009. bus_address.u.a64.address;
  3010. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  3011. def_pdu_ring_sz,
  3012. phba->params.defpdu_data_sz,
  3013. BEISCSI_DEFQ_DATA, ulp_num);
  3014. if (ret) {
  3015. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3016. "BM_%d be_cmd_create_default_pdu_queue"
  3017. " Failed for DEF PDU DATA on ULP : %d\n",
  3018. ulp_num);
  3019. return ret;
  3020. }
  3021. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3022. "BM_%d : iscsi def data id on ULP : %d is %d\n",
  3023. ulp_num,
  3024. phwi_context->be_def_dataq[ulp_num].id);
  3025. hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num);
  3026. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3027. "BM_%d : DEFAULT PDU DATA RING CREATED"
  3028. "on ULP : %d\n", ulp_num);
  3029. return 0;
  3030. }
  3031. static int
  3032. beiscsi_post_template_hdr(struct beiscsi_hba *phba)
  3033. {
  3034. struct be_mem_descriptor *mem_descr;
  3035. struct mem_array *pm_arr;
  3036. struct be_dma_mem sgl;
  3037. int status, i;
  3038. mem_descr = phba->init_mem;
  3039. mem_descr += HWI_MEM_TEMPLATE_HDR;
  3040. pm_arr = mem_descr->mem_array;
  3041. for (i = 0; i < mem_descr->num_elements; i++) {
  3042. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  3043. status = be_cmd_iscsi_post_template_hdr(&phba->ctrl, &sgl);
  3044. if (status != 0) {
  3045. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3046. "BM_%d : Post Template HDR Failed\n");
  3047. return status;
  3048. }
  3049. }
  3050. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3051. "BM_%d : Template HDR Pages Posted\n");
  3052. return 0;
  3053. }
  3054. static int
  3055. beiscsi_post_pages(struct beiscsi_hba *phba)
  3056. {
  3057. struct be_mem_descriptor *mem_descr;
  3058. struct mem_array *pm_arr;
  3059. unsigned int page_offset, i;
  3060. struct be_dma_mem sgl;
  3061. int status, ulp_num = 0;
  3062. mem_descr = phba->init_mem;
  3063. mem_descr += HWI_MEM_SGE;
  3064. pm_arr = mem_descr->mem_array;
  3065. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  3066. phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
  3067. for (i = 0; i < mem_descr->num_elements; i++) {
  3068. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  3069. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  3070. page_offset,
  3071. (pm_arr->size / PAGE_SIZE));
  3072. page_offset += pm_arr->size / PAGE_SIZE;
  3073. if (status != 0) {
  3074. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3075. "BM_%d : post sgl failed.\n");
  3076. return status;
  3077. }
  3078. pm_arr++;
  3079. }
  3080. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3081. "BM_%d : POSTED PAGES\n");
  3082. return 0;
  3083. }
  3084. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  3085. {
  3086. struct be_dma_mem *mem = &q->dma_mem;
  3087. if (mem->va) {
  3088. pci_free_consistent(phba->pcidev, mem->size,
  3089. mem->va, mem->dma);
  3090. mem->va = NULL;
  3091. }
  3092. }
  3093. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  3094. u16 len, u16 entry_size)
  3095. {
  3096. struct be_dma_mem *mem = &q->dma_mem;
  3097. memset(q, 0, sizeof(*q));
  3098. q->len = len;
  3099. q->entry_size = entry_size;
  3100. mem->size = len * entry_size;
  3101. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  3102. if (!mem->va)
  3103. return -ENOMEM;
  3104. memset(mem->va, 0, mem->size);
  3105. return 0;
  3106. }
  3107. static int
  3108. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  3109. struct hwi_context_memory *phwi_context,
  3110. struct hwi_controller *phwi_ctrlr)
  3111. {
  3112. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  3113. u64 pa_addr_lo;
  3114. unsigned int idx, num, i;
  3115. struct mem_array *pwrb_arr;
  3116. void *wrb_vaddr;
  3117. struct be_dma_mem sgl;
  3118. struct be_mem_descriptor *mem_descr;
  3119. struct hwi_wrb_context *pwrb_context;
  3120. int status;
  3121. idx = 0;
  3122. mem_descr = phba->init_mem;
  3123. mem_descr += HWI_MEM_WRB;
  3124. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  3125. GFP_KERNEL);
  3126. if (!pwrb_arr) {
  3127. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3128. "BM_%d : Memory alloc failed in create wrb ring.\n");
  3129. return -ENOMEM;
  3130. }
  3131. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  3132. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  3133. num_wrb_rings = mem_descr->mem_array[idx].size /
  3134. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  3135. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  3136. if (num_wrb_rings) {
  3137. pwrb_arr[num].virtual_address = wrb_vaddr;
  3138. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  3139. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  3140. sizeof(struct iscsi_wrb);
  3141. wrb_vaddr += pwrb_arr[num].size;
  3142. pa_addr_lo += pwrb_arr[num].size;
  3143. num_wrb_rings--;
  3144. } else {
  3145. idx++;
  3146. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  3147. pa_addr_lo = mem_descr->mem_array[idx].\
  3148. bus_address.u.a64.address;
  3149. num_wrb_rings = mem_descr->mem_array[idx].size /
  3150. (phba->params.wrbs_per_cxn *
  3151. sizeof(struct iscsi_wrb));
  3152. pwrb_arr[num].virtual_address = wrb_vaddr;
  3153. pwrb_arr[num].bus_address.u.a64.address\
  3154. = pa_addr_lo;
  3155. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  3156. sizeof(struct iscsi_wrb);
  3157. wrb_vaddr += pwrb_arr[num].size;
  3158. pa_addr_lo += pwrb_arr[num].size;
  3159. num_wrb_rings--;
  3160. }
  3161. }
  3162. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3163. wrb_mem_index = 0;
  3164. offset = 0;
  3165. size = 0;
  3166. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  3167. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  3168. &phwi_context->be_wrbq[i]);
  3169. if (status != 0) {
  3170. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3171. "BM_%d : wrbq create failed.");
  3172. kfree(pwrb_arr);
  3173. return status;
  3174. }
  3175. pwrb_context = &phwi_ctrlr->wrb_context[i];
  3176. pwrb_context->cid = phwi_context->be_wrbq[i].id;
  3177. BE_SET_CID_TO_CRI(i, pwrb_context->cid);
  3178. }
  3179. kfree(pwrb_arr);
  3180. return 0;
  3181. }
  3182. static void free_wrb_handles(struct beiscsi_hba *phba)
  3183. {
  3184. unsigned int index;
  3185. struct hwi_controller *phwi_ctrlr;
  3186. struct hwi_wrb_context *pwrb_context;
  3187. phwi_ctrlr = phba->phwi_ctrlr;
  3188. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  3189. pwrb_context = &phwi_ctrlr->wrb_context[index];
  3190. kfree(pwrb_context->pwrb_handle_base);
  3191. kfree(pwrb_context->pwrb_handle_basestd);
  3192. }
  3193. }
  3194. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  3195. {
  3196. struct be_queue_info *q;
  3197. struct be_ctrl_info *ctrl = &phba->ctrl;
  3198. q = &phba->ctrl.mcc_obj.q;
  3199. if (q->created)
  3200. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  3201. be_queue_free(phba, q);
  3202. q = &phba->ctrl.mcc_obj.cq;
  3203. if (q->created)
  3204. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3205. be_queue_free(phba, q);
  3206. }
  3207. static void hwi_cleanup(struct beiscsi_hba *phba)
  3208. {
  3209. struct be_queue_info *q;
  3210. struct be_ctrl_info *ctrl = &phba->ctrl;
  3211. struct hwi_controller *phwi_ctrlr;
  3212. struct hwi_context_memory *phwi_context;
  3213. struct hwi_async_pdu_context *pasync_ctx;
  3214. int i, eq_num, ulp_num;
  3215. phwi_ctrlr = phba->phwi_ctrlr;
  3216. phwi_context = phwi_ctrlr->phwi_ctxt;
  3217. be_cmd_iscsi_remove_template_hdr(ctrl);
  3218. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3219. q = &phwi_context->be_wrbq[i];
  3220. if (q->created)
  3221. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  3222. }
  3223. kfree(phwi_context->be_wrbq);
  3224. free_wrb_handles(phba);
  3225. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3226. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  3227. q = &phwi_context->be_def_hdrq[ulp_num];
  3228. if (q->created)
  3229. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3230. q = &phwi_context->be_def_dataq[ulp_num];
  3231. if (q->created)
  3232. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3233. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
  3234. }
  3235. }
  3236. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  3237. for (i = 0; i < (phba->num_cpus); i++) {
  3238. q = &phwi_context->be_cq[i];
  3239. if (q->created)
  3240. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3241. }
  3242. if (phba->msix_enabled)
  3243. eq_num = 1;
  3244. else
  3245. eq_num = 0;
  3246. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  3247. q = &phwi_context->be_eq[i].q;
  3248. if (q->created)
  3249. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  3250. }
  3251. be_mcc_queues_destroy(phba);
  3252. be_cmd_fw_uninit(ctrl);
  3253. }
  3254. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  3255. struct hwi_context_memory *phwi_context)
  3256. {
  3257. struct be_queue_info *q, *cq;
  3258. struct be_ctrl_info *ctrl = &phba->ctrl;
  3259. /* Alloc MCC compl queue */
  3260. cq = &phba->ctrl.mcc_obj.cq;
  3261. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  3262. sizeof(struct be_mcc_compl)))
  3263. goto err;
  3264. /* Ask BE to create MCC compl queue; */
  3265. if (phba->msix_enabled) {
  3266. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  3267. [phba->num_cpus].q, false, true, 0))
  3268. goto mcc_cq_free;
  3269. } else {
  3270. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  3271. false, true, 0))
  3272. goto mcc_cq_free;
  3273. }
  3274. /* Alloc MCC queue */
  3275. q = &phba->ctrl.mcc_obj.q;
  3276. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  3277. goto mcc_cq_destroy;
  3278. /* Ask BE to create MCC queue */
  3279. if (beiscsi_cmd_mccq_create(phba, q, cq))
  3280. goto mcc_q_free;
  3281. return 0;
  3282. mcc_q_free:
  3283. be_queue_free(phba, q);
  3284. mcc_cq_destroy:
  3285. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  3286. mcc_cq_free:
  3287. be_queue_free(phba, cq);
  3288. err:
  3289. return -ENOMEM;
  3290. }
  3291. /**
  3292. * find_num_cpus()- Get the CPU online count
  3293. * @phba: ptr to priv structure
  3294. *
  3295. * CPU count is used for creating EQ.
  3296. **/
  3297. static void find_num_cpus(struct beiscsi_hba *phba)
  3298. {
  3299. int num_cpus = 0;
  3300. num_cpus = num_online_cpus();
  3301. switch (phba->generation) {
  3302. case BE_GEN2:
  3303. case BE_GEN3:
  3304. phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
  3305. BEISCSI_MAX_NUM_CPUS : num_cpus;
  3306. break;
  3307. case BE_GEN4:
  3308. phba->num_cpus = (num_cpus > OC_SKH_MAX_NUM_CPUS) ?
  3309. OC_SKH_MAX_NUM_CPUS : num_cpus;
  3310. break;
  3311. default:
  3312. phba->num_cpus = 1;
  3313. }
  3314. }
  3315. static int hwi_init_port(struct beiscsi_hba *phba)
  3316. {
  3317. struct hwi_controller *phwi_ctrlr;
  3318. struct hwi_context_memory *phwi_context;
  3319. unsigned int def_pdu_ring_sz;
  3320. struct be_ctrl_info *ctrl = &phba->ctrl;
  3321. int status, ulp_num;
  3322. phwi_ctrlr = phba->phwi_ctrlr;
  3323. phwi_context = phwi_ctrlr->phwi_ctxt;
  3324. phwi_context->max_eqd = 0;
  3325. phwi_context->min_eqd = 0;
  3326. phwi_context->cur_eqd = 64;
  3327. be_cmd_fw_initialize(&phba->ctrl);
  3328. status = beiscsi_create_eqs(phba, phwi_context);
  3329. if (status != 0) {
  3330. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3331. "BM_%d : EQ not created\n");
  3332. goto error;
  3333. }
  3334. status = be_mcc_queues_create(phba, phwi_context);
  3335. if (status != 0)
  3336. goto error;
  3337. status = mgmt_check_supported_fw(ctrl, phba);
  3338. if (status != 0) {
  3339. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3340. "BM_%d : Unsupported fw version\n");
  3341. goto error;
  3342. }
  3343. status = beiscsi_create_cqs(phba, phwi_context);
  3344. if (status != 0) {
  3345. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3346. "BM_%d : CQ not created\n");
  3347. goto error;
  3348. }
  3349. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3350. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  3351. def_pdu_ring_sz =
  3352. BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  3353. sizeof(struct phys_addr);
  3354. status = beiscsi_create_def_hdr(phba, phwi_context,
  3355. phwi_ctrlr,
  3356. def_pdu_ring_sz,
  3357. ulp_num);
  3358. if (status != 0) {
  3359. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3360. "BM_%d : Default Header not created for ULP : %d\n",
  3361. ulp_num);
  3362. goto error;
  3363. }
  3364. status = beiscsi_create_def_data(phba, phwi_context,
  3365. phwi_ctrlr,
  3366. def_pdu_ring_sz,
  3367. ulp_num);
  3368. if (status != 0) {
  3369. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3370. "BM_%d : Default Data not created for ULP : %d\n",
  3371. ulp_num);
  3372. goto error;
  3373. }
  3374. }
  3375. }
  3376. status = beiscsi_post_pages(phba);
  3377. if (status != 0) {
  3378. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3379. "BM_%d : Post SGL Pages Failed\n");
  3380. goto error;
  3381. }
  3382. status = beiscsi_post_template_hdr(phba);
  3383. if (status != 0) {
  3384. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3385. "BM_%d : Template HDR Posting for CXN Failed\n");
  3386. }
  3387. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3388. if (status != 0) {
  3389. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3390. "BM_%d : WRB Rings not created\n");
  3391. goto error;
  3392. }
  3393. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3394. uint16_t async_arr_idx = 0;
  3395. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  3396. uint16_t cri = 0;
  3397. struct hwi_async_pdu_context *pasync_ctx;
  3398. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(
  3399. phwi_ctrlr, ulp_num);
  3400. for (cri = 0; cri <
  3401. phba->params.cxns_per_ctrl; cri++) {
  3402. if (ulp_num == BEISCSI_GET_ULP_FROM_CRI
  3403. (phwi_ctrlr, cri))
  3404. pasync_ctx->cid_to_async_cri_map[
  3405. phwi_ctrlr->wrb_context[cri].cid] =
  3406. async_arr_idx++;
  3407. }
  3408. }
  3409. }
  3410. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3411. "BM_%d : hwi_init_port success\n");
  3412. return 0;
  3413. error:
  3414. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3415. "BM_%d : hwi_init_port failed");
  3416. hwi_cleanup(phba);
  3417. return status;
  3418. }
  3419. static int hwi_init_controller(struct beiscsi_hba *phba)
  3420. {
  3421. struct hwi_controller *phwi_ctrlr;
  3422. phwi_ctrlr = phba->phwi_ctrlr;
  3423. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3424. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3425. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3426. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3427. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3428. phwi_ctrlr->phwi_ctxt);
  3429. } else {
  3430. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3431. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3432. "than one element.Failing to load\n");
  3433. return -ENOMEM;
  3434. }
  3435. iscsi_init_global_templates(phba);
  3436. if (beiscsi_init_wrb_handle(phba))
  3437. return -ENOMEM;
  3438. if (hwi_init_async_pdu_ctx(phba)) {
  3439. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3440. "BM_%d : hwi_init_async_pdu_ctx failed\n");
  3441. return -ENOMEM;
  3442. }
  3443. if (hwi_init_port(phba) != 0) {
  3444. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3445. "BM_%d : hwi_init_controller failed\n");
  3446. return -ENOMEM;
  3447. }
  3448. return 0;
  3449. }
  3450. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3451. {
  3452. struct be_mem_descriptor *mem_descr;
  3453. int i, j;
  3454. mem_descr = phba->init_mem;
  3455. i = 0;
  3456. j = 0;
  3457. for (i = 0; i < SE_MEM_MAX; i++) {
  3458. for (j = mem_descr->num_elements; j > 0; j--) {
  3459. pci_free_consistent(phba->pcidev,
  3460. mem_descr->mem_array[j - 1].size,
  3461. mem_descr->mem_array[j - 1].virtual_address,
  3462. (unsigned long)mem_descr->mem_array[j - 1].
  3463. bus_address.u.a64.address);
  3464. }
  3465. kfree(mem_descr->mem_array);
  3466. mem_descr++;
  3467. }
  3468. kfree(phba->init_mem);
  3469. kfree(phba->phwi_ctrlr->wrb_context);
  3470. kfree(phba->phwi_ctrlr);
  3471. }
  3472. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3473. {
  3474. int ret = -ENOMEM;
  3475. ret = beiscsi_get_memory(phba);
  3476. if (ret < 0) {
  3477. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3478. "BM_%d : beiscsi_dev_probe -"
  3479. "Failed in beiscsi_alloc_memory\n");
  3480. return ret;
  3481. }
  3482. ret = hwi_init_controller(phba);
  3483. if (ret)
  3484. goto free_init;
  3485. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3486. "BM_%d : Return success from beiscsi_init_controller");
  3487. return 0;
  3488. free_init:
  3489. beiscsi_free_mem(phba);
  3490. return ret;
  3491. }
  3492. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3493. {
  3494. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3495. struct sgl_handle *psgl_handle;
  3496. struct iscsi_sge *pfrag;
  3497. unsigned int arr_index, i, idx, ulp_num = 0;
  3498. phba->io_sgl_hndl_avbl = 0;
  3499. phba->eh_sgl_hndl_avbl = 0;
  3500. mem_descr_sglh = phba->init_mem;
  3501. mem_descr_sglh += HWI_MEM_SGLH;
  3502. if (1 == mem_descr_sglh->num_elements) {
  3503. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3504. phba->params.ios_per_ctrl,
  3505. GFP_KERNEL);
  3506. if (!phba->io_sgl_hndl_base) {
  3507. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3508. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3509. return -ENOMEM;
  3510. }
  3511. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3512. (phba->params.icds_per_ctrl -
  3513. phba->params.ios_per_ctrl),
  3514. GFP_KERNEL);
  3515. if (!phba->eh_sgl_hndl_base) {
  3516. kfree(phba->io_sgl_hndl_base);
  3517. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3518. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3519. return -ENOMEM;
  3520. }
  3521. } else {
  3522. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3523. "BM_%d : HWI_MEM_SGLH is more than one element."
  3524. "Failing to load\n");
  3525. return -ENOMEM;
  3526. }
  3527. arr_index = 0;
  3528. idx = 0;
  3529. while (idx < mem_descr_sglh->num_elements) {
  3530. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3531. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3532. sizeof(struct sgl_handle)); i++) {
  3533. if (arr_index < phba->params.ios_per_ctrl) {
  3534. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3535. phba->io_sgl_hndl_avbl++;
  3536. arr_index++;
  3537. } else {
  3538. phba->eh_sgl_hndl_base[arr_index -
  3539. phba->params.ios_per_ctrl] =
  3540. psgl_handle;
  3541. arr_index++;
  3542. phba->eh_sgl_hndl_avbl++;
  3543. }
  3544. psgl_handle++;
  3545. }
  3546. idx++;
  3547. }
  3548. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3549. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3550. "phba->eh_sgl_hndl_avbl=%d\n",
  3551. phba->io_sgl_hndl_avbl,
  3552. phba->eh_sgl_hndl_avbl);
  3553. mem_descr_sg = phba->init_mem;
  3554. mem_descr_sg += HWI_MEM_SGE;
  3555. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3556. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3557. mem_descr_sg->num_elements);
  3558. arr_index = 0;
  3559. idx = 0;
  3560. while (idx < mem_descr_sg->num_elements) {
  3561. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3562. for (i = 0;
  3563. i < (mem_descr_sg->mem_array[idx].size) /
  3564. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3565. i++) {
  3566. if (arr_index < phba->params.ios_per_ctrl)
  3567. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3568. else
  3569. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3570. phba->params.ios_per_ctrl];
  3571. psgl_handle->pfrag = pfrag;
  3572. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3573. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3574. pfrag += phba->params.num_sge_per_io;
  3575. psgl_handle->sgl_index =
  3576. phba->fw_config.iscsi_icd_start[ulp_num] +
  3577. arr_index++;
  3578. }
  3579. idx++;
  3580. }
  3581. phba->io_sgl_free_index = 0;
  3582. phba->io_sgl_alloc_index = 0;
  3583. phba->eh_sgl_free_index = 0;
  3584. phba->eh_sgl_alloc_index = 0;
  3585. return 0;
  3586. }
  3587. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3588. {
  3589. int i;
  3590. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3591. GFP_KERNEL);
  3592. if (!phba->cid_array) {
  3593. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3594. "BM_%d : Failed to allocate memory in "
  3595. "hba_setup_cid_tbls\n");
  3596. return -ENOMEM;
  3597. }
  3598. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3599. phba->params.cxns_per_ctrl, GFP_KERNEL);
  3600. if (!phba->ep_array) {
  3601. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3602. "BM_%d : Failed to allocate memory in "
  3603. "hba_setup_cid_tbls\n");
  3604. kfree(phba->cid_array);
  3605. phba->cid_array = NULL;
  3606. return -ENOMEM;
  3607. }
  3608. phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
  3609. phba->params.cxns_per_ctrl, GFP_KERNEL);
  3610. if (!phba->conn_table) {
  3611. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3612. "BM_%d : Failed to allocate memory in"
  3613. "hba_setup_cid_tbls\n");
  3614. kfree(phba->cid_array);
  3615. kfree(phba->ep_array);
  3616. phba->cid_array = NULL;
  3617. phba->ep_array = NULL;
  3618. return -ENOMEM;
  3619. }
  3620. for (i = 0; i < phba->params.cxns_per_ctrl; i++)
  3621. phba->cid_array[i] = phba->phwi_ctrlr->wrb_context[i].cid;
  3622. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3623. return 0;
  3624. }
  3625. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3626. {
  3627. struct be_ctrl_info *ctrl = &phba->ctrl;
  3628. struct hwi_controller *phwi_ctrlr;
  3629. struct hwi_context_memory *phwi_context;
  3630. struct be_queue_info *eq;
  3631. u8 __iomem *addr;
  3632. u32 reg, i;
  3633. u32 enabled;
  3634. phwi_ctrlr = phba->phwi_ctrlr;
  3635. phwi_context = phwi_ctrlr->phwi_ctxt;
  3636. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3637. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3638. reg = ioread32(addr);
  3639. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3640. if (!enabled) {
  3641. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3642. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3643. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3644. iowrite32(reg, addr);
  3645. }
  3646. if (!phba->msix_enabled) {
  3647. eq = &phwi_context->be_eq[0].q;
  3648. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3649. "BM_%d : eq->id=%d\n", eq->id);
  3650. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3651. } else {
  3652. for (i = 0; i <= phba->num_cpus; i++) {
  3653. eq = &phwi_context->be_eq[i].q;
  3654. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3655. "BM_%d : eq->id=%d\n", eq->id);
  3656. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3657. }
  3658. }
  3659. }
  3660. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3661. {
  3662. struct be_ctrl_info *ctrl = &phba->ctrl;
  3663. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3664. u32 reg = ioread32(addr);
  3665. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3666. if (enabled) {
  3667. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3668. iowrite32(reg, addr);
  3669. } else
  3670. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3671. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3672. }
  3673. /**
  3674. * beiscsi_get_boot_info()- Get the boot session info
  3675. * @phba: The device priv structure instance
  3676. *
  3677. * Get the boot target info and store in driver priv structure
  3678. *
  3679. * return values
  3680. * Success: 0
  3681. * Failure: Non-Zero Value
  3682. **/
  3683. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3684. {
  3685. struct be_cmd_get_session_resp *session_resp;
  3686. struct be_dma_mem nonemb_cmd;
  3687. unsigned int tag;
  3688. unsigned int s_handle;
  3689. int ret = -ENOMEM;
  3690. /* Get the session handle of the boot target */
  3691. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3692. if (ret) {
  3693. beiscsi_log(phba, KERN_ERR,
  3694. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3695. "BM_%d : No boot session\n");
  3696. return ret;
  3697. }
  3698. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3699. sizeof(*session_resp),
  3700. &nonemb_cmd.dma);
  3701. if (nonemb_cmd.va == NULL) {
  3702. beiscsi_log(phba, KERN_ERR,
  3703. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3704. "BM_%d : Failed to allocate memory for"
  3705. "beiscsi_get_session_info\n");
  3706. return -ENOMEM;
  3707. }
  3708. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3709. tag = mgmt_get_session_info(phba, s_handle,
  3710. &nonemb_cmd);
  3711. if (!tag) {
  3712. beiscsi_log(phba, KERN_ERR,
  3713. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3714. "BM_%d : beiscsi_get_session_info"
  3715. " Failed\n");
  3716. goto boot_freemem;
  3717. }
  3718. ret = beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  3719. if (ret) {
  3720. beiscsi_log(phba, KERN_ERR,
  3721. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3722. "BM_%d : beiscsi_get_session_info Failed");
  3723. goto boot_freemem;
  3724. }
  3725. session_resp = nonemb_cmd.va ;
  3726. memcpy(&phba->boot_sess, &session_resp->session_info,
  3727. sizeof(struct mgmt_session_info));
  3728. ret = 0;
  3729. boot_freemem:
  3730. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3731. nonemb_cmd.va, nonemb_cmd.dma);
  3732. return ret;
  3733. }
  3734. static void beiscsi_boot_release(void *data)
  3735. {
  3736. struct beiscsi_hba *phba = data;
  3737. scsi_host_put(phba->shost);
  3738. }
  3739. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3740. {
  3741. struct iscsi_boot_kobj *boot_kobj;
  3742. /* get boot info using mgmt cmd */
  3743. if (beiscsi_get_boot_info(phba))
  3744. /* Try to see if we can carry on without this */
  3745. return 0;
  3746. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3747. if (!phba->boot_kset)
  3748. return -ENOMEM;
  3749. /* get a ref because the show function will ref the phba */
  3750. if (!scsi_host_get(phba->shost))
  3751. goto free_kset;
  3752. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3753. beiscsi_show_boot_tgt_info,
  3754. beiscsi_tgt_get_attr_visibility,
  3755. beiscsi_boot_release);
  3756. if (!boot_kobj)
  3757. goto put_shost;
  3758. if (!scsi_host_get(phba->shost))
  3759. goto free_kset;
  3760. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3761. beiscsi_show_boot_ini_info,
  3762. beiscsi_ini_get_attr_visibility,
  3763. beiscsi_boot_release);
  3764. if (!boot_kobj)
  3765. goto put_shost;
  3766. if (!scsi_host_get(phba->shost))
  3767. goto free_kset;
  3768. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3769. beiscsi_show_boot_eth_info,
  3770. beiscsi_eth_get_attr_visibility,
  3771. beiscsi_boot_release);
  3772. if (!boot_kobj)
  3773. goto put_shost;
  3774. return 0;
  3775. put_shost:
  3776. scsi_host_put(phba->shost);
  3777. free_kset:
  3778. iscsi_boot_destroy_kset(phba->boot_kset);
  3779. return -ENOMEM;
  3780. }
  3781. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3782. {
  3783. int ret;
  3784. ret = beiscsi_init_controller(phba);
  3785. if (ret < 0) {
  3786. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3787. "BM_%d : beiscsi_dev_probe - Failed in"
  3788. "beiscsi_init_controller\n");
  3789. return ret;
  3790. }
  3791. ret = beiscsi_init_sgl_handle(phba);
  3792. if (ret < 0) {
  3793. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3794. "BM_%d : beiscsi_dev_probe - Failed in"
  3795. "beiscsi_init_sgl_handle\n");
  3796. goto do_cleanup_ctrlr;
  3797. }
  3798. if (hba_setup_cid_tbls(phba)) {
  3799. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3800. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3801. kfree(phba->io_sgl_hndl_base);
  3802. kfree(phba->eh_sgl_hndl_base);
  3803. goto do_cleanup_ctrlr;
  3804. }
  3805. return ret;
  3806. do_cleanup_ctrlr:
  3807. hwi_cleanup(phba);
  3808. return ret;
  3809. }
  3810. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3811. {
  3812. struct hwi_controller *phwi_ctrlr;
  3813. struct hwi_context_memory *phwi_context;
  3814. struct be_queue_info *eq;
  3815. struct be_eq_entry *eqe = NULL;
  3816. int i, eq_msix;
  3817. unsigned int num_processed;
  3818. phwi_ctrlr = phba->phwi_ctrlr;
  3819. phwi_context = phwi_ctrlr->phwi_ctxt;
  3820. if (phba->msix_enabled)
  3821. eq_msix = 1;
  3822. else
  3823. eq_msix = 0;
  3824. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3825. eq = &phwi_context->be_eq[i].q;
  3826. eqe = queue_tail_node(eq);
  3827. num_processed = 0;
  3828. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3829. & EQE_VALID_MASK) {
  3830. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3831. queue_tail_inc(eq);
  3832. eqe = queue_tail_node(eq);
  3833. num_processed++;
  3834. }
  3835. if (num_processed)
  3836. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3837. }
  3838. }
  3839. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3840. {
  3841. int mgmt_status;
  3842. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3843. if (mgmt_status)
  3844. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3845. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3846. hwi_purge_eq(phba);
  3847. hwi_cleanup(phba);
  3848. kfree(phba->io_sgl_hndl_base);
  3849. kfree(phba->eh_sgl_hndl_base);
  3850. kfree(phba->cid_array);
  3851. kfree(phba->ep_array);
  3852. kfree(phba->conn_table);
  3853. }
  3854. /**
  3855. * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
  3856. * @beiscsi_conn: ptr to the conn to be cleaned up
  3857. * @task: ptr to iscsi_task resource to be freed.
  3858. *
  3859. * Free driver mgmt resources binded to CXN.
  3860. **/
  3861. void
  3862. beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
  3863. struct iscsi_task *task)
  3864. {
  3865. struct beiscsi_io_task *io_task;
  3866. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3867. struct hwi_wrb_context *pwrb_context;
  3868. struct hwi_controller *phwi_ctrlr;
  3869. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  3870. beiscsi_conn->beiscsi_conn_cid);
  3871. phwi_ctrlr = phba->phwi_ctrlr;
  3872. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3873. io_task = task->dd_data;
  3874. if (io_task->pwrb_handle) {
  3875. memset(io_task->pwrb_handle->pwrb, 0,
  3876. sizeof(struct iscsi_wrb));
  3877. free_wrb_handle(phba, pwrb_context,
  3878. io_task->pwrb_handle);
  3879. io_task->pwrb_handle = NULL;
  3880. }
  3881. if (io_task->psgl_handle) {
  3882. spin_lock_bh(&phba->mgmt_sgl_lock);
  3883. free_mgmt_sgl_handle(phba,
  3884. io_task->psgl_handle);
  3885. io_task->psgl_handle = NULL;
  3886. spin_unlock_bh(&phba->mgmt_sgl_lock);
  3887. }
  3888. if (io_task->mtask_addr)
  3889. pci_unmap_single(phba->pcidev,
  3890. io_task->mtask_addr,
  3891. io_task->mtask_data_count,
  3892. PCI_DMA_TODEVICE);
  3893. }
  3894. /**
  3895. * beiscsi_cleanup_task()- Free driver resources of the task
  3896. * @task: ptr to the iscsi task
  3897. *
  3898. **/
  3899. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3900. {
  3901. struct beiscsi_io_task *io_task = task->dd_data;
  3902. struct iscsi_conn *conn = task->conn;
  3903. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3904. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3905. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3906. struct hwi_wrb_context *pwrb_context;
  3907. struct hwi_controller *phwi_ctrlr;
  3908. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  3909. beiscsi_conn->beiscsi_conn_cid);
  3910. phwi_ctrlr = phba->phwi_ctrlr;
  3911. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3912. if (io_task->cmd_bhs) {
  3913. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3914. io_task->bhs_pa.u.a64.address);
  3915. io_task->cmd_bhs = NULL;
  3916. }
  3917. if (task->sc) {
  3918. if (io_task->pwrb_handle) {
  3919. free_wrb_handle(phba, pwrb_context,
  3920. io_task->pwrb_handle);
  3921. io_task->pwrb_handle = NULL;
  3922. }
  3923. if (io_task->psgl_handle) {
  3924. spin_lock(&phba->io_sgl_lock);
  3925. free_io_sgl_handle(phba, io_task->psgl_handle);
  3926. spin_unlock(&phba->io_sgl_lock);
  3927. io_task->psgl_handle = NULL;
  3928. }
  3929. } else {
  3930. if (!beiscsi_conn->login_in_progress)
  3931. beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
  3932. }
  3933. }
  3934. void
  3935. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3936. struct beiscsi_offload_params *params)
  3937. {
  3938. struct wrb_handle *pwrb_handle;
  3939. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3940. struct iscsi_task *task = beiscsi_conn->task;
  3941. struct iscsi_session *session = task->conn->session;
  3942. u32 doorbell = 0;
  3943. /*
  3944. * We can always use 0 here because it is reserved by libiscsi for
  3945. * login/startup related tasks.
  3946. */
  3947. beiscsi_conn->login_in_progress = 0;
  3948. spin_lock_bh(&session->lock);
  3949. beiscsi_cleanup_task(task);
  3950. spin_unlock_bh(&session->lock);
  3951. pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid);
  3952. /* Check for the adapter family */
  3953. if (is_chip_be2_be3r(phba))
  3954. beiscsi_offload_cxn_v0(params, pwrb_handle,
  3955. phba->init_mem);
  3956. else
  3957. beiscsi_offload_cxn_v2(params, pwrb_handle);
  3958. be_dws_le_to_cpu(pwrb_handle->pwrb,
  3959. sizeof(struct iscsi_target_context_update_wrb));
  3960. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3961. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3962. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3963. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3964. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3965. }
  3966. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3967. int *index, int *age)
  3968. {
  3969. *index = (int)itt;
  3970. if (age)
  3971. *age = conn->session->age;
  3972. }
  3973. /**
  3974. * beiscsi_alloc_pdu - allocates pdu and related resources
  3975. * @task: libiscsi task
  3976. * @opcode: opcode of pdu for task
  3977. *
  3978. * This is called with the session lock held. It will allocate
  3979. * the wrb and sgl if needed for the command. And it will prep
  3980. * the pdu's itt. beiscsi_parse_pdu will later translate
  3981. * the pdu itt to the libiscsi task itt.
  3982. */
  3983. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3984. {
  3985. struct beiscsi_io_task *io_task = task->dd_data;
  3986. struct iscsi_conn *conn = task->conn;
  3987. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3988. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3989. struct hwi_wrb_context *pwrb_context;
  3990. struct hwi_controller *phwi_ctrlr;
  3991. itt_t itt;
  3992. uint16_t cri_index = 0;
  3993. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3994. dma_addr_t paddr;
  3995. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3996. GFP_ATOMIC, &paddr);
  3997. if (!io_task->cmd_bhs)
  3998. return -ENOMEM;
  3999. io_task->bhs_pa.u.a64.address = paddr;
  4000. io_task->libiscsi_itt = (itt_t)task->itt;
  4001. io_task->conn = beiscsi_conn;
  4002. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  4003. task->hdr_max = sizeof(struct be_cmd_bhs);
  4004. io_task->psgl_handle = NULL;
  4005. io_task->pwrb_handle = NULL;
  4006. if (task->sc) {
  4007. spin_lock(&phba->io_sgl_lock);
  4008. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  4009. spin_unlock(&phba->io_sgl_lock);
  4010. if (!io_task->psgl_handle) {
  4011. beiscsi_log(phba, KERN_ERR,
  4012. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  4013. "BM_%d : Alloc of IO_SGL_ICD Failed"
  4014. "for the CID : %d\n",
  4015. beiscsi_conn->beiscsi_conn_cid);
  4016. goto free_hndls;
  4017. }
  4018. io_task->pwrb_handle = alloc_wrb_handle(phba,
  4019. beiscsi_conn->beiscsi_conn_cid);
  4020. if (!io_task->pwrb_handle) {
  4021. beiscsi_log(phba, KERN_ERR,
  4022. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  4023. "BM_%d : Alloc of WRB_HANDLE Failed"
  4024. "for the CID : %d\n",
  4025. beiscsi_conn->beiscsi_conn_cid);
  4026. goto free_io_hndls;
  4027. }
  4028. } else {
  4029. io_task->scsi_cmnd = NULL;
  4030. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  4031. beiscsi_conn->task = task;
  4032. if (!beiscsi_conn->login_in_progress) {
  4033. spin_lock(&phba->mgmt_sgl_lock);
  4034. io_task->psgl_handle = (struct sgl_handle *)
  4035. alloc_mgmt_sgl_handle(phba);
  4036. spin_unlock(&phba->mgmt_sgl_lock);
  4037. if (!io_task->psgl_handle) {
  4038. beiscsi_log(phba, KERN_ERR,
  4039. BEISCSI_LOG_IO |
  4040. BEISCSI_LOG_CONFIG,
  4041. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  4042. "for the CID : %d\n",
  4043. beiscsi_conn->
  4044. beiscsi_conn_cid);
  4045. goto free_hndls;
  4046. }
  4047. beiscsi_conn->login_in_progress = 1;
  4048. beiscsi_conn->plogin_sgl_handle =
  4049. io_task->psgl_handle;
  4050. io_task->pwrb_handle =
  4051. alloc_wrb_handle(phba,
  4052. beiscsi_conn->beiscsi_conn_cid);
  4053. if (!io_task->pwrb_handle) {
  4054. beiscsi_log(phba, KERN_ERR,
  4055. BEISCSI_LOG_IO |
  4056. BEISCSI_LOG_CONFIG,
  4057. "BM_%d : Alloc of WRB_HANDLE Failed"
  4058. "for the CID : %d\n",
  4059. beiscsi_conn->
  4060. beiscsi_conn_cid);
  4061. goto free_mgmt_hndls;
  4062. }
  4063. beiscsi_conn->plogin_wrb_handle =
  4064. io_task->pwrb_handle;
  4065. } else {
  4066. io_task->psgl_handle =
  4067. beiscsi_conn->plogin_sgl_handle;
  4068. io_task->pwrb_handle =
  4069. beiscsi_conn->plogin_wrb_handle;
  4070. }
  4071. } else {
  4072. spin_lock(&phba->mgmt_sgl_lock);
  4073. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  4074. spin_unlock(&phba->mgmt_sgl_lock);
  4075. if (!io_task->psgl_handle) {
  4076. beiscsi_log(phba, KERN_ERR,
  4077. BEISCSI_LOG_IO |
  4078. BEISCSI_LOG_CONFIG,
  4079. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  4080. "for the CID : %d\n",
  4081. beiscsi_conn->
  4082. beiscsi_conn_cid);
  4083. goto free_hndls;
  4084. }
  4085. io_task->pwrb_handle =
  4086. alloc_wrb_handle(phba,
  4087. beiscsi_conn->beiscsi_conn_cid);
  4088. if (!io_task->pwrb_handle) {
  4089. beiscsi_log(phba, KERN_ERR,
  4090. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  4091. "BM_%d : Alloc of WRB_HANDLE Failed"
  4092. "for the CID : %d\n",
  4093. beiscsi_conn->beiscsi_conn_cid);
  4094. goto free_mgmt_hndls;
  4095. }
  4096. }
  4097. }
  4098. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  4099. wrb_index << 16) | (unsigned int)
  4100. (io_task->psgl_handle->sgl_index));
  4101. io_task->pwrb_handle->pio_handle = task;
  4102. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  4103. return 0;
  4104. free_io_hndls:
  4105. spin_lock(&phba->io_sgl_lock);
  4106. free_io_sgl_handle(phba, io_task->psgl_handle);
  4107. spin_unlock(&phba->io_sgl_lock);
  4108. goto free_hndls;
  4109. free_mgmt_hndls:
  4110. spin_lock(&phba->mgmt_sgl_lock);
  4111. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  4112. io_task->psgl_handle = NULL;
  4113. spin_unlock(&phba->mgmt_sgl_lock);
  4114. free_hndls:
  4115. phwi_ctrlr = phba->phwi_ctrlr;
  4116. cri_index = BE_GET_CRI_FROM_CID(
  4117. beiscsi_conn->beiscsi_conn_cid);
  4118. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  4119. if (io_task->pwrb_handle)
  4120. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  4121. io_task->pwrb_handle = NULL;
  4122. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  4123. io_task->bhs_pa.u.a64.address);
  4124. io_task->cmd_bhs = NULL;
  4125. return -ENOMEM;
  4126. }
  4127. int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
  4128. unsigned int num_sg, unsigned int xferlen,
  4129. unsigned int writedir)
  4130. {
  4131. struct beiscsi_io_task *io_task = task->dd_data;
  4132. struct iscsi_conn *conn = task->conn;
  4133. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4134. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4135. struct iscsi_wrb *pwrb = NULL;
  4136. unsigned int doorbell = 0;
  4137. pwrb = io_task->pwrb_handle->pwrb;
  4138. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  4139. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  4140. if (writedir) {
  4141. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  4142. INI_WR_CMD);
  4143. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
  4144. } else {
  4145. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  4146. INI_RD_CMD);
  4147. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
  4148. }
  4149. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
  4150. type, pwrb);
  4151. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
  4152. cpu_to_be16(*(unsigned short *)
  4153. &io_task->cmd_bhs->iscsi_hdr.lun));
  4154. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
  4155. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  4156. io_task->pwrb_handle->wrb_index);
  4157. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  4158. be32_to_cpu(task->cmdsn));
  4159. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  4160. io_task->psgl_handle->sgl_index);
  4161. hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
  4162. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  4163. io_task->pwrb_handle->nxt_wrb_index);
  4164. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  4165. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  4166. doorbell |= (io_task->pwrb_handle->wrb_index &
  4167. DB_DEF_PDU_WRB_INDEX_MASK) <<
  4168. DB_DEF_PDU_WRB_INDEX_SHIFT;
  4169. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4170. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4171. return 0;
  4172. }
  4173. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  4174. unsigned int num_sg, unsigned int xferlen,
  4175. unsigned int writedir)
  4176. {
  4177. struct beiscsi_io_task *io_task = task->dd_data;
  4178. struct iscsi_conn *conn = task->conn;
  4179. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4180. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4181. struct iscsi_wrb *pwrb = NULL;
  4182. unsigned int doorbell = 0;
  4183. pwrb = io_task->pwrb_handle->pwrb;
  4184. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  4185. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  4186. if (writedir) {
  4187. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  4188. INI_WR_CMD);
  4189. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  4190. } else {
  4191. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  4192. INI_RD_CMD);
  4193. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  4194. }
  4195. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
  4196. type, pwrb);
  4197. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  4198. cpu_to_be16(*(unsigned short *)
  4199. &io_task->cmd_bhs->iscsi_hdr.lun));
  4200. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  4201. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4202. io_task->pwrb_handle->wrb_index);
  4203. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4204. be32_to_cpu(task->cmdsn));
  4205. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4206. io_task->psgl_handle->sgl_index);
  4207. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  4208. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4209. io_task->pwrb_handle->nxt_wrb_index);
  4210. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  4211. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  4212. doorbell |= (io_task->pwrb_handle->wrb_index &
  4213. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4214. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4215. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4216. return 0;
  4217. }
  4218. static int beiscsi_mtask(struct iscsi_task *task)
  4219. {
  4220. struct beiscsi_io_task *io_task = task->dd_data;
  4221. struct iscsi_conn *conn = task->conn;
  4222. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4223. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4224. struct iscsi_wrb *pwrb = NULL;
  4225. unsigned int doorbell = 0;
  4226. unsigned int cid;
  4227. unsigned int pwrb_typeoffset = 0;
  4228. cid = beiscsi_conn->beiscsi_conn_cid;
  4229. pwrb = io_task->pwrb_handle->pwrb;
  4230. memset(pwrb, 0, sizeof(*pwrb));
  4231. if (is_chip_be2_be3r(phba)) {
  4232. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4233. be32_to_cpu(task->cmdsn));
  4234. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4235. io_task->pwrb_handle->wrb_index);
  4236. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4237. io_task->psgl_handle->sgl_index);
  4238. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  4239. task->data_count);
  4240. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4241. io_task->pwrb_handle->nxt_wrb_index);
  4242. pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
  4243. } else {
  4244. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  4245. be32_to_cpu(task->cmdsn));
  4246. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  4247. io_task->pwrb_handle->wrb_index);
  4248. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  4249. io_task->psgl_handle->sgl_index);
  4250. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
  4251. task->data_count);
  4252. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  4253. io_task->pwrb_handle->nxt_wrb_index);
  4254. pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
  4255. }
  4256. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  4257. case ISCSI_OP_LOGIN:
  4258. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  4259. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4260. hwi_write_buffer(pwrb, task);
  4261. break;
  4262. case ISCSI_OP_NOOP_OUT:
  4263. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  4264. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4265. if (is_chip_be2_be3r(phba))
  4266. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4267. dmsg, pwrb, 1);
  4268. else
  4269. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4270. dmsg, pwrb, 1);
  4271. } else {
  4272. ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
  4273. if (is_chip_be2_be3r(phba))
  4274. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4275. dmsg, pwrb, 0);
  4276. else
  4277. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4278. dmsg, pwrb, 0);
  4279. }
  4280. hwi_write_buffer(pwrb, task);
  4281. break;
  4282. case ISCSI_OP_TEXT:
  4283. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4284. hwi_write_buffer(pwrb, task);
  4285. break;
  4286. case ISCSI_OP_SCSI_TMFUNC:
  4287. ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
  4288. hwi_write_buffer(pwrb, task);
  4289. break;
  4290. case ISCSI_OP_LOGOUT:
  4291. ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
  4292. hwi_write_buffer(pwrb, task);
  4293. break;
  4294. default:
  4295. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4296. "BM_%d : opcode =%d Not supported\n",
  4297. task->hdr->opcode & ISCSI_OPCODE_MASK);
  4298. return -EINVAL;
  4299. }
  4300. /* Set the task type */
  4301. io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
  4302. AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
  4303. AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
  4304. doorbell |= cid & DB_WRB_POST_CID_MASK;
  4305. doorbell |= (io_task->pwrb_handle->wrb_index &
  4306. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4307. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4308. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4309. return 0;
  4310. }
  4311. static int beiscsi_task_xmit(struct iscsi_task *task)
  4312. {
  4313. struct beiscsi_io_task *io_task = task->dd_data;
  4314. struct scsi_cmnd *sc = task->sc;
  4315. struct beiscsi_hba *phba = NULL;
  4316. struct scatterlist *sg;
  4317. int num_sg;
  4318. unsigned int writedir = 0, xferlen = 0;
  4319. phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
  4320. if (!sc)
  4321. return beiscsi_mtask(task);
  4322. io_task->scsi_cmnd = sc;
  4323. num_sg = scsi_dma_map(sc);
  4324. if (num_sg < 0) {
  4325. struct iscsi_conn *conn = task->conn;
  4326. struct beiscsi_hba *phba = NULL;
  4327. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  4328. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  4329. "BM_%d : scsi_dma_map Failed\n");
  4330. return num_sg;
  4331. }
  4332. xferlen = scsi_bufflen(sc);
  4333. sg = scsi_sglist(sc);
  4334. if (sc->sc_data_direction == DMA_TO_DEVICE)
  4335. writedir = 1;
  4336. else
  4337. writedir = 0;
  4338. return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
  4339. }
  4340. /**
  4341. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  4342. * @job: job to handle
  4343. */
  4344. static int beiscsi_bsg_request(struct bsg_job *job)
  4345. {
  4346. struct Scsi_Host *shost;
  4347. struct beiscsi_hba *phba;
  4348. struct iscsi_bsg_request *bsg_req = job->request;
  4349. int rc = -EINVAL;
  4350. unsigned int tag;
  4351. struct be_dma_mem nonemb_cmd;
  4352. struct be_cmd_resp_hdr *resp;
  4353. struct iscsi_bsg_reply *bsg_reply = job->reply;
  4354. unsigned short status, extd_status;
  4355. shost = iscsi_job_to_shost(job);
  4356. phba = iscsi_host_priv(shost);
  4357. switch (bsg_req->msgcode) {
  4358. case ISCSI_BSG_HST_VENDOR:
  4359. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  4360. job->request_payload.payload_len,
  4361. &nonemb_cmd.dma);
  4362. if (nonemb_cmd.va == NULL) {
  4363. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4364. "BM_%d : Failed to allocate memory for "
  4365. "beiscsi_bsg_request\n");
  4366. return -ENOMEM;
  4367. }
  4368. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  4369. &nonemb_cmd);
  4370. if (!tag) {
  4371. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4372. "BM_%d : MBX Tag Allocation Failed\n");
  4373. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4374. nonemb_cmd.va, nonemb_cmd.dma);
  4375. return -EAGAIN;
  4376. }
  4377. rc = wait_event_interruptible_timeout(
  4378. phba->ctrl.mcc_wait[tag],
  4379. phba->ctrl.mcc_numtag[tag],
  4380. msecs_to_jiffies(
  4381. BEISCSI_HOST_MBX_TIMEOUT));
  4382. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  4383. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  4384. free_mcc_tag(&phba->ctrl, tag);
  4385. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  4386. sg_copy_from_buffer(job->reply_payload.sg_list,
  4387. job->reply_payload.sg_cnt,
  4388. nonemb_cmd.va, (resp->response_length
  4389. + sizeof(*resp)));
  4390. bsg_reply->reply_payload_rcv_len = resp->response_length;
  4391. bsg_reply->result = status;
  4392. bsg_job_done(job, bsg_reply->result,
  4393. bsg_reply->reply_payload_rcv_len);
  4394. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4395. nonemb_cmd.va, nonemb_cmd.dma);
  4396. if (status || extd_status) {
  4397. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4398. "BM_%d : MBX Cmd Failed"
  4399. " status = %d extd_status = %d\n",
  4400. status, extd_status);
  4401. return -EIO;
  4402. } else {
  4403. rc = 0;
  4404. }
  4405. break;
  4406. default:
  4407. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4408. "BM_%d : Unsupported bsg command: 0x%x\n",
  4409. bsg_req->msgcode);
  4410. break;
  4411. }
  4412. return rc;
  4413. }
  4414. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  4415. {
  4416. /* Set the logging parameter */
  4417. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4418. }
  4419. /*
  4420. * beiscsi_quiesce()- Cleanup Driver resources
  4421. * @phba: Instance Priv structure
  4422. *
  4423. * Free the OS and HW resources held by the driver
  4424. **/
  4425. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4426. {
  4427. struct hwi_controller *phwi_ctrlr;
  4428. struct hwi_context_memory *phwi_context;
  4429. struct be_eq_obj *pbe_eq;
  4430. unsigned int i, msix_vec;
  4431. phwi_ctrlr = phba->phwi_ctrlr;
  4432. phwi_context = phwi_ctrlr->phwi_ctxt;
  4433. hwi_disable_intr(phba);
  4434. if (phba->msix_enabled) {
  4435. for (i = 0; i <= phba->num_cpus; i++) {
  4436. msix_vec = phba->msix_entries[i].vector;
  4437. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4438. kfree(phba->msi_name[i]);
  4439. }
  4440. } else
  4441. if (phba->pcidev->irq)
  4442. free_irq(phba->pcidev->irq, phba);
  4443. pci_disable_msix(phba->pcidev);
  4444. destroy_workqueue(phba->wq);
  4445. if (blk_iopoll_enabled)
  4446. for (i = 0; i < phba->num_cpus; i++) {
  4447. pbe_eq = &phwi_context->be_eq[i];
  4448. blk_iopoll_disable(&pbe_eq->iopoll);
  4449. }
  4450. beiscsi_clean_port(phba);
  4451. beiscsi_free_mem(phba);
  4452. beiscsi_unmap_pci_function(phba);
  4453. pci_free_consistent(phba->pcidev,
  4454. phba->ctrl.mbox_mem_alloced.size,
  4455. phba->ctrl.mbox_mem_alloced.va,
  4456. phba->ctrl.mbox_mem_alloced.dma);
  4457. cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
  4458. }
  4459. static void beiscsi_remove(struct pci_dev *pcidev)
  4460. {
  4461. struct beiscsi_hba *phba = NULL;
  4462. phba = pci_get_drvdata(pcidev);
  4463. if (!phba) {
  4464. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4465. return;
  4466. }
  4467. beiscsi_destroy_def_ifaces(phba);
  4468. beiscsi_quiesce(phba);
  4469. iscsi_boot_destroy_kset(phba->boot_kset);
  4470. iscsi_host_remove(phba->shost);
  4471. pci_dev_put(phba->pcidev);
  4472. iscsi_host_free(phba->shost);
  4473. pci_disable_device(pcidev);
  4474. }
  4475. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4476. {
  4477. struct beiscsi_hba *phba = NULL;
  4478. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4479. if (!phba) {
  4480. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4481. return;
  4482. }
  4483. beiscsi_quiesce(phba);
  4484. pci_disable_device(pcidev);
  4485. }
  4486. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4487. {
  4488. int i, status;
  4489. for (i = 0; i <= phba->num_cpus; i++)
  4490. phba->msix_entries[i].entry = i;
  4491. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4492. (phba->num_cpus + 1));
  4493. if (!status)
  4494. phba->msix_enabled = true;
  4495. return;
  4496. }
  4497. /*
  4498. * beiscsi_hw_health_check()- Check adapter health
  4499. * @work: work item to check HW health
  4500. *
  4501. * Check if adapter in an unrecoverable state or not.
  4502. **/
  4503. static void
  4504. beiscsi_hw_health_check(struct work_struct *work)
  4505. {
  4506. struct beiscsi_hba *phba =
  4507. container_of(work, struct beiscsi_hba,
  4508. beiscsi_hw_check_task.work);
  4509. beiscsi_ue_detect(phba);
  4510. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4511. msecs_to_jiffies(1000));
  4512. }
  4513. static int beiscsi_dev_probe(struct pci_dev *pcidev,
  4514. const struct pci_device_id *id)
  4515. {
  4516. struct beiscsi_hba *phba = NULL;
  4517. struct hwi_controller *phwi_ctrlr;
  4518. struct hwi_context_memory *phwi_context;
  4519. struct be_eq_obj *pbe_eq;
  4520. int ret, i;
  4521. ret = beiscsi_enable_pci(pcidev);
  4522. if (ret < 0) {
  4523. dev_err(&pcidev->dev,
  4524. "beiscsi_dev_probe - Failed to enable pci device\n");
  4525. return ret;
  4526. }
  4527. phba = beiscsi_hba_alloc(pcidev);
  4528. if (!phba) {
  4529. dev_err(&pcidev->dev,
  4530. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4531. goto disable_pci;
  4532. }
  4533. /* Initialize Driver configuration Paramters */
  4534. beiscsi_hba_attrs_init(phba);
  4535. phba->fw_timeout = false;
  4536. phba->mac_addr_set = false;
  4537. switch (pcidev->device) {
  4538. case BE_DEVICE_ID1:
  4539. case OC_DEVICE_ID1:
  4540. case OC_DEVICE_ID2:
  4541. phba->generation = BE_GEN2;
  4542. phba->iotask_fn = beiscsi_iotask;
  4543. break;
  4544. case BE_DEVICE_ID2:
  4545. case OC_DEVICE_ID3:
  4546. phba->generation = BE_GEN3;
  4547. phba->iotask_fn = beiscsi_iotask;
  4548. break;
  4549. case OC_SKH_ID1:
  4550. phba->generation = BE_GEN4;
  4551. phba->iotask_fn = beiscsi_iotask_v2;
  4552. break;
  4553. default:
  4554. phba->generation = 0;
  4555. }
  4556. if (enable_msix)
  4557. find_num_cpus(phba);
  4558. else
  4559. phba->num_cpus = 1;
  4560. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4561. "BM_%d : num_cpus = %d\n",
  4562. phba->num_cpus);
  4563. if (enable_msix) {
  4564. beiscsi_msix_enable(phba);
  4565. if (!phba->msix_enabled)
  4566. phba->num_cpus = 1;
  4567. }
  4568. ret = be_ctrl_init(phba, pcidev);
  4569. if (ret) {
  4570. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4571. "BM_%d : beiscsi_dev_probe-"
  4572. "Failed in be_ctrl_init\n");
  4573. goto hba_free;
  4574. }
  4575. ret = beiscsi_cmd_reset_function(phba);
  4576. if (ret) {
  4577. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4578. "BM_%d : Reset Failed\n");
  4579. goto hba_free;
  4580. }
  4581. ret = be_chk_reset_complete(phba);
  4582. if (ret) {
  4583. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4584. "BM_%d : Failed to get out of reset.\n");
  4585. goto hba_free;
  4586. }
  4587. spin_lock_init(&phba->io_sgl_lock);
  4588. spin_lock_init(&phba->mgmt_sgl_lock);
  4589. spin_lock_init(&phba->isr_lock);
  4590. spin_lock_init(&phba->async_pdu_lock);
  4591. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4592. if (ret != 0) {
  4593. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4594. "BM_%d : Error getting fw config\n");
  4595. goto free_port;
  4596. }
  4597. phba->shost->max_id = phba->params.cxns_per_ctrl;
  4598. beiscsi_get_params(phba);
  4599. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4600. ret = beiscsi_init_port(phba);
  4601. if (ret < 0) {
  4602. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4603. "BM_%d : beiscsi_dev_probe-"
  4604. "Failed in beiscsi_init_port\n");
  4605. goto free_port;
  4606. }
  4607. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4608. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4609. phba->ctrl.mcc_tag[i] = i + 1;
  4610. phba->ctrl.mcc_numtag[i + 1] = 0;
  4611. phba->ctrl.mcc_tag_available++;
  4612. }
  4613. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4614. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4615. phba->shost->host_no);
  4616. phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
  4617. if (!phba->wq) {
  4618. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4619. "BM_%d : beiscsi_dev_probe-"
  4620. "Failed to allocate work queue\n");
  4621. goto free_twq;
  4622. }
  4623. INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
  4624. beiscsi_hw_health_check);
  4625. phwi_ctrlr = phba->phwi_ctrlr;
  4626. phwi_context = phwi_ctrlr->phwi_ctxt;
  4627. if (blk_iopoll_enabled) {
  4628. for (i = 0; i < phba->num_cpus; i++) {
  4629. pbe_eq = &phwi_context->be_eq[i];
  4630. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4631. be_iopoll);
  4632. blk_iopoll_enable(&pbe_eq->iopoll);
  4633. }
  4634. i = (phba->msix_enabled) ? i : 0;
  4635. /* Work item for MCC handling */
  4636. pbe_eq = &phwi_context->be_eq[i];
  4637. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4638. } else {
  4639. if (phba->msix_enabled) {
  4640. for (i = 0; i <= phba->num_cpus; i++) {
  4641. pbe_eq = &phwi_context->be_eq[i];
  4642. INIT_WORK(&pbe_eq->work_cqs,
  4643. beiscsi_process_all_cqs);
  4644. }
  4645. } else {
  4646. pbe_eq = &phwi_context->be_eq[0];
  4647. INIT_WORK(&pbe_eq->work_cqs,
  4648. beiscsi_process_all_cqs);
  4649. }
  4650. }
  4651. ret = beiscsi_init_irqs(phba);
  4652. if (ret < 0) {
  4653. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4654. "BM_%d : beiscsi_dev_probe-"
  4655. "Failed to beiscsi_init_irqs\n");
  4656. goto free_blkenbld;
  4657. }
  4658. hwi_enable_intr(phba);
  4659. if (beiscsi_setup_boot_info(phba))
  4660. /*
  4661. * log error but continue, because we may not be using
  4662. * iscsi boot.
  4663. */
  4664. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4665. "BM_%d : Could not set up "
  4666. "iSCSI boot info.\n");
  4667. beiscsi_create_def_ifaces(phba);
  4668. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4669. msecs_to_jiffies(1000));
  4670. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4671. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4672. return 0;
  4673. free_blkenbld:
  4674. destroy_workqueue(phba->wq);
  4675. if (blk_iopoll_enabled)
  4676. for (i = 0; i < phba->num_cpus; i++) {
  4677. pbe_eq = &phwi_context->be_eq[i];
  4678. blk_iopoll_disable(&pbe_eq->iopoll);
  4679. }
  4680. free_twq:
  4681. beiscsi_clean_port(phba);
  4682. beiscsi_free_mem(phba);
  4683. free_port:
  4684. pci_free_consistent(phba->pcidev,
  4685. phba->ctrl.mbox_mem_alloced.size,
  4686. phba->ctrl.mbox_mem_alloced.va,
  4687. phba->ctrl.mbox_mem_alloced.dma);
  4688. beiscsi_unmap_pci_function(phba);
  4689. hba_free:
  4690. if (phba->msix_enabled)
  4691. pci_disable_msix(phba->pcidev);
  4692. iscsi_host_remove(phba->shost);
  4693. pci_dev_put(phba->pcidev);
  4694. iscsi_host_free(phba->shost);
  4695. disable_pci:
  4696. pci_disable_device(pcidev);
  4697. return ret;
  4698. }
  4699. struct iscsi_transport beiscsi_iscsi_transport = {
  4700. .owner = THIS_MODULE,
  4701. .name = DRV_NAME,
  4702. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4703. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4704. .create_session = beiscsi_session_create,
  4705. .destroy_session = beiscsi_session_destroy,
  4706. .create_conn = beiscsi_conn_create,
  4707. .bind_conn = beiscsi_conn_bind,
  4708. .destroy_conn = iscsi_conn_teardown,
  4709. .attr_is_visible = be2iscsi_attr_is_visible,
  4710. .set_iface_param = be2iscsi_iface_set_param,
  4711. .get_iface_param = be2iscsi_iface_get_param,
  4712. .set_param = beiscsi_set_param,
  4713. .get_conn_param = iscsi_conn_get_param,
  4714. .get_session_param = iscsi_session_get_param,
  4715. .get_host_param = beiscsi_get_host_param,
  4716. .start_conn = beiscsi_conn_start,
  4717. .stop_conn = iscsi_conn_stop,
  4718. .send_pdu = iscsi_conn_send_pdu,
  4719. .xmit_task = beiscsi_task_xmit,
  4720. .cleanup_task = beiscsi_cleanup_task,
  4721. .alloc_pdu = beiscsi_alloc_pdu,
  4722. .parse_pdu_itt = beiscsi_parse_pdu,
  4723. .get_stats = beiscsi_conn_get_stats,
  4724. .get_ep_param = beiscsi_ep_get_param,
  4725. .ep_connect = beiscsi_ep_connect,
  4726. .ep_poll = beiscsi_ep_poll,
  4727. .ep_disconnect = beiscsi_ep_disconnect,
  4728. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4729. .bsg_request = beiscsi_bsg_request,
  4730. };
  4731. static struct pci_driver beiscsi_pci_driver = {
  4732. .name = DRV_NAME,
  4733. .probe = beiscsi_dev_probe,
  4734. .remove = beiscsi_remove,
  4735. .shutdown = beiscsi_shutdown,
  4736. .id_table = beiscsi_pci_id_table
  4737. };
  4738. static int __init beiscsi_module_init(void)
  4739. {
  4740. int ret;
  4741. beiscsi_scsi_transport =
  4742. iscsi_register_transport(&beiscsi_iscsi_transport);
  4743. if (!beiscsi_scsi_transport) {
  4744. printk(KERN_ERR
  4745. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4746. return -ENOMEM;
  4747. }
  4748. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4749. &beiscsi_iscsi_transport);
  4750. ret = pci_register_driver(&beiscsi_pci_driver);
  4751. if (ret) {
  4752. printk(KERN_ERR
  4753. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4754. goto unregister_iscsi_transport;
  4755. }
  4756. return 0;
  4757. unregister_iscsi_transport:
  4758. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4759. return ret;
  4760. }
  4761. static void __exit beiscsi_module_exit(void)
  4762. {
  4763. pci_unregister_driver(&beiscsi_pci_driver);
  4764. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4765. }
  4766. module_init(beiscsi_module_init);
  4767. module_exit(beiscsi_module_exit);