swim3.c 29 KB

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  1. /*
  2. * Driver for the SWIM3 (Super Woz Integrated Machine 3)
  3. * floppy controller found on Power Macintoshes.
  4. *
  5. * Copyright (C) 1996 Paul Mackerras.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. /*
  13. * TODO:
  14. * handle 2 drives
  15. * handle GCR disks
  16. */
  17. #include <linux/stddef.h>
  18. #include <linux/kernel.h>
  19. #include <linux/sched.h>
  20. #include <linux/timer.h>
  21. #include <linux/delay.h>
  22. #include <linux/fd.h>
  23. #include <linux/ioctl.h>
  24. #include <linux/blkdev.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/smp_lock.h>
  27. #include <linux/module.h>
  28. #include <linux/spinlock.h>
  29. #include <asm/io.h>
  30. #include <asm/dbdma.h>
  31. #include <asm/prom.h>
  32. #include <asm/uaccess.h>
  33. #include <asm/mediabay.h>
  34. #include <asm/machdep.h>
  35. #include <asm/pmac_feature.h>
  36. static struct request_queue *swim3_queue;
  37. static struct gendisk *disks[2];
  38. static struct request *fd_req;
  39. #define MAX_FLOPPIES 2
  40. enum swim_state {
  41. idle,
  42. locating,
  43. seeking,
  44. settling,
  45. do_transfer,
  46. jogging,
  47. available,
  48. revalidating,
  49. ejecting
  50. };
  51. #define REG(x) unsigned char x; char x ## _pad[15];
  52. /*
  53. * The names for these registers mostly represent speculation on my part.
  54. * It will be interesting to see how close they are to the names Apple uses.
  55. */
  56. struct swim3 {
  57. REG(data);
  58. REG(timer); /* counts down at 1MHz */
  59. REG(error);
  60. REG(mode);
  61. REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
  62. REG(setup);
  63. REG(control); /* writing bits clears them */
  64. REG(status); /* writing bits sets them in control */
  65. REG(intr);
  66. REG(nseek); /* # tracks to seek */
  67. REG(ctrack); /* current track number */
  68. REG(csect); /* current sector number */
  69. REG(gap3); /* size of gap 3 in track format */
  70. REG(sector); /* sector # to read or write */
  71. REG(nsect); /* # sectors to read or write */
  72. REG(intr_enable);
  73. };
  74. #define control_bic control
  75. #define control_bis status
  76. /* Bits in select register */
  77. #define CA_MASK 7
  78. #define LSTRB 8
  79. /* Bits in control register */
  80. #define DO_SEEK 0x80
  81. #define FORMAT 0x40
  82. #define SELECT 0x20
  83. #define WRITE_SECTORS 0x10
  84. #define DO_ACTION 0x08
  85. #define DRIVE2_ENABLE 0x04
  86. #define DRIVE_ENABLE 0x02
  87. #define INTR_ENABLE 0x01
  88. /* Bits in status register */
  89. #define FIFO_1BYTE 0x80
  90. #define FIFO_2BYTE 0x40
  91. #define ERROR 0x20
  92. #define DATA 0x08
  93. #define RDDATA 0x04
  94. #define INTR_PENDING 0x02
  95. #define MARK_BYTE 0x01
  96. /* Bits in intr and intr_enable registers */
  97. #define ERROR_INTR 0x20
  98. #define DATA_CHANGED 0x10
  99. #define TRANSFER_DONE 0x08
  100. #define SEEN_SECTOR 0x04
  101. #define SEEK_DONE 0x02
  102. #define TIMER_DONE 0x01
  103. /* Bits in error register */
  104. #define ERR_DATA_CRC 0x80
  105. #define ERR_ADDR_CRC 0x40
  106. #define ERR_OVERRUN 0x04
  107. #define ERR_UNDERRUN 0x01
  108. /* Bits in setup register */
  109. #define S_SW_RESET 0x80
  110. #define S_GCR_WRITE 0x40
  111. #define S_IBM_DRIVE 0x20
  112. #define S_TEST_MODE 0x10
  113. #define S_FCLK_DIV2 0x08
  114. #define S_GCR 0x04
  115. #define S_COPY_PROT 0x02
  116. #define S_INV_WDATA 0x01
  117. /* Select values for swim3_action */
  118. #define SEEK_POSITIVE 0
  119. #define SEEK_NEGATIVE 4
  120. #define STEP 1
  121. #define MOTOR_ON 2
  122. #define MOTOR_OFF 6
  123. #define INDEX 3
  124. #define EJECT 7
  125. #define SETMFM 9
  126. #define SETGCR 13
  127. /* Select values for swim3_select and swim3_readbit */
  128. #define STEP_DIR 0
  129. #define STEPPING 1
  130. #define MOTOR_ON 2
  131. #define RELAX 3 /* also eject in progress */
  132. #define READ_DATA_0 4
  133. #define TWOMEG_DRIVE 5
  134. #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */
  135. #define DRIVE_PRESENT 7
  136. #define DISK_IN 8
  137. #define WRITE_PROT 9
  138. #define TRACK_ZERO 10
  139. #define TACHO 11
  140. #define READ_DATA_1 12
  141. #define MFM_MODE 13
  142. #define SEEK_COMPLETE 14
  143. #define ONEMEG_MEDIA 15
  144. /* Definitions of values used in writing and formatting */
  145. #define DATA_ESCAPE 0x99
  146. #define GCR_SYNC_EXC 0x3f
  147. #define GCR_SYNC_CONV 0x80
  148. #define GCR_FIRST_MARK 0xd5
  149. #define GCR_SECOND_MARK 0xaa
  150. #define GCR_ADDR_MARK "\xd5\xaa\x00"
  151. #define GCR_DATA_MARK "\xd5\xaa\x0b"
  152. #define GCR_SLIP_BYTE "\x27\xaa"
  153. #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f"
  154. #define DATA_99 "\x99\x99"
  155. #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe"
  156. #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc"
  157. #define MFM_GAP_LEN 12
  158. struct floppy_state {
  159. enum swim_state state;
  160. spinlock_t lock;
  161. struct swim3 __iomem *swim3; /* hardware registers */
  162. struct dbdma_regs __iomem *dma; /* DMA controller registers */
  163. int swim3_intr; /* interrupt number for SWIM3 */
  164. int dma_intr; /* interrupt number for DMA channel */
  165. int cur_cyl; /* cylinder head is on, or -1 */
  166. int cur_sector; /* last sector we saw go past */
  167. int req_cyl; /* the cylinder for the current r/w request */
  168. int head; /* head number ditto */
  169. int req_sector; /* sector number ditto */
  170. int scount; /* # sectors we're transferring at present */
  171. int retries;
  172. int settle_time;
  173. int secpercyl; /* disk geometry information */
  174. int secpertrack;
  175. int total_secs;
  176. int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */
  177. struct dbdma_cmd *dma_cmd;
  178. int ref_count;
  179. int expect_cyl;
  180. struct timer_list timeout;
  181. int timeout_pending;
  182. int ejected;
  183. wait_queue_head_t wait;
  184. int wanted;
  185. struct macio_dev *mdev;
  186. char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
  187. };
  188. static struct floppy_state floppy_states[MAX_FLOPPIES];
  189. static int floppy_count = 0;
  190. static DEFINE_SPINLOCK(swim3_lock);
  191. static unsigned short write_preamble[] = {
  192. 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */
  193. 0, 0, 0, 0, 0, 0, /* sync field */
  194. 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */
  195. 0x990f /* no escape for 512 bytes */
  196. };
  197. static unsigned short write_postamble[] = {
  198. 0x9904, /* insert CRC */
  199. 0x4e4e, 0x4e4e,
  200. 0x9908, /* stop writing */
  201. 0, 0, 0, 0, 0, 0
  202. };
  203. static void swim3_select(struct floppy_state *fs, int sel);
  204. static void swim3_action(struct floppy_state *fs, int action);
  205. static int swim3_readbit(struct floppy_state *fs, int bit);
  206. static void do_fd_request(struct request_queue * q);
  207. static void start_request(struct floppy_state *fs);
  208. static void set_timeout(struct floppy_state *fs, int nticks,
  209. void (*proc)(unsigned long));
  210. static void scan_track(struct floppy_state *fs);
  211. static void seek_track(struct floppy_state *fs, int n);
  212. static void init_dma(struct dbdma_cmd *cp, int cmd, void *buf, int count);
  213. static void setup_transfer(struct floppy_state *fs);
  214. static void act(struct floppy_state *fs);
  215. static void scan_timeout(unsigned long data);
  216. static void seek_timeout(unsigned long data);
  217. static void settle_timeout(unsigned long data);
  218. static void xfer_timeout(unsigned long data);
  219. static irqreturn_t swim3_interrupt(int irq, void *dev_id);
  220. /*static void fd_dma_interrupt(int irq, void *dev_id);*/
  221. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  222. int interruptible);
  223. static void release_drive(struct floppy_state *fs);
  224. static int fd_eject(struct floppy_state *fs);
  225. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  226. unsigned int cmd, unsigned long param);
  227. static int floppy_open(struct block_device *bdev, fmode_t mode);
  228. static int floppy_release(struct gendisk *disk, fmode_t mode);
  229. static int floppy_check_change(struct gendisk *disk);
  230. static int floppy_revalidate(struct gendisk *disk);
  231. static bool swim3_end_request(int err, unsigned int nr_bytes)
  232. {
  233. if (__blk_end_request(fd_req, err, nr_bytes))
  234. return true;
  235. fd_req = NULL;
  236. return false;
  237. }
  238. static bool swim3_end_request_cur(int err)
  239. {
  240. return swim3_end_request(err, blk_rq_cur_bytes(fd_req));
  241. }
  242. static void swim3_select(struct floppy_state *fs, int sel)
  243. {
  244. struct swim3 __iomem *sw = fs->swim3;
  245. out_8(&sw->select, RELAX);
  246. if (sel & 8)
  247. out_8(&sw->control_bis, SELECT);
  248. else
  249. out_8(&sw->control_bic, SELECT);
  250. out_8(&sw->select, sel & CA_MASK);
  251. }
  252. static void swim3_action(struct floppy_state *fs, int action)
  253. {
  254. struct swim3 __iomem *sw = fs->swim3;
  255. swim3_select(fs, action);
  256. udelay(1);
  257. out_8(&sw->select, sw->select | LSTRB);
  258. udelay(2);
  259. out_8(&sw->select, sw->select & ~LSTRB);
  260. udelay(1);
  261. }
  262. static int swim3_readbit(struct floppy_state *fs, int bit)
  263. {
  264. struct swim3 __iomem *sw = fs->swim3;
  265. int stat;
  266. swim3_select(fs, bit);
  267. udelay(1);
  268. stat = in_8(&sw->status);
  269. return (stat & DATA) == 0;
  270. }
  271. static void do_fd_request(struct request_queue * q)
  272. {
  273. int i;
  274. for(i=0; i<floppy_count; i++) {
  275. struct floppy_state *fs = &floppy_states[i];
  276. if (fs->mdev->media_bay &&
  277. check_media_bay(fs->mdev->media_bay) != MB_FD)
  278. continue;
  279. start_request(fs);
  280. }
  281. }
  282. static void start_request(struct floppy_state *fs)
  283. {
  284. struct request *req;
  285. unsigned long x;
  286. if (fs->state == idle && fs->wanted) {
  287. fs->state = available;
  288. wake_up(&fs->wait);
  289. return;
  290. }
  291. while (fs->state == idle) {
  292. if (!fd_req) {
  293. fd_req = blk_fetch_request(swim3_queue);
  294. if (!fd_req)
  295. break;
  296. }
  297. req = fd_req;
  298. #if 0
  299. printk("do_fd_req: dev=%s cmd=%d sec=%ld nr_sec=%u buf=%p\n",
  300. req->rq_disk->disk_name, req->cmd,
  301. (long)blk_rq_pos(req), blk_rq_sectors(req), req->buffer);
  302. printk(" errors=%d current_nr_sectors=%u\n",
  303. req->errors, blk_rq_cur_sectors(req));
  304. #endif
  305. if (blk_rq_pos(req) >= fs->total_secs) {
  306. swim3_end_request_cur(-EIO);
  307. continue;
  308. }
  309. if (fs->ejected) {
  310. swim3_end_request_cur(-EIO);
  311. continue;
  312. }
  313. if (rq_data_dir(req) == WRITE) {
  314. if (fs->write_prot < 0)
  315. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  316. if (fs->write_prot) {
  317. swim3_end_request_cur(-EIO);
  318. continue;
  319. }
  320. }
  321. /* Do not remove the cast. blk_rq_pos(req) is now a
  322. * sector_t and can be 64 bits, but it will never go
  323. * past 32 bits for this driver anyway, so we can
  324. * safely cast it down and not have to do a 64/32
  325. * division
  326. */
  327. fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl;
  328. x = ((long)blk_rq_pos(req)) % fs->secpercyl;
  329. fs->head = x / fs->secpertrack;
  330. fs->req_sector = x % fs->secpertrack + 1;
  331. fd_req = req;
  332. fs->state = do_transfer;
  333. fs->retries = 0;
  334. act(fs);
  335. }
  336. }
  337. static void set_timeout(struct floppy_state *fs, int nticks,
  338. void (*proc)(unsigned long))
  339. {
  340. unsigned long flags;
  341. spin_lock_irqsave(&fs->lock, flags);
  342. if (fs->timeout_pending)
  343. del_timer(&fs->timeout);
  344. fs->timeout.expires = jiffies + nticks;
  345. fs->timeout.function = proc;
  346. fs->timeout.data = (unsigned long) fs;
  347. add_timer(&fs->timeout);
  348. fs->timeout_pending = 1;
  349. spin_unlock_irqrestore(&fs->lock, flags);
  350. }
  351. static inline void scan_track(struct floppy_state *fs)
  352. {
  353. struct swim3 __iomem *sw = fs->swim3;
  354. swim3_select(fs, READ_DATA_0);
  355. in_8(&sw->intr); /* clear SEEN_SECTOR bit */
  356. in_8(&sw->error);
  357. out_8(&sw->intr_enable, SEEN_SECTOR);
  358. out_8(&sw->control_bis, DO_ACTION);
  359. /* enable intr when track found */
  360. set_timeout(fs, HZ, scan_timeout); /* enable timeout */
  361. }
  362. static inline void seek_track(struct floppy_state *fs, int n)
  363. {
  364. struct swim3 __iomem *sw = fs->swim3;
  365. if (n >= 0) {
  366. swim3_action(fs, SEEK_POSITIVE);
  367. sw->nseek = n;
  368. } else {
  369. swim3_action(fs, SEEK_NEGATIVE);
  370. sw->nseek = -n;
  371. }
  372. fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1;
  373. swim3_select(fs, STEP);
  374. in_8(&sw->error);
  375. /* enable intr when seek finished */
  376. out_8(&sw->intr_enable, SEEK_DONE);
  377. out_8(&sw->control_bis, DO_SEEK);
  378. set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */
  379. fs->settle_time = 0;
  380. }
  381. static inline void init_dma(struct dbdma_cmd *cp, int cmd,
  382. void *buf, int count)
  383. {
  384. st_le16(&cp->req_count, count);
  385. st_le16(&cp->command, cmd);
  386. st_le32(&cp->phy_addr, virt_to_bus(buf));
  387. cp->xfer_status = 0;
  388. }
  389. static inline void setup_transfer(struct floppy_state *fs)
  390. {
  391. int n;
  392. struct swim3 __iomem *sw = fs->swim3;
  393. struct dbdma_cmd *cp = fs->dma_cmd;
  394. struct dbdma_regs __iomem *dr = fs->dma;
  395. if (blk_rq_cur_sectors(fd_req) <= 0) {
  396. printk(KERN_ERR "swim3: transfer 0 sectors?\n");
  397. return;
  398. }
  399. if (rq_data_dir(fd_req) == WRITE)
  400. n = 1;
  401. else {
  402. n = fs->secpertrack - fs->req_sector + 1;
  403. if (n > blk_rq_cur_sectors(fd_req))
  404. n = blk_rq_cur_sectors(fd_req);
  405. }
  406. fs->scount = n;
  407. swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
  408. out_8(&sw->sector, fs->req_sector);
  409. out_8(&sw->nsect, n);
  410. out_8(&sw->gap3, 0);
  411. out_le32(&dr->cmdptr, virt_to_bus(cp));
  412. if (rq_data_dir(fd_req) == WRITE) {
  413. /* Set up 3 dma commands: write preamble, data, postamble */
  414. init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
  415. ++cp;
  416. init_dma(cp, OUTPUT_MORE, fd_req->buffer, 512);
  417. ++cp;
  418. init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
  419. } else {
  420. init_dma(cp, INPUT_LAST, fd_req->buffer, n * 512);
  421. }
  422. ++cp;
  423. out_le16(&cp->command, DBDMA_STOP);
  424. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  425. in_8(&sw->error);
  426. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  427. if (rq_data_dir(fd_req) == WRITE)
  428. out_8(&sw->control_bis, WRITE_SECTORS);
  429. in_8(&sw->intr);
  430. out_le32(&dr->control, (RUN << 16) | RUN);
  431. /* enable intr when transfer complete */
  432. out_8(&sw->intr_enable, TRANSFER_DONE);
  433. out_8(&sw->control_bis, DO_ACTION);
  434. set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */
  435. }
  436. static void act(struct floppy_state *fs)
  437. {
  438. for (;;) {
  439. switch (fs->state) {
  440. case idle:
  441. return; /* XXX shouldn't get here */
  442. case locating:
  443. if (swim3_readbit(fs, TRACK_ZERO)) {
  444. fs->cur_cyl = 0;
  445. if (fs->req_cyl == 0)
  446. fs->state = do_transfer;
  447. else
  448. fs->state = seeking;
  449. break;
  450. }
  451. scan_track(fs);
  452. return;
  453. case seeking:
  454. if (fs->cur_cyl < 0) {
  455. fs->expect_cyl = -1;
  456. fs->state = locating;
  457. break;
  458. }
  459. if (fs->req_cyl == fs->cur_cyl) {
  460. printk("whoops, seeking 0\n");
  461. fs->state = do_transfer;
  462. break;
  463. }
  464. seek_track(fs, fs->req_cyl - fs->cur_cyl);
  465. return;
  466. case settling:
  467. /* check for SEEK_COMPLETE after 30ms */
  468. fs->settle_time = (HZ + 32) / 33;
  469. set_timeout(fs, fs->settle_time, settle_timeout);
  470. return;
  471. case do_transfer:
  472. if (fs->cur_cyl != fs->req_cyl) {
  473. if (fs->retries > 5) {
  474. swim3_end_request_cur(-EIO);
  475. fs->state = idle;
  476. return;
  477. }
  478. fs->state = seeking;
  479. break;
  480. }
  481. setup_transfer(fs);
  482. return;
  483. case jogging:
  484. seek_track(fs, -5);
  485. return;
  486. default:
  487. printk(KERN_ERR"swim3: unknown state %d\n", fs->state);
  488. return;
  489. }
  490. }
  491. }
  492. static void scan_timeout(unsigned long data)
  493. {
  494. struct floppy_state *fs = (struct floppy_state *) data;
  495. struct swim3 __iomem *sw = fs->swim3;
  496. fs->timeout_pending = 0;
  497. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  498. out_8(&sw->select, RELAX);
  499. out_8(&sw->intr_enable, 0);
  500. fs->cur_cyl = -1;
  501. if (fs->retries > 5) {
  502. swim3_end_request_cur(-EIO);
  503. fs->state = idle;
  504. start_request(fs);
  505. } else {
  506. fs->state = jogging;
  507. act(fs);
  508. }
  509. }
  510. static void seek_timeout(unsigned long data)
  511. {
  512. struct floppy_state *fs = (struct floppy_state *) data;
  513. struct swim3 __iomem *sw = fs->swim3;
  514. fs->timeout_pending = 0;
  515. out_8(&sw->control_bic, DO_SEEK);
  516. out_8(&sw->select, RELAX);
  517. out_8(&sw->intr_enable, 0);
  518. printk(KERN_ERR "swim3: seek timeout\n");
  519. swim3_end_request_cur(-EIO);
  520. fs->state = idle;
  521. start_request(fs);
  522. }
  523. static void settle_timeout(unsigned long data)
  524. {
  525. struct floppy_state *fs = (struct floppy_state *) data;
  526. struct swim3 __iomem *sw = fs->swim3;
  527. fs->timeout_pending = 0;
  528. if (swim3_readbit(fs, SEEK_COMPLETE)) {
  529. out_8(&sw->select, RELAX);
  530. fs->state = locating;
  531. act(fs);
  532. return;
  533. }
  534. out_8(&sw->select, RELAX);
  535. if (fs->settle_time < 2*HZ) {
  536. ++fs->settle_time;
  537. set_timeout(fs, 1, settle_timeout);
  538. return;
  539. }
  540. printk(KERN_ERR "swim3: seek settle timeout\n");
  541. swim3_end_request_cur(-EIO);
  542. fs->state = idle;
  543. start_request(fs);
  544. }
  545. static void xfer_timeout(unsigned long data)
  546. {
  547. struct floppy_state *fs = (struct floppy_state *) data;
  548. struct swim3 __iomem *sw = fs->swim3;
  549. struct dbdma_regs __iomem *dr = fs->dma;
  550. int n;
  551. fs->timeout_pending = 0;
  552. out_le32(&dr->control, RUN << 16);
  553. /* We must wait a bit for dbdma to stop */
  554. for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++)
  555. udelay(1);
  556. out_8(&sw->intr_enable, 0);
  557. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  558. out_8(&sw->select, RELAX);
  559. printk(KERN_ERR "swim3: timeout %sing sector %ld\n",
  560. (rq_data_dir(fd_req)==WRITE? "writ": "read"),
  561. (long)blk_rq_pos(fd_req));
  562. swim3_end_request_cur(-EIO);
  563. fs->state = idle;
  564. start_request(fs);
  565. }
  566. static irqreturn_t swim3_interrupt(int irq, void *dev_id)
  567. {
  568. struct floppy_state *fs = (struct floppy_state *) dev_id;
  569. struct swim3 __iomem *sw = fs->swim3;
  570. int intr, err, n;
  571. int stat, resid;
  572. struct dbdma_regs __iomem *dr;
  573. struct dbdma_cmd *cp;
  574. intr = in_8(&sw->intr);
  575. err = (intr & ERROR_INTR)? in_8(&sw->error): 0;
  576. if ((intr & ERROR_INTR) && fs->state != do_transfer)
  577. printk(KERN_ERR "swim3_interrupt, state=%d, dir=%x, intr=%x, err=%x\n",
  578. fs->state, rq_data_dir(fd_req), intr, err);
  579. switch (fs->state) {
  580. case locating:
  581. if (intr & SEEN_SECTOR) {
  582. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  583. out_8(&sw->select, RELAX);
  584. out_8(&sw->intr_enable, 0);
  585. del_timer(&fs->timeout);
  586. fs->timeout_pending = 0;
  587. if (sw->ctrack == 0xff) {
  588. printk(KERN_ERR "swim3: seen sector but cyl=ff?\n");
  589. fs->cur_cyl = -1;
  590. if (fs->retries > 5) {
  591. swim3_end_request_cur(-EIO);
  592. fs->state = idle;
  593. start_request(fs);
  594. } else {
  595. fs->state = jogging;
  596. act(fs);
  597. }
  598. break;
  599. }
  600. fs->cur_cyl = sw->ctrack;
  601. fs->cur_sector = sw->csect;
  602. if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl)
  603. printk(KERN_ERR "swim3: expected cyl %d, got %d\n",
  604. fs->expect_cyl, fs->cur_cyl);
  605. fs->state = do_transfer;
  606. act(fs);
  607. }
  608. break;
  609. case seeking:
  610. case jogging:
  611. if (sw->nseek == 0) {
  612. out_8(&sw->control_bic, DO_SEEK);
  613. out_8(&sw->select, RELAX);
  614. out_8(&sw->intr_enable, 0);
  615. del_timer(&fs->timeout);
  616. fs->timeout_pending = 0;
  617. if (fs->state == seeking)
  618. ++fs->retries;
  619. fs->state = settling;
  620. act(fs);
  621. }
  622. break;
  623. case settling:
  624. out_8(&sw->intr_enable, 0);
  625. del_timer(&fs->timeout);
  626. fs->timeout_pending = 0;
  627. act(fs);
  628. break;
  629. case do_transfer:
  630. if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0)
  631. break;
  632. out_8(&sw->intr_enable, 0);
  633. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  634. out_8(&sw->select, RELAX);
  635. del_timer(&fs->timeout);
  636. fs->timeout_pending = 0;
  637. dr = fs->dma;
  638. cp = fs->dma_cmd;
  639. if (rq_data_dir(fd_req) == WRITE)
  640. ++cp;
  641. /*
  642. * Check that the main data transfer has finished.
  643. * On writing, the swim3 sometimes doesn't use
  644. * up all the bytes of the postamble, so we can still
  645. * see DMA active here. That doesn't matter as long
  646. * as all the sector data has been transferred.
  647. */
  648. if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) {
  649. /* wait a little while for DMA to complete */
  650. for (n = 0; n < 100; ++n) {
  651. if (cp->xfer_status != 0)
  652. break;
  653. udelay(1);
  654. barrier();
  655. }
  656. }
  657. /* turn off DMA */
  658. out_le32(&dr->control, (RUN | PAUSE) << 16);
  659. stat = ld_le16(&cp->xfer_status);
  660. resid = ld_le16(&cp->res_count);
  661. if (intr & ERROR_INTR) {
  662. n = fs->scount - 1 - resid / 512;
  663. if (n > 0) {
  664. blk_update_request(fd_req, 0, n << 9);
  665. fs->req_sector += n;
  666. }
  667. if (fs->retries < 5) {
  668. ++fs->retries;
  669. act(fs);
  670. } else {
  671. printk("swim3: error %sing block %ld (err=%x)\n",
  672. rq_data_dir(fd_req) == WRITE? "writ": "read",
  673. (long)blk_rq_pos(fd_req), err);
  674. swim3_end_request_cur(-EIO);
  675. fs->state = idle;
  676. }
  677. } else {
  678. if ((stat & ACTIVE) == 0 || resid != 0) {
  679. /* musta been an error */
  680. printk(KERN_ERR "swim3: fd dma: stat=%x resid=%d\n", stat, resid);
  681. printk(KERN_ERR " state=%d, dir=%x, intr=%x, err=%x\n",
  682. fs->state, rq_data_dir(fd_req), intr, err);
  683. swim3_end_request_cur(-EIO);
  684. fs->state = idle;
  685. start_request(fs);
  686. break;
  687. }
  688. if (swim3_end_request(0, fs->scount << 9)) {
  689. fs->req_sector += fs->scount;
  690. if (fs->req_sector > fs->secpertrack) {
  691. fs->req_sector -= fs->secpertrack;
  692. if (++fs->head > 1) {
  693. fs->head = 0;
  694. ++fs->req_cyl;
  695. }
  696. }
  697. act(fs);
  698. } else
  699. fs->state = idle;
  700. }
  701. if (fs->state == idle)
  702. start_request(fs);
  703. break;
  704. default:
  705. printk(KERN_ERR "swim3: don't know what to do in state %d\n", fs->state);
  706. }
  707. return IRQ_HANDLED;
  708. }
  709. /*
  710. static void fd_dma_interrupt(int irq, void *dev_id)
  711. {
  712. }
  713. */
  714. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  715. int interruptible)
  716. {
  717. unsigned long flags;
  718. spin_lock_irqsave(&fs->lock, flags);
  719. if (fs->state != idle) {
  720. ++fs->wanted;
  721. while (fs->state != available) {
  722. if (interruptible && signal_pending(current)) {
  723. --fs->wanted;
  724. spin_unlock_irqrestore(&fs->lock, flags);
  725. return -EINTR;
  726. }
  727. interruptible_sleep_on(&fs->wait);
  728. }
  729. --fs->wanted;
  730. }
  731. fs->state = state;
  732. spin_unlock_irqrestore(&fs->lock, flags);
  733. return 0;
  734. }
  735. static void release_drive(struct floppy_state *fs)
  736. {
  737. unsigned long flags;
  738. spin_lock_irqsave(&fs->lock, flags);
  739. fs->state = idle;
  740. start_request(fs);
  741. spin_unlock_irqrestore(&fs->lock, flags);
  742. }
  743. static int fd_eject(struct floppy_state *fs)
  744. {
  745. int err, n;
  746. err = grab_drive(fs, ejecting, 1);
  747. if (err)
  748. return err;
  749. swim3_action(fs, EJECT);
  750. for (n = 20; n > 0; --n) {
  751. if (signal_pending(current)) {
  752. err = -EINTR;
  753. break;
  754. }
  755. swim3_select(fs, RELAX);
  756. schedule_timeout_interruptible(1);
  757. if (swim3_readbit(fs, DISK_IN) == 0)
  758. break;
  759. }
  760. swim3_select(fs, RELAX);
  761. udelay(150);
  762. fs->ejected = 1;
  763. release_drive(fs);
  764. return err;
  765. }
  766. static struct floppy_struct floppy_type =
  767. { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */
  768. static int floppy_locked_ioctl(struct block_device *bdev, fmode_t mode,
  769. unsigned int cmd, unsigned long param)
  770. {
  771. struct floppy_state *fs = bdev->bd_disk->private_data;
  772. int err;
  773. if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
  774. return -EPERM;
  775. if (fs->mdev->media_bay &&
  776. check_media_bay(fs->mdev->media_bay) != MB_FD)
  777. return -ENXIO;
  778. switch (cmd) {
  779. case FDEJECT:
  780. if (fs->ref_count != 1)
  781. return -EBUSY;
  782. err = fd_eject(fs);
  783. return err;
  784. case FDGETPRM:
  785. if (copy_to_user((void __user *) param, &floppy_type,
  786. sizeof(struct floppy_struct)))
  787. return -EFAULT;
  788. return 0;
  789. }
  790. return -ENOTTY;
  791. }
  792. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  793. unsigned int cmd, unsigned long param)
  794. {
  795. int ret;
  796. lock_kernel();
  797. ret = floppy_locked_ioctl(bdev, mode, cmd, param);
  798. unlock_kernel();
  799. return ret;
  800. }
  801. static int floppy_open(struct block_device *bdev, fmode_t mode)
  802. {
  803. struct floppy_state *fs = bdev->bd_disk->private_data;
  804. struct swim3 __iomem *sw = fs->swim3;
  805. int n, err = 0;
  806. if (fs->ref_count == 0) {
  807. if (fs->mdev->media_bay &&
  808. check_media_bay(fs->mdev->media_bay) != MB_FD)
  809. return -ENXIO;
  810. out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
  811. out_8(&sw->control_bic, 0xff);
  812. out_8(&sw->mode, 0x95);
  813. udelay(10);
  814. out_8(&sw->intr_enable, 0);
  815. out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE);
  816. swim3_action(fs, MOTOR_ON);
  817. fs->write_prot = -1;
  818. fs->cur_cyl = -1;
  819. for (n = 0; n < 2 * HZ; ++n) {
  820. if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE))
  821. break;
  822. if (signal_pending(current)) {
  823. err = -EINTR;
  824. break;
  825. }
  826. swim3_select(fs, RELAX);
  827. schedule_timeout_interruptible(1);
  828. }
  829. if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0
  830. || swim3_readbit(fs, DISK_IN) == 0))
  831. err = -ENXIO;
  832. swim3_action(fs, SETMFM);
  833. swim3_select(fs, RELAX);
  834. } else if (fs->ref_count == -1 || mode & FMODE_EXCL)
  835. return -EBUSY;
  836. if (err == 0 && (mode & FMODE_NDELAY) == 0
  837. && (mode & (FMODE_READ|FMODE_WRITE))) {
  838. check_disk_change(bdev);
  839. if (fs->ejected)
  840. err = -ENXIO;
  841. }
  842. if (err == 0 && (mode & FMODE_WRITE)) {
  843. if (fs->write_prot < 0)
  844. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  845. if (fs->write_prot)
  846. err = -EROFS;
  847. }
  848. if (err) {
  849. if (fs->ref_count == 0) {
  850. swim3_action(fs, MOTOR_OFF);
  851. out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE);
  852. swim3_select(fs, RELAX);
  853. }
  854. return err;
  855. }
  856. if (mode & FMODE_EXCL)
  857. fs->ref_count = -1;
  858. else
  859. ++fs->ref_count;
  860. return 0;
  861. }
  862. static int floppy_release(struct gendisk *disk, fmode_t mode)
  863. {
  864. struct floppy_state *fs = disk->private_data;
  865. struct swim3 __iomem *sw = fs->swim3;
  866. if (fs->ref_count > 0 && --fs->ref_count == 0) {
  867. swim3_action(fs, MOTOR_OFF);
  868. out_8(&sw->control_bic, 0xff);
  869. swim3_select(fs, RELAX);
  870. }
  871. return 0;
  872. }
  873. static int floppy_check_change(struct gendisk *disk)
  874. {
  875. struct floppy_state *fs = disk->private_data;
  876. return fs->ejected;
  877. }
  878. static int floppy_revalidate(struct gendisk *disk)
  879. {
  880. struct floppy_state *fs = disk->private_data;
  881. struct swim3 __iomem *sw;
  882. int ret, n;
  883. if (fs->mdev->media_bay &&
  884. check_media_bay(fs->mdev->media_bay) != MB_FD)
  885. return -ENXIO;
  886. sw = fs->swim3;
  887. grab_drive(fs, revalidating, 0);
  888. out_8(&sw->intr_enable, 0);
  889. out_8(&sw->control_bis, DRIVE_ENABLE);
  890. swim3_action(fs, MOTOR_ON); /* necessary? */
  891. fs->write_prot = -1;
  892. fs->cur_cyl = -1;
  893. mdelay(1);
  894. for (n = HZ; n > 0; --n) {
  895. if (swim3_readbit(fs, SEEK_COMPLETE))
  896. break;
  897. if (signal_pending(current))
  898. break;
  899. swim3_select(fs, RELAX);
  900. schedule_timeout_interruptible(1);
  901. }
  902. ret = swim3_readbit(fs, SEEK_COMPLETE) == 0
  903. || swim3_readbit(fs, DISK_IN) == 0;
  904. if (ret)
  905. swim3_action(fs, MOTOR_OFF);
  906. else {
  907. fs->ejected = 0;
  908. swim3_action(fs, SETMFM);
  909. }
  910. swim3_select(fs, RELAX);
  911. release_drive(fs);
  912. return ret;
  913. }
  914. static const struct block_device_operations floppy_fops = {
  915. .open = floppy_open,
  916. .release = floppy_release,
  917. .ioctl = floppy_ioctl,
  918. .media_changed = floppy_check_change,
  919. .revalidate_disk= floppy_revalidate,
  920. };
  921. static int swim3_add_device(struct macio_dev *mdev, int index)
  922. {
  923. struct device_node *swim = mdev->ofdev.dev.of_node;
  924. struct floppy_state *fs = &floppy_states[index];
  925. int rc = -EBUSY;
  926. /* Check & Request resources */
  927. if (macio_resource_count(mdev) < 2) {
  928. printk(KERN_WARNING "ifd%d: no address for %s\n",
  929. index, swim->full_name);
  930. return -ENXIO;
  931. }
  932. if (macio_irq_count(mdev) < 2) {
  933. printk(KERN_WARNING "fd%d: no intrs for device %s\n",
  934. index, swim->full_name);
  935. }
  936. if (macio_request_resource(mdev, 0, "swim3 (mmio)")) {
  937. printk(KERN_ERR "fd%d: can't request mmio resource for %s\n",
  938. index, swim->full_name);
  939. return -EBUSY;
  940. }
  941. if (macio_request_resource(mdev, 1, "swim3 (dma)")) {
  942. printk(KERN_ERR "fd%d: can't request dma resource for %s\n",
  943. index, swim->full_name);
  944. macio_release_resource(mdev, 0);
  945. return -EBUSY;
  946. }
  947. dev_set_drvdata(&mdev->ofdev.dev, fs);
  948. if (mdev->media_bay == NULL)
  949. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
  950. memset(fs, 0, sizeof(*fs));
  951. spin_lock_init(&fs->lock);
  952. fs->state = idle;
  953. fs->swim3 = (struct swim3 __iomem *)
  954. ioremap(macio_resource_start(mdev, 0), 0x200);
  955. if (fs->swim3 == NULL) {
  956. printk("fd%d: couldn't map registers for %s\n",
  957. index, swim->full_name);
  958. rc = -ENOMEM;
  959. goto out_release;
  960. }
  961. fs->dma = (struct dbdma_regs __iomem *)
  962. ioremap(macio_resource_start(mdev, 1), 0x200);
  963. if (fs->dma == NULL) {
  964. printk("fd%d: couldn't map DMA for %s\n",
  965. index, swim->full_name);
  966. iounmap(fs->swim3);
  967. rc = -ENOMEM;
  968. goto out_release;
  969. }
  970. fs->swim3_intr = macio_irq(mdev, 0);
  971. fs->dma_intr = macio_irq(mdev, 1);
  972. fs->cur_cyl = -1;
  973. fs->cur_sector = -1;
  974. fs->secpercyl = 36;
  975. fs->secpertrack = 18;
  976. fs->total_secs = 2880;
  977. fs->mdev = mdev;
  978. init_waitqueue_head(&fs->wait);
  979. fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
  980. memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd));
  981. st_le16(&fs->dma_cmd[1].command, DBDMA_STOP);
  982. if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) {
  983. printk(KERN_ERR "fd%d: couldn't request irq %d for %s\n",
  984. index, fs->swim3_intr, swim->full_name);
  985. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0);
  986. goto out_unmap;
  987. return -EBUSY;
  988. }
  989. /*
  990. if (request_irq(fs->dma_intr, fd_dma_interrupt, 0, "SWIM3-dma", fs)) {
  991. printk(KERN_ERR "Couldn't get irq %d for SWIM3 DMA",
  992. fs->dma_intr);
  993. return -EBUSY;
  994. }
  995. */
  996. init_timer(&fs->timeout);
  997. printk(KERN_INFO "fd%d: SWIM3 floppy controller %s\n", floppy_count,
  998. mdev->media_bay ? "in media bay" : "");
  999. return 0;
  1000. out_unmap:
  1001. iounmap(fs->dma);
  1002. iounmap(fs->swim3);
  1003. out_release:
  1004. macio_release_resource(mdev, 0);
  1005. macio_release_resource(mdev, 1);
  1006. return rc;
  1007. }
  1008. static int __devinit swim3_attach(struct macio_dev *mdev, const struct of_device_id *match)
  1009. {
  1010. int i, rc;
  1011. struct gendisk *disk;
  1012. /* Add the drive */
  1013. rc = swim3_add_device(mdev, floppy_count);
  1014. if (rc)
  1015. return rc;
  1016. /* Now create the queue if not there yet */
  1017. if (swim3_queue == NULL) {
  1018. /* If we failed, there isn't much we can do as the driver is still
  1019. * too dumb to remove the device, just bail out
  1020. */
  1021. if (register_blkdev(FLOPPY_MAJOR, "fd"))
  1022. return 0;
  1023. swim3_queue = blk_init_queue(do_fd_request, &swim3_lock);
  1024. if (swim3_queue == NULL) {
  1025. unregister_blkdev(FLOPPY_MAJOR, "fd");
  1026. return 0;
  1027. }
  1028. }
  1029. /* Now register that disk. Same comment about failure handling */
  1030. i = floppy_count++;
  1031. disk = disks[i] = alloc_disk(1);
  1032. if (disk == NULL)
  1033. return 0;
  1034. disk->major = FLOPPY_MAJOR;
  1035. disk->first_minor = i;
  1036. disk->fops = &floppy_fops;
  1037. disk->private_data = &floppy_states[i];
  1038. disk->queue = swim3_queue;
  1039. disk->flags |= GENHD_FL_REMOVABLE;
  1040. sprintf(disk->disk_name, "fd%d", i);
  1041. set_capacity(disk, 2880);
  1042. add_disk(disk);
  1043. return 0;
  1044. }
  1045. static struct of_device_id swim3_match[] =
  1046. {
  1047. {
  1048. .name = "swim3",
  1049. },
  1050. {
  1051. .compatible = "ohare-swim3"
  1052. },
  1053. {
  1054. .compatible = "swim3"
  1055. },
  1056. };
  1057. static struct macio_driver swim3_driver =
  1058. {
  1059. .driver = {
  1060. .name = "swim3",
  1061. .of_match_table = swim3_match,
  1062. },
  1063. .probe = swim3_attach,
  1064. #if 0
  1065. .suspend = swim3_suspend,
  1066. .resume = swim3_resume,
  1067. #endif
  1068. };
  1069. int swim3_init(void)
  1070. {
  1071. macio_register_driver(&swim3_driver);
  1072. return 0;
  1073. }
  1074. module_init(swim3_init)
  1075. MODULE_LICENSE("GPL");
  1076. MODULE_AUTHOR("Paul Mackerras");
  1077. MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR);