i915_drv.c 15 KB

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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #include <linux/device.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include <linux/console.h>
  35. #include "drm_crtc_helper.h"
  36. static int i915_modeset = -1;
  37. module_param_named(modeset, i915_modeset, int, 0400);
  38. unsigned int i915_fbpercrtc = 0;
  39. module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  40. unsigned int i915_powersave = 1;
  41. module_param_named(powersave, i915_powersave, int, 0400);
  42. unsigned int i915_lvds_downclock = 0;
  43. module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  44. static struct drm_driver driver;
  45. #define INTEL_VGA_DEVICE(id, info) { \
  46. .class = PCI_CLASS_DISPLAY_VGA << 8, \
  47. .class_mask = 0xffff00, \
  48. .vendor = 0x8086, \
  49. .device = id, \
  50. .subvendor = PCI_ANY_ID, \
  51. .subdevice = PCI_ANY_ID, \
  52. .driver_data = (unsigned long) info }
  53. const static struct intel_device_info intel_i830_info = {
  54. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  55. };
  56. const static struct intel_device_info intel_845g_info = {
  57. .is_i8xx = 1,
  58. };
  59. const static struct intel_device_info intel_i85x_info = {
  60. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  61. };
  62. const static struct intel_device_info intel_i865g_info = {
  63. .is_i8xx = 1,
  64. };
  65. const static struct intel_device_info intel_i915g_info = {
  66. .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
  67. };
  68. const static struct intel_device_info intel_i915gm_info = {
  69. .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
  70. .cursor_needs_physical = 1,
  71. };
  72. const static struct intel_device_info intel_i945g_info = {
  73. .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
  74. };
  75. const static struct intel_device_info intel_i945gm_info = {
  76. .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
  77. .has_hotplug = 1, .cursor_needs_physical = 1,
  78. };
  79. const static struct intel_device_info intel_i965g_info = {
  80. .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
  81. };
  82. const static struct intel_device_info intel_i965gm_info = {
  83. .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
  84. .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
  85. .has_hotplug = 1,
  86. };
  87. const static struct intel_device_info intel_g33_info = {
  88. .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  89. .has_hotplug = 1,
  90. };
  91. const static struct intel_device_info intel_g45_info = {
  92. .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  93. .has_pipe_cxsr = 1,
  94. .has_hotplug = 1,
  95. };
  96. const static struct intel_device_info intel_gm45_info = {
  97. .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
  98. .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
  99. .has_pipe_cxsr = 1,
  100. .has_hotplug = 1,
  101. };
  102. const static struct intel_device_info intel_pineview_info = {
  103. .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
  104. .need_gfx_hws = 1,
  105. .has_hotplug = 1,
  106. };
  107. const static struct intel_device_info intel_ironlake_d_info = {
  108. .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  109. .has_pipe_cxsr = 1,
  110. .has_hotplug = 1,
  111. };
  112. const static struct intel_device_info intel_ironlake_m_info = {
  113. .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
  114. .need_gfx_hws = 1, .has_rc6 = 1,
  115. .has_hotplug = 1,
  116. };
  117. const static struct pci_device_id pciidlist[] = {
  118. INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
  119. INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
  120. INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
  121. INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
  122. INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
  123. INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
  124. INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
  125. INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
  126. INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
  127. INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
  128. INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
  129. INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
  130. INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
  131. INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
  132. INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
  133. INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
  134. INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
  135. INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
  136. INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
  137. INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
  138. INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
  139. INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
  140. INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
  141. INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
  142. INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
  143. INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
  144. INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  145. INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  146. INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  147. INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  148. {0, 0, 0}
  149. };
  150. #if defined(CONFIG_DRM_I915_KMS)
  151. MODULE_DEVICE_TABLE(pci, pciidlist);
  152. #endif
  153. static int i915_suspend(struct drm_device *dev, pm_message_t state)
  154. {
  155. struct drm_i915_private *dev_priv = dev->dev_private;
  156. if (!dev || !dev_priv) {
  157. DRM_ERROR("dev: %p, dev_priv: %p\n", dev, dev_priv);
  158. DRM_ERROR("DRM not initialized, aborting suspend.\n");
  159. return -ENODEV;
  160. }
  161. if (state.event == PM_EVENT_PRETHAW)
  162. return 0;
  163. pci_save_state(dev->pdev);
  164. /* If KMS is active, we do the leavevt stuff here */
  165. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  166. if (i915_gem_idle(dev))
  167. dev_err(&dev->pdev->dev,
  168. "GEM idle failed, resume may fail\n");
  169. drm_irq_uninstall(dev);
  170. }
  171. i915_save_state(dev);
  172. intel_opregion_free(dev, 1);
  173. if (state.event == PM_EVENT_SUSPEND) {
  174. /* Shut down the device */
  175. pci_disable_device(dev->pdev);
  176. pci_set_power_state(dev->pdev, PCI_D3hot);
  177. }
  178. /* Modeset on resume, not lid events */
  179. dev_priv->modeset_on_lid = 0;
  180. return 0;
  181. }
  182. static int i915_resume(struct drm_device *dev)
  183. {
  184. struct drm_i915_private *dev_priv = dev->dev_private;
  185. int ret = 0;
  186. if (pci_enable_device(dev->pdev))
  187. return -1;
  188. pci_set_master(dev->pdev);
  189. i915_restore_state(dev);
  190. intel_opregion_init(dev, 1);
  191. /* KMS EnterVT equivalent */
  192. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  193. mutex_lock(&dev->struct_mutex);
  194. dev_priv->mm.suspended = 0;
  195. ret = i915_gem_init_ringbuffer(dev);
  196. if (ret != 0)
  197. ret = -1;
  198. mutex_unlock(&dev->struct_mutex);
  199. drm_irq_install(dev);
  200. }
  201. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  202. /* Resume the modeset for every activated CRTC */
  203. drm_helper_resume_force_mode(dev);
  204. }
  205. dev_priv->modeset_on_lid = 0;
  206. return ret;
  207. }
  208. /**
  209. * i965_reset - reset chip after a hang
  210. * @dev: drm device to reset
  211. * @flags: reset domains
  212. *
  213. * Reset the chip. Useful if a hang is detected. Returns zero on successful
  214. * reset or otherwise an error code.
  215. *
  216. * Procedure is fairly simple:
  217. * - reset the chip using the reset reg
  218. * - re-init context state
  219. * - re-init hardware status page
  220. * - re-init ring buffer
  221. * - re-init interrupt state
  222. * - re-init display
  223. */
  224. int i965_reset(struct drm_device *dev, u8 flags)
  225. {
  226. drm_i915_private_t *dev_priv = dev->dev_private;
  227. unsigned long timeout;
  228. u8 gdrst;
  229. /*
  230. * We really should only reset the display subsystem if we actually
  231. * need to
  232. */
  233. bool need_display = true;
  234. mutex_lock(&dev->struct_mutex);
  235. /*
  236. * Clear request list
  237. */
  238. i915_gem_retire_requests(dev);
  239. if (need_display)
  240. i915_save_display(dev);
  241. if (IS_I965G(dev) || IS_G4X(dev)) {
  242. /*
  243. * Set the domains we want to reset, then the reset bit (bit 0).
  244. * Clear the reset bit after a while and wait for hardware status
  245. * bit (bit 1) to be set
  246. */
  247. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  248. pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
  249. udelay(50);
  250. pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
  251. /* ...we don't want to loop forever though, 500ms should be plenty */
  252. timeout = jiffies + msecs_to_jiffies(500);
  253. do {
  254. udelay(100);
  255. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  256. } while ((gdrst & 0x1) && time_after(timeout, jiffies));
  257. if (gdrst & 0x1) {
  258. WARN(true, "i915: Failed to reset chip\n");
  259. mutex_unlock(&dev->struct_mutex);
  260. return -EIO;
  261. }
  262. } else {
  263. DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
  264. return -ENODEV;
  265. }
  266. /* Ok, now get things going again... */
  267. /*
  268. * Everything depends on having the GTT running, so we need to start
  269. * there. Fortunately we don't need to do this unless we reset the
  270. * chip at a PCI level.
  271. *
  272. * Next we need to restore the context, but we don't use those
  273. * yet either...
  274. *
  275. * Ring buffer needs to be re-initialized in the KMS case, or if X
  276. * was running at the time of the reset (i.e. we weren't VT
  277. * switched away).
  278. */
  279. if (drm_core_check_feature(dev, DRIVER_MODESET) ||
  280. !dev_priv->mm.suspended) {
  281. drm_i915_ring_buffer_t *ring = &dev_priv->ring;
  282. struct drm_gem_object *obj = ring->ring_obj;
  283. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  284. dev_priv->mm.suspended = 0;
  285. /* Stop the ring if it's running. */
  286. I915_WRITE(PRB0_CTL, 0);
  287. I915_WRITE(PRB0_TAIL, 0);
  288. I915_WRITE(PRB0_HEAD, 0);
  289. /* Initialize the ring. */
  290. I915_WRITE(PRB0_START, obj_priv->gtt_offset);
  291. I915_WRITE(PRB0_CTL,
  292. ((obj->size - 4096) & RING_NR_PAGES) |
  293. RING_NO_REPORT |
  294. RING_VALID);
  295. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  296. i915_kernel_lost_context(dev);
  297. else {
  298. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  299. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  300. ring->space = ring->head - (ring->tail + 8);
  301. if (ring->space < 0)
  302. ring->space += ring->Size;
  303. }
  304. mutex_unlock(&dev->struct_mutex);
  305. drm_irq_uninstall(dev);
  306. drm_irq_install(dev);
  307. mutex_lock(&dev->struct_mutex);
  308. }
  309. /*
  310. * Display needs restore too...
  311. */
  312. if (need_display)
  313. i915_restore_display(dev);
  314. mutex_unlock(&dev->struct_mutex);
  315. return 0;
  316. }
  317. static int __devinit
  318. i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  319. {
  320. return drm_get_dev(pdev, ent, &driver);
  321. }
  322. static void
  323. i915_pci_remove(struct pci_dev *pdev)
  324. {
  325. struct drm_device *dev = pci_get_drvdata(pdev);
  326. drm_put_dev(dev);
  327. }
  328. static int
  329. i915_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  330. {
  331. struct drm_device *dev = pci_get_drvdata(pdev);
  332. return i915_suspend(dev, state);
  333. }
  334. static int
  335. i915_pci_resume(struct pci_dev *pdev)
  336. {
  337. struct drm_device *dev = pci_get_drvdata(pdev);
  338. return i915_resume(dev);
  339. }
  340. static int
  341. i915_pm_suspend(struct device *dev)
  342. {
  343. return i915_pci_suspend(to_pci_dev(dev), PMSG_SUSPEND);
  344. }
  345. static int
  346. i915_pm_resume(struct device *dev)
  347. {
  348. return i915_pci_resume(to_pci_dev(dev));
  349. }
  350. static int
  351. i915_pm_freeze(struct device *dev)
  352. {
  353. return i915_pci_suspend(to_pci_dev(dev), PMSG_FREEZE);
  354. }
  355. static int
  356. i915_pm_thaw(struct device *dev)
  357. {
  358. /* thaw during hibernate, do nothing! */
  359. return 0;
  360. }
  361. static int
  362. i915_pm_poweroff(struct device *dev)
  363. {
  364. return i915_pci_suspend(to_pci_dev(dev), PMSG_HIBERNATE);
  365. }
  366. static int
  367. i915_pm_restore(struct device *dev)
  368. {
  369. return i915_pci_resume(to_pci_dev(dev));
  370. }
  371. const struct dev_pm_ops i915_pm_ops = {
  372. .suspend = i915_pm_suspend,
  373. .resume = i915_pm_resume,
  374. .freeze = i915_pm_freeze,
  375. .thaw = i915_pm_thaw,
  376. .poweroff = i915_pm_poweroff,
  377. .restore = i915_pm_restore,
  378. };
  379. static struct vm_operations_struct i915_gem_vm_ops = {
  380. .fault = i915_gem_fault,
  381. .open = drm_gem_vm_open,
  382. .close = drm_gem_vm_close,
  383. };
  384. static struct drm_driver driver = {
  385. /* don't use mtrr's here, the Xserver or user space app should
  386. * deal with them for intel hardware.
  387. */
  388. .driver_features =
  389. DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  390. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  391. .load = i915_driver_load,
  392. .unload = i915_driver_unload,
  393. .open = i915_driver_open,
  394. .lastclose = i915_driver_lastclose,
  395. .preclose = i915_driver_preclose,
  396. .postclose = i915_driver_postclose,
  397. /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  398. .suspend = i915_suspend,
  399. .resume = i915_resume,
  400. .device_is_agp = i915_driver_device_is_agp,
  401. .enable_vblank = i915_enable_vblank,
  402. .disable_vblank = i915_disable_vblank,
  403. .irq_preinstall = i915_driver_irq_preinstall,
  404. .irq_postinstall = i915_driver_irq_postinstall,
  405. .irq_uninstall = i915_driver_irq_uninstall,
  406. .irq_handler = i915_driver_irq_handler,
  407. .reclaim_buffers = drm_core_reclaim_buffers,
  408. .get_map_ofs = drm_core_get_map_ofs,
  409. .get_reg_ofs = drm_core_get_reg_ofs,
  410. .master_create = i915_master_create,
  411. .master_destroy = i915_master_destroy,
  412. #if defined(CONFIG_DEBUG_FS)
  413. .debugfs_init = i915_debugfs_init,
  414. .debugfs_cleanup = i915_debugfs_cleanup,
  415. #endif
  416. .gem_init_object = i915_gem_init_object,
  417. .gem_free_object = i915_gem_free_object,
  418. .gem_vm_ops = &i915_gem_vm_ops,
  419. .ioctls = i915_ioctls,
  420. .fops = {
  421. .owner = THIS_MODULE,
  422. .open = drm_open,
  423. .release = drm_release,
  424. .unlocked_ioctl = drm_ioctl,
  425. .mmap = drm_gem_mmap,
  426. .poll = drm_poll,
  427. .fasync = drm_fasync,
  428. .read = drm_read,
  429. #ifdef CONFIG_COMPAT
  430. .compat_ioctl = i915_compat_ioctl,
  431. #endif
  432. },
  433. .pci_driver = {
  434. .name = DRIVER_NAME,
  435. .id_table = pciidlist,
  436. .probe = i915_pci_probe,
  437. .remove = i915_pci_remove,
  438. .driver.pm = &i915_pm_ops,
  439. },
  440. .name = DRIVER_NAME,
  441. .desc = DRIVER_DESC,
  442. .date = DRIVER_DATE,
  443. .major = DRIVER_MAJOR,
  444. .minor = DRIVER_MINOR,
  445. .patchlevel = DRIVER_PATCHLEVEL,
  446. };
  447. static int __init i915_init(void)
  448. {
  449. driver.num_ioctls = i915_max_ioctl;
  450. i915_gem_shrinker_init();
  451. /*
  452. * If CONFIG_DRM_I915_KMS is set, default to KMS unless
  453. * explicitly disabled with the module pararmeter.
  454. *
  455. * Otherwise, just follow the parameter (defaulting to off).
  456. *
  457. * Allow optional vga_text_mode_force boot option to override
  458. * the default behavior.
  459. */
  460. #if defined(CONFIG_DRM_I915_KMS)
  461. if (i915_modeset != 0)
  462. driver.driver_features |= DRIVER_MODESET;
  463. #endif
  464. if (i915_modeset == 1)
  465. driver.driver_features |= DRIVER_MODESET;
  466. #ifdef CONFIG_VGA_CONSOLE
  467. if (vgacon_text_force() && i915_modeset == -1)
  468. driver.driver_features &= ~DRIVER_MODESET;
  469. #endif
  470. return drm_init(&driver);
  471. }
  472. static void __exit i915_exit(void)
  473. {
  474. i915_gem_shrinker_exit();
  475. drm_exit(&driver);
  476. }
  477. module_init(i915_init);
  478. module_exit(i915_exit);
  479. MODULE_AUTHOR(DRIVER_AUTHOR);
  480. MODULE_DESCRIPTION(DRIVER_DESC);
  481. MODULE_LICENSE("GPL and additional rights");