mce_amd.c 16 KB

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  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/interrupt.h>
  17. #include <linux/notifier.h>
  18. #include <linux/kobject.h>
  19. #include <linux/percpu.h>
  20. #include <linux/errno.h>
  21. #include <linux/sched.h>
  22. #include <linux/sysfs.h>
  23. #include <linux/slab.h>
  24. #include <linux/init.h>
  25. #include <linux/cpu.h>
  26. #include <linux/smp.h>
  27. #include <asm/apic.h>
  28. #include <asm/idle.h>
  29. #include <asm/mce.h>
  30. #include <asm/msr.h>
  31. #define NR_BANKS 6
  32. #define NR_BLOCKS 9
  33. #define THRESHOLD_MAX 0xFFF
  34. #define INT_TYPE_APIC 0x00020000
  35. #define MASK_VALID_HI 0x80000000
  36. #define MASK_CNTP_HI 0x40000000
  37. #define MASK_LOCKED_HI 0x20000000
  38. #define MASK_LVTOFF_HI 0x00F00000
  39. #define MASK_COUNT_EN_HI 0x00080000
  40. #define MASK_INT_TYPE_HI 0x00060000
  41. #define MASK_OVERFLOW_HI 0x00010000
  42. #define MASK_ERR_COUNT_HI 0x00000FFF
  43. #define MASK_BLKPTR_LO 0xFF000000
  44. #define MCG_XBLK_ADDR 0xC0000400
  45. struct threshold_block {
  46. unsigned int block;
  47. unsigned int bank;
  48. unsigned int cpu;
  49. u32 address;
  50. u16 interrupt_enable;
  51. u16 threshold_limit;
  52. struct kobject kobj;
  53. struct list_head miscj;
  54. };
  55. struct threshold_bank {
  56. struct kobject *kobj;
  57. struct threshold_block *blocks;
  58. cpumask_var_t cpus;
  59. };
  60. static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
  61. #ifdef CONFIG_SMP
  62. static unsigned char shared_bank[NR_BANKS] = {
  63. 0, 0, 0, 0, 1
  64. };
  65. #endif
  66. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  67. static void amd_threshold_interrupt(void);
  68. /*
  69. * CPU Initialization
  70. */
  71. struct thresh_restart {
  72. struct threshold_block *b;
  73. int reset;
  74. int set_lvt_off;
  75. int lvt_off;
  76. u16 old_limit;
  77. };
  78. static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
  79. {
  80. int msr = (hi & MASK_LVTOFF_HI) >> 20;
  81. if (apic < 0) {
  82. pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
  83. "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
  84. b->bank, b->block, b->address, hi, lo);
  85. return 0;
  86. }
  87. if (apic != msr) {
  88. pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
  89. "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
  90. b->cpu, apic, b->bank, b->block, b->address, hi, lo);
  91. return 0;
  92. }
  93. return 1;
  94. };
  95. /* must be called with correct cpu affinity */
  96. /* Called via smp_call_function_single() */
  97. static void threshold_restart_bank(void *_tr)
  98. {
  99. struct thresh_restart *tr = _tr;
  100. u32 hi, lo;
  101. rdmsr(tr->b->address, lo, hi);
  102. if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
  103. tr->reset = 1; /* limit cannot be lower than err count */
  104. if (tr->reset) { /* reset err count and overflow bit */
  105. hi =
  106. (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  107. (THRESHOLD_MAX - tr->b->threshold_limit);
  108. } else if (tr->old_limit) { /* change limit w/o reset */
  109. int new_count = (hi & THRESHOLD_MAX) +
  110. (tr->old_limit - tr->b->threshold_limit);
  111. hi = (hi & ~MASK_ERR_COUNT_HI) |
  112. (new_count & THRESHOLD_MAX);
  113. }
  114. if (tr->set_lvt_off) {
  115. if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
  116. /* set new lvt offset */
  117. hi &= ~MASK_LVTOFF_HI;
  118. hi |= tr->lvt_off << 20;
  119. }
  120. }
  121. tr->b->interrupt_enable ?
  122. (hi = (hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  123. (hi &= ~MASK_INT_TYPE_HI);
  124. hi |= MASK_COUNT_EN_HI;
  125. wrmsr(tr->b->address, lo, hi);
  126. }
  127. static void mce_threshold_block_init(struct threshold_block *b, int offset)
  128. {
  129. struct thresh_restart tr = {
  130. .b = b,
  131. .set_lvt_off = 1,
  132. .lvt_off = offset,
  133. };
  134. b->threshold_limit = THRESHOLD_MAX;
  135. threshold_restart_bank(&tr);
  136. };
  137. static int setup_APIC_mce(int reserved, int new)
  138. {
  139. if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
  140. APIC_EILVT_MSG_FIX, 0))
  141. return new;
  142. return reserved;
  143. }
  144. /* cpu init entry point, called from mce.c with preempt off */
  145. void mce_amd_feature_init(struct cpuinfo_x86 *c)
  146. {
  147. struct threshold_block b;
  148. unsigned int cpu = smp_processor_id();
  149. u32 low = 0, high = 0, address = 0;
  150. unsigned int bank, block;
  151. int offset = -1;
  152. for (bank = 0; bank < NR_BANKS; ++bank) {
  153. for (block = 0; block < NR_BLOCKS; ++block) {
  154. if (block == 0)
  155. address = MSR_IA32_MC0_MISC + bank * 4;
  156. else if (block == 1) {
  157. address = (low & MASK_BLKPTR_LO) >> 21;
  158. if (!address)
  159. break;
  160. address += MCG_XBLK_ADDR;
  161. } else
  162. ++address;
  163. if (rdmsr_safe(address, &low, &high))
  164. break;
  165. if (!(high & MASK_VALID_HI))
  166. continue;
  167. if (!(high & MASK_CNTP_HI) ||
  168. (high & MASK_LOCKED_HI))
  169. continue;
  170. if (!block)
  171. per_cpu(bank_map, cpu) |= (1 << bank);
  172. #ifdef CONFIG_SMP
  173. if (shared_bank[bank] && c->cpu_core_id)
  174. break;
  175. #endif
  176. offset = setup_APIC_mce(offset,
  177. (high & MASK_LVTOFF_HI) >> 20);
  178. memset(&b, 0, sizeof(b));
  179. b.cpu = cpu;
  180. b.bank = bank;
  181. b.block = block;
  182. b.address = address;
  183. mce_threshold_block_init(&b, offset);
  184. mce_threshold_vector = amd_threshold_interrupt;
  185. }
  186. }
  187. }
  188. /*
  189. * APIC Interrupt Handler
  190. */
  191. /*
  192. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  193. * the interrupt goes off when error_count reaches threshold_limit.
  194. * the handler will simply log mcelog w/ software defined bank number.
  195. */
  196. static void amd_threshold_interrupt(void)
  197. {
  198. u32 low = 0, high = 0, address = 0;
  199. unsigned int bank, block;
  200. struct mce m;
  201. mce_setup(&m);
  202. /* assume first bank caused it */
  203. for (bank = 0; bank < NR_BANKS; ++bank) {
  204. if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
  205. continue;
  206. for (block = 0; block < NR_BLOCKS; ++block) {
  207. if (block == 0) {
  208. address = MSR_IA32_MC0_MISC + bank * 4;
  209. } else if (block == 1) {
  210. address = (low & MASK_BLKPTR_LO) >> 21;
  211. if (!address)
  212. break;
  213. address += MCG_XBLK_ADDR;
  214. } else {
  215. ++address;
  216. }
  217. if (rdmsr_safe(address, &low, &high))
  218. break;
  219. if (!(high & MASK_VALID_HI)) {
  220. if (block)
  221. continue;
  222. else
  223. break;
  224. }
  225. if (!(high & MASK_CNTP_HI) ||
  226. (high & MASK_LOCKED_HI))
  227. continue;
  228. /*
  229. * Log the machine check that caused the threshold
  230. * event.
  231. */
  232. machine_check_poll(MCP_TIMESTAMP,
  233. &__get_cpu_var(mce_poll_banks));
  234. if (high & MASK_OVERFLOW_HI) {
  235. rdmsrl(address, m.misc);
  236. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  237. m.status);
  238. m.bank = K8_MCE_THRESHOLD_BASE
  239. + bank * NR_BLOCKS
  240. + block;
  241. mce_log(&m);
  242. return;
  243. }
  244. }
  245. }
  246. }
  247. /*
  248. * Sysfs Interface
  249. */
  250. struct threshold_attr {
  251. struct attribute attr;
  252. ssize_t (*show) (struct threshold_block *, char *);
  253. ssize_t (*store) (struct threshold_block *, const char *, size_t count);
  254. };
  255. #define SHOW_FIELDS(name) \
  256. static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
  257. { \
  258. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  259. }
  260. SHOW_FIELDS(interrupt_enable)
  261. SHOW_FIELDS(threshold_limit)
  262. static ssize_t
  263. store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
  264. {
  265. struct thresh_restart tr;
  266. unsigned long new;
  267. if (strict_strtoul(buf, 0, &new) < 0)
  268. return -EINVAL;
  269. b->interrupt_enable = !!new;
  270. memset(&tr, 0, sizeof(tr));
  271. tr.b = b;
  272. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  273. return size;
  274. }
  275. static ssize_t
  276. store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
  277. {
  278. struct thresh_restart tr;
  279. unsigned long new;
  280. if (strict_strtoul(buf, 0, &new) < 0)
  281. return -EINVAL;
  282. if (new > THRESHOLD_MAX)
  283. new = THRESHOLD_MAX;
  284. if (new < 1)
  285. new = 1;
  286. memset(&tr, 0, sizeof(tr));
  287. tr.old_limit = b->threshold_limit;
  288. b->threshold_limit = new;
  289. tr.b = b;
  290. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  291. return size;
  292. }
  293. struct threshold_block_cross_cpu {
  294. struct threshold_block *tb;
  295. long retval;
  296. };
  297. static void local_error_count_handler(void *_tbcc)
  298. {
  299. struct threshold_block_cross_cpu *tbcc = _tbcc;
  300. struct threshold_block *b = tbcc->tb;
  301. u32 low, high;
  302. rdmsr(b->address, low, high);
  303. tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
  304. }
  305. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  306. {
  307. struct threshold_block_cross_cpu tbcc = { .tb = b, };
  308. smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
  309. return sprintf(buf, "%lx\n", tbcc.retval);
  310. }
  311. static ssize_t store_error_count(struct threshold_block *b,
  312. const char *buf, size_t count)
  313. {
  314. struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
  315. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  316. return 1;
  317. }
  318. #define RW_ATTR(val) \
  319. static struct threshold_attr val = { \
  320. .attr = {.name = __stringify(val), .mode = 0644 }, \
  321. .show = show_## val, \
  322. .store = store_## val, \
  323. };
  324. RW_ATTR(interrupt_enable);
  325. RW_ATTR(threshold_limit);
  326. RW_ATTR(error_count);
  327. static struct attribute *default_attrs[] = {
  328. &interrupt_enable.attr,
  329. &threshold_limit.attr,
  330. &error_count.attr,
  331. NULL
  332. };
  333. #define to_block(k) container_of(k, struct threshold_block, kobj)
  334. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  335. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  336. {
  337. struct threshold_block *b = to_block(kobj);
  338. struct threshold_attr *a = to_attr(attr);
  339. ssize_t ret;
  340. ret = a->show ? a->show(b, buf) : -EIO;
  341. return ret;
  342. }
  343. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  344. const char *buf, size_t count)
  345. {
  346. struct threshold_block *b = to_block(kobj);
  347. struct threshold_attr *a = to_attr(attr);
  348. ssize_t ret;
  349. ret = a->store ? a->store(b, buf, count) : -EIO;
  350. return ret;
  351. }
  352. static const struct sysfs_ops threshold_ops = {
  353. .show = show,
  354. .store = store,
  355. };
  356. static struct kobj_type threshold_ktype = {
  357. .sysfs_ops = &threshold_ops,
  358. .default_attrs = default_attrs,
  359. };
  360. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  361. unsigned int bank,
  362. unsigned int block,
  363. u32 address)
  364. {
  365. struct threshold_block *b = NULL;
  366. u32 low, high;
  367. int err;
  368. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  369. return 0;
  370. if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
  371. return 0;
  372. if (!(high & MASK_VALID_HI)) {
  373. if (block)
  374. goto recurse;
  375. else
  376. return 0;
  377. }
  378. if (!(high & MASK_CNTP_HI) ||
  379. (high & MASK_LOCKED_HI))
  380. goto recurse;
  381. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  382. if (!b)
  383. return -ENOMEM;
  384. b->block = block;
  385. b->bank = bank;
  386. b->cpu = cpu;
  387. b->address = address;
  388. b->interrupt_enable = 0;
  389. b->threshold_limit = THRESHOLD_MAX;
  390. INIT_LIST_HEAD(&b->miscj);
  391. if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
  392. list_add(&b->miscj,
  393. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  394. } else {
  395. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  396. }
  397. err = kobject_init_and_add(&b->kobj, &threshold_ktype,
  398. per_cpu(threshold_banks, cpu)[bank]->kobj,
  399. "misc%i", block);
  400. if (err)
  401. goto out_free;
  402. recurse:
  403. if (!block) {
  404. address = (low & MASK_BLKPTR_LO) >> 21;
  405. if (!address)
  406. return 0;
  407. address += MCG_XBLK_ADDR;
  408. } else {
  409. ++address;
  410. }
  411. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  412. if (err)
  413. goto out_free;
  414. if (b)
  415. kobject_uevent(&b->kobj, KOBJ_ADD);
  416. return err;
  417. out_free:
  418. if (b) {
  419. kobject_put(&b->kobj);
  420. list_del(&b->miscj);
  421. kfree(b);
  422. }
  423. return err;
  424. }
  425. static __cpuinit long
  426. local_allocate_threshold_blocks(int cpu, unsigned int bank)
  427. {
  428. return allocate_threshold_blocks(cpu, bank, 0,
  429. MSR_IA32_MC0_MISC + bank * 4);
  430. }
  431. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  432. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  433. {
  434. int i, err = 0;
  435. struct threshold_bank *b = NULL;
  436. char name[32];
  437. sprintf(name, "threshold_bank%i", bank);
  438. #ifdef CONFIG_SMP
  439. if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
  440. i = cpumask_first(cpu_llc_shared_mask(cpu));
  441. /* first core not up yet */
  442. if (cpu_data(i).cpu_core_id)
  443. goto out;
  444. /* already linked */
  445. if (per_cpu(threshold_banks, cpu)[bank])
  446. goto out;
  447. b = per_cpu(threshold_banks, i)[bank];
  448. if (!b)
  449. goto out;
  450. err = sysfs_create_link(&per_cpu(mce_device, cpu).kobj,
  451. b->kobj, name);
  452. if (err)
  453. goto out;
  454. cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));
  455. per_cpu(threshold_banks, cpu)[bank] = b;
  456. goto out;
  457. }
  458. #endif
  459. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  460. if (!b) {
  461. err = -ENOMEM;
  462. goto out;
  463. }
  464. if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
  465. kfree(b);
  466. err = -ENOMEM;
  467. goto out;
  468. }
  469. b->kobj = kobject_create_and_add(name, &per_cpu(mce_device, cpu).kobj);
  470. if (!b->kobj)
  471. goto out_free;
  472. #ifndef CONFIG_SMP
  473. cpumask_setall(b->cpus);
  474. #else
  475. cpumask_set_cpu(cpu, b->cpus);
  476. #endif
  477. per_cpu(threshold_banks, cpu)[bank] = b;
  478. err = local_allocate_threshold_blocks(cpu, bank);
  479. if (err)
  480. goto out_free;
  481. for_each_cpu(i, b->cpus) {
  482. if (i == cpu)
  483. continue;
  484. err = sysfs_create_link(&per_cpu(mce_device, i).kobj,
  485. b->kobj, name);
  486. if (err)
  487. goto out;
  488. per_cpu(threshold_banks, i)[bank] = b;
  489. }
  490. goto out;
  491. out_free:
  492. per_cpu(threshold_banks, cpu)[bank] = NULL;
  493. free_cpumask_var(b->cpus);
  494. kfree(b);
  495. out:
  496. return err;
  497. }
  498. /* create dir/files for all valid threshold banks */
  499. static __cpuinit int threshold_create_device(unsigned int cpu)
  500. {
  501. unsigned int bank;
  502. int err = 0;
  503. for (bank = 0; bank < NR_BANKS; ++bank) {
  504. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  505. continue;
  506. err = threshold_create_bank(cpu, bank);
  507. if (err)
  508. return err;
  509. }
  510. return err;
  511. }
  512. /*
  513. * let's be hotplug friendly.
  514. * in case of multiple core processors, the first core always takes ownership
  515. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  516. */
  517. static void deallocate_threshold_block(unsigned int cpu,
  518. unsigned int bank)
  519. {
  520. struct threshold_block *pos = NULL;
  521. struct threshold_block *tmp = NULL;
  522. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  523. if (!head)
  524. return;
  525. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  526. kobject_put(&pos->kobj);
  527. list_del(&pos->miscj);
  528. kfree(pos);
  529. }
  530. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  531. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  532. }
  533. static void threshold_remove_bank(unsigned int cpu, int bank)
  534. {
  535. struct threshold_bank *b;
  536. char name[32];
  537. int i = 0;
  538. b = per_cpu(threshold_banks, cpu)[bank];
  539. if (!b)
  540. return;
  541. if (!b->blocks)
  542. goto free_out;
  543. sprintf(name, "threshold_bank%i", bank);
  544. #ifdef CONFIG_SMP
  545. /* sibling symlink */
  546. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  547. sysfs_remove_link(&per_cpu(mce_device, cpu).kobj, name);
  548. per_cpu(threshold_banks, cpu)[bank] = NULL;
  549. return;
  550. }
  551. #endif
  552. /* remove all sibling symlinks before unregistering */
  553. for_each_cpu(i, b->cpus) {
  554. if (i == cpu)
  555. continue;
  556. sysfs_remove_link(&per_cpu(mce_device, i).kobj, name);
  557. per_cpu(threshold_banks, i)[bank] = NULL;
  558. }
  559. deallocate_threshold_block(cpu, bank);
  560. free_out:
  561. kobject_del(b->kobj);
  562. kobject_put(b->kobj);
  563. free_cpumask_var(b->cpus);
  564. kfree(b);
  565. per_cpu(threshold_banks, cpu)[bank] = NULL;
  566. }
  567. static void threshold_remove_device(unsigned int cpu)
  568. {
  569. unsigned int bank;
  570. for (bank = 0; bank < NR_BANKS; ++bank) {
  571. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  572. continue;
  573. threshold_remove_bank(cpu, bank);
  574. }
  575. }
  576. /* get notified when a cpu comes on/off */
  577. static void __cpuinit
  578. amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
  579. {
  580. switch (action) {
  581. case CPU_ONLINE:
  582. case CPU_ONLINE_FROZEN:
  583. threshold_create_device(cpu);
  584. break;
  585. case CPU_DEAD:
  586. case CPU_DEAD_FROZEN:
  587. threshold_remove_device(cpu);
  588. break;
  589. default:
  590. break;
  591. }
  592. }
  593. static __init int threshold_init_device(void)
  594. {
  595. unsigned lcpu = 0;
  596. /* to hit CPUs online before the notifier is up */
  597. for_each_online_cpu(lcpu) {
  598. int err = threshold_create_device(lcpu);
  599. if (err)
  600. return err;
  601. }
  602. threshold_cpu_callback = amd_64_threshold_cpu_callback;
  603. return 0;
  604. }
  605. device_initcall(threshold_init_device);