sh_mobile_meram.c 18 KB

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  1. /*
  2. * SuperH Mobile MERAM Driver for SuperH Mobile LCDC Driver
  3. *
  4. * Copyright (c) 2011 Damian Hobson-Garcia <dhobsong@igel.co.jp>
  5. * Takanari Hayama <taki@igel.co.jp>
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/device.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/io.h>
  16. #include <linux/slab.h>
  17. #include <linux/platform_device.h>
  18. #include <video/sh_mobile_meram.h>
  19. /* meram registers */
  20. #define MEVCR1 0x4
  21. #define MEVCR1_RST (1 << 31)
  22. #define MEVCR1_WD (1 << 30)
  23. #define MEVCR1_AMD1 (1 << 29)
  24. #define MEVCR1_AMD0 (1 << 28)
  25. #define MEQSEL1 0x40
  26. #define MEQSEL2 0x44
  27. #define MExxCTL 0x400
  28. #define MExxCTL_BV (1 << 31)
  29. #define MExxCTL_BSZ_SHIFT 28
  30. #define MExxCTL_MSAR_MASK (0x7ff << MExxCTL_MSAR_SHIFT)
  31. #define MExxCTL_MSAR_SHIFT 16
  32. #define MExxCTL_NXT_MASK (0x1f << MExxCTL_NXT_SHIFT)
  33. #define MExxCTL_NXT_SHIFT 11
  34. #define MExxCTL_WD1 (1 << 10)
  35. #define MExxCTL_WD0 (1 << 9)
  36. #define MExxCTL_WS (1 << 8)
  37. #define MExxCTL_CB (1 << 7)
  38. #define MExxCTL_WBF (1 << 6)
  39. #define MExxCTL_WF (1 << 5)
  40. #define MExxCTL_RF (1 << 4)
  41. #define MExxCTL_CM (1 << 3)
  42. #define MExxCTL_MD_READ (1 << 0)
  43. #define MExxCTL_MD_WRITE (2 << 0)
  44. #define MExxCTL_MD_ICB_WB (3 << 0)
  45. #define MExxCTL_MD_ICB (4 << 0)
  46. #define MExxCTL_MD_FB (7 << 0)
  47. #define MExxCTL_MD_MASK (7 << 0)
  48. #define MExxBSIZE 0x404
  49. #define MExxBSIZE_RCNT_SHIFT 28
  50. #define MExxBSIZE_YSZM1_SHIFT 16
  51. #define MExxBSIZE_XSZM1_SHIFT 0
  52. #define MExxMNCF 0x408
  53. #define MExxMNCF_KWBNM_SHIFT 28
  54. #define MExxMNCF_KRBNM_SHIFT 24
  55. #define MExxMNCF_BNM_SHIFT 16
  56. #define MExxMNCF_XBV (1 << 15)
  57. #define MExxMNCF_CPL_YCBCR444 (1 << 12)
  58. #define MExxMNCF_CPL_YCBCR420 (2 << 12)
  59. #define MExxMNCF_CPL_YCBCR422 (3 << 12)
  60. #define MExxMNCF_CPL_MSK (3 << 12)
  61. #define MExxMNCF_BL (1 << 2)
  62. #define MExxMNCF_LNM_SHIFT 0
  63. #define MExxSARA 0x410
  64. #define MExxSARB 0x414
  65. #define MExxSBSIZE 0x418
  66. #define MExxSBSIZE_HDV (1 << 31)
  67. #define MExxSBSIZE_HSZ16 (0 << 28)
  68. #define MExxSBSIZE_HSZ32 (1 << 28)
  69. #define MExxSBSIZE_HSZ64 (2 << 28)
  70. #define MExxSBSIZE_HSZ128 (3 << 28)
  71. #define MExxSBSIZE_SBSIZZ_SHIFT 0
  72. #define MERAM_MExxCTL_VAL(next, addr) \
  73. ((((next) << MExxCTL_NXT_SHIFT) & MExxCTL_NXT_MASK) | \
  74. (((addr) << MExxCTL_MSAR_SHIFT) & MExxCTL_MSAR_MASK))
  75. #define MERAM_MExxBSIZE_VAL(rcnt, yszm1, xszm1) \
  76. (((rcnt) << MExxBSIZE_RCNT_SHIFT) | \
  77. ((yszm1) << MExxBSIZE_YSZM1_SHIFT) | \
  78. ((xszm1) << MExxBSIZE_XSZM1_SHIFT))
  79. #define SH_MOBILE_MERAM_ICB_NUM 32
  80. static unsigned long common_regs[] = {
  81. MEVCR1,
  82. MEQSEL1,
  83. MEQSEL2,
  84. };
  85. #define CMN_REGS_SIZE ARRAY_SIZE(common_regs)
  86. static unsigned long icb_regs[] = {
  87. MExxCTL,
  88. MExxBSIZE,
  89. MExxMNCF,
  90. MExxSARA,
  91. MExxSARB,
  92. MExxSBSIZE,
  93. };
  94. #define ICB_REGS_SIZE ARRAY_SIZE(icb_regs)
  95. struct sh_mobile_meram_priv {
  96. void __iomem *base;
  97. struct mutex lock;
  98. unsigned long used_icb;
  99. int used_meram_cache_regions;
  100. unsigned long used_meram_cache[SH_MOBILE_MERAM_ICB_NUM];
  101. unsigned long cmn_saved_regs[CMN_REGS_SIZE];
  102. unsigned long icb_saved_regs[ICB_REGS_SIZE * SH_MOBILE_MERAM_ICB_NUM];
  103. };
  104. /* settings */
  105. #define MERAM_SEC_LINE 15
  106. #define MERAM_LINE_WIDTH 2048
  107. /*
  108. * MERAM/ICB access functions
  109. */
  110. #define MERAM_ICB_OFFSET(base, idx, off) ((base) + (off) + (idx) * 0x20)
  111. static inline void meram_write_icb(void __iomem *base, int idx, int off,
  112. unsigned long val)
  113. {
  114. iowrite32(val, MERAM_ICB_OFFSET(base, idx, off));
  115. }
  116. static inline unsigned long meram_read_icb(void __iomem *base, int idx, int off)
  117. {
  118. return ioread32(MERAM_ICB_OFFSET(base, idx, off));
  119. }
  120. static inline void meram_write_reg(void __iomem *base, int off,
  121. unsigned long val)
  122. {
  123. iowrite32(val, base + off);
  124. }
  125. static inline unsigned long meram_read_reg(void __iomem *base, int off)
  126. {
  127. return ioread32(base + off);
  128. }
  129. /*
  130. * register ICB
  131. */
  132. #define MERAM_CACHE_START(p) ((p) >> 16)
  133. #define MERAM_CACHE_END(p) ((p) & 0xffff)
  134. #define MERAM_CACHE_SET(o, s) ((((o) & 0xffff) << 16) | \
  135. (((o) + (s) - 1) & 0xffff))
  136. /*
  137. * check if there's no overlaps in MERAM allocation.
  138. */
  139. static inline int meram_check_overlap(struct sh_mobile_meram_priv *priv,
  140. struct sh_mobile_meram_icb *new)
  141. {
  142. int i;
  143. int used_start, used_end, meram_start, meram_end;
  144. /* valid ICB? */
  145. if (new->marker_icb & ~0x1f || new->cache_icb & ~0x1f)
  146. return 1;
  147. if (test_bit(new->marker_icb, &priv->used_icb) ||
  148. test_bit(new->cache_icb, &priv->used_icb))
  149. return 1;
  150. for (i = 0; i < priv->used_meram_cache_regions; i++) {
  151. used_start = MERAM_CACHE_START(priv->used_meram_cache[i]);
  152. used_end = MERAM_CACHE_END(priv->used_meram_cache[i]);
  153. meram_start = new->meram_offset;
  154. meram_end = new->meram_offset + new->meram_size;
  155. if ((meram_start >= used_start && meram_start < used_end) ||
  156. (meram_end > used_start && meram_end < used_end))
  157. return 1;
  158. }
  159. return 0;
  160. }
  161. /*
  162. * mark the specified ICB as used
  163. */
  164. static inline void meram_mark(struct sh_mobile_meram_priv *priv,
  165. struct sh_mobile_meram_icb *new)
  166. {
  167. int n;
  168. if (new->marker_icb < 0 || new->cache_icb < 0)
  169. return;
  170. __set_bit(new->marker_icb, &priv->used_icb);
  171. __set_bit(new->cache_icb, &priv->used_icb);
  172. n = priv->used_meram_cache_regions;
  173. priv->used_meram_cache[n] = MERAM_CACHE_SET(new->meram_offset,
  174. new->meram_size);
  175. priv->used_meram_cache_regions++;
  176. }
  177. /*
  178. * unmark the specified ICB as used
  179. */
  180. static inline void meram_unmark(struct sh_mobile_meram_priv *priv,
  181. struct sh_mobile_meram_icb *icb)
  182. {
  183. int i;
  184. unsigned long pattern;
  185. if (icb->marker_icb < 0 || icb->cache_icb < 0)
  186. return;
  187. __clear_bit(icb->marker_icb, &priv->used_icb);
  188. __clear_bit(icb->cache_icb, &priv->used_icb);
  189. pattern = MERAM_CACHE_SET(icb->meram_offset, icb->meram_size);
  190. for (i = 0; i < priv->used_meram_cache_regions; i++) {
  191. if (priv->used_meram_cache[i] == pattern) {
  192. while (i < priv->used_meram_cache_regions - 1) {
  193. priv->used_meram_cache[i] =
  194. priv->used_meram_cache[i + 1] ;
  195. i++;
  196. }
  197. priv->used_meram_cache[i] = 0;
  198. priv->used_meram_cache_regions--;
  199. break;
  200. }
  201. }
  202. }
  203. /*
  204. * is this a YCbCr(NV12, NV16 or NV24) colorspace
  205. */
  206. static inline int is_nvcolor(int cspace)
  207. {
  208. if (cspace == SH_MOBILE_MERAM_PF_NV ||
  209. cspace == SH_MOBILE_MERAM_PF_NV24)
  210. return 1;
  211. return 0;
  212. }
  213. /*
  214. * set the next address to fetch
  215. */
  216. static inline void meram_set_next_addr(struct sh_mobile_meram_priv *priv,
  217. struct sh_mobile_meram_cfg *cfg,
  218. unsigned long base_addr_y,
  219. unsigned long base_addr_c)
  220. {
  221. unsigned long target;
  222. target = (cfg->current_reg) ? MExxSARA : MExxSARB;
  223. cfg->current_reg ^= 1;
  224. /* set the next address to fetch */
  225. meram_write_icb(priv->base, cfg->icb[0].cache_icb, target,
  226. base_addr_y);
  227. meram_write_icb(priv->base, cfg->icb[0].marker_icb, target,
  228. base_addr_y + cfg->icb[0].cache_unit);
  229. if (is_nvcolor(cfg->pixelformat)) {
  230. meram_write_icb(priv->base, cfg->icb[1].cache_icb, target,
  231. base_addr_c);
  232. meram_write_icb(priv->base, cfg->icb[1].marker_icb, target,
  233. base_addr_c + cfg->icb[1].cache_unit);
  234. }
  235. }
  236. /*
  237. * get the next ICB address
  238. */
  239. static inline void meram_get_next_icb_addr(struct sh_mobile_meram_info *pdata,
  240. struct sh_mobile_meram_cfg *cfg,
  241. unsigned long *icb_addr_y,
  242. unsigned long *icb_addr_c)
  243. {
  244. unsigned long icb_offset;
  245. if (pdata->addr_mode == SH_MOBILE_MERAM_MODE0)
  246. icb_offset = 0x80000000 | (cfg->current_reg << 29);
  247. else
  248. icb_offset = 0xc0000000 | (cfg->current_reg << 23);
  249. *icb_addr_y = icb_offset | (cfg->icb[0].marker_icb << 24);
  250. if (is_nvcolor(cfg->pixelformat))
  251. *icb_addr_c = icb_offset | (cfg->icb[1].marker_icb << 24);
  252. }
  253. #define MERAM_CALC_BYTECOUNT(x, y) \
  254. (((x) * (y) + (MERAM_LINE_WIDTH - 1)) & ~(MERAM_LINE_WIDTH - 1))
  255. /*
  256. * initialize MERAM
  257. */
  258. static int meram_init(struct sh_mobile_meram_priv *priv,
  259. struct sh_mobile_meram_icb *icb,
  260. int xres, int yres, int *out_pitch)
  261. {
  262. unsigned long total_byte_count = MERAM_CALC_BYTECOUNT(xres, yres);
  263. unsigned long bnm;
  264. int lcdc_pitch, xpitch, line_cnt;
  265. int save_lines;
  266. /* adjust pitch to 1024, 2048, 4096 or 8192 */
  267. lcdc_pitch = (xres - 1) | 1023;
  268. lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 1);
  269. lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 2);
  270. lcdc_pitch += 1;
  271. /* derive settings */
  272. if (lcdc_pitch == 8192 && yres >= 1024) {
  273. lcdc_pitch = xpitch = MERAM_LINE_WIDTH;
  274. line_cnt = total_byte_count >> 11;
  275. *out_pitch = xres;
  276. save_lines = (icb->meram_size / 16 / MERAM_SEC_LINE);
  277. save_lines *= MERAM_SEC_LINE;
  278. } else {
  279. xpitch = xres;
  280. line_cnt = yres;
  281. *out_pitch = lcdc_pitch;
  282. save_lines = icb->meram_size / (lcdc_pitch >> 10) / 2;
  283. save_lines &= 0xff;
  284. }
  285. bnm = (save_lines - 1) << 16;
  286. /* TODO: we better to check if we have enough MERAM buffer size */
  287. /* set up ICB */
  288. meram_write_icb(priv->base, icb->cache_icb, MExxBSIZE,
  289. MERAM_MExxBSIZE_VAL(0x0, line_cnt - 1, xpitch - 1));
  290. meram_write_icb(priv->base, icb->marker_icb, MExxBSIZE,
  291. MERAM_MExxBSIZE_VAL(0xf, line_cnt - 1, xpitch - 1));
  292. meram_write_icb(priv->base, icb->cache_icb, MExxMNCF, bnm);
  293. meram_write_icb(priv->base, icb->marker_icb, MExxMNCF, bnm);
  294. meram_write_icb(priv->base, icb->cache_icb, MExxSBSIZE, xpitch);
  295. meram_write_icb(priv->base, icb->marker_icb, MExxSBSIZE, xpitch);
  296. /* save a cache unit size */
  297. icb->cache_unit = xres * save_lines;
  298. /*
  299. * Set MERAM for framebuffer
  300. *
  301. * we also chain the cache_icb and the marker_icb.
  302. * we also split the allocated MERAM buffer between two ICBs.
  303. */
  304. meram_write_icb(priv->base, icb->cache_icb, MExxCTL,
  305. MERAM_MExxCTL_VAL(icb->marker_icb, icb->meram_offset) |
  306. MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
  307. MExxCTL_MD_FB);
  308. meram_write_icb(priv->base, icb->marker_icb, MExxCTL,
  309. MERAM_MExxCTL_VAL(icb->cache_icb, icb->meram_offset +
  310. icb->meram_size / 2) |
  311. MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
  312. MExxCTL_MD_FB);
  313. return 0;
  314. }
  315. static void meram_deinit(struct sh_mobile_meram_priv *priv,
  316. struct sh_mobile_meram_icb *icb)
  317. {
  318. /* disable ICB */
  319. meram_write_icb(priv->base, icb->cache_icb, MExxCTL, 0);
  320. meram_write_icb(priv->base, icb->marker_icb, MExxCTL, 0);
  321. icb->cache_unit = 0;
  322. }
  323. /*
  324. * register the ICB
  325. */
  326. static int sh_mobile_meram_register(struct sh_mobile_meram_info *pdata,
  327. struct sh_mobile_meram_cfg *cfg,
  328. int xres, int yres, int pixelformat,
  329. unsigned long base_addr_y,
  330. unsigned long base_addr_c,
  331. unsigned long *icb_addr_y,
  332. unsigned long *icb_addr_c,
  333. int *pitch)
  334. {
  335. struct platform_device *pdev;
  336. struct sh_mobile_meram_priv *priv;
  337. int n, out_pitch;
  338. int error = 0;
  339. if (!pdata || !pdata->priv || !pdata->pdev || !cfg)
  340. return -EINVAL;
  341. if (pixelformat != SH_MOBILE_MERAM_PF_NV &&
  342. pixelformat != SH_MOBILE_MERAM_PF_NV24 &&
  343. pixelformat != SH_MOBILE_MERAM_PF_RGB)
  344. return -EINVAL;
  345. priv = pdata->priv;
  346. pdev = pdata->pdev;
  347. dev_dbg(&pdev->dev, "registering %dx%d (%s) (y=%08lx, c=%08lx)",
  348. xres, yres, (!pixelformat) ? "yuv" : "rgb",
  349. base_addr_y, base_addr_c);
  350. /* we can't handle wider than 8192px */
  351. if (xres > 8192) {
  352. dev_err(&pdev->dev, "width exceeding the limit (> 8192).");
  353. return -EINVAL;
  354. }
  355. /* do we have at least one ICB config? */
  356. if (cfg->icb[0].marker_icb < 0 || cfg->icb[0].cache_icb < 0) {
  357. dev_err(&pdev->dev, "at least one ICB is required.");
  358. return -EINVAL;
  359. }
  360. mutex_lock(&priv->lock);
  361. if (priv->used_meram_cache_regions + 2 > SH_MOBILE_MERAM_ICB_NUM) {
  362. dev_err(&pdev->dev, "no more ICB available.");
  363. error = -EINVAL;
  364. goto err;
  365. }
  366. /* make sure that there's no overlaps */
  367. if (meram_check_overlap(priv, &cfg->icb[0])) {
  368. dev_err(&pdev->dev, "conflicting config detected.");
  369. error = -EINVAL;
  370. goto err;
  371. }
  372. n = 1;
  373. /* do the same if we have the second ICB set */
  374. if (cfg->icb[1].marker_icb >= 0 && cfg->icb[1].cache_icb >= 0) {
  375. if (meram_check_overlap(priv, &cfg->icb[1])) {
  376. dev_err(&pdev->dev, "conflicting config detected.");
  377. error = -EINVAL;
  378. goto err;
  379. }
  380. n = 2;
  381. }
  382. if (is_nvcolor(pixelformat) && n != 2) {
  383. dev_err(&pdev->dev, "requires two ICB sets for planar Y/C.");
  384. error = -EINVAL;
  385. goto err;
  386. }
  387. /* we now register the ICB */
  388. cfg->pixelformat = pixelformat;
  389. meram_mark(priv, &cfg->icb[0]);
  390. if (is_nvcolor(pixelformat))
  391. meram_mark(priv, &cfg->icb[1]);
  392. /* initialize MERAM */
  393. meram_init(priv, &cfg->icb[0], xres, yres, &out_pitch);
  394. *pitch = out_pitch;
  395. if (pixelformat == SH_MOBILE_MERAM_PF_NV)
  396. meram_init(priv, &cfg->icb[1], xres, (yres + 1) / 2,
  397. &out_pitch);
  398. else if (pixelformat == SH_MOBILE_MERAM_PF_NV24)
  399. meram_init(priv, &cfg->icb[1], 2 * xres, (yres + 1) / 2,
  400. &out_pitch);
  401. cfg->current_reg = 1;
  402. meram_set_next_addr(priv, cfg, base_addr_y, base_addr_c);
  403. meram_get_next_icb_addr(pdata, cfg, icb_addr_y, icb_addr_c);
  404. dev_dbg(&pdev->dev, "registered - can access via y=%08lx, c=%08lx",
  405. *icb_addr_y, *icb_addr_c);
  406. err:
  407. mutex_unlock(&priv->lock);
  408. return error;
  409. }
  410. static int sh_mobile_meram_unregister(struct sh_mobile_meram_info *pdata,
  411. struct sh_mobile_meram_cfg *cfg)
  412. {
  413. struct sh_mobile_meram_priv *priv;
  414. if (!pdata || !pdata->priv || !cfg)
  415. return -EINVAL;
  416. priv = pdata->priv;
  417. mutex_lock(&priv->lock);
  418. /* deinit & unmark */
  419. if (is_nvcolor(cfg->pixelformat)) {
  420. meram_deinit(priv, &cfg->icb[1]);
  421. meram_unmark(priv, &cfg->icb[1]);
  422. }
  423. meram_deinit(priv, &cfg->icb[0]);
  424. meram_unmark(priv, &cfg->icb[0]);
  425. mutex_unlock(&priv->lock);
  426. return 0;
  427. }
  428. static int sh_mobile_meram_update(struct sh_mobile_meram_info *pdata,
  429. struct sh_mobile_meram_cfg *cfg,
  430. unsigned long base_addr_y,
  431. unsigned long base_addr_c,
  432. unsigned long *icb_addr_y,
  433. unsigned long *icb_addr_c)
  434. {
  435. struct sh_mobile_meram_priv *priv;
  436. if (!pdata || !pdata->priv || !cfg)
  437. return -EINVAL;
  438. priv = pdata->priv;
  439. mutex_lock(&priv->lock);
  440. meram_set_next_addr(priv, cfg, base_addr_y, base_addr_c);
  441. meram_get_next_icb_addr(pdata, cfg, icb_addr_y, icb_addr_c);
  442. mutex_unlock(&priv->lock);
  443. return 0;
  444. }
  445. static int sh_mobile_meram_runtime_suspend(struct device *dev)
  446. {
  447. struct platform_device *pdev = to_platform_device(dev);
  448. struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
  449. int k, j;
  450. for (k = 0; k < CMN_REGS_SIZE; k++)
  451. priv->cmn_saved_regs[k] = meram_read_reg(priv->base,
  452. common_regs[k]);
  453. for (j = 0; j < 32; j++) {
  454. if (!test_bit(j, &priv->used_icb))
  455. continue;
  456. for (k = 0; k < ICB_REGS_SIZE; k++) {
  457. priv->icb_saved_regs[j * ICB_REGS_SIZE + k] =
  458. meram_read_icb(priv->base, j, icb_regs[k]);
  459. /* Reset ICB on resume */
  460. if (icb_regs[k] == MExxCTL)
  461. priv->icb_saved_regs[j * ICB_REGS_SIZE + k] |=
  462. MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF;
  463. }
  464. }
  465. return 0;
  466. }
  467. static int sh_mobile_meram_runtime_resume(struct device *dev)
  468. {
  469. struct platform_device *pdev = to_platform_device(dev);
  470. struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
  471. int k, j;
  472. for (j = 0; j < 32; j++) {
  473. if (!test_bit(j, &priv->used_icb))
  474. continue;
  475. for (k = 0; k < ICB_REGS_SIZE; k++) {
  476. meram_write_icb(priv->base, j, icb_regs[k],
  477. priv->icb_saved_regs[j * ICB_REGS_SIZE + k]);
  478. }
  479. }
  480. for (k = 0; k < CMN_REGS_SIZE; k++)
  481. meram_write_reg(priv->base, common_regs[k],
  482. priv->cmn_saved_regs[k]);
  483. return 0;
  484. }
  485. static const struct dev_pm_ops sh_mobile_meram_dev_pm_ops = {
  486. .runtime_suspend = sh_mobile_meram_runtime_suspend,
  487. .runtime_resume = sh_mobile_meram_runtime_resume,
  488. };
  489. static struct sh_mobile_meram_ops sh_mobile_meram_ops = {
  490. .module = THIS_MODULE,
  491. .meram_register = sh_mobile_meram_register,
  492. .meram_unregister = sh_mobile_meram_unregister,
  493. .meram_update = sh_mobile_meram_update,
  494. };
  495. /*
  496. * initialize MERAM
  497. */
  498. static int sh_mobile_meram_remove(struct platform_device *pdev);
  499. static int __devinit sh_mobile_meram_probe(struct platform_device *pdev)
  500. {
  501. struct sh_mobile_meram_priv *priv;
  502. struct sh_mobile_meram_info *pdata = pdev->dev.platform_data;
  503. struct resource *res;
  504. int error;
  505. if (!pdata) {
  506. dev_err(&pdev->dev, "no platform data defined\n");
  507. return -EINVAL;
  508. }
  509. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  510. if (!res) {
  511. dev_err(&pdev->dev, "cannot get platform resources\n");
  512. return -ENOENT;
  513. }
  514. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  515. if (!priv) {
  516. dev_err(&pdev->dev, "cannot allocate device data\n");
  517. return -ENOMEM;
  518. }
  519. platform_set_drvdata(pdev, priv);
  520. /* initialize private data */
  521. mutex_init(&priv->lock);
  522. priv->base = ioremap_nocache(res->start, resource_size(res));
  523. if (!priv->base) {
  524. dev_err(&pdev->dev, "ioremap failed\n");
  525. error = -EFAULT;
  526. goto err;
  527. }
  528. pdata->ops = &sh_mobile_meram_ops;
  529. pdata->priv = priv;
  530. pdata->pdev = pdev;
  531. /* initialize ICB addressing mode */
  532. if (pdata->addr_mode == SH_MOBILE_MERAM_MODE1)
  533. meram_write_reg(priv->base, MEVCR1, MEVCR1_AMD1);
  534. pm_runtime_enable(&pdev->dev);
  535. dev_info(&pdev->dev, "sh_mobile_meram initialized.");
  536. return 0;
  537. err:
  538. sh_mobile_meram_remove(pdev);
  539. return error;
  540. }
  541. static int sh_mobile_meram_remove(struct platform_device *pdev)
  542. {
  543. struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
  544. pm_runtime_disable(&pdev->dev);
  545. if (priv->base)
  546. iounmap(priv->base);
  547. mutex_destroy(&priv->lock);
  548. kfree(priv);
  549. return 0;
  550. }
  551. static struct platform_driver sh_mobile_meram_driver = {
  552. .driver = {
  553. .name = "sh_mobile_meram",
  554. .owner = THIS_MODULE,
  555. .pm = &sh_mobile_meram_dev_pm_ops,
  556. },
  557. .probe = sh_mobile_meram_probe,
  558. .remove = sh_mobile_meram_remove,
  559. };
  560. static int __init sh_mobile_meram_init(void)
  561. {
  562. return platform_driver_register(&sh_mobile_meram_driver);
  563. }
  564. static void __exit sh_mobile_meram_exit(void)
  565. {
  566. platform_driver_unregister(&sh_mobile_meram_driver);
  567. }
  568. module_init(sh_mobile_meram_init);
  569. module_exit(sh_mobile_meram_exit);
  570. MODULE_DESCRIPTION("SuperH Mobile MERAM driver");
  571. MODULE_AUTHOR("Damian Hobson-Garcia / Takanari Hayama");
  572. MODULE_LICENSE("GPL v2");