phy-samsung-usb.c 5.6 KB

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  1. /* linux/drivers/usb/phy/phy-samsung-usb.c
  2. *
  3. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Author: Praveen Paneri <p.paneri@samsung.com>
  7. *
  8. * Samsung USB-PHY helper driver with common function calls;
  9. * interacts with Samsung USB 2.0 PHY controller driver and later
  10. * with Samsung USB 3.0 PHY driver.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/clk.h>
  24. #include <linux/device.h>
  25. #include <linux/err.h>
  26. #include <linux/io.h>
  27. #include <linux/of.h>
  28. #include <linux/of_address.h>
  29. #include <linux/usb/samsung_usb_phy.h>
  30. #include "phy-samsung-usb.h"
  31. int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
  32. {
  33. struct device_node *usbphy_sys;
  34. /* Getting node for system controller interface for usb-phy */
  35. usbphy_sys = of_get_child_by_name(sphy->dev->of_node, "usbphy-sys");
  36. if (!usbphy_sys) {
  37. dev_err(sphy->dev, "No sys-controller interface for usb-phy\n");
  38. return -ENODEV;
  39. }
  40. sphy->pmuregs = of_iomap(usbphy_sys, 0);
  41. if (sphy->pmuregs == NULL) {
  42. dev_err(sphy->dev, "Can't get usb-phy pmu control register\n");
  43. goto err0;
  44. }
  45. sphy->sysreg = of_iomap(usbphy_sys, 1);
  46. /*
  47. * Not returning error code here, since this situation is not fatal.
  48. * Few SoCs may not have this switch available
  49. */
  50. if (sphy->sysreg == NULL)
  51. dev_warn(sphy->dev, "Can't get usb-phy sysreg cfg register\n");
  52. of_node_put(usbphy_sys);
  53. return 0;
  54. err0:
  55. of_node_put(usbphy_sys);
  56. return -ENXIO;
  57. }
  58. EXPORT_SYMBOL_GPL(samsung_usbphy_parse_dt);
  59. /*
  60. * Set isolation here for phy.
  61. * Here 'on = true' would mean USB PHY block is isolated, hence
  62. * de-activated and vice-versa.
  63. */
  64. void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
  65. {
  66. void __iomem *reg = NULL;
  67. u32 reg_val;
  68. u32 en_mask = 0;
  69. if (!sphy->pmuregs) {
  70. dev_warn(sphy->dev, "Can't set pmu isolation\n");
  71. return;
  72. }
  73. switch (sphy->drv_data->cpu_type) {
  74. case TYPE_S3C64XX:
  75. /*
  76. * Do nothing: We will add here once S3C64xx goes for DT support
  77. */
  78. break;
  79. case TYPE_EXYNOS4210:
  80. /*
  81. * Fall through since exynos4210 and exynos5250 have similar
  82. * register architecture: two separate registers for host and
  83. * device phy control with enable bit at position 0.
  84. */
  85. case TYPE_EXYNOS5250:
  86. if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
  87. reg = sphy->pmuregs +
  88. sphy->drv_data->devphy_reg_offset;
  89. en_mask = sphy->drv_data->devphy_en_mask;
  90. } else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
  91. reg = sphy->pmuregs +
  92. sphy->drv_data->hostphy_reg_offset;
  93. en_mask = sphy->drv_data->hostphy_en_mask;
  94. }
  95. break;
  96. default:
  97. dev_err(sphy->dev, "Invalid SoC type\n");
  98. return;
  99. }
  100. reg_val = readl(reg);
  101. if (on)
  102. reg_val &= ~en_mask;
  103. else
  104. reg_val |= en_mask;
  105. writel(reg_val, reg);
  106. }
  107. EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation);
  108. /*
  109. * Configure the mode of working of usb-phy here: HOST/DEVICE.
  110. */
  111. void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
  112. {
  113. u32 reg;
  114. if (!sphy->sysreg) {
  115. dev_warn(sphy->dev, "Can't configure specified phy mode\n");
  116. return;
  117. }
  118. reg = readl(sphy->sysreg);
  119. if (sphy->phy_type == USB_PHY_TYPE_DEVICE)
  120. reg &= ~EXYNOS_USB20PHY_CFG_HOST_LINK;
  121. else if (sphy->phy_type == USB_PHY_TYPE_HOST)
  122. reg |= EXYNOS_USB20PHY_CFG_HOST_LINK;
  123. writel(reg, sphy->sysreg);
  124. }
  125. EXPORT_SYMBOL_GPL(samsung_usbphy_cfg_sel);
  126. /*
  127. * PHYs are different for USB Device and USB Host.
  128. * This make sure that correct PHY type is selected before
  129. * any operation on PHY.
  130. */
  131. int samsung_usbphy_set_type(struct usb_phy *phy,
  132. enum samsung_usb_phy_type phy_type)
  133. {
  134. struct samsung_usbphy *sphy = phy_to_sphy(phy);
  135. sphy->phy_type = phy_type;
  136. return 0;
  137. }
  138. EXPORT_SYMBOL_GPL(samsung_usbphy_set_type);
  139. /*
  140. * Returns reference clock frequency selection value
  141. */
  142. int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
  143. {
  144. struct clk *ref_clk;
  145. int refclk_freq = 0;
  146. /*
  147. * In exynos5250 USB host and device PHY use
  148. * external crystal clock XXTI
  149. */
  150. if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
  151. ref_clk = devm_clk_get(sphy->dev, "ext_xtal");
  152. else
  153. ref_clk = devm_clk_get(sphy->dev, "xusbxti");
  154. if (IS_ERR(ref_clk)) {
  155. dev_err(sphy->dev, "Failed to get reference clock\n");
  156. return PTR_ERR(ref_clk);
  157. }
  158. if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) {
  159. /* set clock frequency for PLL */
  160. switch (clk_get_rate(ref_clk)) {
  161. case 9600 * KHZ:
  162. refclk_freq = FSEL_CLKSEL_9600K;
  163. break;
  164. case 10 * MHZ:
  165. refclk_freq = FSEL_CLKSEL_10M;
  166. break;
  167. case 12 * MHZ:
  168. refclk_freq = FSEL_CLKSEL_12M;
  169. break;
  170. case 19200 * KHZ:
  171. refclk_freq = FSEL_CLKSEL_19200K;
  172. break;
  173. case 20 * MHZ:
  174. refclk_freq = FSEL_CLKSEL_20M;
  175. break;
  176. case 50 * MHZ:
  177. refclk_freq = FSEL_CLKSEL_50M;
  178. break;
  179. case 24 * MHZ:
  180. default:
  181. /* default reference clock */
  182. refclk_freq = FSEL_CLKSEL_24M;
  183. break;
  184. }
  185. } else {
  186. switch (clk_get_rate(ref_clk)) {
  187. case 12 * MHZ:
  188. refclk_freq = PHYCLK_CLKSEL_12M;
  189. break;
  190. case 24 * MHZ:
  191. refclk_freq = PHYCLK_CLKSEL_24M;
  192. break;
  193. case 48 * MHZ:
  194. refclk_freq = PHYCLK_CLKSEL_48M;
  195. break;
  196. default:
  197. if (sphy->drv_data->cpu_type == TYPE_S3C64XX)
  198. refclk_freq = PHYCLK_CLKSEL_48M;
  199. else
  200. refclk_freq = PHYCLK_CLKSEL_24M;
  201. break;
  202. }
  203. }
  204. clk_put(ref_clk);
  205. return refclk_freq;
  206. }
  207. EXPORT_SYMBOL_GPL(samsung_usbphy_get_refclk_freq);