fsl_udc_core.c 72 KB

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  1. /*
  2. * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
  3. * All rights reserved.
  4. *
  5. * Author: Li Yang <leoli@freescale.com>
  6. * Jiang Bo <tanya.jiang@freescale.com>
  7. *
  8. * Description:
  9. * Freescale high-speed USB SOC DR module device controller driver.
  10. * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  11. * The driver is previously named as mpc_udc. Based on bare board
  12. * code from Dave Liu and Shlomi Gridish.
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License as published by the
  16. * Free Software Foundation; either version 2 of the License, or (at your
  17. * option) any later version.
  18. */
  19. #undef VERBOSE
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/ioport.h>
  23. #include <linux/types.h>
  24. #include <linux/errno.h>
  25. #include <linux/err.h>
  26. #include <linux/slab.h>
  27. #include <linux/init.h>
  28. #include <linux/list.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/proc_fs.h>
  31. #include <linux/mm.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/device.h>
  34. #include <linux/usb/ch9.h>
  35. #include <linux/usb/gadget.h>
  36. #include <linux/usb/otg.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/fsl_devices.h>
  40. #include <linux/dmapool.h>
  41. #include <linux/delay.h>
  42. #include <linux/of_device.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/unaligned.h>
  46. #include <asm/dma.h>
  47. #include "fsl_usb2_udc.h"
  48. #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
  49. #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
  50. #define DRIVER_VERSION "Apr 20, 2007"
  51. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  52. static const char driver_name[] = "fsl-usb2-udc";
  53. static const char driver_desc[] = DRIVER_DESC;
  54. static struct usb_dr_device *dr_regs;
  55. static struct usb_sys_interface *usb_sys_regs;
  56. /* it is initialized in probe() */
  57. static struct fsl_udc *udc_controller = NULL;
  58. static const struct usb_endpoint_descriptor
  59. fsl_ep0_desc = {
  60. .bLength = USB_DT_ENDPOINT_SIZE,
  61. .bDescriptorType = USB_DT_ENDPOINT,
  62. .bEndpointAddress = 0,
  63. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  64. .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
  65. };
  66. static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  67. #ifdef CONFIG_PPC32
  68. /*
  69. * On some SoCs, the USB controller registers can be big or little endian,
  70. * depending on the version of the chip. In order to be able to run the
  71. * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  72. * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  73. * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  74. * call through those pointers. Platform code for SoCs that have BE USB
  75. * registers should set pdata->big_endian_mmio flag.
  76. *
  77. * This also applies to controller-to-cpu accessors for the USB descriptors,
  78. * since their endianness is also SoC dependant. Platform code for SoCs that
  79. * have BE USB descriptors should set pdata->big_endian_desc flag.
  80. */
  81. static u32 _fsl_readl_be(const unsigned __iomem *p)
  82. {
  83. return in_be32(p);
  84. }
  85. static u32 _fsl_readl_le(const unsigned __iomem *p)
  86. {
  87. return in_le32(p);
  88. }
  89. static void _fsl_writel_be(u32 v, unsigned __iomem *p)
  90. {
  91. out_be32(p, v);
  92. }
  93. static void _fsl_writel_le(u32 v, unsigned __iomem *p)
  94. {
  95. out_le32(p, v);
  96. }
  97. static u32 (*_fsl_readl)(const unsigned __iomem *p);
  98. static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
  99. #define fsl_readl(p) (*_fsl_readl)((p))
  100. #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
  101. static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
  102. {
  103. if (pdata->big_endian_mmio) {
  104. _fsl_readl = _fsl_readl_be;
  105. _fsl_writel = _fsl_writel_be;
  106. } else {
  107. _fsl_readl = _fsl_readl_le;
  108. _fsl_writel = _fsl_writel_le;
  109. }
  110. }
  111. static inline u32 cpu_to_hc32(const u32 x)
  112. {
  113. return udc_controller->pdata->big_endian_desc
  114. ? (__force u32)cpu_to_be32(x)
  115. : (__force u32)cpu_to_le32(x);
  116. }
  117. static inline u32 hc32_to_cpu(const u32 x)
  118. {
  119. return udc_controller->pdata->big_endian_desc
  120. ? be32_to_cpu((__force __be32)x)
  121. : le32_to_cpu((__force __le32)x);
  122. }
  123. #else /* !CONFIG_PPC32 */
  124. static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
  125. #define fsl_readl(addr) readl(addr)
  126. #define fsl_writel(val32, addr) writel(val32, addr)
  127. #define cpu_to_hc32(x) cpu_to_le32(x)
  128. #define hc32_to_cpu(x) le32_to_cpu(x)
  129. #endif /* CONFIG_PPC32 */
  130. /********************************************************************
  131. * Internal Used Function
  132. ********************************************************************/
  133. /*-----------------------------------------------------------------
  134. * done() - retire a request; caller blocked irqs
  135. * @status : request status to be set, only works when
  136. * request is still in progress.
  137. *--------------------------------------------------------------*/
  138. static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
  139. {
  140. struct fsl_udc *udc = NULL;
  141. unsigned char stopped = ep->stopped;
  142. struct ep_td_struct *curr_td, *next_td;
  143. int j;
  144. udc = (struct fsl_udc *)ep->udc;
  145. /* Removed the req from fsl_ep->queue */
  146. list_del_init(&req->queue);
  147. /* req.status should be set as -EINPROGRESS in ep_queue() */
  148. if (req->req.status == -EINPROGRESS)
  149. req->req.status = status;
  150. else
  151. status = req->req.status;
  152. /* Free dtd for the request */
  153. next_td = req->head;
  154. for (j = 0; j < req->dtd_count; j++) {
  155. curr_td = next_td;
  156. if (j != req->dtd_count - 1) {
  157. next_td = curr_td->next_td_virt;
  158. }
  159. dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
  160. }
  161. usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
  162. if (status && (status != -ESHUTDOWN))
  163. VDBG("complete %s req %p stat %d len %u/%u",
  164. ep->ep.name, &req->req, status,
  165. req->req.actual, req->req.length);
  166. ep->stopped = 1;
  167. spin_unlock(&ep->udc->lock);
  168. /* complete() is from gadget layer,
  169. * eg fsg->bulk_in_complete() */
  170. if (req->req.complete)
  171. req->req.complete(&ep->ep, &req->req);
  172. spin_lock(&ep->udc->lock);
  173. ep->stopped = stopped;
  174. }
  175. /*-----------------------------------------------------------------
  176. * nuke(): delete all requests related to this ep
  177. * called with spinlock held
  178. *--------------------------------------------------------------*/
  179. static void nuke(struct fsl_ep *ep, int status)
  180. {
  181. ep->stopped = 1;
  182. /* Flush fifo */
  183. fsl_ep_fifo_flush(&ep->ep);
  184. /* Whether this eq has request linked */
  185. while (!list_empty(&ep->queue)) {
  186. struct fsl_req *req = NULL;
  187. req = list_entry(ep->queue.next, struct fsl_req, queue);
  188. done(ep, req, status);
  189. }
  190. }
  191. /*------------------------------------------------------------------
  192. Internal Hardware related function
  193. ------------------------------------------------------------------*/
  194. static int dr_controller_setup(struct fsl_udc *udc)
  195. {
  196. unsigned int tmp, portctrl, ep_num;
  197. unsigned int max_no_of_ep;
  198. unsigned int ctrl;
  199. unsigned long timeout;
  200. #define FSL_UDC_RESET_TIMEOUT 1000
  201. /* Config PHY interface */
  202. portctrl = fsl_readl(&dr_regs->portsc1);
  203. portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
  204. switch (udc->phy_mode) {
  205. case FSL_USB2_PHY_ULPI:
  206. if (udc->pdata->have_sysif_regs) {
  207. if (udc->pdata->controller_ver) {
  208. /* controller version 1.6 or above */
  209. ctrl = __raw_readl(&usb_sys_regs->control);
  210. ctrl &= ~USB_CTRL_UTMI_PHY_EN;
  211. ctrl |= USB_CTRL_USB_EN;
  212. __raw_writel(ctrl, &usb_sys_regs->control);
  213. }
  214. }
  215. portctrl |= PORTSCX_PTS_ULPI;
  216. break;
  217. case FSL_USB2_PHY_UTMI_WIDE:
  218. portctrl |= PORTSCX_PTW_16BIT;
  219. /* fall through */
  220. case FSL_USB2_PHY_UTMI:
  221. if (udc->pdata->have_sysif_regs) {
  222. if (udc->pdata->controller_ver) {
  223. /* controller version 1.6 or above */
  224. ctrl = __raw_readl(&usb_sys_regs->control);
  225. ctrl |= (USB_CTRL_UTMI_PHY_EN |
  226. USB_CTRL_USB_EN);
  227. __raw_writel(ctrl, &usb_sys_regs->control);
  228. mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
  229. PHY CLK to become stable - 10ms*/
  230. }
  231. }
  232. portctrl |= PORTSCX_PTS_UTMI;
  233. break;
  234. case FSL_USB2_PHY_SERIAL:
  235. portctrl |= PORTSCX_PTS_FSLS;
  236. break;
  237. default:
  238. return -EINVAL;
  239. }
  240. fsl_writel(portctrl, &dr_regs->portsc1);
  241. /* Stop and reset the usb controller */
  242. tmp = fsl_readl(&dr_regs->usbcmd);
  243. tmp &= ~USB_CMD_RUN_STOP;
  244. fsl_writel(tmp, &dr_regs->usbcmd);
  245. tmp = fsl_readl(&dr_regs->usbcmd);
  246. tmp |= USB_CMD_CTRL_RESET;
  247. fsl_writel(tmp, &dr_regs->usbcmd);
  248. /* Wait for reset to complete */
  249. timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
  250. while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
  251. if (time_after(jiffies, timeout)) {
  252. ERR("udc reset timeout!\n");
  253. return -ETIMEDOUT;
  254. }
  255. cpu_relax();
  256. }
  257. /* Set the controller as device mode */
  258. tmp = fsl_readl(&dr_regs->usbmode);
  259. tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
  260. tmp |= USB_MODE_CTRL_MODE_DEVICE;
  261. /* Disable Setup Lockout */
  262. tmp |= USB_MODE_SETUP_LOCK_OFF;
  263. if (udc->pdata->es)
  264. tmp |= USB_MODE_ES;
  265. fsl_writel(tmp, &dr_regs->usbmode);
  266. /* Clear the setup status */
  267. fsl_writel(0, &dr_regs->usbsts);
  268. tmp = udc->ep_qh_dma;
  269. tmp &= USB_EP_LIST_ADDRESS_MASK;
  270. fsl_writel(tmp, &dr_regs->endpointlistaddr);
  271. VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
  272. udc->ep_qh, (int)tmp,
  273. fsl_readl(&dr_regs->endpointlistaddr));
  274. max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
  275. for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
  276. tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
  277. tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
  278. tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
  279. | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
  280. fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
  281. }
  282. /* Config control enable i/o output, cpu endian register */
  283. #ifndef CONFIG_ARCH_MXC
  284. if (udc->pdata->have_sysif_regs) {
  285. ctrl = __raw_readl(&usb_sys_regs->control);
  286. ctrl |= USB_CTRL_IOENB;
  287. __raw_writel(ctrl, &usb_sys_regs->control);
  288. }
  289. #endif
  290. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  291. /* Turn on cache snooping hardware, since some PowerPC platforms
  292. * wholly rely on hardware to deal with cache coherent. */
  293. if (udc->pdata->have_sysif_regs) {
  294. /* Setup Snooping for all the 4GB space */
  295. tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
  296. __raw_writel(tmp, &usb_sys_regs->snoop1);
  297. tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
  298. __raw_writel(tmp, &usb_sys_regs->snoop2);
  299. }
  300. #endif
  301. return 0;
  302. }
  303. /* Enable DR irq and set controller to run state */
  304. static void dr_controller_run(struct fsl_udc *udc)
  305. {
  306. u32 temp;
  307. /* Enable DR irq reg */
  308. temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
  309. | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
  310. | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
  311. fsl_writel(temp, &dr_regs->usbintr);
  312. /* Clear stopped bit */
  313. udc->stopped = 0;
  314. /* Set the controller as device mode */
  315. temp = fsl_readl(&dr_regs->usbmode);
  316. temp |= USB_MODE_CTRL_MODE_DEVICE;
  317. fsl_writel(temp, &dr_regs->usbmode);
  318. /* Set controller to Run */
  319. temp = fsl_readl(&dr_regs->usbcmd);
  320. temp |= USB_CMD_RUN_STOP;
  321. fsl_writel(temp, &dr_regs->usbcmd);
  322. }
  323. static void dr_controller_stop(struct fsl_udc *udc)
  324. {
  325. unsigned int tmp;
  326. pr_debug("%s\n", __func__);
  327. /* if we're in OTG mode, and the Host is currently using the port,
  328. * stop now and don't rip the controller out from under the
  329. * ehci driver
  330. */
  331. if (udc->gadget.is_otg) {
  332. if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
  333. pr_debug("udc: Leaving early\n");
  334. return;
  335. }
  336. }
  337. /* disable all INTR */
  338. fsl_writel(0, &dr_regs->usbintr);
  339. /* Set stopped bit for isr */
  340. udc->stopped = 1;
  341. /* disable IO output */
  342. /* usb_sys_regs->control = 0; */
  343. /* set controller to Stop */
  344. tmp = fsl_readl(&dr_regs->usbcmd);
  345. tmp &= ~USB_CMD_RUN_STOP;
  346. fsl_writel(tmp, &dr_regs->usbcmd);
  347. }
  348. static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
  349. unsigned char ep_type)
  350. {
  351. unsigned int tmp_epctrl = 0;
  352. tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  353. if (dir) {
  354. if (ep_num)
  355. tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
  356. tmp_epctrl |= EPCTRL_TX_ENABLE;
  357. tmp_epctrl &= ~EPCTRL_TX_TYPE;
  358. tmp_epctrl |= ((unsigned int)(ep_type)
  359. << EPCTRL_TX_EP_TYPE_SHIFT);
  360. } else {
  361. if (ep_num)
  362. tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
  363. tmp_epctrl |= EPCTRL_RX_ENABLE;
  364. tmp_epctrl &= ~EPCTRL_RX_TYPE;
  365. tmp_epctrl |= ((unsigned int)(ep_type)
  366. << EPCTRL_RX_EP_TYPE_SHIFT);
  367. }
  368. fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
  369. }
  370. static void
  371. dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
  372. {
  373. u32 tmp_epctrl = 0;
  374. tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  375. if (value) {
  376. /* set the stall bit */
  377. if (dir)
  378. tmp_epctrl |= EPCTRL_TX_EP_STALL;
  379. else
  380. tmp_epctrl |= EPCTRL_RX_EP_STALL;
  381. } else {
  382. /* clear the stall bit and reset data toggle */
  383. if (dir) {
  384. tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
  385. tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
  386. } else {
  387. tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
  388. tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
  389. }
  390. }
  391. fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
  392. }
  393. /* Get stall status of a specific ep
  394. Return: 0: not stalled; 1:stalled */
  395. static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
  396. {
  397. u32 epctrl;
  398. epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  399. if (dir)
  400. return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
  401. else
  402. return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
  403. }
  404. /********************************************************************
  405. Internal Structure Build up functions
  406. ********************************************************************/
  407. /*------------------------------------------------------------------
  408. * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
  409. * @zlt: Zero Length Termination Select (1: disable; 0: enable)
  410. * @mult: Mult field
  411. ------------------------------------------------------------------*/
  412. static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
  413. unsigned char dir, unsigned char ep_type,
  414. unsigned int max_pkt_len,
  415. unsigned int zlt, unsigned char mult)
  416. {
  417. struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
  418. unsigned int tmp = 0;
  419. /* set the Endpoint Capabilites in QH */
  420. switch (ep_type) {
  421. case USB_ENDPOINT_XFER_CONTROL:
  422. /* Interrupt On Setup (IOS). for control ep */
  423. tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
  424. | EP_QUEUE_HEAD_IOS;
  425. break;
  426. case USB_ENDPOINT_XFER_ISOC:
  427. tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
  428. | (mult << EP_QUEUE_HEAD_MULT_POS);
  429. break;
  430. case USB_ENDPOINT_XFER_BULK:
  431. case USB_ENDPOINT_XFER_INT:
  432. tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
  433. break;
  434. default:
  435. VDBG("error ep type is %d", ep_type);
  436. return;
  437. }
  438. if (zlt)
  439. tmp |= EP_QUEUE_HEAD_ZLT_SEL;
  440. p_QH->max_pkt_length = cpu_to_hc32(tmp);
  441. p_QH->next_dtd_ptr = 1;
  442. p_QH->size_ioc_int_sts = 0;
  443. }
  444. /* Setup qh structure and ep register for ep0. */
  445. static void ep0_setup(struct fsl_udc *udc)
  446. {
  447. /* the intialization of an ep includes: fields in QH, Regs,
  448. * fsl_ep struct */
  449. struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
  450. USB_MAX_CTRL_PAYLOAD, 0, 0);
  451. struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
  452. USB_MAX_CTRL_PAYLOAD, 0, 0);
  453. dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
  454. dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
  455. return;
  456. }
  457. /***********************************************************************
  458. Endpoint Management Functions
  459. ***********************************************************************/
  460. /*-------------------------------------------------------------------------
  461. * when configurations are set, or when interface settings change
  462. * for example the do_set_interface() in gadget layer,
  463. * the driver will enable or disable the relevant endpoints
  464. * ep0 doesn't use this routine. It is always enabled.
  465. -------------------------------------------------------------------------*/
  466. static int fsl_ep_enable(struct usb_ep *_ep,
  467. const struct usb_endpoint_descriptor *desc)
  468. {
  469. struct fsl_udc *udc = NULL;
  470. struct fsl_ep *ep = NULL;
  471. unsigned short max = 0;
  472. unsigned char mult = 0, zlt;
  473. int retval = -EINVAL;
  474. unsigned long flags = 0;
  475. ep = container_of(_ep, struct fsl_ep, ep);
  476. /* catch various bogus parameters */
  477. if (!_ep || !desc
  478. || (desc->bDescriptorType != USB_DT_ENDPOINT))
  479. return -EINVAL;
  480. udc = ep->udc;
  481. if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
  482. return -ESHUTDOWN;
  483. max = usb_endpoint_maxp(desc);
  484. /* Disable automatic zlp generation. Driver is responsible to indicate
  485. * explicitly through req->req.zero. This is needed to enable multi-td
  486. * request. */
  487. zlt = 1;
  488. /* Assume the max packet size from gadget is always correct */
  489. switch (desc->bmAttributes & 0x03) {
  490. case USB_ENDPOINT_XFER_CONTROL:
  491. case USB_ENDPOINT_XFER_BULK:
  492. case USB_ENDPOINT_XFER_INT:
  493. /* mult = 0. Execute N Transactions as demonstrated by
  494. * the USB variable length packet protocol where N is
  495. * computed using the Maximum Packet Length (dQH) and
  496. * the Total Bytes field (dTD) */
  497. mult = 0;
  498. break;
  499. case USB_ENDPOINT_XFER_ISOC:
  500. /* Calculate transactions needed for high bandwidth iso */
  501. mult = (unsigned char)(1 + ((max >> 11) & 0x03));
  502. max = max & 0x7ff; /* bit 0~10 */
  503. /* 3 transactions at most */
  504. if (mult > 3)
  505. goto en_done;
  506. break;
  507. default:
  508. goto en_done;
  509. }
  510. spin_lock_irqsave(&udc->lock, flags);
  511. ep->ep.maxpacket = max;
  512. ep->ep.desc = desc;
  513. ep->stopped = 0;
  514. /* Controller related setup */
  515. /* Init EPx Queue Head (Ep Capabilites field in QH
  516. * according to max, zlt, mult) */
  517. struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
  518. (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
  519. ? USB_SEND : USB_RECV),
  520. (unsigned char) (desc->bmAttributes
  521. & USB_ENDPOINT_XFERTYPE_MASK),
  522. max, zlt, mult);
  523. /* Init endpoint ctrl register */
  524. dr_ep_setup((unsigned char) ep_index(ep),
  525. (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
  526. ? USB_SEND : USB_RECV),
  527. (unsigned char) (desc->bmAttributes
  528. & USB_ENDPOINT_XFERTYPE_MASK));
  529. spin_unlock_irqrestore(&udc->lock, flags);
  530. retval = 0;
  531. VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
  532. ep->ep.desc->bEndpointAddress & 0x0f,
  533. (desc->bEndpointAddress & USB_DIR_IN)
  534. ? "in" : "out", max);
  535. en_done:
  536. return retval;
  537. }
  538. /*---------------------------------------------------------------------
  539. * @ep : the ep being unconfigured. May not be ep0
  540. * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
  541. *---------------------------------------------------------------------*/
  542. static int fsl_ep_disable(struct usb_ep *_ep)
  543. {
  544. struct fsl_udc *udc = NULL;
  545. struct fsl_ep *ep = NULL;
  546. unsigned long flags = 0;
  547. u32 epctrl;
  548. int ep_num;
  549. ep = container_of(_ep, struct fsl_ep, ep);
  550. if (!_ep || !ep->ep.desc) {
  551. VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
  552. return -EINVAL;
  553. }
  554. /* disable ep on controller */
  555. ep_num = ep_index(ep);
  556. epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  557. if (ep_is_in(ep)) {
  558. epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
  559. epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
  560. } else {
  561. epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
  562. epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
  563. }
  564. fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
  565. udc = (struct fsl_udc *)ep->udc;
  566. spin_lock_irqsave(&udc->lock, flags);
  567. /* nuke all pending requests (does flush) */
  568. nuke(ep, -ESHUTDOWN);
  569. ep->ep.desc = NULL;
  570. ep->stopped = 1;
  571. spin_unlock_irqrestore(&udc->lock, flags);
  572. VDBG("disabled %s OK", _ep->name);
  573. return 0;
  574. }
  575. /*---------------------------------------------------------------------
  576. * allocate a request object used by this endpoint
  577. * the main operation is to insert the req->queue to the eq->queue
  578. * Returns the request, or null if one could not be allocated
  579. *---------------------------------------------------------------------*/
  580. static struct usb_request *
  581. fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  582. {
  583. struct fsl_req *req = NULL;
  584. req = kzalloc(sizeof *req, gfp_flags);
  585. if (!req)
  586. return NULL;
  587. req->req.dma = DMA_ADDR_INVALID;
  588. INIT_LIST_HEAD(&req->queue);
  589. return &req->req;
  590. }
  591. static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
  592. {
  593. struct fsl_req *req = NULL;
  594. req = container_of(_req, struct fsl_req, req);
  595. if (_req)
  596. kfree(req);
  597. }
  598. /* Actually add a dTD chain to an empty dQH and let go */
  599. static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
  600. {
  601. struct ep_queue_head *qh = get_qh_by_ep(ep);
  602. /* Write dQH next pointer and terminate bit to 0 */
  603. qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
  604. & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
  605. /* Clear active and halt bit */
  606. qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
  607. | EP_QUEUE_HEAD_STATUS_HALT));
  608. /* Ensure that updates to the QH will occur before priming. */
  609. wmb();
  610. /* Prime endpoint by writing correct bit to ENDPTPRIME */
  611. fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
  612. : (1 << (ep_index(ep))), &dr_regs->endpointprime);
  613. }
  614. /* Add dTD chain to the dQH of an EP */
  615. static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
  616. {
  617. u32 temp, bitmask, tmp_stat;
  618. /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
  619. VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
  620. bitmask = ep_is_in(ep)
  621. ? (1 << (ep_index(ep) + 16))
  622. : (1 << (ep_index(ep)));
  623. /* check if the pipe is empty */
  624. if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
  625. /* Add td to the end */
  626. struct fsl_req *lastreq;
  627. lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
  628. lastreq->tail->next_td_ptr =
  629. cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
  630. /* Ensure dTD's next dtd pointer to be updated */
  631. wmb();
  632. /* Read prime bit, if 1 goto done */
  633. if (fsl_readl(&dr_regs->endpointprime) & bitmask)
  634. return;
  635. do {
  636. /* Set ATDTW bit in USBCMD */
  637. temp = fsl_readl(&dr_regs->usbcmd);
  638. fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
  639. /* Read correct status bit */
  640. tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
  641. } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
  642. /* Write ATDTW bit to 0 */
  643. temp = fsl_readl(&dr_regs->usbcmd);
  644. fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
  645. if (tmp_stat)
  646. return;
  647. }
  648. fsl_prime_ep(ep, req->head);
  649. }
  650. /* Fill in the dTD structure
  651. * @req: request that the transfer belongs to
  652. * @length: return actually data length of the dTD
  653. * @dma: return dma address of the dTD
  654. * @is_last: return flag if it is the last dTD of the request
  655. * return: pointer to the built dTD */
  656. static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
  657. dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
  658. {
  659. u32 swap_temp;
  660. struct ep_td_struct *dtd;
  661. /* how big will this transfer be? */
  662. *length = min(req->req.length - req->req.actual,
  663. (unsigned)EP_MAX_LENGTH_TRANSFER);
  664. dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
  665. if (dtd == NULL)
  666. return dtd;
  667. dtd->td_dma = *dma;
  668. /* Clear reserved field */
  669. swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
  670. swap_temp &= ~DTD_RESERVED_FIELDS;
  671. dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
  672. /* Init all of buffer page pointers */
  673. swap_temp = (u32) (req->req.dma + req->req.actual);
  674. dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
  675. dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
  676. dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
  677. dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
  678. dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
  679. req->req.actual += *length;
  680. /* zlp is needed if req->req.zero is set */
  681. if (req->req.zero) {
  682. if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
  683. *is_last = 1;
  684. else
  685. *is_last = 0;
  686. } else if (req->req.length == req->req.actual)
  687. *is_last = 1;
  688. else
  689. *is_last = 0;
  690. if ((*is_last) == 0)
  691. VDBG("multi-dtd request!");
  692. /* Fill in the transfer size; set active bit */
  693. swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
  694. /* Enable interrupt for the last dtd of a request */
  695. if (*is_last && !req->req.no_interrupt)
  696. swap_temp |= DTD_IOC;
  697. dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
  698. mb();
  699. VDBG("length = %d address= 0x%x", *length, (int)*dma);
  700. return dtd;
  701. }
  702. /* Generate dtd chain for a request */
  703. static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
  704. {
  705. unsigned count;
  706. int is_last;
  707. int is_first =1;
  708. struct ep_td_struct *last_dtd = NULL, *dtd;
  709. dma_addr_t dma;
  710. do {
  711. dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
  712. if (dtd == NULL)
  713. return -ENOMEM;
  714. if (is_first) {
  715. is_first = 0;
  716. req->head = dtd;
  717. } else {
  718. last_dtd->next_td_ptr = cpu_to_hc32(dma);
  719. last_dtd->next_td_virt = dtd;
  720. }
  721. last_dtd = dtd;
  722. req->dtd_count++;
  723. } while (!is_last);
  724. dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
  725. req->tail = dtd;
  726. return 0;
  727. }
  728. /* queues (submits) an I/O request to an endpoint */
  729. static int
  730. fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  731. {
  732. struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
  733. struct fsl_req *req = container_of(_req, struct fsl_req, req);
  734. struct fsl_udc *udc;
  735. unsigned long flags;
  736. int ret;
  737. /* catch various bogus parameters */
  738. if (!_req || !req->req.complete || !req->req.buf
  739. || !list_empty(&req->queue)) {
  740. VDBG("%s, bad params", __func__);
  741. return -EINVAL;
  742. }
  743. if (unlikely(!_ep || !ep->ep.desc)) {
  744. VDBG("%s, bad ep", __func__);
  745. return -EINVAL;
  746. }
  747. if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
  748. if (req->req.length > ep->ep.maxpacket)
  749. return -EMSGSIZE;
  750. }
  751. udc = ep->udc;
  752. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
  753. return -ESHUTDOWN;
  754. req->ep = ep;
  755. ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
  756. if (ret)
  757. return ret;
  758. req->req.status = -EINPROGRESS;
  759. req->req.actual = 0;
  760. req->dtd_count = 0;
  761. /* build dtds and push them to device queue */
  762. if (!fsl_req_to_dtd(req, gfp_flags)) {
  763. spin_lock_irqsave(&udc->lock, flags);
  764. fsl_queue_td(ep, req);
  765. } else {
  766. return -ENOMEM;
  767. }
  768. /* irq handler advances the queue */
  769. if (req != NULL)
  770. list_add_tail(&req->queue, &ep->queue);
  771. spin_unlock_irqrestore(&udc->lock, flags);
  772. return 0;
  773. }
  774. /* dequeues (cancels, unlinks) an I/O request from an endpoint */
  775. static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  776. {
  777. struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
  778. struct fsl_req *req;
  779. unsigned long flags;
  780. int ep_num, stopped, ret = 0;
  781. u32 epctrl;
  782. if (!_ep || !_req)
  783. return -EINVAL;
  784. spin_lock_irqsave(&ep->udc->lock, flags);
  785. stopped = ep->stopped;
  786. /* Stop the ep before we deal with the queue */
  787. ep->stopped = 1;
  788. ep_num = ep_index(ep);
  789. epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  790. if (ep_is_in(ep))
  791. epctrl &= ~EPCTRL_TX_ENABLE;
  792. else
  793. epctrl &= ~EPCTRL_RX_ENABLE;
  794. fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
  795. /* make sure it's actually queued on this endpoint */
  796. list_for_each_entry(req, &ep->queue, queue) {
  797. if (&req->req == _req)
  798. break;
  799. }
  800. if (&req->req != _req) {
  801. ret = -EINVAL;
  802. goto out;
  803. }
  804. /* The request is in progress, or completed but not dequeued */
  805. if (ep->queue.next == &req->queue) {
  806. _req->status = -ECONNRESET;
  807. fsl_ep_fifo_flush(_ep); /* flush current transfer */
  808. /* The request isn't the last request in this ep queue */
  809. if (req->queue.next != &ep->queue) {
  810. struct fsl_req *next_req;
  811. next_req = list_entry(req->queue.next, struct fsl_req,
  812. queue);
  813. /* prime with dTD of next request */
  814. fsl_prime_ep(ep, next_req->head);
  815. }
  816. /* The request hasn't been processed, patch up the TD chain */
  817. } else {
  818. struct fsl_req *prev_req;
  819. prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
  820. prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
  821. }
  822. done(ep, req, -ECONNRESET);
  823. /* Enable EP */
  824. out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  825. if (ep_is_in(ep))
  826. epctrl |= EPCTRL_TX_ENABLE;
  827. else
  828. epctrl |= EPCTRL_RX_ENABLE;
  829. fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
  830. ep->stopped = stopped;
  831. spin_unlock_irqrestore(&ep->udc->lock, flags);
  832. return ret;
  833. }
  834. /*-------------------------------------------------------------------------*/
  835. /*-----------------------------------------------------------------
  836. * modify the endpoint halt feature
  837. * @ep: the non-isochronous endpoint being stalled
  838. * @value: 1--set halt 0--clear halt
  839. * Returns zero, or a negative error code.
  840. *----------------------------------------------------------------*/
  841. static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
  842. {
  843. struct fsl_ep *ep = NULL;
  844. unsigned long flags = 0;
  845. int status = -EOPNOTSUPP; /* operation not supported */
  846. unsigned char ep_dir = 0, ep_num = 0;
  847. struct fsl_udc *udc = NULL;
  848. ep = container_of(_ep, struct fsl_ep, ep);
  849. udc = ep->udc;
  850. if (!_ep || !ep->ep.desc) {
  851. status = -EINVAL;
  852. goto out;
  853. }
  854. if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
  855. status = -EOPNOTSUPP;
  856. goto out;
  857. }
  858. /* Attempt to halt IN ep will fail if any transfer requests
  859. * are still queue */
  860. if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
  861. status = -EAGAIN;
  862. goto out;
  863. }
  864. status = 0;
  865. ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
  866. ep_num = (unsigned char)(ep_index(ep));
  867. spin_lock_irqsave(&ep->udc->lock, flags);
  868. dr_ep_change_stall(ep_num, ep_dir, value);
  869. spin_unlock_irqrestore(&ep->udc->lock, flags);
  870. if (ep_index(ep) == 0) {
  871. udc->ep0_state = WAIT_FOR_SETUP;
  872. udc->ep0_dir = 0;
  873. }
  874. out:
  875. VDBG(" %s %s halt stat %d", ep->ep.name,
  876. value ? "set" : "clear", status);
  877. return status;
  878. }
  879. static int fsl_ep_fifo_status(struct usb_ep *_ep)
  880. {
  881. struct fsl_ep *ep;
  882. struct fsl_udc *udc;
  883. int size = 0;
  884. u32 bitmask;
  885. struct ep_queue_head *qh;
  886. ep = container_of(_ep, struct fsl_ep, ep);
  887. if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
  888. return -ENODEV;
  889. udc = (struct fsl_udc *)ep->udc;
  890. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
  891. return -ESHUTDOWN;
  892. qh = get_qh_by_ep(ep);
  893. bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
  894. (1 << (ep_index(ep)));
  895. if (fsl_readl(&dr_regs->endptstatus) & bitmask)
  896. size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
  897. >> DTD_LENGTH_BIT_POS;
  898. pr_debug("%s %u\n", __func__, size);
  899. return size;
  900. }
  901. static void fsl_ep_fifo_flush(struct usb_ep *_ep)
  902. {
  903. struct fsl_ep *ep;
  904. int ep_num, ep_dir;
  905. u32 bits;
  906. unsigned long timeout;
  907. #define FSL_UDC_FLUSH_TIMEOUT 1000
  908. if (!_ep) {
  909. return;
  910. } else {
  911. ep = container_of(_ep, struct fsl_ep, ep);
  912. if (!ep->ep.desc)
  913. return;
  914. }
  915. ep_num = ep_index(ep);
  916. ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
  917. if (ep_num == 0)
  918. bits = (1 << 16) | 1;
  919. else if (ep_dir == USB_SEND)
  920. bits = 1 << (16 + ep_num);
  921. else
  922. bits = 1 << ep_num;
  923. timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
  924. do {
  925. fsl_writel(bits, &dr_regs->endptflush);
  926. /* Wait until flush complete */
  927. while (fsl_readl(&dr_regs->endptflush)) {
  928. if (time_after(jiffies, timeout)) {
  929. ERR("ep flush timeout\n");
  930. return;
  931. }
  932. cpu_relax();
  933. }
  934. /* See if we need to flush again */
  935. } while (fsl_readl(&dr_regs->endptstatus) & bits);
  936. }
  937. static struct usb_ep_ops fsl_ep_ops = {
  938. .enable = fsl_ep_enable,
  939. .disable = fsl_ep_disable,
  940. .alloc_request = fsl_alloc_request,
  941. .free_request = fsl_free_request,
  942. .queue = fsl_ep_queue,
  943. .dequeue = fsl_ep_dequeue,
  944. .set_halt = fsl_ep_set_halt,
  945. .fifo_status = fsl_ep_fifo_status,
  946. .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
  947. };
  948. /*-------------------------------------------------------------------------
  949. Gadget Driver Layer Operations
  950. -------------------------------------------------------------------------*/
  951. /*----------------------------------------------------------------------
  952. * Get the current frame number (from DR frame_index Reg )
  953. *----------------------------------------------------------------------*/
  954. static int fsl_get_frame(struct usb_gadget *gadget)
  955. {
  956. return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
  957. }
  958. /*-----------------------------------------------------------------------
  959. * Tries to wake up the host connected to this gadget
  960. -----------------------------------------------------------------------*/
  961. static int fsl_wakeup(struct usb_gadget *gadget)
  962. {
  963. struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
  964. u32 portsc;
  965. /* Remote wakeup feature not enabled by host */
  966. if (!udc->remote_wakeup)
  967. return -ENOTSUPP;
  968. portsc = fsl_readl(&dr_regs->portsc1);
  969. /* not suspended? */
  970. if (!(portsc & PORTSCX_PORT_SUSPEND))
  971. return 0;
  972. /* trigger force resume */
  973. portsc |= PORTSCX_PORT_FORCE_RESUME;
  974. fsl_writel(portsc, &dr_regs->portsc1);
  975. return 0;
  976. }
  977. static int can_pullup(struct fsl_udc *udc)
  978. {
  979. return udc->driver && udc->softconnect && udc->vbus_active;
  980. }
  981. /* Notify controller that VBUS is powered, Called by whatever
  982. detects VBUS sessions */
  983. static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
  984. {
  985. struct fsl_udc *udc;
  986. unsigned long flags;
  987. udc = container_of(gadget, struct fsl_udc, gadget);
  988. spin_lock_irqsave(&udc->lock, flags);
  989. VDBG("VBUS %s", is_active ? "on" : "off");
  990. udc->vbus_active = (is_active != 0);
  991. if (can_pullup(udc))
  992. fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
  993. &dr_regs->usbcmd);
  994. else
  995. fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
  996. &dr_regs->usbcmd);
  997. spin_unlock_irqrestore(&udc->lock, flags);
  998. return 0;
  999. }
  1000. /* constrain controller's VBUS power usage
  1001. * This call is used by gadget drivers during SET_CONFIGURATION calls,
  1002. * reporting how much power the device may consume. For example, this
  1003. * could affect how quickly batteries are recharged.
  1004. *
  1005. * Returns zero on success, else negative errno.
  1006. */
  1007. static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
  1008. {
  1009. struct fsl_udc *udc;
  1010. udc = container_of(gadget, struct fsl_udc, gadget);
  1011. if (!IS_ERR_OR_NULL(udc->transceiver))
  1012. return usb_phy_set_power(udc->transceiver, mA);
  1013. return -ENOTSUPP;
  1014. }
  1015. /* Change Data+ pullup status
  1016. * this func is used by usb_gadget_connect/disconnet
  1017. */
  1018. static int fsl_pullup(struct usb_gadget *gadget, int is_on)
  1019. {
  1020. struct fsl_udc *udc;
  1021. udc = container_of(gadget, struct fsl_udc, gadget);
  1022. udc->softconnect = (is_on != 0);
  1023. if (can_pullup(udc))
  1024. fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
  1025. &dr_regs->usbcmd);
  1026. else
  1027. fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
  1028. &dr_regs->usbcmd);
  1029. return 0;
  1030. }
  1031. static int fsl_udc_start(struct usb_gadget *g,
  1032. struct usb_gadget_driver *driver);
  1033. static int fsl_udc_stop(struct usb_gadget *g,
  1034. struct usb_gadget_driver *driver);
  1035. /* defined in gadget.h */
  1036. static const struct usb_gadget_ops fsl_gadget_ops = {
  1037. .get_frame = fsl_get_frame,
  1038. .wakeup = fsl_wakeup,
  1039. /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
  1040. .vbus_session = fsl_vbus_session,
  1041. .vbus_draw = fsl_vbus_draw,
  1042. .pullup = fsl_pullup,
  1043. .udc_start = fsl_udc_start,
  1044. .udc_stop = fsl_udc_stop,
  1045. };
  1046. /* Set protocol stall on ep0, protocol stall will automatically be cleared
  1047. on new transaction */
  1048. static void ep0stall(struct fsl_udc *udc)
  1049. {
  1050. u32 tmp;
  1051. /* must set tx and rx to stall at the same time */
  1052. tmp = fsl_readl(&dr_regs->endptctrl[0]);
  1053. tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
  1054. fsl_writel(tmp, &dr_regs->endptctrl[0]);
  1055. udc->ep0_state = WAIT_FOR_SETUP;
  1056. udc->ep0_dir = 0;
  1057. }
  1058. /* Prime a status phase for ep0 */
  1059. static int ep0_prime_status(struct fsl_udc *udc, int direction)
  1060. {
  1061. struct fsl_req *req = udc->status_req;
  1062. struct fsl_ep *ep;
  1063. int ret;
  1064. if (direction == EP_DIR_IN)
  1065. udc->ep0_dir = USB_DIR_IN;
  1066. else
  1067. udc->ep0_dir = USB_DIR_OUT;
  1068. ep = &udc->eps[0];
  1069. if (udc->ep0_state != DATA_STATE_XMIT)
  1070. udc->ep0_state = WAIT_FOR_OUT_STATUS;
  1071. req->ep = ep;
  1072. req->req.length = 0;
  1073. req->req.status = -EINPROGRESS;
  1074. req->req.actual = 0;
  1075. req->req.complete = NULL;
  1076. req->dtd_count = 0;
  1077. ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
  1078. if (ret)
  1079. return ret;
  1080. if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
  1081. fsl_queue_td(ep, req);
  1082. else
  1083. return -ENOMEM;
  1084. list_add_tail(&req->queue, &ep->queue);
  1085. return 0;
  1086. }
  1087. static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
  1088. {
  1089. struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
  1090. if (ep->name)
  1091. nuke(ep, -ESHUTDOWN);
  1092. }
  1093. /*
  1094. * ch9 Set address
  1095. */
  1096. static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
  1097. {
  1098. /* Save the new address to device struct */
  1099. udc->device_address = (u8) value;
  1100. /* Update usb state */
  1101. udc->usb_state = USB_STATE_ADDRESS;
  1102. /* Status phase */
  1103. if (ep0_prime_status(udc, EP_DIR_IN))
  1104. ep0stall(udc);
  1105. }
  1106. /*
  1107. * ch9 Get status
  1108. */
  1109. static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
  1110. u16 index, u16 length)
  1111. {
  1112. u16 tmp = 0; /* Status, cpu endian */
  1113. struct fsl_req *req;
  1114. struct fsl_ep *ep;
  1115. int ret;
  1116. ep = &udc->eps[0];
  1117. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1118. /* Get device status */
  1119. tmp = 1 << USB_DEVICE_SELF_POWERED;
  1120. tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  1121. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1122. /* Get interface status */
  1123. /* We don't have interface information in udc driver */
  1124. tmp = 0;
  1125. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1126. /* Get endpoint status */
  1127. struct fsl_ep *target_ep;
  1128. target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
  1129. /* stall if endpoint doesn't exist */
  1130. if (!target_ep->ep.desc)
  1131. goto stall;
  1132. tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
  1133. << USB_ENDPOINT_HALT;
  1134. }
  1135. udc->ep0_dir = USB_DIR_IN;
  1136. /* Borrow the per device status_req */
  1137. req = udc->status_req;
  1138. /* Fill in the reqest structure */
  1139. *((u16 *) req->req.buf) = cpu_to_le16(tmp);
  1140. req->ep = ep;
  1141. req->req.length = 2;
  1142. req->req.status = -EINPROGRESS;
  1143. req->req.actual = 0;
  1144. req->req.complete = NULL;
  1145. req->dtd_count = 0;
  1146. ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
  1147. if (ret)
  1148. goto stall;
  1149. /* prime the data phase */
  1150. if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
  1151. fsl_queue_td(ep, req);
  1152. else /* no mem */
  1153. goto stall;
  1154. list_add_tail(&req->queue, &ep->queue);
  1155. udc->ep0_state = DATA_STATE_XMIT;
  1156. if (ep0_prime_status(udc, EP_DIR_OUT))
  1157. ep0stall(udc);
  1158. return;
  1159. stall:
  1160. ep0stall(udc);
  1161. }
  1162. static void setup_received_irq(struct fsl_udc *udc,
  1163. struct usb_ctrlrequest *setup)
  1164. {
  1165. u16 wValue = le16_to_cpu(setup->wValue);
  1166. u16 wIndex = le16_to_cpu(setup->wIndex);
  1167. u16 wLength = le16_to_cpu(setup->wLength);
  1168. udc_reset_ep_queue(udc, 0);
  1169. /* We process some stardard setup requests here */
  1170. switch (setup->bRequest) {
  1171. case USB_REQ_GET_STATUS:
  1172. /* Data+Status phase from udc */
  1173. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1174. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1175. break;
  1176. ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
  1177. return;
  1178. case USB_REQ_SET_ADDRESS:
  1179. /* Status phase from udc */
  1180. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
  1181. | USB_RECIP_DEVICE))
  1182. break;
  1183. ch9setaddress(udc, wValue, wIndex, wLength);
  1184. return;
  1185. case USB_REQ_CLEAR_FEATURE:
  1186. case USB_REQ_SET_FEATURE:
  1187. /* Status phase from udc */
  1188. {
  1189. int rc = -EOPNOTSUPP;
  1190. u16 ptc = 0;
  1191. if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
  1192. == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
  1193. int pipe = get_pipe_by_windex(wIndex);
  1194. struct fsl_ep *ep;
  1195. if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
  1196. break;
  1197. ep = get_ep_by_pipe(udc, pipe);
  1198. spin_unlock(&udc->lock);
  1199. rc = fsl_ep_set_halt(&ep->ep,
  1200. (setup->bRequest == USB_REQ_SET_FEATURE)
  1201. ? 1 : 0);
  1202. spin_lock(&udc->lock);
  1203. } else if ((setup->bRequestType & (USB_RECIP_MASK
  1204. | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
  1205. | USB_TYPE_STANDARD)) {
  1206. /* Note: The driver has not include OTG support yet.
  1207. * This will be set when OTG support is added */
  1208. if (wValue == USB_DEVICE_TEST_MODE)
  1209. ptc = wIndex >> 8;
  1210. else if (gadget_is_otg(&udc->gadget)) {
  1211. if (setup->bRequest ==
  1212. USB_DEVICE_B_HNP_ENABLE)
  1213. udc->gadget.b_hnp_enable = 1;
  1214. else if (setup->bRequest ==
  1215. USB_DEVICE_A_HNP_SUPPORT)
  1216. udc->gadget.a_hnp_support = 1;
  1217. else if (setup->bRequest ==
  1218. USB_DEVICE_A_ALT_HNP_SUPPORT)
  1219. udc->gadget.a_alt_hnp_support = 1;
  1220. }
  1221. rc = 0;
  1222. } else
  1223. break;
  1224. if (rc == 0) {
  1225. if (ep0_prime_status(udc, EP_DIR_IN))
  1226. ep0stall(udc);
  1227. }
  1228. if (ptc) {
  1229. u32 tmp;
  1230. mdelay(10);
  1231. tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
  1232. fsl_writel(tmp, &dr_regs->portsc1);
  1233. printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
  1234. }
  1235. return;
  1236. }
  1237. default:
  1238. break;
  1239. }
  1240. /* Requests handled by gadget */
  1241. if (wLength) {
  1242. /* Data phase from gadget, status phase from udc */
  1243. udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
  1244. ? USB_DIR_IN : USB_DIR_OUT;
  1245. spin_unlock(&udc->lock);
  1246. if (udc->driver->setup(&udc->gadget,
  1247. &udc->local_setup_buff) < 0)
  1248. ep0stall(udc);
  1249. spin_lock(&udc->lock);
  1250. udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
  1251. ? DATA_STATE_XMIT : DATA_STATE_RECV;
  1252. /*
  1253. * If the data stage is IN, send status prime immediately.
  1254. * See 2.0 Spec chapter 8.5.3.3 for detail.
  1255. */
  1256. if (udc->ep0_state == DATA_STATE_XMIT)
  1257. if (ep0_prime_status(udc, EP_DIR_OUT))
  1258. ep0stall(udc);
  1259. } else {
  1260. /* No data phase, IN status from gadget */
  1261. udc->ep0_dir = USB_DIR_IN;
  1262. spin_unlock(&udc->lock);
  1263. if (udc->driver->setup(&udc->gadget,
  1264. &udc->local_setup_buff) < 0)
  1265. ep0stall(udc);
  1266. spin_lock(&udc->lock);
  1267. udc->ep0_state = WAIT_FOR_OUT_STATUS;
  1268. }
  1269. }
  1270. /* Process request for Data or Status phase of ep0
  1271. * prime status phase if needed */
  1272. static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
  1273. struct fsl_req *req)
  1274. {
  1275. if (udc->usb_state == USB_STATE_ADDRESS) {
  1276. /* Set the new address */
  1277. u32 new_address = (u32) udc->device_address;
  1278. fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
  1279. &dr_regs->deviceaddr);
  1280. }
  1281. done(ep0, req, 0);
  1282. switch (udc->ep0_state) {
  1283. case DATA_STATE_XMIT:
  1284. /* already primed at setup_received_irq */
  1285. udc->ep0_state = WAIT_FOR_OUT_STATUS;
  1286. break;
  1287. case DATA_STATE_RECV:
  1288. /* send status phase */
  1289. if (ep0_prime_status(udc, EP_DIR_IN))
  1290. ep0stall(udc);
  1291. break;
  1292. case WAIT_FOR_OUT_STATUS:
  1293. udc->ep0_state = WAIT_FOR_SETUP;
  1294. break;
  1295. case WAIT_FOR_SETUP:
  1296. ERR("Unexpect ep0 packets\n");
  1297. break;
  1298. default:
  1299. ep0stall(udc);
  1300. break;
  1301. }
  1302. }
  1303. /* Tripwire mechanism to ensure a setup packet payload is extracted without
  1304. * being corrupted by another incoming setup packet */
  1305. static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
  1306. {
  1307. u32 temp;
  1308. struct ep_queue_head *qh;
  1309. struct fsl_usb2_platform_data *pdata = udc->pdata;
  1310. qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
  1311. /* Clear bit in ENDPTSETUPSTAT */
  1312. temp = fsl_readl(&dr_regs->endptsetupstat);
  1313. fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
  1314. /* while a hazard exists when setup package arrives */
  1315. do {
  1316. /* Set Setup Tripwire */
  1317. temp = fsl_readl(&dr_regs->usbcmd);
  1318. fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
  1319. /* Copy the setup packet to local buffer */
  1320. if (pdata->le_setup_buf) {
  1321. u32 *p = (u32 *)buffer_ptr;
  1322. u32 *s = (u32 *)qh->setup_buffer;
  1323. /* Convert little endian setup buffer to CPU endian */
  1324. *p++ = le32_to_cpu(*s++);
  1325. *p = le32_to_cpu(*s);
  1326. } else {
  1327. memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
  1328. }
  1329. } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
  1330. /* Clear Setup Tripwire */
  1331. temp = fsl_readl(&dr_regs->usbcmd);
  1332. fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
  1333. }
  1334. /* process-ep_req(): free the completed Tds for this req */
  1335. static int process_ep_req(struct fsl_udc *udc, int pipe,
  1336. struct fsl_req *curr_req)
  1337. {
  1338. struct ep_td_struct *curr_td;
  1339. int td_complete, actual, remaining_length, j, tmp;
  1340. int status = 0;
  1341. int errors = 0;
  1342. struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
  1343. int direction = pipe % 2;
  1344. curr_td = curr_req->head;
  1345. td_complete = 0;
  1346. actual = curr_req->req.length;
  1347. for (j = 0; j < curr_req->dtd_count; j++) {
  1348. remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
  1349. & DTD_PACKET_SIZE)
  1350. >> DTD_LENGTH_BIT_POS;
  1351. actual -= remaining_length;
  1352. errors = hc32_to_cpu(curr_td->size_ioc_sts);
  1353. if (errors & DTD_ERROR_MASK) {
  1354. if (errors & DTD_STATUS_HALTED) {
  1355. ERR("dTD error %08x QH=%d\n", errors, pipe);
  1356. /* Clear the errors and Halt condition */
  1357. tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
  1358. tmp &= ~errors;
  1359. curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
  1360. status = -EPIPE;
  1361. /* FIXME: continue with next queued TD? */
  1362. break;
  1363. }
  1364. if (errors & DTD_STATUS_DATA_BUFF_ERR) {
  1365. VDBG("Transfer overflow");
  1366. status = -EPROTO;
  1367. break;
  1368. } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
  1369. VDBG("ISO error");
  1370. status = -EILSEQ;
  1371. break;
  1372. } else
  1373. ERR("Unknown error has occurred (0x%x)!\n",
  1374. errors);
  1375. } else if (hc32_to_cpu(curr_td->size_ioc_sts)
  1376. & DTD_STATUS_ACTIVE) {
  1377. VDBG("Request not complete");
  1378. status = REQ_UNCOMPLETE;
  1379. return status;
  1380. } else if (remaining_length) {
  1381. if (direction) {
  1382. VDBG("Transmit dTD remaining length not zero");
  1383. status = -EPROTO;
  1384. break;
  1385. } else {
  1386. td_complete++;
  1387. break;
  1388. }
  1389. } else {
  1390. td_complete++;
  1391. VDBG("dTD transmitted successful");
  1392. }
  1393. if (j != curr_req->dtd_count - 1)
  1394. curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
  1395. }
  1396. if (status)
  1397. return status;
  1398. curr_req->req.actual = actual;
  1399. return 0;
  1400. }
  1401. /* Process a DTD completion interrupt */
  1402. static void dtd_complete_irq(struct fsl_udc *udc)
  1403. {
  1404. u32 bit_pos;
  1405. int i, ep_num, direction, bit_mask, status;
  1406. struct fsl_ep *curr_ep;
  1407. struct fsl_req *curr_req, *temp_req;
  1408. /* Clear the bits in the register */
  1409. bit_pos = fsl_readl(&dr_regs->endptcomplete);
  1410. fsl_writel(bit_pos, &dr_regs->endptcomplete);
  1411. if (!bit_pos)
  1412. return;
  1413. for (i = 0; i < udc->max_ep; i++) {
  1414. ep_num = i >> 1;
  1415. direction = i % 2;
  1416. bit_mask = 1 << (ep_num + 16 * direction);
  1417. if (!(bit_pos & bit_mask))
  1418. continue;
  1419. curr_ep = get_ep_by_pipe(udc, i);
  1420. /* If the ep is configured */
  1421. if (curr_ep->name == NULL) {
  1422. WARNING("Invalid EP?");
  1423. continue;
  1424. }
  1425. /* process the req queue until an uncomplete request */
  1426. list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
  1427. queue) {
  1428. status = process_ep_req(udc, i, curr_req);
  1429. VDBG("status of process_ep_req= %d, ep = %d",
  1430. status, ep_num);
  1431. if (status == REQ_UNCOMPLETE)
  1432. break;
  1433. /* write back status to req */
  1434. curr_req->req.status = status;
  1435. if (ep_num == 0) {
  1436. ep0_req_complete(udc, curr_ep, curr_req);
  1437. break;
  1438. } else
  1439. done(curr_ep, curr_req, status);
  1440. }
  1441. }
  1442. }
  1443. static inline enum usb_device_speed portscx_device_speed(u32 reg)
  1444. {
  1445. switch (reg & PORTSCX_PORT_SPEED_MASK) {
  1446. case PORTSCX_PORT_SPEED_HIGH:
  1447. return USB_SPEED_HIGH;
  1448. case PORTSCX_PORT_SPEED_FULL:
  1449. return USB_SPEED_FULL;
  1450. case PORTSCX_PORT_SPEED_LOW:
  1451. return USB_SPEED_LOW;
  1452. default:
  1453. return USB_SPEED_UNKNOWN;
  1454. }
  1455. }
  1456. /* Process a port change interrupt */
  1457. static void port_change_irq(struct fsl_udc *udc)
  1458. {
  1459. if (udc->bus_reset)
  1460. udc->bus_reset = 0;
  1461. /* Bus resetting is finished */
  1462. if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
  1463. /* Get the speed */
  1464. udc->gadget.speed =
  1465. portscx_device_speed(fsl_readl(&dr_regs->portsc1));
  1466. /* Update USB state */
  1467. if (!udc->resume_state)
  1468. udc->usb_state = USB_STATE_DEFAULT;
  1469. }
  1470. /* Process suspend interrupt */
  1471. static void suspend_irq(struct fsl_udc *udc)
  1472. {
  1473. udc->resume_state = udc->usb_state;
  1474. udc->usb_state = USB_STATE_SUSPENDED;
  1475. /* report suspend to the driver, serial.c does not support this */
  1476. if (udc->driver->suspend)
  1477. udc->driver->suspend(&udc->gadget);
  1478. }
  1479. static void bus_resume(struct fsl_udc *udc)
  1480. {
  1481. udc->usb_state = udc->resume_state;
  1482. udc->resume_state = 0;
  1483. /* report resume to the driver, serial.c does not support this */
  1484. if (udc->driver->resume)
  1485. udc->driver->resume(&udc->gadget);
  1486. }
  1487. /* Clear up all ep queues */
  1488. static int reset_queues(struct fsl_udc *udc)
  1489. {
  1490. u8 pipe;
  1491. for (pipe = 0; pipe < udc->max_pipes; pipe++)
  1492. udc_reset_ep_queue(udc, pipe);
  1493. /* report disconnect; the driver is already quiesced */
  1494. spin_unlock(&udc->lock);
  1495. udc->driver->disconnect(&udc->gadget);
  1496. spin_lock(&udc->lock);
  1497. return 0;
  1498. }
  1499. /* Process reset interrupt */
  1500. static void reset_irq(struct fsl_udc *udc)
  1501. {
  1502. u32 temp;
  1503. unsigned long timeout;
  1504. /* Clear the device address */
  1505. temp = fsl_readl(&dr_regs->deviceaddr);
  1506. fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
  1507. udc->device_address = 0;
  1508. /* Clear usb state */
  1509. udc->resume_state = 0;
  1510. udc->ep0_dir = 0;
  1511. udc->ep0_state = WAIT_FOR_SETUP;
  1512. udc->remote_wakeup = 0; /* default to 0 on reset */
  1513. udc->gadget.b_hnp_enable = 0;
  1514. udc->gadget.a_hnp_support = 0;
  1515. udc->gadget.a_alt_hnp_support = 0;
  1516. /* Clear all the setup token semaphores */
  1517. temp = fsl_readl(&dr_regs->endptsetupstat);
  1518. fsl_writel(temp, &dr_regs->endptsetupstat);
  1519. /* Clear all the endpoint complete status bits */
  1520. temp = fsl_readl(&dr_regs->endptcomplete);
  1521. fsl_writel(temp, &dr_regs->endptcomplete);
  1522. timeout = jiffies + 100;
  1523. while (fsl_readl(&dr_regs->endpointprime)) {
  1524. /* Wait until all endptprime bits cleared */
  1525. if (time_after(jiffies, timeout)) {
  1526. ERR("Timeout for reset\n");
  1527. break;
  1528. }
  1529. cpu_relax();
  1530. }
  1531. /* Write 1s to the flush register */
  1532. fsl_writel(0xffffffff, &dr_regs->endptflush);
  1533. if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
  1534. VDBG("Bus reset");
  1535. /* Bus is reseting */
  1536. udc->bus_reset = 1;
  1537. /* Reset all the queues, include XD, dTD, EP queue
  1538. * head and TR Queue */
  1539. reset_queues(udc);
  1540. udc->usb_state = USB_STATE_DEFAULT;
  1541. } else {
  1542. VDBG("Controller reset");
  1543. /* initialize usb hw reg except for regs for EP, not
  1544. * touch usbintr reg */
  1545. dr_controller_setup(udc);
  1546. /* Reset all internal used Queues */
  1547. reset_queues(udc);
  1548. ep0_setup(udc);
  1549. /* Enable DR IRQ reg, Set Run bit, change udc state */
  1550. dr_controller_run(udc);
  1551. udc->usb_state = USB_STATE_ATTACHED;
  1552. }
  1553. }
  1554. /*
  1555. * USB device controller interrupt handler
  1556. */
  1557. static irqreturn_t fsl_udc_irq(int irq, void *_udc)
  1558. {
  1559. struct fsl_udc *udc = _udc;
  1560. u32 irq_src;
  1561. irqreturn_t status = IRQ_NONE;
  1562. unsigned long flags;
  1563. /* Disable ISR for OTG host mode */
  1564. if (udc->stopped)
  1565. return IRQ_NONE;
  1566. spin_lock_irqsave(&udc->lock, flags);
  1567. irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
  1568. /* Clear notification bits */
  1569. fsl_writel(irq_src, &dr_regs->usbsts);
  1570. /* VDBG("irq_src [0x%8x]", irq_src); */
  1571. /* Need to resume? */
  1572. if (udc->usb_state == USB_STATE_SUSPENDED)
  1573. if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
  1574. bus_resume(udc);
  1575. /* USB Interrupt */
  1576. if (irq_src & USB_STS_INT) {
  1577. VDBG("Packet int");
  1578. /* Setup package, we only support ep0 as control ep */
  1579. if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
  1580. tripwire_handler(udc, 0,
  1581. (u8 *) (&udc->local_setup_buff));
  1582. setup_received_irq(udc, &udc->local_setup_buff);
  1583. status = IRQ_HANDLED;
  1584. }
  1585. /* completion of dtd */
  1586. if (fsl_readl(&dr_regs->endptcomplete)) {
  1587. dtd_complete_irq(udc);
  1588. status = IRQ_HANDLED;
  1589. }
  1590. }
  1591. /* SOF (for ISO transfer) */
  1592. if (irq_src & USB_STS_SOF) {
  1593. status = IRQ_HANDLED;
  1594. }
  1595. /* Port Change */
  1596. if (irq_src & USB_STS_PORT_CHANGE) {
  1597. port_change_irq(udc);
  1598. status = IRQ_HANDLED;
  1599. }
  1600. /* Reset Received */
  1601. if (irq_src & USB_STS_RESET) {
  1602. VDBG("reset int");
  1603. reset_irq(udc);
  1604. status = IRQ_HANDLED;
  1605. }
  1606. /* Sleep Enable (Suspend) */
  1607. if (irq_src & USB_STS_SUSPEND) {
  1608. suspend_irq(udc);
  1609. status = IRQ_HANDLED;
  1610. }
  1611. if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
  1612. VDBG("Error IRQ %x", irq_src);
  1613. }
  1614. spin_unlock_irqrestore(&udc->lock, flags);
  1615. return status;
  1616. }
  1617. /*----------------------------------------------------------------*
  1618. * Hook to gadget drivers
  1619. * Called by initialization code of gadget drivers
  1620. *----------------------------------------------------------------*/
  1621. static int fsl_udc_start(struct usb_gadget *g,
  1622. struct usb_gadget_driver *driver)
  1623. {
  1624. int retval = 0;
  1625. unsigned long flags = 0;
  1626. /* lock is needed but whether should use this lock or another */
  1627. spin_lock_irqsave(&udc_controller->lock, flags);
  1628. driver->driver.bus = NULL;
  1629. /* hook up the driver */
  1630. udc_controller->driver = driver;
  1631. spin_unlock_irqrestore(&udc_controller->lock, flags);
  1632. if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
  1633. /* Suspend the controller until OTG enable it */
  1634. udc_controller->stopped = 1;
  1635. printk(KERN_INFO "Suspend udc for OTG auto detect\n");
  1636. /* connect to bus through transceiver */
  1637. if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
  1638. retval = otg_set_peripheral(
  1639. udc_controller->transceiver->otg,
  1640. &udc_controller->gadget);
  1641. if (retval < 0) {
  1642. ERR("can't bind to transceiver\n");
  1643. driver->unbind(&udc_controller->gadget);
  1644. udc_controller->driver = 0;
  1645. return retval;
  1646. }
  1647. }
  1648. } else {
  1649. /* Enable DR IRQ reg and set USBCMD reg Run bit */
  1650. dr_controller_run(udc_controller);
  1651. udc_controller->usb_state = USB_STATE_ATTACHED;
  1652. udc_controller->ep0_state = WAIT_FOR_SETUP;
  1653. udc_controller->ep0_dir = 0;
  1654. }
  1655. return retval;
  1656. }
  1657. /* Disconnect from gadget driver */
  1658. static int fsl_udc_stop(struct usb_gadget *g,
  1659. struct usb_gadget_driver *driver)
  1660. {
  1661. struct fsl_ep *loop_ep;
  1662. unsigned long flags;
  1663. if (!IS_ERR_OR_NULL(udc_controller->transceiver))
  1664. otg_set_peripheral(udc_controller->transceiver->otg, NULL);
  1665. /* stop DR, disable intr */
  1666. dr_controller_stop(udc_controller);
  1667. /* in fact, no needed */
  1668. udc_controller->usb_state = USB_STATE_ATTACHED;
  1669. udc_controller->ep0_state = WAIT_FOR_SETUP;
  1670. udc_controller->ep0_dir = 0;
  1671. /* stand operation */
  1672. spin_lock_irqsave(&udc_controller->lock, flags);
  1673. udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
  1674. nuke(&udc_controller->eps[0], -ESHUTDOWN);
  1675. list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
  1676. ep.ep_list)
  1677. nuke(loop_ep, -ESHUTDOWN);
  1678. spin_unlock_irqrestore(&udc_controller->lock, flags);
  1679. udc_controller->driver = NULL;
  1680. return 0;
  1681. }
  1682. /*-------------------------------------------------------------------------
  1683. PROC File System Support
  1684. -------------------------------------------------------------------------*/
  1685. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  1686. #include <linux/seq_file.h>
  1687. static const char proc_filename[] = "driver/fsl_usb2_udc";
  1688. static int fsl_proc_read(char *page, char **start, off_t off, int count,
  1689. int *eof, void *_dev)
  1690. {
  1691. char *buf = page;
  1692. char *next = buf;
  1693. unsigned size = count;
  1694. unsigned long flags;
  1695. int t, i;
  1696. u32 tmp_reg;
  1697. struct fsl_ep *ep = NULL;
  1698. struct fsl_req *req;
  1699. struct fsl_udc *udc = udc_controller;
  1700. if (off != 0)
  1701. return 0;
  1702. spin_lock_irqsave(&udc->lock, flags);
  1703. /* ------basic driver information ---- */
  1704. t = scnprintf(next, size,
  1705. DRIVER_DESC "\n"
  1706. "%s version: %s\n"
  1707. "Gadget driver: %s\n\n",
  1708. driver_name, DRIVER_VERSION,
  1709. udc->driver ? udc->driver->driver.name : "(none)");
  1710. size -= t;
  1711. next += t;
  1712. /* ------ DR Registers ----- */
  1713. tmp_reg = fsl_readl(&dr_regs->usbcmd);
  1714. t = scnprintf(next, size,
  1715. "USBCMD reg:\n"
  1716. "SetupTW: %d\n"
  1717. "Run/Stop: %s\n\n",
  1718. (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
  1719. (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
  1720. size -= t;
  1721. next += t;
  1722. tmp_reg = fsl_readl(&dr_regs->usbsts);
  1723. t = scnprintf(next, size,
  1724. "USB Status Reg:\n"
  1725. "Dr Suspend: %d Reset Received: %d System Error: %s "
  1726. "USB Error Interrupt: %s\n\n",
  1727. (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
  1728. (tmp_reg & USB_STS_RESET) ? 1 : 0,
  1729. (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
  1730. (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
  1731. size -= t;
  1732. next += t;
  1733. tmp_reg = fsl_readl(&dr_regs->usbintr);
  1734. t = scnprintf(next, size,
  1735. "USB Interrupt Enable Reg:\n"
  1736. "Sleep Enable: %d SOF Received Enable: %d "
  1737. "Reset Enable: %d\n"
  1738. "System Error Enable: %d "
  1739. "Port Change Dectected Enable: %d\n"
  1740. "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
  1741. (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
  1742. (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
  1743. (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
  1744. (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
  1745. (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
  1746. (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
  1747. (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
  1748. size -= t;
  1749. next += t;
  1750. tmp_reg = fsl_readl(&dr_regs->frindex);
  1751. t = scnprintf(next, size,
  1752. "USB Frame Index Reg: Frame Number is 0x%x\n\n",
  1753. (tmp_reg & USB_FRINDEX_MASKS));
  1754. size -= t;
  1755. next += t;
  1756. tmp_reg = fsl_readl(&dr_regs->deviceaddr);
  1757. t = scnprintf(next, size,
  1758. "USB Device Address Reg: Device Addr is 0x%x\n\n",
  1759. (tmp_reg & USB_DEVICE_ADDRESS_MASK));
  1760. size -= t;
  1761. next += t;
  1762. tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
  1763. t = scnprintf(next, size,
  1764. "USB Endpoint List Address Reg: "
  1765. "Device Addr is 0x%x\n\n",
  1766. (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
  1767. size -= t;
  1768. next += t;
  1769. tmp_reg = fsl_readl(&dr_regs->portsc1);
  1770. t = scnprintf(next, size,
  1771. "USB Port Status&Control Reg:\n"
  1772. "Port Transceiver Type : %s Port Speed: %s\n"
  1773. "PHY Low Power Suspend: %s Port Reset: %s "
  1774. "Port Suspend Mode: %s\n"
  1775. "Over-current Change: %s "
  1776. "Port Enable/Disable Change: %s\n"
  1777. "Port Enabled/Disabled: %s "
  1778. "Current Connect Status: %s\n\n", ( {
  1779. char *s;
  1780. switch (tmp_reg & PORTSCX_PTS_FSLS) {
  1781. case PORTSCX_PTS_UTMI:
  1782. s = "UTMI"; break;
  1783. case PORTSCX_PTS_ULPI:
  1784. s = "ULPI "; break;
  1785. case PORTSCX_PTS_FSLS:
  1786. s = "FS/LS Serial"; break;
  1787. default:
  1788. s = "None"; break;
  1789. }
  1790. s;} ),
  1791. usb_speed_string(portscx_device_speed(tmp_reg)),
  1792. (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
  1793. "Normal PHY mode" : "Low power mode",
  1794. (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
  1795. "Not in Reset",
  1796. (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
  1797. (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
  1798. "No",
  1799. (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
  1800. "Not change",
  1801. (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
  1802. "Not correct",
  1803. (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
  1804. "Attached" : "Not-Att");
  1805. size -= t;
  1806. next += t;
  1807. tmp_reg = fsl_readl(&dr_regs->usbmode);
  1808. t = scnprintf(next, size,
  1809. "USB Mode Reg: Controller Mode is: %s\n\n", ( {
  1810. char *s;
  1811. switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
  1812. case USB_MODE_CTRL_MODE_IDLE:
  1813. s = "Idle"; break;
  1814. case USB_MODE_CTRL_MODE_DEVICE:
  1815. s = "Device Controller"; break;
  1816. case USB_MODE_CTRL_MODE_HOST:
  1817. s = "Host Controller"; break;
  1818. default:
  1819. s = "None"; break;
  1820. }
  1821. s;
  1822. } ));
  1823. size -= t;
  1824. next += t;
  1825. tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
  1826. t = scnprintf(next, size,
  1827. "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
  1828. (tmp_reg & EP_SETUP_STATUS_MASK));
  1829. size -= t;
  1830. next += t;
  1831. for (i = 0; i < udc->max_ep / 2; i++) {
  1832. tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
  1833. t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
  1834. i, tmp_reg);
  1835. size -= t;
  1836. next += t;
  1837. }
  1838. tmp_reg = fsl_readl(&dr_regs->endpointprime);
  1839. t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
  1840. size -= t;
  1841. next += t;
  1842. #ifndef CONFIG_ARCH_MXC
  1843. if (udc->pdata->have_sysif_regs) {
  1844. tmp_reg = usb_sys_regs->snoop1;
  1845. t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
  1846. size -= t;
  1847. next += t;
  1848. tmp_reg = usb_sys_regs->control;
  1849. t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
  1850. tmp_reg);
  1851. size -= t;
  1852. next += t;
  1853. }
  1854. #endif
  1855. /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
  1856. ep = &udc->eps[0];
  1857. t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
  1858. ep->ep.name, ep_maxpacket(ep), ep_index(ep));
  1859. size -= t;
  1860. next += t;
  1861. if (list_empty(&ep->queue)) {
  1862. t = scnprintf(next, size, "its req queue is empty\n\n");
  1863. size -= t;
  1864. next += t;
  1865. } else {
  1866. list_for_each_entry(req, &ep->queue, queue) {
  1867. t = scnprintf(next, size,
  1868. "req %p actual 0x%x length 0x%x buf %p\n",
  1869. &req->req, req->req.actual,
  1870. req->req.length, req->req.buf);
  1871. size -= t;
  1872. next += t;
  1873. }
  1874. }
  1875. /* other gadget->eplist ep */
  1876. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  1877. if (ep->ep.desc) {
  1878. t = scnprintf(next, size,
  1879. "\nFor %s Maxpkt is 0x%x "
  1880. "index is 0x%x\n",
  1881. ep->ep.name, ep_maxpacket(ep),
  1882. ep_index(ep));
  1883. size -= t;
  1884. next += t;
  1885. if (list_empty(&ep->queue)) {
  1886. t = scnprintf(next, size,
  1887. "its req queue is empty\n\n");
  1888. size -= t;
  1889. next += t;
  1890. } else {
  1891. list_for_each_entry(req, &ep->queue, queue) {
  1892. t = scnprintf(next, size,
  1893. "req %p actual 0x%x length "
  1894. "0x%x buf %p\n",
  1895. &req->req, req->req.actual,
  1896. req->req.length, req->req.buf);
  1897. size -= t;
  1898. next += t;
  1899. } /* end for each_entry of ep req */
  1900. } /* end for else */
  1901. } /* end for if(ep->queue) */
  1902. } /* end (ep->desc) */
  1903. spin_unlock_irqrestore(&udc->lock, flags);
  1904. *eof = 1;
  1905. return count - size;
  1906. }
  1907. #define create_proc_file() create_proc_read_entry(proc_filename, \
  1908. 0, NULL, fsl_proc_read, NULL)
  1909. #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
  1910. #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
  1911. #define create_proc_file() do {} while (0)
  1912. #define remove_proc_file() do {} while (0)
  1913. #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
  1914. /*-------------------------------------------------------------------------*/
  1915. /* Release udc structures */
  1916. static void fsl_udc_release(struct device *dev)
  1917. {
  1918. complete(udc_controller->done);
  1919. dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
  1920. udc_controller->ep_qh, udc_controller->ep_qh_dma);
  1921. kfree(udc_controller);
  1922. }
  1923. /******************************************************************
  1924. Internal structure setup functions
  1925. *******************************************************************/
  1926. /*------------------------------------------------------------------
  1927. * init resource for globle controller
  1928. * Return the udc handle on success or NULL on failure
  1929. ------------------------------------------------------------------*/
  1930. static int __init struct_udc_setup(struct fsl_udc *udc,
  1931. struct platform_device *pdev)
  1932. {
  1933. struct fsl_usb2_platform_data *pdata;
  1934. size_t size;
  1935. pdata = pdev->dev.platform_data;
  1936. udc->phy_mode = pdata->phy_mode;
  1937. udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
  1938. if (!udc->eps) {
  1939. ERR("malloc fsl_ep failed\n");
  1940. return -1;
  1941. }
  1942. /* initialized QHs, take care of alignment */
  1943. size = udc->max_ep * sizeof(struct ep_queue_head);
  1944. if (size < QH_ALIGNMENT)
  1945. size = QH_ALIGNMENT;
  1946. else if ((size % QH_ALIGNMENT) != 0) {
  1947. size += QH_ALIGNMENT + 1;
  1948. size &= ~(QH_ALIGNMENT - 1);
  1949. }
  1950. udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
  1951. &udc->ep_qh_dma, GFP_KERNEL);
  1952. if (!udc->ep_qh) {
  1953. ERR("malloc QHs for udc failed\n");
  1954. kfree(udc->eps);
  1955. return -1;
  1956. }
  1957. udc->ep_qh_size = size;
  1958. /* Initialize ep0 status request structure */
  1959. /* FIXME: fsl_alloc_request() ignores ep argument */
  1960. udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
  1961. struct fsl_req, req);
  1962. /* allocate a small amount of memory to get valid address */
  1963. udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
  1964. udc->resume_state = USB_STATE_NOTATTACHED;
  1965. udc->usb_state = USB_STATE_POWERED;
  1966. udc->ep0_dir = 0;
  1967. udc->remote_wakeup = 0; /* default to 0 on reset */
  1968. return 0;
  1969. }
  1970. /*----------------------------------------------------------------
  1971. * Setup the fsl_ep struct for eps
  1972. * Link fsl_ep->ep to gadget->ep_list
  1973. * ep0out is not used so do nothing here
  1974. * ep0in should be taken care
  1975. *--------------------------------------------------------------*/
  1976. static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
  1977. char *name, int link)
  1978. {
  1979. struct fsl_ep *ep = &udc->eps[index];
  1980. ep->udc = udc;
  1981. strcpy(ep->name, name);
  1982. ep->ep.name = ep->name;
  1983. ep->ep.ops = &fsl_ep_ops;
  1984. ep->stopped = 0;
  1985. /* for ep0: maxP defined in desc
  1986. * for other eps, maxP is set by epautoconfig() called by gadget layer
  1987. */
  1988. ep->ep.maxpacket = (unsigned short) ~0;
  1989. /* the queue lists any req for this ep */
  1990. INIT_LIST_HEAD(&ep->queue);
  1991. /* gagdet.ep_list used for ep_autoconfig so no ep0 */
  1992. if (link)
  1993. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1994. ep->gadget = &udc->gadget;
  1995. ep->qh = &udc->ep_qh[index];
  1996. return 0;
  1997. }
  1998. /* Driver probe function
  1999. * all intialization operations implemented here except enabling usb_intr reg
  2000. * board setup should have been done in the platform code
  2001. */
  2002. static int __init fsl_udc_probe(struct platform_device *pdev)
  2003. {
  2004. struct fsl_usb2_platform_data *pdata;
  2005. struct resource *res;
  2006. int ret = -ENODEV;
  2007. unsigned int i;
  2008. u32 dccparams;
  2009. udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
  2010. if (udc_controller == NULL) {
  2011. ERR("malloc udc failed\n");
  2012. return -ENOMEM;
  2013. }
  2014. pdata = pdev->dev.platform_data;
  2015. udc_controller->pdata = pdata;
  2016. spin_lock_init(&udc_controller->lock);
  2017. udc_controller->stopped = 1;
  2018. #ifdef CONFIG_USB_OTG
  2019. if (pdata->operating_mode == FSL_USB2_DR_OTG) {
  2020. udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
  2021. if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
  2022. ERR("Can't find OTG driver!\n");
  2023. ret = -ENODEV;
  2024. goto err_kfree;
  2025. }
  2026. }
  2027. #endif
  2028. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2029. if (!res) {
  2030. ret = -ENXIO;
  2031. goto err_kfree;
  2032. }
  2033. if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
  2034. if (!request_mem_region(res->start, resource_size(res),
  2035. driver_name)) {
  2036. ERR("request mem region for %s failed\n", pdev->name);
  2037. ret = -EBUSY;
  2038. goto err_kfree;
  2039. }
  2040. }
  2041. dr_regs = ioremap(res->start, resource_size(res));
  2042. if (!dr_regs) {
  2043. ret = -ENOMEM;
  2044. goto err_release_mem_region;
  2045. }
  2046. pdata->regs = (void *)dr_regs;
  2047. /*
  2048. * do platform specific init: check the clock, grab/config pins, etc.
  2049. */
  2050. if (pdata->init && pdata->init(pdev)) {
  2051. ret = -ENODEV;
  2052. goto err_iounmap_noclk;
  2053. }
  2054. /* Set accessors only after pdata->init() ! */
  2055. fsl_set_accessors(pdata);
  2056. #ifndef CONFIG_ARCH_MXC
  2057. if (pdata->have_sysif_regs)
  2058. usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
  2059. #endif
  2060. /* Initialize USB clocks */
  2061. ret = fsl_udc_clk_init(pdev);
  2062. if (ret < 0)
  2063. goto err_iounmap_noclk;
  2064. /* Read Device Controller Capability Parameters register */
  2065. dccparams = fsl_readl(&dr_regs->dccparams);
  2066. if (!(dccparams & DCCPARAMS_DC)) {
  2067. ERR("This SOC doesn't support device role\n");
  2068. ret = -ENODEV;
  2069. goto err_iounmap;
  2070. }
  2071. /* Get max device endpoints */
  2072. /* DEN is bidirectional ep number, max_ep doubles the number */
  2073. udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
  2074. udc_controller->irq = platform_get_irq(pdev, 0);
  2075. if (!udc_controller->irq) {
  2076. ret = -ENODEV;
  2077. goto err_iounmap;
  2078. }
  2079. ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
  2080. driver_name, udc_controller);
  2081. if (ret != 0) {
  2082. ERR("cannot request irq %d err %d\n",
  2083. udc_controller->irq, ret);
  2084. goto err_iounmap;
  2085. }
  2086. /* Initialize the udc structure including QH member and other member */
  2087. if (struct_udc_setup(udc_controller, pdev)) {
  2088. ERR("Can't initialize udc data structure\n");
  2089. ret = -ENOMEM;
  2090. goto err_free_irq;
  2091. }
  2092. if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
  2093. /* initialize usb hw reg except for regs for EP,
  2094. * leave usbintr reg untouched */
  2095. dr_controller_setup(udc_controller);
  2096. }
  2097. ret = fsl_udc_clk_finalize(pdev);
  2098. if (ret)
  2099. goto err_free_irq;
  2100. /* Setup gadget structure */
  2101. udc_controller->gadget.ops = &fsl_gadget_ops;
  2102. udc_controller->gadget.max_speed = USB_SPEED_HIGH;
  2103. udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
  2104. INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
  2105. udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
  2106. udc_controller->gadget.name = driver_name;
  2107. /* Setup gadget.dev and register with kernel */
  2108. dev_set_name(&udc_controller->gadget.dev, "gadget");
  2109. udc_controller->gadget.dev.of_node = pdev->dev.of_node;
  2110. if (!IS_ERR_OR_NULL(udc_controller->transceiver))
  2111. udc_controller->gadget.is_otg = 1;
  2112. /* setup QH and epctrl for ep0 */
  2113. ep0_setup(udc_controller);
  2114. /* setup udc->eps[] for ep0 */
  2115. struct_ep_setup(udc_controller, 0, "ep0", 0);
  2116. /* for ep0: the desc defined here;
  2117. * for other eps, gadget layer called ep_enable with defined desc
  2118. */
  2119. udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
  2120. udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
  2121. /* setup the udc->eps[] for non-control endpoints and link
  2122. * to gadget.ep_list */
  2123. for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
  2124. char name[14];
  2125. sprintf(name, "ep%dout", i);
  2126. struct_ep_setup(udc_controller, i * 2, name, 1);
  2127. sprintf(name, "ep%din", i);
  2128. struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
  2129. }
  2130. /* use dma_pool for TD management */
  2131. udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
  2132. sizeof(struct ep_td_struct),
  2133. DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
  2134. if (udc_controller->td_pool == NULL) {
  2135. ret = -ENOMEM;
  2136. goto err_free_irq;
  2137. }
  2138. ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
  2139. fsl_udc_release);
  2140. if (ret)
  2141. goto err_del_udc;
  2142. create_proc_file();
  2143. return 0;
  2144. err_del_udc:
  2145. dma_pool_destroy(udc_controller->td_pool);
  2146. err_free_irq:
  2147. free_irq(udc_controller->irq, udc_controller);
  2148. err_iounmap:
  2149. if (pdata->exit)
  2150. pdata->exit(pdev);
  2151. fsl_udc_clk_release();
  2152. err_iounmap_noclk:
  2153. iounmap(dr_regs);
  2154. err_release_mem_region:
  2155. if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
  2156. release_mem_region(res->start, resource_size(res));
  2157. err_kfree:
  2158. kfree(udc_controller);
  2159. udc_controller = NULL;
  2160. return ret;
  2161. }
  2162. /* Driver removal function
  2163. * Free resources and finish pending transactions
  2164. */
  2165. static int __exit fsl_udc_remove(struct platform_device *pdev)
  2166. {
  2167. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2168. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  2169. DECLARE_COMPLETION(done);
  2170. if (!udc_controller)
  2171. return -ENODEV;
  2172. usb_del_gadget_udc(&udc_controller->gadget);
  2173. udc_controller->done = &done;
  2174. fsl_udc_clk_release();
  2175. /* DR has been stopped in usb_gadget_unregister_driver() */
  2176. remove_proc_file();
  2177. /* Free allocated memory */
  2178. kfree(udc_controller->status_req->req.buf);
  2179. kfree(udc_controller->status_req);
  2180. kfree(udc_controller->eps);
  2181. dma_pool_destroy(udc_controller->td_pool);
  2182. free_irq(udc_controller->irq, udc_controller);
  2183. iounmap(dr_regs);
  2184. if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
  2185. release_mem_region(res->start, resource_size(res));
  2186. /* free udc --wait for the release() finished */
  2187. wait_for_completion(&done);
  2188. /*
  2189. * do platform specific un-initialization:
  2190. * release iomux pins, etc.
  2191. */
  2192. if (pdata->exit)
  2193. pdata->exit(pdev);
  2194. return 0;
  2195. }
  2196. /*-----------------------------------------------------------------
  2197. * Modify Power management attributes
  2198. * Used by OTG statemachine to disable gadget temporarily
  2199. -----------------------------------------------------------------*/
  2200. static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
  2201. {
  2202. dr_controller_stop(udc_controller);
  2203. return 0;
  2204. }
  2205. /*-----------------------------------------------------------------
  2206. * Invoked on USB resume. May be called in_interrupt.
  2207. * Here we start the DR controller and enable the irq
  2208. *-----------------------------------------------------------------*/
  2209. static int fsl_udc_resume(struct platform_device *pdev)
  2210. {
  2211. /* Enable DR irq reg and set controller Run */
  2212. if (udc_controller->stopped) {
  2213. dr_controller_setup(udc_controller);
  2214. dr_controller_run(udc_controller);
  2215. }
  2216. udc_controller->usb_state = USB_STATE_ATTACHED;
  2217. udc_controller->ep0_state = WAIT_FOR_SETUP;
  2218. udc_controller->ep0_dir = 0;
  2219. return 0;
  2220. }
  2221. static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
  2222. {
  2223. struct fsl_udc *udc = udc_controller;
  2224. u32 mode, usbcmd;
  2225. mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
  2226. pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
  2227. /*
  2228. * If the controller is already stopped, then this must be a
  2229. * PM suspend. Remember this fact, so that we will leave the
  2230. * controller stopped at PM resume time.
  2231. */
  2232. if (udc->stopped) {
  2233. pr_debug("gadget already stopped, leaving early\n");
  2234. udc->already_stopped = 1;
  2235. return 0;
  2236. }
  2237. if (mode != USB_MODE_CTRL_MODE_DEVICE) {
  2238. pr_debug("gadget not in device mode, leaving early\n");
  2239. return 0;
  2240. }
  2241. /* stop the controller */
  2242. usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
  2243. fsl_writel(usbcmd, &dr_regs->usbcmd);
  2244. udc->stopped = 1;
  2245. pr_info("USB Gadget suspended\n");
  2246. return 0;
  2247. }
  2248. static int fsl_udc_otg_resume(struct device *dev)
  2249. {
  2250. pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
  2251. udc_controller->stopped, udc_controller->already_stopped);
  2252. /*
  2253. * If the controller was stopped at suspend time, then
  2254. * don't resume it now.
  2255. */
  2256. if (udc_controller->already_stopped) {
  2257. udc_controller->already_stopped = 0;
  2258. pr_debug("gadget was already stopped, leaving early\n");
  2259. return 0;
  2260. }
  2261. pr_info("USB Gadget resume\n");
  2262. return fsl_udc_resume(NULL);
  2263. }
  2264. /*-------------------------------------------------------------------------
  2265. Register entry point for the peripheral controller driver
  2266. --------------------------------------------------------------------------*/
  2267. static const struct platform_device_id fsl_udc_devtype[] = {
  2268. {
  2269. .name = "imx-udc-mx27",
  2270. }, {
  2271. .name = "imx-udc-mx51",
  2272. }, {
  2273. /* sentinel */
  2274. }
  2275. };
  2276. MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
  2277. static struct platform_driver udc_driver = {
  2278. .remove = __exit_p(fsl_udc_remove),
  2279. /* Just for FSL i.mx SoC currently */
  2280. .id_table = fsl_udc_devtype,
  2281. /* these suspend and resume are not usb suspend and resume */
  2282. .suspend = fsl_udc_suspend,
  2283. .resume = fsl_udc_resume,
  2284. .driver = {
  2285. .name = (char *)driver_name,
  2286. .owner = THIS_MODULE,
  2287. /* udc suspend/resume called from OTG driver */
  2288. .suspend = fsl_udc_otg_suspend,
  2289. .resume = fsl_udc_otg_resume,
  2290. },
  2291. };
  2292. module_platform_driver_probe(udc_driver, fsl_udc_probe);
  2293. MODULE_DESCRIPTION(DRIVER_DESC);
  2294. MODULE_AUTHOR(DRIVER_AUTHOR);
  2295. MODULE_LICENSE("GPL");
  2296. MODULE_ALIAS("platform:fsl-usb2-udc");