soc-cache.c 34 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475
  1. /*
  2. * soc-cache.c -- ASoC register cache helpers
  3. *
  4. * Copyright 2009 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/i2c.h>
  14. #include <linux/spi/spi.h>
  15. #include <sound/soc.h>
  16. #include <linux/lzo.h>
  17. #include <linux/bitmap.h>
  18. #include <linux/rbtree.h>
  19. #include <trace/events/asoc.h>
  20. #if defined(CONFIG_SPI_MASTER)
  21. static int do_spi_write(void *control_data, const void *msg,
  22. int len)
  23. {
  24. struct spi_device *spi = control_data;
  25. struct spi_transfer t;
  26. struct spi_message m;
  27. if (len <= 0)
  28. return 0;
  29. spi_message_init(&m);
  30. memset(&t, 0, sizeof t);
  31. t.tx_buf = msg;
  32. t.len = len;
  33. spi_message_add_tail(&t, &m);
  34. spi_sync(spi, &m);
  35. return len;
  36. }
  37. #endif
  38. static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
  39. unsigned int value, const void *data, int len)
  40. {
  41. int ret;
  42. if (!snd_soc_codec_volatile_register(codec, reg) &&
  43. reg < codec->driver->reg_cache_size &&
  44. !codec->cache_bypass) {
  45. ret = snd_soc_cache_write(codec, reg, value);
  46. if (ret < 0)
  47. return -1;
  48. }
  49. if (codec->cache_only) {
  50. codec->cache_sync = 1;
  51. return 0;
  52. }
  53. ret = codec->hw_write(codec->control_data, data, len);
  54. if (ret == len)
  55. return 0;
  56. if (ret < 0)
  57. return ret;
  58. else
  59. return -EIO;
  60. }
  61. static unsigned int do_hw_read(struct snd_soc_codec *codec, unsigned int reg)
  62. {
  63. int ret;
  64. unsigned int val;
  65. if (reg >= codec->driver->reg_cache_size ||
  66. snd_soc_codec_volatile_register(codec, reg) ||
  67. codec->cache_bypass) {
  68. if (codec->cache_only)
  69. return -1;
  70. BUG_ON(!codec->hw_read);
  71. return codec->hw_read(codec, reg);
  72. }
  73. ret = snd_soc_cache_read(codec, reg, &val);
  74. if (ret < 0)
  75. return -1;
  76. return val;
  77. }
  78. static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
  79. unsigned int reg)
  80. {
  81. return do_hw_read(codec, reg);
  82. }
  83. static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
  84. unsigned int value)
  85. {
  86. u8 data[2];
  87. data[0] = (reg << 4) | ((value >> 8) & 0x000f);
  88. data[1] = value & 0x00ff;
  89. return do_hw_write(codec, reg, value, data, 2);
  90. }
  91. #if defined(CONFIG_SPI_MASTER)
  92. static int snd_soc_4_12_spi_write(void *control_data, const char *data,
  93. int len)
  94. {
  95. u8 msg[2];
  96. msg[0] = data[1];
  97. msg[1] = data[0];
  98. return do_spi_write(control_data, msg, len);
  99. }
  100. #else
  101. #define snd_soc_4_12_spi_write NULL
  102. #endif
  103. static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
  104. unsigned int reg)
  105. {
  106. return do_hw_read(codec, reg);
  107. }
  108. static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
  109. unsigned int value)
  110. {
  111. u8 data[2];
  112. data[0] = (reg << 1) | ((value >> 8) & 0x0001);
  113. data[1] = value & 0x00ff;
  114. return do_hw_write(codec, reg, value, data, 2);
  115. }
  116. #if defined(CONFIG_SPI_MASTER)
  117. static int snd_soc_7_9_spi_write(void *control_data, const char *data,
  118. int len)
  119. {
  120. u8 msg[2];
  121. msg[0] = data[0];
  122. msg[1] = data[1];
  123. return do_spi_write(control_data, msg, len);
  124. }
  125. #else
  126. #define snd_soc_7_9_spi_write NULL
  127. #endif
  128. static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
  129. unsigned int value)
  130. {
  131. u8 data[2];
  132. reg &= 0xff;
  133. data[0] = reg;
  134. data[1] = value & 0xff;
  135. return do_hw_write(codec, reg, value, data, 2);
  136. }
  137. static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
  138. unsigned int reg)
  139. {
  140. return do_hw_read(codec, reg);
  141. }
  142. #if defined(CONFIG_SPI_MASTER)
  143. static int snd_soc_8_8_spi_write(void *control_data, const char *data,
  144. int len)
  145. {
  146. u8 msg[2];
  147. msg[0] = data[0];
  148. msg[1] = data[1];
  149. return do_spi_write(control_data, msg, len);
  150. }
  151. #else
  152. #define snd_soc_8_8_spi_write NULL
  153. #endif
  154. static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
  155. unsigned int value)
  156. {
  157. u8 data[3];
  158. data[0] = reg;
  159. data[1] = (value >> 8) & 0xff;
  160. data[2] = value & 0xff;
  161. return do_hw_write(codec, reg, value, data, 3);
  162. }
  163. static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
  164. unsigned int reg)
  165. {
  166. return do_hw_read(codec, reg);
  167. }
  168. #if defined(CONFIG_SPI_MASTER)
  169. static int snd_soc_8_16_spi_write(void *control_data, const char *data,
  170. int len)
  171. {
  172. u8 msg[3];
  173. msg[0] = data[0];
  174. msg[1] = data[1];
  175. msg[2] = data[2];
  176. return do_spi_write(control_data, msg, len);
  177. }
  178. #else
  179. #define snd_soc_8_16_spi_write NULL
  180. #endif
  181. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  182. static unsigned int do_i2c_read(struct snd_soc_codec *codec,
  183. void *reg, int reglen,
  184. void *data, int datalen)
  185. {
  186. struct i2c_msg xfer[2];
  187. int ret;
  188. struct i2c_client *client = codec->control_data;
  189. /* Write register */
  190. xfer[0].addr = client->addr;
  191. xfer[0].flags = 0;
  192. xfer[0].len = reglen;
  193. xfer[0].buf = reg;
  194. /* Read data */
  195. xfer[1].addr = client->addr;
  196. xfer[1].flags = I2C_M_RD;
  197. xfer[1].len = datalen;
  198. xfer[1].buf = data;
  199. ret = i2c_transfer(client->adapter, xfer, 2);
  200. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  201. if (ret == 2)
  202. return 0;
  203. else if (ret < 0)
  204. return ret;
  205. else
  206. return -EIO;
  207. }
  208. #endif
  209. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  210. static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
  211. unsigned int r)
  212. {
  213. u8 reg = r;
  214. u8 data;
  215. int ret;
  216. ret = do_i2c_read(codec, &reg, 1, &data, 1);
  217. if (ret < 0)
  218. return 0;
  219. return data;
  220. }
  221. #else
  222. #define snd_soc_8_8_read_i2c NULL
  223. #endif
  224. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  225. static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
  226. unsigned int r)
  227. {
  228. u8 reg = r;
  229. u16 data;
  230. int ret;
  231. ret = do_i2c_read(codec, &reg, 1, &data, 2);
  232. if (ret < 0)
  233. return 0;
  234. return (data >> 8) | ((data & 0xff) << 8);
  235. }
  236. #else
  237. #define snd_soc_8_16_read_i2c NULL
  238. #endif
  239. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  240. static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
  241. unsigned int r)
  242. {
  243. u16 reg = r;
  244. u8 data;
  245. int ret;
  246. ret = do_i2c_read(codec, &reg, 2, &data, 1);
  247. if (ret < 0)
  248. return 0;
  249. return data;
  250. }
  251. #else
  252. #define snd_soc_16_8_read_i2c NULL
  253. #endif
  254. static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
  255. unsigned int reg)
  256. {
  257. return do_hw_read(codec, reg);
  258. }
  259. static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
  260. unsigned int value)
  261. {
  262. u8 data[3];
  263. data[0] = (reg >> 8) & 0xff;
  264. data[1] = reg & 0xff;
  265. data[2] = value;
  266. reg &= 0xff;
  267. return do_hw_write(codec, reg, value, data, 3);
  268. }
  269. #if defined(CONFIG_SPI_MASTER)
  270. static int snd_soc_16_8_spi_write(void *control_data, const char *data,
  271. int len)
  272. {
  273. u8 msg[3];
  274. msg[0] = data[0];
  275. msg[1] = data[1];
  276. msg[2] = data[2];
  277. return do_spi_write(control_data, msg, len);
  278. }
  279. #else
  280. #define snd_soc_16_8_spi_write NULL
  281. #endif
  282. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  283. static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
  284. unsigned int r)
  285. {
  286. u16 reg = cpu_to_be16(r);
  287. u16 data;
  288. int ret;
  289. ret = do_i2c_read(codec, &reg, 2, &data, 2);
  290. if (ret < 0)
  291. return 0;
  292. return be16_to_cpu(data);
  293. }
  294. #else
  295. #define snd_soc_16_16_read_i2c NULL
  296. #endif
  297. static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
  298. unsigned int reg)
  299. {
  300. return do_hw_read(codec, reg);
  301. }
  302. static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
  303. unsigned int value)
  304. {
  305. u8 data[4];
  306. data[0] = (reg >> 8) & 0xff;
  307. data[1] = reg & 0xff;
  308. data[2] = (value >> 8) & 0xff;
  309. data[3] = value & 0xff;
  310. return do_hw_write(codec, reg, value, data, 4);
  311. }
  312. #if defined(CONFIG_SPI_MASTER)
  313. static int snd_soc_16_16_spi_write(void *control_data, const char *data,
  314. int len)
  315. {
  316. u8 msg[4];
  317. msg[0] = data[0];
  318. msg[1] = data[1];
  319. msg[2] = data[2];
  320. msg[3] = data[3];
  321. return do_spi_write(control_data, msg, len);
  322. }
  323. #else
  324. #define snd_soc_16_16_spi_write NULL
  325. #endif
  326. /* Primitive bulk write support for soc-cache. The data pointed to by `data' needs
  327. * to already be in the form the hardware expects including any leading register specific
  328. * data. Any data written through this function will not go through the cache as it
  329. * only handles writing to volatile or out of bounds registers.
  330. */
  331. static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
  332. const void *data, size_t len)
  333. {
  334. int ret;
  335. /* Ensure that the base register is volatile. Subsequently
  336. * any other register that is touched by this routine should be
  337. * volatile as well to ensure that we don't get out of sync with
  338. * the cache.
  339. */
  340. if (!snd_soc_codec_volatile_register(codec, reg)
  341. && reg < codec->driver->reg_cache_size)
  342. return -EINVAL;
  343. switch (codec->control_type) {
  344. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  345. case SND_SOC_I2C:
  346. ret = i2c_master_send(codec->control_data, data, len);
  347. break;
  348. #endif
  349. #if defined(CONFIG_SPI_MASTER)
  350. case SND_SOC_SPI:
  351. ret = do_spi_write(codec->control_data, data, len);
  352. break;
  353. #endif
  354. default:
  355. BUG();
  356. }
  357. if (ret == len)
  358. return 0;
  359. if (ret < 0)
  360. return ret;
  361. else
  362. return -EIO;
  363. }
  364. static struct {
  365. int addr_bits;
  366. int data_bits;
  367. int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
  368. int (*spi_write)(void *, const char *, int);
  369. unsigned int (*read)(struct snd_soc_codec *, unsigned int);
  370. unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
  371. } io_types[] = {
  372. {
  373. .addr_bits = 4, .data_bits = 12,
  374. .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
  375. .spi_write = snd_soc_4_12_spi_write,
  376. },
  377. {
  378. .addr_bits = 7, .data_bits = 9,
  379. .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
  380. .spi_write = snd_soc_7_9_spi_write,
  381. },
  382. {
  383. .addr_bits = 8, .data_bits = 8,
  384. .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
  385. .i2c_read = snd_soc_8_8_read_i2c,
  386. .spi_write = snd_soc_8_8_spi_write,
  387. },
  388. {
  389. .addr_bits = 8, .data_bits = 16,
  390. .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
  391. .i2c_read = snd_soc_8_16_read_i2c,
  392. .spi_write = snd_soc_8_16_spi_write,
  393. },
  394. {
  395. .addr_bits = 16, .data_bits = 8,
  396. .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
  397. .i2c_read = snd_soc_16_8_read_i2c,
  398. .spi_write = snd_soc_16_8_spi_write,
  399. },
  400. {
  401. .addr_bits = 16, .data_bits = 16,
  402. .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
  403. .i2c_read = snd_soc_16_16_read_i2c,
  404. .spi_write = snd_soc_16_16_spi_write,
  405. },
  406. };
  407. /**
  408. * snd_soc_codec_set_cache_io: Set up standard I/O functions.
  409. *
  410. * @codec: CODEC to configure.
  411. * @type: Type of cache.
  412. * @addr_bits: Number of bits of register address data.
  413. * @data_bits: Number of bits of data per register.
  414. * @control: Control bus used.
  415. *
  416. * Register formats are frequently shared between many I2C and SPI
  417. * devices. In order to promote code reuse the ASoC core provides
  418. * some standard implementations of CODEC read and write operations
  419. * which can be set up using this function.
  420. *
  421. * The caller is responsible for allocating and initialising the
  422. * actual cache.
  423. *
  424. * Note that at present this code cannot be used by CODECs with
  425. * volatile registers.
  426. */
  427. int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
  428. int addr_bits, int data_bits,
  429. enum snd_soc_control_type control)
  430. {
  431. int i;
  432. for (i = 0; i < ARRAY_SIZE(io_types); i++)
  433. if (io_types[i].addr_bits == addr_bits &&
  434. io_types[i].data_bits == data_bits)
  435. break;
  436. if (i == ARRAY_SIZE(io_types)) {
  437. printk(KERN_ERR
  438. "No I/O functions for %d bit address %d bit data\n",
  439. addr_bits, data_bits);
  440. return -EINVAL;
  441. }
  442. codec->write = io_types[i].write;
  443. codec->read = io_types[i].read;
  444. codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
  445. switch (control) {
  446. case SND_SOC_CUSTOM:
  447. break;
  448. case SND_SOC_I2C:
  449. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  450. codec->hw_write = (hw_write_t)i2c_master_send;
  451. #endif
  452. if (io_types[i].i2c_read)
  453. codec->hw_read = io_types[i].i2c_read;
  454. codec->control_data = container_of(codec->dev,
  455. struct i2c_client,
  456. dev);
  457. break;
  458. case SND_SOC_SPI:
  459. if (io_types[i].spi_write)
  460. codec->hw_write = io_types[i].spi_write;
  461. codec->control_data = container_of(codec->dev,
  462. struct spi_device,
  463. dev);
  464. break;
  465. }
  466. return 0;
  467. }
  468. EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
  469. static bool snd_soc_set_cache_val(void *base, unsigned int idx,
  470. unsigned int val, unsigned int word_size)
  471. {
  472. switch (word_size) {
  473. case 1: {
  474. u8 *cache = base;
  475. if (cache[idx] == val)
  476. return true;
  477. cache[idx] = val;
  478. break;
  479. }
  480. case 2: {
  481. u16 *cache = base;
  482. if (cache[idx] == val)
  483. return true;
  484. cache[idx] = val;
  485. break;
  486. }
  487. default:
  488. BUG();
  489. }
  490. return false;
  491. }
  492. static unsigned int snd_soc_get_cache_val(const void *base, unsigned int idx,
  493. unsigned int word_size)
  494. {
  495. switch (word_size) {
  496. case 1: {
  497. const u8 *cache = base;
  498. return cache[idx];
  499. }
  500. case 2: {
  501. const u16 *cache = base;
  502. return cache[idx];
  503. }
  504. default:
  505. BUG();
  506. }
  507. /* unreachable */
  508. return -1;
  509. }
  510. struct snd_soc_rbtree_node {
  511. struct rb_node node;
  512. unsigned int reg;
  513. unsigned int value;
  514. unsigned int defval;
  515. } __attribute__ ((packed));
  516. struct snd_soc_rbtree_ctx {
  517. struct rb_root root;
  518. };
  519. static struct snd_soc_rbtree_node *snd_soc_rbtree_lookup(
  520. struct rb_root *root, unsigned int reg)
  521. {
  522. struct rb_node *node;
  523. struct snd_soc_rbtree_node *rbnode;
  524. node = root->rb_node;
  525. while (node) {
  526. rbnode = container_of(node, struct snd_soc_rbtree_node, node);
  527. if (rbnode->reg < reg)
  528. node = node->rb_left;
  529. else if (rbnode->reg > reg)
  530. node = node->rb_right;
  531. else
  532. return rbnode;
  533. }
  534. return NULL;
  535. }
  536. static int snd_soc_rbtree_insert(struct rb_root *root,
  537. struct snd_soc_rbtree_node *rbnode)
  538. {
  539. struct rb_node **new, *parent;
  540. struct snd_soc_rbtree_node *rbnode_tmp;
  541. parent = NULL;
  542. new = &root->rb_node;
  543. while (*new) {
  544. rbnode_tmp = container_of(*new, struct snd_soc_rbtree_node,
  545. node);
  546. parent = *new;
  547. if (rbnode_tmp->reg < rbnode->reg)
  548. new = &((*new)->rb_left);
  549. else if (rbnode_tmp->reg > rbnode->reg)
  550. new = &((*new)->rb_right);
  551. else
  552. return 0;
  553. }
  554. /* insert the node into the rbtree */
  555. rb_link_node(&rbnode->node, parent, new);
  556. rb_insert_color(&rbnode->node, root);
  557. return 1;
  558. }
  559. static int snd_soc_rbtree_cache_sync(struct snd_soc_codec *codec)
  560. {
  561. struct snd_soc_rbtree_ctx *rbtree_ctx;
  562. struct rb_node *node;
  563. struct snd_soc_rbtree_node *rbnode;
  564. unsigned int val;
  565. int ret;
  566. rbtree_ctx = codec->reg_cache;
  567. for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
  568. rbnode = rb_entry(node, struct snd_soc_rbtree_node, node);
  569. if (rbnode->value == rbnode->defval)
  570. continue;
  571. WARN_ON(codec->writable_register &&
  572. codec->writable_register(codec, rbnode->reg));
  573. ret = snd_soc_cache_read(codec, rbnode->reg, &val);
  574. if (ret)
  575. return ret;
  576. codec->cache_bypass = 1;
  577. ret = snd_soc_write(codec, rbnode->reg, val);
  578. codec->cache_bypass = 0;
  579. if (ret)
  580. return ret;
  581. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  582. rbnode->reg, val);
  583. }
  584. return 0;
  585. }
  586. static int snd_soc_rbtree_cache_write(struct snd_soc_codec *codec,
  587. unsigned int reg, unsigned int value)
  588. {
  589. struct snd_soc_rbtree_ctx *rbtree_ctx;
  590. struct snd_soc_rbtree_node *rbnode;
  591. rbtree_ctx = codec->reg_cache;
  592. rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
  593. if (rbnode) {
  594. if (rbnode->value == value)
  595. return 0;
  596. rbnode->value = value;
  597. } else {
  598. /* bail out early, no need to create the rbnode yet */
  599. if (!value)
  600. return 0;
  601. /*
  602. * for uninitialized registers whose value is changed
  603. * from the default zero, create an rbnode and insert
  604. * it into the tree.
  605. */
  606. rbnode = kzalloc(sizeof *rbnode, GFP_KERNEL);
  607. if (!rbnode)
  608. return -ENOMEM;
  609. rbnode->reg = reg;
  610. rbnode->value = value;
  611. snd_soc_rbtree_insert(&rbtree_ctx->root, rbnode);
  612. }
  613. return 0;
  614. }
  615. static int snd_soc_rbtree_cache_read(struct snd_soc_codec *codec,
  616. unsigned int reg, unsigned int *value)
  617. {
  618. struct snd_soc_rbtree_ctx *rbtree_ctx;
  619. struct snd_soc_rbtree_node *rbnode;
  620. rbtree_ctx = codec->reg_cache;
  621. rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
  622. if (rbnode) {
  623. *value = rbnode->value;
  624. } else {
  625. /* uninitialized registers default to 0 */
  626. *value = 0;
  627. }
  628. return 0;
  629. }
  630. static int snd_soc_rbtree_cache_exit(struct snd_soc_codec *codec)
  631. {
  632. struct rb_node *next;
  633. struct snd_soc_rbtree_ctx *rbtree_ctx;
  634. struct snd_soc_rbtree_node *rbtree_node;
  635. /* if we've already been called then just return */
  636. rbtree_ctx = codec->reg_cache;
  637. if (!rbtree_ctx)
  638. return 0;
  639. /* free up the rbtree */
  640. next = rb_first(&rbtree_ctx->root);
  641. while (next) {
  642. rbtree_node = rb_entry(next, struct snd_soc_rbtree_node, node);
  643. next = rb_next(&rbtree_node->node);
  644. rb_erase(&rbtree_node->node, &rbtree_ctx->root);
  645. kfree(rbtree_node);
  646. }
  647. /* release the resources */
  648. kfree(codec->reg_cache);
  649. codec->reg_cache = NULL;
  650. return 0;
  651. }
  652. static int snd_soc_rbtree_cache_init(struct snd_soc_codec *codec)
  653. {
  654. struct snd_soc_rbtree_node *rbtree_node;
  655. struct snd_soc_rbtree_ctx *rbtree_ctx;
  656. unsigned int val;
  657. unsigned int word_size;
  658. int i;
  659. int ret;
  660. codec->reg_cache = kmalloc(sizeof *rbtree_ctx, GFP_KERNEL);
  661. if (!codec->reg_cache)
  662. return -ENOMEM;
  663. rbtree_ctx = codec->reg_cache;
  664. rbtree_ctx->root = RB_ROOT;
  665. if (!codec->reg_def_copy)
  666. return 0;
  667. /*
  668. * populate the rbtree with the initialized registers. All other
  669. * registers will be inserted when they are first modified.
  670. */
  671. word_size = codec->driver->reg_word_size;
  672. for (i = 0; i < codec->driver->reg_cache_size; ++i) {
  673. val = snd_soc_get_cache_val(codec->reg_def_copy, i, word_size);
  674. if (!val)
  675. continue;
  676. rbtree_node = kzalloc(sizeof *rbtree_node, GFP_KERNEL);
  677. if (!rbtree_node) {
  678. ret = -ENOMEM;
  679. snd_soc_cache_exit(codec);
  680. break;
  681. }
  682. rbtree_node->reg = i;
  683. rbtree_node->value = val;
  684. rbtree_node->defval = val;
  685. snd_soc_rbtree_insert(&rbtree_ctx->root, rbtree_node);
  686. }
  687. return 0;
  688. }
  689. #ifdef CONFIG_SND_SOC_CACHE_LZO
  690. struct snd_soc_lzo_ctx {
  691. void *wmem;
  692. void *dst;
  693. const void *src;
  694. size_t src_len;
  695. size_t dst_len;
  696. size_t decompressed_size;
  697. unsigned long *sync_bmp;
  698. int sync_bmp_nbits;
  699. };
  700. #define LZO_BLOCK_NUM 8
  701. static int snd_soc_lzo_block_count(void)
  702. {
  703. return LZO_BLOCK_NUM;
  704. }
  705. static int snd_soc_lzo_prepare(struct snd_soc_lzo_ctx *lzo_ctx)
  706. {
  707. lzo_ctx->wmem = kmalloc(LZO1X_MEM_COMPRESS, GFP_KERNEL);
  708. if (!lzo_ctx->wmem)
  709. return -ENOMEM;
  710. return 0;
  711. }
  712. static int snd_soc_lzo_compress(struct snd_soc_lzo_ctx *lzo_ctx)
  713. {
  714. size_t compress_size;
  715. int ret;
  716. ret = lzo1x_1_compress(lzo_ctx->src, lzo_ctx->src_len,
  717. lzo_ctx->dst, &compress_size, lzo_ctx->wmem);
  718. if (ret != LZO_E_OK || compress_size > lzo_ctx->dst_len)
  719. return -EINVAL;
  720. lzo_ctx->dst_len = compress_size;
  721. return 0;
  722. }
  723. static int snd_soc_lzo_decompress(struct snd_soc_lzo_ctx *lzo_ctx)
  724. {
  725. size_t dst_len;
  726. int ret;
  727. dst_len = lzo_ctx->dst_len;
  728. ret = lzo1x_decompress_safe(lzo_ctx->src, lzo_ctx->src_len,
  729. lzo_ctx->dst, &dst_len);
  730. if (ret != LZO_E_OK || dst_len != lzo_ctx->dst_len)
  731. return -EINVAL;
  732. return 0;
  733. }
  734. static int snd_soc_lzo_compress_cache_block(struct snd_soc_codec *codec,
  735. struct snd_soc_lzo_ctx *lzo_ctx)
  736. {
  737. int ret;
  738. lzo_ctx->dst_len = lzo1x_worst_compress(PAGE_SIZE);
  739. lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
  740. if (!lzo_ctx->dst) {
  741. lzo_ctx->dst_len = 0;
  742. return -ENOMEM;
  743. }
  744. ret = snd_soc_lzo_compress(lzo_ctx);
  745. if (ret < 0)
  746. return ret;
  747. return 0;
  748. }
  749. static int snd_soc_lzo_decompress_cache_block(struct snd_soc_codec *codec,
  750. struct snd_soc_lzo_ctx *lzo_ctx)
  751. {
  752. int ret;
  753. lzo_ctx->dst_len = lzo_ctx->decompressed_size;
  754. lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
  755. if (!lzo_ctx->dst) {
  756. lzo_ctx->dst_len = 0;
  757. return -ENOMEM;
  758. }
  759. ret = snd_soc_lzo_decompress(lzo_ctx);
  760. if (ret < 0)
  761. return ret;
  762. return 0;
  763. }
  764. static inline int snd_soc_lzo_get_blkindex(struct snd_soc_codec *codec,
  765. unsigned int reg)
  766. {
  767. const struct snd_soc_codec_driver *codec_drv;
  768. codec_drv = codec->driver;
  769. return (reg * codec_drv->reg_word_size) /
  770. DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count());
  771. }
  772. static inline int snd_soc_lzo_get_blkpos(struct snd_soc_codec *codec,
  773. unsigned int reg)
  774. {
  775. const struct snd_soc_codec_driver *codec_drv;
  776. codec_drv = codec->driver;
  777. return reg % (DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count()) /
  778. codec_drv->reg_word_size);
  779. }
  780. static inline int snd_soc_lzo_get_blksize(struct snd_soc_codec *codec)
  781. {
  782. const struct snd_soc_codec_driver *codec_drv;
  783. codec_drv = codec->driver;
  784. return DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count());
  785. }
  786. static int snd_soc_lzo_cache_sync(struct snd_soc_codec *codec)
  787. {
  788. struct snd_soc_lzo_ctx **lzo_blocks;
  789. unsigned int val;
  790. int i;
  791. int ret;
  792. lzo_blocks = codec->reg_cache;
  793. for_each_set_bit(i, lzo_blocks[0]->sync_bmp, lzo_blocks[0]->sync_bmp_nbits) {
  794. WARN_ON(codec->writable_register &&
  795. codec->writable_register(codec, i));
  796. ret = snd_soc_cache_read(codec, i, &val);
  797. if (ret)
  798. return ret;
  799. codec->cache_bypass = 1;
  800. ret = snd_soc_write(codec, i, val);
  801. codec->cache_bypass = 0;
  802. if (ret)
  803. return ret;
  804. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  805. i, val);
  806. }
  807. return 0;
  808. }
  809. static int snd_soc_lzo_cache_write(struct snd_soc_codec *codec,
  810. unsigned int reg, unsigned int value)
  811. {
  812. struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
  813. int ret, blkindex, blkpos;
  814. size_t blksize, tmp_dst_len;
  815. void *tmp_dst;
  816. /* index of the compressed lzo block */
  817. blkindex = snd_soc_lzo_get_blkindex(codec, reg);
  818. /* register index within the decompressed block */
  819. blkpos = snd_soc_lzo_get_blkpos(codec, reg);
  820. /* size of the compressed block */
  821. blksize = snd_soc_lzo_get_blksize(codec);
  822. lzo_blocks = codec->reg_cache;
  823. lzo_block = lzo_blocks[blkindex];
  824. /* save the pointer and length of the compressed block */
  825. tmp_dst = lzo_block->dst;
  826. tmp_dst_len = lzo_block->dst_len;
  827. /* prepare the source to be the compressed block */
  828. lzo_block->src = lzo_block->dst;
  829. lzo_block->src_len = lzo_block->dst_len;
  830. /* decompress the block */
  831. ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
  832. if (ret < 0) {
  833. kfree(lzo_block->dst);
  834. goto out;
  835. }
  836. /* write the new value to the cache */
  837. if (snd_soc_set_cache_val(lzo_block->dst, blkpos, value,
  838. codec->driver->reg_word_size)) {
  839. kfree(lzo_block->dst);
  840. goto out;
  841. }
  842. /* prepare the source to be the decompressed block */
  843. lzo_block->src = lzo_block->dst;
  844. lzo_block->src_len = lzo_block->dst_len;
  845. /* compress the block */
  846. ret = snd_soc_lzo_compress_cache_block(codec, lzo_block);
  847. if (ret < 0) {
  848. kfree(lzo_block->dst);
  849. kfree(lzo_block->src);
  850. goto out;
  851. }
  852. /* set the bit so we know we have to sync this register */
  853. set_bit(reg, lzo_block->sync_bmp);
  854. kfree(tmp_dst);
  855. kfree(lzo_block->src);
  856. return 0;
  857. out:
  858. lzo_block->dst = tmp_dst;
  859. lzo_block->dst_len = tmp_dst_len;
  860. return ret;
  861. }
  862. static int snd_soc_lzo_cache_read(struct snd_soc_codec *codec,
  863. unsigned int reg, unsigned int *value)
  864. {
  865. struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
  866. int ret, blkindex, blkpos;
  867. size_t blksize, tmp_dst_len;
  868. void *tmp_dst;
  869. *value = 0;
  870. /* index of the compressed lzo block */
  871. blkindex = snd_soc_lzo_get_blkindex(codec, reg);
  872. /* register index within the decompressed block */
  873. blkpos = snd_soc_lzo_get_blkpos(codec, reg);
  874. /* size of the compressed block */
  875. blksize = snd_soc_lzo_get_blksize(codec);
  876. lzo_blocks = codec->reg_cache;
  877. lzo_block = lzo_blocks[blkindex];
  878. /* save the pointer and length of the compressed block */
  879. tmp_dst = lzo_block->dst;
  880. tmp_dst_len = lzo_block->dst_len;
  881. /* prepare the source to be the compressed block */
  882. lzo_block->src = lzo_block->dst;
  883. lzo_block->src_len = lzo_block->dst_len;
  884. /* decompress the block */
  885. ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
  886. if (ret >= 0)
  887. /* fetch the value from the cache */
  888. *value = snd_soc_get_cache_val(lzo_block->dst, blkpos,
  889. codec->driver->reg_word_size);
  890. kfree(lzo_block->dst);
  891. /* restore the pointer and length of the compressed block */
  892. lzo_block->dst = tmp_dst;
  893. lzo_block->dst_len = tmp_dst_len;
  894. return 0;
  895. }
  896. static int snd_soc_lzo_cache_exit(struct snd_soc_codec *codec)
  897. {
  898. struct snd_soc_lzo_ctx **lzo_blocks;
  899. int i, blkcount;
  900. lzo_blocks = codec->reg_cache;
  901. if (!lzo_blocks)
  902. return 0;
  903. blkcount = snd_soc_lzo_block_count();
  904. /*
  905. * the pointer to the bitmap used for syncing the cache
  906. * is shared amongst all lzo_blocks. Ensure it is freed
  907. * only once.
  908. */
  909. if (lzo_blocks[0])
  910. kfree(lzo_blocks[0]->sync_bmp);
  911. for (i = 0; i < blkcount; ++i) {
  912. if (lzo_blocks[i]) {
  913. kfree(lzo_blocks[i]->wmem);
  914. kfree(lzo_blocks[i]->dst);
  915. }
  916. /* each lzo_block is a pointer returned by kmalloc or NULL */
  917. kfree(lzo_blocks[i]);
  918. }
  919. kfree(lzo_blocks);
  920. codec->reg_cache = NULL;
  921. return 0;
  922. }
  923. static int snd_soc_lzo_cache_init(struct snd_soc_codec *codec)
  924. {
  925. struct snd_soc_lzo_ctx **lzo_blocks;
  926. size_t bmp_size;
  927. const struct snd_soc_codec_driver *codec_drv;
  928. int ret, tofree, i, blksize, blkcount;
  929. const char *p, *end;
  930. unsigned long *sync_bmp;
  931. ret = 0;
  932. codec_drv = codec->driver;
  933. /*
  934. * If we have not been given a default register cache
  935. * then allocate a dummy zero-ed out region, compress it
  936. * and remember to free it afterwards.
  937. */
  938. tofree = 0;
  939. if (!codec->reg_def_copy)
  940. tofree = 1;
  941. if (!codec->reg_def_copy) {
  942. codec->reg_def_copy = kzalloc(codec->reg_size, GFP_KERNEL);
  943. if (!codec->reg_def_copy)
  944. return -ENOMEM;
  945. }
  946. blkcount = snd_soc_lzo_block_count();
  947. codec->reg_cache = kzalloc(blkcount * sizeof *lzo_blocks,
  948. GFP_KERNEL);
  949. if (!codec->reg_cache) {
  950. ret = -ENOMEM;
  951. goto err_tofree;
  952. }
  953. lzo_blocks = codec->reg_cache;
  954. /*
  955. * allocate a bitmap to be used when syncing the cache with
  956. * the hardware. Each time a register is modified, the corresponding
  957. * bit is set in the bitmap, so we know that we have to sync
  958. * that register.
  959. */
  960. bmp_size = codec_drv->reg_cache_size;
  961. sync_bmp = kmalloc(BITS_TO_LONGS(bmp_size) * sizeof(long),
  962. GFP_KERNEL);
  963. if (!sync_bmp) {
  964. ret = -ENOMEM;
  965. goto err;
  966. }
  967. bitmap_zero(sync_bmp, bmp_size);
  968. /* allocate the lzo blocks and initialize them */
  969. for (i = 0; i < blkcount; ++i) {
  970. lzo_blocks[i] = kzalloc(sizeof **lzo_blocks,
  971. GFP_KERNEL);
  972. if (!lzo_blocks[i]) {
  973. kfree(sync_bmp);
  974. ret = -ENOMEM;
  975. goto err;
  976. }
  977. lzo_blocks[i]->sync_bmp = sync_bmp;
  978. lzo_blocks[i]->sync_bmp_nbits = bmp_size;
  979. /* alloc the working space for the compressed block */
  980. ret = snd_soc_lzo_prepare(lzo_blocks[i]);
  981. if (ret < 0)
  982. goto err;
  983. }
  984. blksize = snd_soc_lzo_get_blksize(codec);
  985. p = codec->reg_def_copy;
  986. end = codec->reg_def_copy + codec->reg_size;
  987. /* compress the register map and fill the lzo blocks */
  988. for (i = 0; i < blkcount; ++i, p += blksize) {
  989. lzo_blocks[i]->src = p;
  990. if (p + blksize > end)
  991. lzo_blocks[i]->src_len = end - p;
  992. else
  993. lzo_blocks[i]->src_len = blksize;
  994. ret = snd_soc_lzo_compress_cache_block(codec,
  995. lzo_blocks[i]);
  996. if (ret < 0)
  997. goto err;
  998. lzo_blocks[i]->decompressed_size =
  999. lzo_blocks[i]->src_len;
  1000. }
  1001. if (tofree) {
  1002. kfree(codec->reg_def_copy);
  1003. codec->reg_def_copy = NULL;
  1004. }
  1005. return 0;
  1006. err:
  1007. snd_soc_cache_exit(codec);
  1008. err_tofree:
  1009. if (tofree) {
  1010. kfree(codec->reg_def_copy);
  1011. codec->reg_def_copy = NULL;
  1012. }
  1013. return ret;
  1014. }
  1015. #endif
  1016. static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec)
  1017. {
  1018. int i;
  1019. int ret;
  1020. const struct snd_soc_codec_driver *codec_drv;
  1021. unsigned int val;
  1022. codec_drv = codec->driver;
  1023. for (i = 0; i < codec_drv->reg_cache_size; ++i) {
  1024. WARN_ON(codec->writable_register &&
  1025. codec->writable_register(codec, i));
  1026. ret = snd_soc_cache_read(codec, i, &val);
  1027. if (ret)
  1028. return ret;
  1029. if (codec->reg_def_copy)
  1030. if (snd_soc_get_cache_val(codec->reg_def_copy,
  1031. i, codec_drv->reg_word_size) == val)
  1032. continue;
  1033. ret = snd_soc_write(codec, i, val);
  1034. if (ret)
  1035. return ret;
  1036. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  1037. i, val);
  1038. }
  1039. return 0;
  1040. }
  1041. static int snd_soc_flat_cache_write(struct snd_soc_codec *codec,
  1042. unsigned int reg, unsigned int value)
  1043. {
  1044. snd_soc_set_cache_val(codec->reg_cache, reg, value,
  1045. codec->driver->reg_word_size);
  1046. return 0;
  1047. }
  1048. static int snd_soc_flat_cache_read(struct snd_soc_codec *codec,
  1049. unsigned int reg, unsigned int *value)
  1050. {
  1051. *value = snd_soc_get_cache_val(codec->reg_cache, reg,
  1052. codec->driver->reg_word_size);
  1053. return 0;
  1054. }
  1055. static int snd_soc_flat_cache_exit(struct snd_soc_codec *codec)
  1056. {
  1057. if (!codec->reg_cache)
  1058. return 0;
  1059. kfree(codec->reg_cache);
  1060. codec->reg_cache = NULL;
  1061. return 0;
  1062. }
  1063. static int snd_soc_flat_cache_init(struct snd_soc_codec *codec)
  1064. {
  1065. const struct snd_soc_codec_driver *codec_drv;
  1066. codec_drv = codec->driver;
  1067. if (codec->reg_def_copy)
  1068. codec->reg_cache = kmemdup(codec->reg_def_copy,
  1069. codec->reg_size, GFP_KERNEL);
  1070. else
  1071. codec->reg_cache = kzalloc(codec->reg_size, GFP_KERNEL);
  1072. if (!codec->reg_cache)
  1073. return -ENOMEM;
  1074. return 0;
  1075. }
  1076. /* an array of all supported compression types */
  1077. static const struct snd_soc_cache_ops cache_types[] = {
  1078. /* Flat *must* be the first entry for fallback */
  1079. {
  1080. .id = SND_SOC_FLAT_COMPRESSION,
  1081. .name = "flat",
  1082. .init = snd_soc_flat_cache_init,
  1083. .exit = snd_soc_flat_cache_exit,
  1084. .read = snd_soc_flat_cache_read,
  1085. .write = snd_soc_flat_cache_write,
  1086. .sync = snd_soc_flat_cache_sync
  1087. },
  1088. #ifdef CONFIG_SND_SOC_CACHE_LZO
  1089. {
  1090. .id = SND_SOC_LZO_COMPRESSION,
  1091. .name = "LZO",
  1092. .init = snd_soc_lzo_cache_init,
  1093. .exit = snd_soc_lzo_cache_exit,
  1094. .read = snd_soc_lzo_cache_read,
  1095. .write = snd_soc_lzo_cache_write,
  1096. .sync = snd_soc_lzo_cache_sync
  1097. },
  1098. #endif
  1099. {
  1100. .id = SND_SOC_RBTREE_COMPRESSION,
  1101. .name = "rbtree",
  1102. .init = snd_soc_rbtree_cache_init,
  1103. .exit = snd_soc_rbtree_cache_exit,
  1104. .read = snd_soc_rbtree_cache_read,
  1105. .write = snd_soc_rbtree_cache_write,
  1106. .sync = snd_soc_rbtree_cache_sync
  1107. }
  1108. };
  1109. int snd_soc_cache_init(struct snd_soc_codec *codec)
  1110. {
  1111. int i;
  1112. for (i = 0; i < ARRAY_SIZE(cache_types); ++i)
  1113. if (cache_types[i].id == codec->compress_type)
  1114. break;
  1115. /* Fall back to flat compression */
  1116. if (i == ARRAY_SIZE(cache_types)) {
  1117. dev_warn(codec->dev, "Could not match compress type: %d\n",
  1118. codec->compress_type);
  1119. i = 0;
  1120. }
  1121. mutex_init(&codec->cache_rw_mutex);
  1122. codec->cache_ops = &cache_types[i];
  1123. if (codec->cache_ops->init) {
  1124. if (codec->cache_ops->name)
  1125. dev_dbg(codec->dev, "Initializing %s cache for %s codec\n",
  1126. codec->cache_ops->name, codec->name);
  1127. return codec->cache_ops->init(codec);
  1128. }
  1129. return -ENOSYS;
  1130. }
  1131. /*
  1132. * NOTE: keep in mind that this function might be called
  1133. * multiple times.
  1134. */
  1135. int snd_soc_cache_exit(struct snd_soc_codec *codec)
  1136. {
  1137. if (codec->cache_ops && codec->cache_ops->exit) {
  1138. if (codec->cache_ops->name)
  1139. dev_dbg(codec->dev, "Destroying %s cache for %s codec\n",
  1140. codec->cache_ops->name, codec->name);
  1141. return codec->cache_ops->exit(codec);
  1142. }
  1143. return -ENOSYS;
  1144. }
  1145. /**
  1146. * snd_soc_cache_read: Fetch the value of a given register from the cache.
  1147. *
  1148. * @codec: CODEC to configure.
  1149. * @reg: The register index.
  1150. * @value: The value to be returned.
  1151. */
  1152. int snd_soc_cache_read(struct snd_soc_codec *codec,
  1153. unsigned int reg, unsigned int *value)
  1154. {
  1155. int ret;
  1156. mutex_lock(&codec->cache_rw_mutex);
  1157. if (value && codec->cache_ops && codec->cache_ops->read) {
  1158. ret = codec->cache_ops->read(codec, reg, value);
  1159. mutex_unlock(&codec->cache_rw_mutex);
  1160. return ret;
  1161. }
  1162. mutex_unlock(&codec->cache_rw_mutex);
  1163. return -ENOSYS;
  1164. }
  1165. EXPORT_SYMBOL_GPL(snd_soc_cache_read);
  1166. /**
  1167. * snd_soc_cache_write: Set the value of a given register in the cache.
  1168. *
  1169. * @codec: CODEC to configure.
  1170. * @reg: The register index.
  1171. * @value: The new register value.
  1172. */
  1173. int snd_soc_cache_write(struct snd_soc_codec *codec,
  1174. unsigned int reg, unsigned int value)
  1175. {
  1176. int ret;
  1177. mutex_lock(&codec->cache_rw_mutex);
  1178. if (codec->cache_ops && codec->cache_ops->write) {
  1179. ret = codec->cache_ops->write(codec, reg, value);
  1180. mutex_unlock(&codec->cache_rw_mutex);
  1181. return ret;
  1182. }
  1183. mutex_unlock(&codec->cache_rw_mutex);
  1184. return -ENOSYS;
  1185. }
  1186. EXPORT_SYMBOL_GPL(snd_soc_cache_write);
  1187. /**
  1188. * snd_soc_cache_sync: Sync the register cache with the hardware.
  1189. *
  1190. * @codec: CODEC to configure.
  1191. *
  1192. * Any registers that should not be synced should be marked as
  1193. * volatile. In general drivers can choose not to use the provided
  1194. * syncing functionality if they so require.
  1195. */
  1196. int snd_soc_cache_sync(struct snd_soc_codec *codec)
  1197. {
  1198. int ret;
  1199. const char *name;
  1200. if (!codec->cache_sync) {
  1201. return 0;
  1202. }
  1203. if (!codec->cache_ops || !codec->cache_ops->sync)
  1204. return -ENOSYS;
  1205. if (codec->cache_ops->name)
  1206. name = codec->cache_ops->name;
  1207. else
  1208. name = "unknown";
  1209. if (codec->cache_ops->name)
  1210. dev_dbg(codec->dev, "Syncing %s cache for %s codec\n",
  1211. codec->cache_ops->name, codec->name);
  1212. trace_snd_soc_cache_sync(codec, name, "start");
  1213. ret = codec->cache_ops->sync(codec);
  1214. if (!ret)
  1215. codec->cache_sync = 0;
  1216. trace_snd_soc_cache_sync(codec, name, "end");
  1217. return ret;
  1218. }
  1219. EXPORT_SYMBOL_GPL(snd_soc_cache_sync);
  1220. static int snd_soc_get_reg_access_index(struct snd_soc_codec *codec,
  1221. unsigned int reg)
  1222. {
  1223. const struct snd_soc_codec_driver *codec_drv;
  1224. unsigned int min, max, index;
  1225. codec_drv = codec->driver;
  1226. min = 0;
  1227. max = codec_drv->reg_access_size - 1;
  1228. do {
  1229. index = (min + max) / 2;
  1230. if (codec_drv->reg_access_default[index].reg == reg)
  1231. return index;
  1232. if (codec_drv->reg_access_default[index].reg < reg)
  1233. min = index + 1;
  1234. else
  1235. max = index;
  1236. } while (min <= max);
  1237. return -1;
  1238. }
  1239. int snd_soc_default_volatile_register(struct snd_soc_codec *codec,
  1240. unsigned int reg)
  1241. {
  1242. int index;
  1243. if (reg >= codec->driver->reg_cache_size)
  1244. return 1;
  1245. index = snd_soc_get_reg_access_index(codec, reg);
  1246. if (index < 0)
  1247. return 0;
  1248. return codec->driver->reg_access_default[index].vol;
  1249. }
  1250. EXPORT_SYMBOL_GPL(snd_soc_default_volatile_register);
  1251. int snd_soc_default_readable_register(struct snd_soc_codec *codec,
  1252. unsigned int reg)
  1253. {
  1254. int index;
  1255. if (reg >= codec->driver->reg_cache_size)
  1256. return 1;
  1257. index = snd_soc_get_reg_access_index(codec, reg);
  1258. if (index < 0)
  1259. return 0;
  1260. return codec->driver->reg_access_default[index].read;
  1261. }
  1262. EXPORT_SYMBOL_GPL(snd_soc_default_readable_register);
  1263. int snd_soc_default_writable_register(struct snd_soc_codec *codec,
  1264. unsigned int reg)
  1265. {
  1266. int index;
  1267. if (reg >= codec->driver->reg_cache_size)
  1268. return 1;
  1269. index = snd_soc_get_reg_access_index(codec, reg);
  1270. if (index < 0)
  1271. return 0;
  1272. return codec->driver->reg_access_default[index].write;
  1273. }
  1274. EXPORT_SYMBOL_GPL(snd_soc_default_writable_register);