km83xx.c 4.5 KB

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  1. /*
  2. * Copyright 2008-2011 DENX Software Engineering GmbH
  3. * Author: Heiko Schocher <hs@denx.de>
  4. *
  5. * Description:
  6. * Keymile 83xx platform specific routines.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/stddef.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/reboot.h>
  18. #include <linux/pci.h>
  19. #include <linux/kdev_t.h>
  20. #include <linux/major.h>
  21. #include <linux/console.h>
  22. #include <linux/delay.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/root_dev.h>
  25. #include <linux/initrd.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/of_device.h>
  28. #include <linux/atomic.h>
  29. #include <linux/time.h>
  30. #include <linux/io.h>
  31. #include <asm/machdep.h>
  32. #include <asm/ipic.h>
  33. #include <asm/irq.h>
  34. #include <asm/prom.h>
  35. #include <asm/udbg.h>
  36. #include <sysdev/fsl_soc.h>
  37. #include <sysdev/fsl_pci.h>
  38. #include <asm/qe.h>
  39. #include <asm/qe_ic.h>
  40. #include "mpc83xx.h"
  41. #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
  42. /* ************************************************************************
  43. *
  44. * Setup the architecture
  45. *
  46. */
  47. static void __init mpc83xx_km_setup_arch(void)
  48. {
  49. #ifdef CONFIG_QUICC_ENGINE
  50. struct device_node *np;
  51. #endif
  52. if (ppc_md.progress)
  53. ppc_md.progress("kmpbec83xx_setup_arch()", 0);
  54. mpc83xx_setup_pci();
  55. #ifdef CONFIG_QUICC_ENGINE
  56. qe_reset();
  57. np = of_find_node_by_name(NULL, "par_io");
  58. if (np != NULL) {
  59. par_io_init(np);
  60. of_node_put(np);
  61. for_each_node_by_name(np, "spi")
  62. par_io_of_config(np);
  63. for_each_node_by_name(np, "ucc")
  64. par_io_of_config(np);
  65. }
  66. np = of_find_compatible_node(NULL, "network", "ucc_geth");
  67. if (np != NULL) {
  68. /*
  69. * handle mpc8360E Erratum QE_ENET10:
  70. * RGMII AC values do not meet the specification
  71. */
  72. uint svid = mfspr(SPRN_SVR);
  73. struct device_node *np_par;
  74. struct resource res;
  75. void __iomem *base;
  76. int ret;
  77. np_par = of_find_node_by_name(NULL, "par_io");
  78. if (np_par == NULL) {
  79. pr_warn("%s couldn;t find par_io node\n", __func__);
  80. return;
  81. }
  82. /* Map Parallel I/O ports registers */
  83. ret = of_address_to_resource(np_par, 0, &res);
  84. if (ret) {
  85. pr_warn("%s couldn;t map par_io registers\n", __func__);
  86. return;
  87. }
  88. base = ioremap(res.start, res.end - res.start + 1);
  89. /*
  90. * set output delay adjustments to default values according
  91. * table 5 in Errata Rev. 5, 9/2011:
  92. *
  93. * write 0b01 to UCC1 bits 18:19
  94. * write 0b01 to UCC2 option 1 bits 4:5
  95. * write 0b01 to UCC2 option 2 bits 16:17
  96. */
  97. clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
  98. /*
  99. * set output delay adjustments to default values according
  100. * table 3-13 in Reference Manual Rev.3 05/2010:
  101. *
  102. * write 0b01 to UCC2 option 2 bits 16:17
  103. * write 0b0101 to UCC1 bits 20:23
  104. * write 0b0101 to UCC2 option 1 bits 24:27
  105. */
  106. clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
  107. if (SVR_REV(svid) == 0x0021) {
  108. /*
  109. * UCC2 option 1: write 0b1010 to bits 24:27
  110. * at address IMMRBAR+0x14AC
  111. */
  112. clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
  113. } else if (SVR_REV(svid) == 0x0020) {
  114. /*
  115. * UCC1: write 0b11 to bits 18:19
  116. * at address IMMRBAR+0x14A8
  117. */
  118. setbits32((base + 0xa8), 0x00003000);
  119. /*
  120. * UCC2 option 1: write 0b11 to bits 4:5
  121. * at address IMMRBAR+0x14A8
  122. */
  123. setbits32((base + 0xa8), 0x0c000000);
  124. /*
  125. * UCC2 option 2: write 0b11 to bits 16:17
  126. * at address IMMRBAR+0x14AC
  127. */
  128. setbits32((base + 0xac), 0x0000c000);
  129. }
  130. iounmap(base);
  131. of_node_put(np_par);
  132. of_node_put(np);
  133. }
  134. #endif /* CONFIG_QUICC_ENGINE */
  135. }
  136. machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
  137. /* list of the supported boards */
  138. static char *board[] __initdata = {
  139. "Keymile,KMETER1",
  140. "Keymile,kmpbec8321",
  141. NULL
  142. };
  143. /*
  144. * Called very early, MMU is off, device-tree isn't unflattened
  145. */
  146. static int __init mpc83xx_km_probe(void)
  147. {
  148. unsigned long node = of_get_flat_dt_root();
  149. int i = 0;
  150. while (board[i]) {
  151. if (of_flat_dt_is_compatible(node, board[i]))
  152. break;
  153. i++;
  154. }
  155. return (board[i] != NULL);
  156. }
  157. define_machine(mpc83xx_km) {
  158. .name = "mpc83xx-km-platform",
  159. .probe = mpc83xx_km_probe,
  160. .setup_arch = mpc83xx_km_setup_arch,
  161. .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
  162. .get_irq = ipic_get_irq,
  163. .restart = mpc83xx_restart,
  164. .time_init = mpc83xx_time_init,
  165. .calibrate_decr = generic_calibrate_decr,
  166. .progress = udbg_progress,
  167. };