pcnet32.c 84 KB

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  1. /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
  2. /*
  3. * Copyright 1996-1999 Thomas Bogendoerfer
  4. *
  5. * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  6. *
  7. * Copyright 1993 United States Government as represented by the
  8. * Director, National Security Agency.
  9. *
  10. * This software may be used and distributed according to the terms
  11. * of the GNU General Public License, incorporated herein by reference.
  12. *
  13. * This driver is for PCnet32 and PCnetPCI based ethercards
  14. */
  15. /**************************************************************************
  16. * 23 Oct, 2000.
  17. * Fixed a few bugs, related to running the controller in 32bit mode.
  18. *
  19. * Carsten Langgaard, carstenl@mips.com
  20. * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  21. *
  22. *************************************************************************/
  23. #define DRV_NAME "pcnet32"
  24. #ifdef CONFIG_PCNET32_NAPI
  25. #define DRV_VERSION "1.34-NAPI"
  26. #else
  27. #define DRV_VERSION "1.34"
  28. #endif
  29. #define DRV_RELDATE "14.Aug.2007"
  30. #define PFX DRV_NAME ": "
  31. static const char *const version =
  32. DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  33. #include <linux/module.h>
  34. #include <linux/kernel.h>
  35. #include <linux/string.h>
  36. #include <linux/errno.h>
  37. #include <linux/ioport.h>
  38. #include <linux/slab.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/pci.h>
  41. #include <linux/delay.h>
  42. #include <linux/init.h>
  43. #include <linux/ethtool.h>
  44. #include <linux/mii.h>
  45. #include <linux/crc32.h>
  46. #include <linux/netdevice.h>
  47. #include <linux/etherdevice.h>
  48. #include <linux/skbuff.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/moduleparam.h>
  51. #include <linux/bitops.h>
  52. #include <asm/dma.h>
  53. #include <asm/io.h>
  54. #include <asm/uaccess.h>
  55. #include <asm/irq.h>
  56. /*
  57. * PCI device identifiers for "new style" Linux PCI Device Drivers
  58. */
  59. static struct pci_device_id pcnet32_pci_tbl[] = {
  60. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  61. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  62. /*
  63. * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  64. * the incorrect vendor id.
  65. */
  66. { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  67. .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  68. { } /* terminate list */
  69. };
  70. MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  71. static int cards_found;
  72. /*
  73. * VLB I/O addresses
  74. */
  75. static unsigned int pcnet32_portlist[] __initdata =
  76. { 0x300, 0x320, 0x340, 0x360, 0 };
  77. static int pcnet32_debug = 0;
  78. static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  79. static int pcnet32vlb; /* check for VLB cards ? */
  80. static struct net_device *pcnet32_dev;
  81. static int max_interrupt_work = 2;
  82. static int rx_copybreak = 200;
  83. #define PCNET32_PORT_AUI 0x00
  84. #define PCNET32_PORT_10BT 0x01
  85. #define PCNET32_PORT_GPSI 0x02
  86. #define PCNET32_PORT_MII 0x03
  87. #define PCNET32_PORT_PORTSEL 0x03
  88. #define PCNET32_PORT_ASEL 0x04
  89. #define PCNET32_PORT_100 0x40
  90. #define PCNET32_PORT_FD 0x80
  91. #define PCNET32_DMA_MASK 0xffffffff
  92. #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
  93. #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
  94. /*
  95. * table to translate option values from tulip
  96. * to internal options
  97. */
  98. static const unsigned char options_mapping[] = {
  99. PCNET32_PORT_ASEL, /* 0 Auto-select */
  100. PCNET32_PORT_AUI, /* 1 BNC/AUI */
  101. PCNET32_PORT_AUI, /* 2 AUI/BNC */
  102. PCNET32_PORT_ASEL, /* 3 not supported */
  103. PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
  104. PCNET32_PORT_ASEL, /* 5 not supported */
  105. PCNET32_PORT_ASEL, /* 6 not supported */
  106. PCNET32_PORT_ASEL, /* 7 not supported */
  107. PCNET32_PORT_ASEL, /* 8 not supported */
  108. PCNET32_PORT_MII, /* 9 MII 10baseT */
  109. PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
  110. PCNET32_PORT_MII, /* 11 MII (autosel) */
  111. PCNET32_PORT_10BT, /* 12 10BaseT */
  112. PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
  113. /* 14 MII 100BaseTx-FD */
  114. PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
  115. PCNET32_PORT_ASEL /* 15 not supported */
  116. };
  117. static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
  118. "Loopback test (offline)"
  119. };
  120. #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
  121. #define PCNET32_NUM_REGS 136
  122. #define MAX_UNITS 8 /* More are supported, limit only on options */
  123. static int options[MAX_UNITS];
  124. static int full_duplex[MAX_UNITS];
  125. static int homepna[MAX_UNITS];
  126. /*
  127. * Theory of Operation
  128. *
  129. * This driver uses the same software structure as the normal lance
  130. * driver. So look for a verbose description in lance.c. The differences
  131. * to the normal lance driver is the use of the 32bit mode of PCnet32
  132. * and PCnetPCI chips. Because these chips are 32bit chips, there is no
  133. * 16MB limitation and we don't need bounce buffers.
  134. */
  135. /*
  136. * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  137. * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  138. * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  139. */
  140. #ifndef PCNET32_LOG_TX_BUFFERS
  141. #define PCNET32_LOG_TX_BUFFERS 4
  142. #define PCNET32_LOG_RX_BUFFERS 5
  143. #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
  144. #define PCNET32_LOG_MAX_RX_BUFFERS 9
  145. #endif
  146. #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
  147. #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
  148. #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
  149. #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
  150. #define PKT_BUF_SZ 1544
  151. /* Offsets from base I/O address. */
  152. #define PCNET32_WIO_RDP 0x10
  153. #define PCNET32_WIO_RAP 0x12
  154. #define PCNET32_WIO_RESET 0x14
  155. #define PCNET32_WIO_BDP 0x16
  156. #define PCNET32_DWIO_RDP 0x10
  157. #define PCNET32_DWIO_RAP 0x14
  158. #define PCNET32_DWIO_RESET 0x18
  159. #define PCNET32_DWIO_BDP 0x1C
  160. #define PCNET32_TOTAL_SIZE 0x20
  161. #define CSR0 0
  162. #define CSR0_INIT 0x1
  163. #define CSR0_START 0x2
  164. #define CSR0_STOP 0x4
  165. #define CSR0_TXPOLL 0x8
  166. #define CSR0_INTEN 0x40
  167. #define CSR0_IDON 0x0100
  168. #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
  169. #define PCNET32_INIT_LOW 1
  170. #define PCNET32_INIT_HIGH 2
  171. #define CSR3 3
  172. #define CSR4 4
  173. #define CSR5 5
  174. #define CSR5_SUSPEND 0x0001
  175. #define CSR15 15
  176. #define PCNET32_MC_FILTER 8
  177. #define PCNET32_79C970A 0x2621
  178. /* The PCNET32 Rx and Tx ring descriptors. */
  179. struct pcnet32_rx_head {
  180. u32 base;
  181. s16 buf_length; /* two`s complement of length */
  182. s16 status;
  183. u32 msg_length;
  184. u32 reserved;
  185. };
  186. struct pcnet32_tx_head {
  187. u32 base;
  188. s16 length; /* two`s complement of length */
  189. s16 status;
  190. u32 misc;
  191. u32 reserved;
  192. };
  193. /* The PCNET32 32-Bit initialization block, described in databook. */
  194. struct pcnet32_init_block {
  195. u16 mode;
  196. u16 tlen_rlen;
  197. u8 phys_addr[6];
  198. u16 reserved;
  199. u32 filter[2];
  200. /* Receive and transmit ring base, along with extra bits. */
  201. u32 rx_ring;
  202. u32 tx_ring;
  203. };
  204. /* PCnet32 access functions */
  205. struct pcnet32_access {
  206. u16 (*read_csr) (unsigned long, int);
  207. void (*write_csr) (unsigned long, int, u16);
  208. u16 (*read_bcr) (unsigned long, int);
  209. void (*write_bcr) (unsigned long, int, u16);
  210. u16 (*read_rap) (unsigned long);
  211. void (*write_rap) (unsigned long, u16);
  212. void (*reset) (unsigned long);
  213. };
  214. /*
  215. * The first field of pcnet32_private is read by the ethernet device
  216. * so the structure should be allocated using pci_alloc_consistent().
  217. */
  218. struct pcnet32_private {
  219. struct pcnet32_init_block *init_block;
  220. /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
  221. struct pcnet32_rx_head *rx_ring;
  222. struct pcnet32_tx_head *tx_ring;
  223. dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
  224. returned by pci_alloc_consistent */
  225. struct pci_dev *pci_dev;
  226. const char *name;
  227. /* The saved address of a sent-in-place packet/buffer, for skfree(). */
  228. struct sk_buff **tx_skbuff;
  229. struct sk_buff **rx_skbuff;
  230. dma_addr_t *tx_dma_addr;
  231. dma_addr_t *rx_dma_addr;
  232. struct pcnet32_access a;
  233. spinlock_t lock; /* Guard lock */
  234. unsigned int cur_rx, cur_tx; /* The next free ring entry */
  235. unsigned int rx_ring_size; /* current rx ring size */
  236. unsigned int tx_ring_size; /* current tx ring size */
  237. unsigned int rx_mod_mask; /* rx ring modular mask */
  238. unsigned int tx_mod_mask; /* tx ring modular mask */
  239. unsigned short rx_len_bits;
  240. unsigned short tx_len_bits;
  241. dma_addr_t rx_ring_dma_addr;
  242. dma_addr_t tx_ring_dma_addr;
  243. unsigned int dirty_rx, /* ring entries to be freed. */
  244. dirty_tx;
  245. struct net_device *dev;
  246. struct napi_struct napi;
  247. struct net_device_stats stats;
  248. char tx_full;
  249. char phycount; /* number of phys found */
  250. int options;
  251. unsigned int shared_irq:1, /* shared irq possible */
  252. dxsuflo:1, /* disable transmit stop on uflo */
  253. mii:1; /* mii port available */
  254. struct net_device *next;
  255. struct mii_if_info mii_if;
  256. struct timer_list watchdog_timer;
  257. struct timer_list blink_timer;
  258. u32 msg_enable; /* debug message level */
  259. /* each bit indicates an available PHY */
  260. u32 phymask;
  261. unsigned short chip_version; /* which variant this is */
  262. };
  263. static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
  264. static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
  265. static int pcnet32_open(struct net_device *);
  266. static int pcnet32_init_ring(struct net_device *);
  267. static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
  268. static void pcnet32_tx_timeout(struct net_device *dev);
  269. static irqreturn_t pcnet32_interrupt(int, void *);
  270. static int pcnet32_close(struct net_device *);
  271. static struct net_device_stats *pcnet32_get_stats(struct net_device *);
  272. static void pcnet32_load_multicast(struct net_device *dev);
  273. static void pcnet32_set_multicast_list(struct net_device *);
  274. static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
  275. static void pcnet32_watchdog(struct net_device *);
  276. static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
  277. static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
  278. int val);
  279. static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
  280. static void pcnet32_ethtool_test(struct net_device *dev,
  281. struct ethtool_test *eth_test, u64 * data);
  282. static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
  283. static int pcnet32_phys_id(struct net_device *dev, u32 data);
  284. static void pcnet32_led_blink_callback(struct net_device *dev);
  285. static int pcnet32_get_regs_len(struct net_device *dev);
  286. static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  287. void *ptr);
  288. static void pcnet32_purge_tx_ring(struct net_device *dev);
  289. static int pcnet32_alloc_ring(struct net_device *dev, char *name);
  290. static void pcnet32_free_ring(struct net_device *dev);
  291. static void pcnet32_check_media(struct net_device *dev, int verbose);
  292. static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
  293. {
  294. outw(index, addr + PCNET32_WIO_RAP);
  295. return inw(addr + PCNET32_WIO_RDP);
  296. }
  297. static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
  298. {
  299. outw(index, addr + PCNET32_WIO_RAP);
  300. outw(val, addr + PCNET32_WIO_RDP);
  301. }
  302. static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
  303. {
  304. outw(index, addr + PCNET32_WIO_RAP);
  305. return inw(addr + PCNET32_WIO_BDP);
  306. }
  307. static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
  308. {
  309. outw(index, addr + PCNET32_WIO_RAP);
  310. outw(val, addr + PCNET32_WIO_BDP);
  311. }
  312. static u16 pcnet32_wio_read_rap(unsigned long addr)
  313. {
  314. return inw(addr + PCNET32_WIO_RAP);
  315. }
  316. static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
  317. {
  318. outw(val, addr + PCNET32_WIO_RAP);
  319. }
  320. static void pcnet32_wio_reset(unsigned long addr)
  321. {
  322. inw(addr + PCNET32_WIO_RESET);
  323. }
  324. static int pcnet32_wio_check(unsigned long addr)
  325. {
  326. outw(88, addr + PCNET32_WIO_RAP);
  327. return (inw(addr + PCNET32_WIO_RAP) == 88);
  328. }
  329. static struct pcnet32_access pcnet32_wio = {
  330. .read_csr = pcnet32_wio_read_csr,
  331. .write_csr = pcnet32_wio_write_csr,
  332. .read_bcr = pcnet32_wio_read_bcr,
  333. .write_bcr = pcnet32_wio_write_bcr,
  334. .read_rap = pcnet32_wio_read_rap,
  335. .write_rap = pcnet32_wio_write_rap,
  336. .reset = pcnet32_wio_reset
  337. };
  338. static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
  339. {
  340. outl(index, addr + PCNET32_DWIO_RAP);
  341. return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
  342. }
  343. static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
  344. {
  345. outl(index, addr + PCNET32_DWIO_RAP);
  346. outl(val, addr + PCNET32_DWIO_RDP);
  347. }
  348. static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
  349. {
  350. outl(index, addr + PCNET32_DWIO_RAP);
  351. return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
  352. }
  353. static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
  354. {
  355. outl(index, addr + PCNET32_DWIO_RAP);
  356. outl(val, addr + PCNET32_DWIO_BDP);
  357. }
  358. static u16 pcnet32_dwio_read_rap(unsigned long addr)
  359. {
  360. return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
  361. }
  362. static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
  363. {
  364. outl(val, addr + PCNET32_DWIO_RAP);
  365. }
  366. static void pcnet32_dwio_reset(unsigned long addr)
  367. {
  368. inl(addr + PCNET32_DWIO_RESET);
  369. }
  370. static int pcnet32_dwio_check(unsigned long addr)
  371. {
  372. outl(88, addr + PCNET32_DWIO_RAP);
  373. return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
  374. }
  375. static struct pcnet32_access pcnet32_dwio = {
  376. .read_csr = pcnet32_dwio_read_csr,
  377. .write_csr = pcnet32_dwio_write_csr,
  378. .read_bcr = pcnet32_dwio_read_bcr,
  379. .write_bcr = pcnet32_dwio_write_bcr,
  380. .read_rap = pcnet32_dwio_read_rap,
  381. .write_rap = pcnet32_dwio_write_rap,
  382. .reset = pcnet32_dwio_reset
  383. };
  384. static void pcnet32_netif_stop(struct net_device *dev)
  385. {
  386. struct pcnet32_private *lp = netdev_priv(dev);
  387. dev->trans_start = jiffies;
  388. #ifdef CONFIG_PCNET32_NAPI
  389. napi_disable(&lp->napi);
  390. #endif
  391. netif_tx_disable(dev);
  392. }
  393. static void pcnet32_netif_start(struct net_device *dev)
  394. {
  395. struct pcnet32_private *lp = netdev_priv(dev);
  396. netif_wake_queue(dev);
  397. #ifdef CONFIG_PCNET32_NAPI
  398. napi_enable(&lp->napi);
  399. #endif
  400. }
  401. /*
  402. * Allocate space for the new sized tx ring.
  403. * Free old resources
  404. * Save new resources.
  405. * Any failure keeps old resources.
  406. * Must be called with lp->lock held.
  407. */
  408. static void pcnet32_realloc_tx_ring(struct net_device *dev,
  409. struct pcnet32_private *lp,
  410. unsigned int size)
  411. {
  412. dma_addr_t new_ring_dma_addr;
  413. dma_addr_t *new_dma_addr_list;
  414. struct pcnet32_tx_head *new_tx_ring;
  415. struct sk_buff **new_skb_list;
  416. pcnet32_purge_tx_ring(dev);
  417. new_tx_ring = pci_alloc_consistent(lp->pci_dev,
  418. sizeof(struct pcnet32_tx_head) *
  419. (1 << size),
  420. &new_ring_dma_addr);
  421. if (new_tx_ring == NULL) {
  422. if (netif_msg_drv(lp))
  423. printk("\n" KERN_ERR
  424. "%s: Consistent memory allocation failed.\n",
  425. dev->name);
  426. return;
  427. }
  428. memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
  429. new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
  430. GFP_ATOMIC);
  431. if (!new_dma_addr_list) {
  432. if (netif_msg_drv(lp))
  433. printk("\n" KERN_ERR
  434. "%s: Memory allocation failed.\n", dev->name);
  435. goto free_new_tx_ring;
  436. }
  437. new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
  438. GFP_ATOMIC);
  439. if (!new_skb_list) {
  440. if (netif_msg_drv(lp))
  441. printk("\n" KERN_ERR
  442. "%s: Memory allocation failed.\n", dev->name);
  443. goto free_new_lists;
  444. }
  445. kfree(lp->tx_skbuff);
  446. kfree(lp->tx_dma_addr);
  447. pci_free_consistent(lp->pci_dev,
  448. sizeof(struct pcnet32_tx_head) *
  449. lp->tx_ring_size, lp->tx_ring,
  450. lp->tx_ring_dma_addr);
  451. lp->tx_ring_size = (1 << size);
  452. lp->tx_mod_mask = lp->tx_ring_size - 1;
  453. lp->tx_len_bits = (size << 12);
  454. lp->tx_ring = new_tx_ring;
  455. lp->tx_ring_dma_addr = new_ring_dma_addr;
  456. lp->tx_dma_addr = new_dma_addr_list;
  457. lp->tx_skbuff = new_skb_list;
  458. return;
  459. free_new_lists:
  460. kfree(new_dma_addr_list);
  461. free_new_tx_ring:
  462. pci_free_consistent(lp->pci_dev,
  463. sizeof(struct pcnet32_tx_head) *
  464. (1 << size),
  465. new_tx_ring,
  466. new_ring_dma_addr);
  467. return;
  468. }
  469. /*
  470. * Allocate space for the new sized rx ring.
  471. * Re-use old receive buffers.
  472. * alloc extra buffers
  473. * free unneeded buffers
  474. * free unneeded buffers
  475. * Save new resources.
  476. * Any failure keeps old resources.
  477. * Must be called with lp->lock held.
  478. */
  479. static void pcnet32_realloc_rx_ring(struct net_device *dev,
  480. struct pcnet32_private *lp,
  481. unsigned int size)
  482. {
  483. dma_addr_t new_ring_dma_addr;
  484. dma_addr_t *new_dma_addr_list;
  485. struct pcnet32_rx_head *new_rx_ring;
  486. struct sk_buff **new_skb_list;
  487. int new, overlap;
  488. new_rx_ring = pci_alloc_consistent(lp->pci_dev,
  489. sizeof(struct pcnet32_rx_head) *
  490. (1 << size),
  491. &new_ring_dma_addr);
  492. if (new_rx_ring == NULL) {
  493. if (netif_msg_drv(lp))
  494. printk("\n" KERN_ERR
  495. "%s: Consistent memory allocation failed.\n",
  496. dev->name);
  497. return;
  498. }
  499. memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
  500. new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
  501. GFP_ATOMIC);
  502. if (!new_dma_addr_list) {
  503. if (netif_msg_drv(lp))
  504. printk("\n" KERN_ERR
  505. "%s: Memory allocation failed.\n", dev->name);
  506. goto free_new_rx_ring;
  507. }
  508. new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
  509. GFP_ATOMIC);
  510. if (!new_skb_list) {
  511. if (netif_msg_drv(lp))
  512. printk("\n" KERN_ERR
  513. "%s: Memory allocation failed.\n", dev->name);
  514. goto free_new_lists;
  515. }
  516. /* first copy the current receive buffers */
  517. overlap = min(size, lp->rx_ring_size);
  518. for (new = 0; new < overlap; new++) {
  519. new_rx_ring[new] = lp->rx_ring[new];
  520. new_dma_addr_list[new] = lp->rx_dma_addr[new];
  521. new_skb_list[new] = lp->rx_skbuff[new];
  522. }
  523. /* now allocate any new buffers needed */
  524. for (; new < size; new++ ) {
  525. struct sk_buff *rx_skbuff;
  526. new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
  527. if (!(rx_skbuff = new_skb_list[new])) {
  528. /* keep the original lists and buffers */
  529. if (netif_msg_drv(lp))
  530. printk(KERN_ERR
  531. "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
  532. dev->name);
  533. goto free_all_new;
  534. }
  535. skb_reserve(rx_skbuff, 2);
  536. new_dma_addr_list[new] =
  537. pci_map_single(lp->pci_dev, rx_skbuff->data,
  538. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  539. new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
  540. new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
  541. new_rx_ring[new].status = le16_to_cpu(0x8000);
  542. }
  543. /* and free any unneeded buffers */
  544. for (; new < lp->rx_ring_size; new++) {
  545. if (lp->rx_skbuff[new]) {
  546. pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
  547. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  548. dev_kfree_skb(lp->rx_skbuff[new]);
  549. }
  550. }
  551. kfree(lp->rx_skbuff);
  552. kfree(lp->rx_dma_addr);
  553. pci_free_consistent(lp->pci_dev,
  554. sizeof(struct pcnet32_rx_head) *
  555. lp->rx_ring_size, lp->rx_ring,
  556. lp->rx_ring_dma_addr);
  557. lp->rx_ring_size = (1 << size);
  558. lp->rx_mod_mask = lp->rx_ring_size - 1;
  559. lp->rx_len_bits = (size << 4);
  560. lp->rx_ring = new_rx_ring;
  561. lp->rx_ring_dma_addr = new_ring_dma_addr;
  562. lp->rx_dma_addr = new_dma_addr_list;
  563. lp->rx_skbuff = new_skb_list;
  564. return;
  565. free_all_new:
  566. for (; --new >= lp->rx_ring_size; ) {
  567. if (new_skb_list[new]) {
  568. pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
  569. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  570. dev_kfree_skb(new_skb_list[new]);
  571. }
  572. }
  573. kfree(new_skb_list);
  574. free_new_lists:
  575. kfree(new_dma_addr_list);
  576. free_new_rx_ring:
  577. pci_free_consistent(lp->pci_dev,
  578. sizeof(struct pcnet32_rx_head) *
  579. (1 << size),
  580. new_rx_ring,
  581. new_ring_dma_addr);
  582. return;
  583. }
  584. static void pcnet32_purge_rx_ring(struct net_device *dev)
  585. {
  586. struct pcnet32_private *lp = netdev_priv(dev);
  587. int i;
  588. /* free all allocated skbuffs */
  589. for (i = 0; i < lp->rx_ring_size; i++) {
  590. lp->rx_ring[i].status = 0; /* CPU owns buffer */
  591. wmb(); /* Make sure adapter sees owner change */
  592. if (lp->rx_skbuff[i]) {
  593. pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
  594. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  595. dev_kfree_skb_any(lp->rx_skbuff[i]);
  596. }
  597. lp->rx_skbuff[i] = NULL;
  598. lp->rx_dma_addr[i] = 0;
  599. }
  600. }
  601. #ifdef CONFIG_NET_POLL_CONTROLLER
  602. static void pcnet32_poll_controller(struct net_device *dev)
  603. {
  604. disable_irq(dev->irq);
  605. pcnet32_interrupt(0, dev);
  606. enable_irq(dev->irq);
  607. }
  608. #endif
  609. static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  610. {
  611. struct pcnet32_private *lp = netdev_priv(dev);
  612. unsigned long flags;
  613. int r = -EOPNOTSUPP;
  614. if (lp->mii) {
  615. spin_lock_irqsave(&lp->lock, flags);
  616. mii_ethtool_gset(&lp->mii_if, cmd);
  617. spin_unlock_irqrestore(&lp->lock, flags);
  618. r = 0;
  619. }
  620. return r;
  621. }
  622. static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  623. {
  624. struct pcnet32_private *lp = netdev_priv(dev);
  625. unsigned long flags;
  626. int r = -EOPNOTSUPP;
  627. if (lp->mii) {
  628. spin_lock_irqsave(&lp->lock, flags);
  629. r = mii_ethtool_sset(&lp->mii_if, cmd);
  630. spin_unlock_irqrestore(&lp->lock, flags);
  631. }
  632. return r;
  633. }
  634. static void pcnet32_get_drvinfo(struct net_device *dev,
  635. struct ethtool_drvinfo *info)
  636. {
  637. struct pcnet32_private *lp = netdev_priv(dev);
  638. strcpy(info->driver, DRV_NAME);
  639. strcpy(info->version, DRV_VERSION);
  640. if (lp->pci_dev)
  641. strcpy(info->bus_info, pci_name(lp->pci_dev));
  642. else
  643. sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
  644. }
  645. static u32 pcnet32_get_link(struct net_device *dev)
  646. {
  647. struct pcnet32_private *lp = netdev_priv(dev);
  648. unsigned long flags;
  649. int r;
  650. spin_lock_irqsave(&lp->lock, flags);
  651. if (lp->mii) {
  652. r = mii_link_ok(&lp->mii_if);
  653. } else if (lp->chip_version >= PCNET32_79C970A) {
  654. ulong ioaddr = dev->base_addr; /* card base I/O address */
  655. r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
  656. } else { /* can not detect link on really old chips */
  657. r = 1;
  658. }
  659. spin_unlock_irqrestore(&lp->lock, flags);
  660. return r;
  661. }
  662. static u32 pcnet32_get_msglevel(struct net_device *dev)
  663. {
  664. struct pcnet32_private *lp = netdev_priv(dev);
  665. return lp->msg_enable;
  666. }
  667. static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
  668. {
  669. struct pcnet32_private *lp = netdev_priv(dev);
  670. lp->msg_enable = value;
  671. }
  672. static int pcnet32_nway_reset(struct net_device *dev)
  673. {
  674. struct pcnet32_private *lp = netdev_priv(dev);
  675. unsigned long flags;
  676. int r = -EOPNOTSUPP;
  677. if (lp->mii) {
  678. spin_lock_irqsave(&lp->lock, flags);
  679. r = mii_nway_restart(&lp->mii_if);
  680. spin_unlock_irqrestore(&lp->lock, flags);
  681. }
  682. return r;
  683. }
  684. static void pcnet32_get_ringparam(struct net_device *dev,
  685. struct ethtool_ringparam *ering)
  686. {
  687. struct pcnet32_private *lp = netdev_priv(dev);
  688. ering->tx_max_pending = TX_MAX_RING_SIZE;
  689. ering->tx_pending = lp->tx_ring_size;
  690. ering->rx_max_pending = RX_MAX_RING_SIZE;
  691. ering->rx_pending = lp->rx_ring_size;
  692. }
  693. static int pcnet32_set_ringparam(struct net_device *dev,
  694. struct ethtool_ringparam *ering)
  695. {
  696. struct pcnet32_private *lp = netdev_priv(dev);
  697. unsigned long flags;
  698. unsigned int size;
  699. ulong ioaddr = dev->base_addr;
  700. int i;
  701. if (ering->rx_mini_pending || ering->rx_jumbo_pending)
  702. return -EINVAL;
  703. if (netif_running(dev))
  704. pcnet32_netif_stop(dev);
  705. spin_lock_irqsave(&lp->lock, flags);
  706. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
  707. size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
  708. /* set the minimum ring size to 4, to allow the loopback test to work
  709. * unchanged.
  710. */
  711. for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
  712. if (size <= (1 << i))
  713. break;
  714. }
  715. if ((1 << i) != lp->tx_ring_size)
  716. pcnet32_realloc_tx_ring(dev, lp, i);
  717. size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
  718. for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
  719. if (size <= (1 << i))
  720. break;
  721. }
  722. if ((1 << i) != lp->rx_ring_size)
  723. pcnet32_realloc_rx_ring(dev, lp, i);
  724. lp->napi.weight = lp->rx_ring_size / 2;
  725. if (netif_running(dev)) {
  726. pcnet32_netif_start(dev);
  727. pcnet32_restart(dev, CSR0_NORMAL);
  728. }
  729. spin_unlock_irqrestore(&lp->lock, flags);
  730. if (netif_msg_drv(lp))
  731. printk(KERN_INFO
  732. "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
  733. lp->rx_ring_size, lp->tx_ring_size);
  734. return 0;
  735. }
  736. static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
  737. u8 * data)
  738. {
  739. memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
  740. }
  741. static int pcnet32_self_test_count(struct net_device *dev)
  742. {
  743. return PCNET32_TEST_LEN;
  744. }
  745. static void pcnet32_ethtool_test(struct net_device *dev,
  746. struct ethtool_test *test, u64 * data)
  747. {
  748. struct pcnet32_private *lp = netdev_priv(dev);
  749. int rc;
  750. if (test->flags == ETH_TEST_FL_OFFLINE) {
  751. rc = pcnet32_loopback_test(dev, data);
  752. if (rc) {
  753. if (netif_msg_hw(lp))
  754. printk(KERN_DEBUG "%s: Loopback test failed.\n",
  755. dev->name);
  756. test->flags |= ETH_TEST_FL_FAILED;
  757. } else if (netif_msg_hw(lp))
  758. printk(KERN_DEBUG "%s: Loopback test passed.\n",
  759. dev->name);
  760. } else if (netif_msg_hw(lp))
  761. printk(KERN_DEBUG
  762. "%s: No tests to run (specify 'Offline' on ethtool).",
  763. dev->name);
  764. } /* end pcnet32_ethtool_test */
  765. static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
  766. {
  767. struct pcnet32_private *lp = netdev_priv(dev);
  768. struct pcnet32_access *a = &lp->a; /* access to registers */
  769. ulong ioaddr = dev->base_addr; /* card base I/O address */
  770. struct sk_buff *skb; /* sk buff */
  771. int x, i; /* counters */
  772. int numbuffs = 4; /* number of TX/RX buffers and descs */
  773. u16 status = 0x8300; /* TX ring status */
  774. u16 teststatus; /* test of ring status */
  775. int rc; /* return code */
  776. int size; /* size of packets */
  777. unsigned char *packet; /* source packet data */
  778. static const int data_len = 60; /* length of source packets */
  779. unsigned long flags;
  780. unsigned long ticks;
  781. rc = 1; /* default to fail */
  782. if (netif_running(dev))
  783. #ifdef CONFIG_PCNET32_NAPI
  784. pcnet32_netif_stop(dev);
  785. #else
  786. pcnet32_close(dev);
  787. #endif
  788. spin_lock_irqsave(&lp->lock, flags);
  789. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
  790. numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
  791. /* Reset the PCNET32 */
  792. lp->a.reset(ioaddr);
  793. lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
  794. /* switch pcnet32 to 32bit mode */
  795. lp->a.write_bcr(ioaddr, 20, 2);
  796. /* purge & init rings but don't actually restart */
  797. pcnet32_restart(dev, 0x0000);
  798. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
  799. /* Initialize Transmit buffers. */
  800. size = data_len + 15;
  801. for (x = 0; x < numbuffs; x++) {
  802. if (!(skb = dev_alloc_skb(size))) {
  803. if (netif_msg_hw(lp))
  804. printk(KERN_DEBUG
  805. "%s: Cannot allocate skb at line: %d!\n",
  806. dev->name, __LINE__);
  807. goto clean_up;
  808. } else {
  809. packet = skb->data;
  810. skb_put(skb, size); /* create space for data */
  811. lp->tx_skbuff[x] = skb;
  812. lp->tx_ring[x].length = le16_to_cpu(-skb->len);
  813. lp->tx_ring[x].misc = 0;
  814. /* put DA and SA into the skb */
  815. for (i = 0; i < 6; i++)
  816. *packet++ = dev->dev_addr[i];
  817. for (i = 0; i < 6; i++)
  818. *packet++ = dev->dev_addr[i];
  819. /* type */
  820. *packet++ = 0x08;
  821. *packet++ = 0x06;
  822. /* packet number */
  823. *packet++ = x;
  824. /* fill packet with data */
  825. for (i = 0; i < data_len; i++)
  826. *packet++ = i;
  827. lp->tx_dma_addr[x] =
  828. pci_map_single(lp->pci_dev, skb->data, skb->len,
  829. PCI_DMA_TODEVICE);
  830. lp->tx_ring[x].base =
  831. (u32) le32_to_cpu(lp->tx_dma_addr[x]);
  832. wmb(); /* Make sure owner changes after all others are visible */
  833. lp->tx_ring[x].status = le16_to_cpu(status);
  834. }
  835. }
  836. x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
  837. a->write_bcr(ioaddr, 32, x | 0x0002);
  838. /* set int loopback in CSR15 */
  839. x = a->read_csr(ioaddr, CSR15) & 0xfffc;
  840. lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
  841. teststatus = le16_to_cpu(0x8000);
  842. lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
  843. /* Check status of descriptors */
  844. for (x = 0; x < numbuffs; x++) {
  845. ticks = 0;
  846. rmb();
  847. while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
  848. spin_unlock_irqrestore(&lp->lock, flags);
  849. msleep(1);
  850. spin_lock_irqsave(&lp->lock, flags);
  851. rmb();
  852. ticks++;
  853. }
  854. if (ticks == 200) {
  855. if (netif_msg_hw(lp))
  856. printk("%s: Desc %d failed to reset!\n",
  857. dev->name, x);
  858. break;
  859. }
  860. }
  861. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
  862. wmb();
  863. if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
  864. printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
  865. for (x = 0; x < numbuffs; x++) {
  866. printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
  867. skb = lp->rx_skbuff[x];
  868. for (i = 0; i < size; i++) {
  869. printk("%02x ", *(skb->data + i));
  870. }
  871. printk("\n");
  872. }
  873. }
  874. x = 0;
  875. rc = 0;
  876. while (x < numbuffs && !rc) {
  877. skb = lp->rx_skbuff[x];
  878. packet = lp->tx_skbuff[x]->data;
  879. for (i = 0; i < size; i++) {
  880. if (*(skb->data + i) != packet[i]) {
  881. if (netif_msg_hw(lp))
  882. printk(KERN_DEBUG
  883. "%s: Error in compare! %2x - %02x %02x\n",
  884. dev->name, i, *(skb->data + i),
  885. packet[i]);
  886. rc = 1;
  887. break;
  888. }
  889. }
  890. x++;
  891. }
  892. clean_up:
  893. *data1 = rc;
  894. pcnet32_purge_tx_ring(dev);
  895. x = a->read_csr(ioaddr, CSR15);
  896. a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
  897. x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
  898. a->write_bcr(ioaddr, 32, (x & ~0x0002));
  899. #ifdef CONFIG_PCNET32_NAPI
  900. if (netif_running(dev)) {
  901. pcnet32_netif_start(dev);
  902. pcnet32_restart(dev, CSR0_NORMAL);
  903. } else {
  904. pcnet32_purge_rx_ring(dev);
  905. lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
  906. }
  907. spin_unlock_irqrestore(&lp->lock, flags);
  908. #else
  909. if (netif_running(dev)) {
  910. spin_unlock_irqrestore(&lp->lock, flags);
  911. pcnet32_open(dev);
  912. } else {
  913. pcnet32_purge_rx_ring(dev);
  914. lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
  915. spin_unlock_irqrestore(&lp->lock, flags);
  916. }
  917. #endif
  918. return (rc);
  919. } /* end pcnet32_loopback_test */
  920. static void pcnet32_led_blink_callback(struct net_device *dev)
  921. {
  922. struct pcnet32_private *lp = netdev_priv(dev);
  923. struct pcnet32_access *a = &lp->a;
  924. ulong ioaddr = dev->base_addr;
  925. unsigned long flags;
  926. int i;
  927. spin_lock_irqsave(&lp->lock, flags);
  928. for (i = 4; i < 8; i++) {
  929. a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
  930. }
  931. spin_unlock_irqrestore(&lp->lock, flags);
  932. mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
  933. }
  934. static int pcnet32_phys_id(struct net_device *dev, u32 data)
  935. {
  936. struct pcnet32_private *lp = netdev_priv(dev);
  937. struct pcnet32_access *a = &lp->a;
  938. ulong ioaddr = dev->base_addr;
  939. unsigned long flags;
  940. int i, regs[4];
  941. if (!lp->blink_timer.function) {
  942. init_timer(&lp->blink_timer);
  943. lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
  944. lp->blink_timer.data = (unsigned long)dev;
  945. }
  946. /* Save the current value of the bcrs */
  947. spin_lock_irqsave(&lp->lock, flags);
  948. for (i = 4; i < 8; i++) {
  949. regs[i - 4] = a->read_bcr(ioaddr, i);
  950. }
  951. spin_unlock_irqrestore(&lp->lock, flags);
  952. mod_timer(&lp->blink_timer, jiffies);
  953. set_current_state(TASK_INTERRUPTIBLE);
  954. if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
  955. data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
  956. msleep_interruptible(data * 1000);
  957. del_timer_sync(&lp->blink_timer);
  958. /* Restore the original value of the bcrs */
  959. spin_lock_irqsave(&lp->lock, flags);
  960. for (i = 4; i < 8; i++) {
  961. a->write_bcr(ioaddr, i, regs[i - 4]);
  962. }
  963. spin_unlock_irqrestore(&lp->lock, flags);
  964. return 0;
  965. }
  966. /*
  967. * lp->lock must be held.
  968. */
  969. static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
  970. int can_sleep)
  971. {
  972. int csr5;
  973. struct pcnet32_private *lp = netdev_priv(dev);
  974. struct pcnet32_access *a = &lp->a;
  975. ulong ioaddr = dev->base_addr;
  976. int ticks;
  977. /* really old chips have to be stopped. */
  978. if (lp->chip_version < PCNET32_79C970A)
  979. return 0;
  980. /* set SUSPEND (SPND) - CSR5 bit 0 */
  981. csr5 = a->read_csr(ioaddr, CSR5);
  982. a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
  983. /* poll waiting for bit to be set */
  984. ticks = 0;
  985. while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
  986. spin_unlock_irqrestore(&lp->lock, *flags);
  987. if (can_sleep)
  988. msleep(1);
  989. else
  990. mdelay(1);
  991. spin_lock_irqsave(&lp->lock, *flags);
  992. ticks++;
  993. if (ticks > 200) {
  994. if (netif_msg_hw(lp))
  995. printk(KERN_DEBUG
  996. "%s: Error getting into suspend!\n",
  997. dev->name);
  998. return 0;
  999. }
  1000. }
  1001. return 1;
  1002. }
  1003. /*
  1004. * process one receive descriptor entry
  1005. */
  1006. static void pcnet32_rx_entry(struct net_device *dev,
  1007. struct pcnet32_private *lp,
  1008. struct pcnet32_rx_head *rxp,
  1009. int entry)
  1010. {
  1011. int status = (short)le16_to_cpu(rxp->status) >> 8;
  1012. int rx_in_place = 0;
  1013. struct sk_buff *skb;
  1014. short pkt_len;
  1015. if (status != 0x03) { /* There was an error. */
  1016. /*
  1017. * There is a tricky error noted by John Murphy,
  1018. * <murf@perftech.com> to Russ Nelson: Even with full-sized
  1019. * buffers it's possible for a jabber packet to use two
  1020. * buffers, with only the last correctly noting the error.
  1021. */
  1022. if (status & 0x01) /* Only count a general error at the */
  1023. lp->stats.rx_errors++; /* end of a packet. */
  1024. if (status & 0x20)
  1025. lp->stats.rx_frame_errors++;
  1026. if (status & 0x10)
  1027. lp->stats.rx_over_errors++;
  1028. if (status & 0x08)
  1029. lp->stats.rx_crc_errors++;
  1030. if (status & 0x04)
  1031. lp->stats.rx_fifo_errors++;
  1032. return;
  1033. }
  1034. pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
  1035. /* Discard oversize frames. */
  1036. if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
  1037. if (netif_msg_drv(lp))
  1038. printk(KERN_ERR "%s: Impossible packet size %d!\n",
  1039. dev->name, pkt_len);
  1040. lp->stats.rx_errors++;
  1041. return;
  1042. }
  1043. if (pkt_len < 60) {
  1044. if (netif_msg_rx_err(lp))
  1045. printk(KERN_ERR "%s: Runt packet!\n", dev->name);
  1046. lp->stats.rx_errors++;
  1047. return;
  1048. }
  1049. if (pkt_len > rx_copybreak) {
  1050. struct sk_buff *newskb;
  1051. if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
  1052. skb_reserve(newskb, 2);
  1053. skb = lp->rx_skbuff[entry];
  1054. pci_unmap_single(lp->pci_dev,
  1055. lp->rx_dma_addr[entry],
  1056. PKT_BUF_SZ - 2,
  1057. PCI_DMA_FROMDEVICE);
  1058. skb_put(skb, pkt_len);
  1059. lp->rx_skbuff[entry] = newskb;
  1060. lp->rx_dma_addr[entry] =
  1061. pci_map_single(lp->pci_dev,
  1062. newskb->data,
  1063. PKT_BUF_SZ - 2,
  1064. PCI_DMA_FROMDEVICE);
  1065. rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]);
  1066. rx_in_place = 1;
  1067. } else
  1068. skb = NULL;
  1069. } else {
  1070. skb = dev_alloc_skb(pkt_len + 2);
  1071. }
  1072. if (skb == NULL) {
  1073. if (netif_msg_drv(lp))
  1074. printk(KERN_ERR
  1075. "%s: Memory squeeze, dropping packet.\n",
  1076. dev->name);
  1077. lp->stats.rx_dropped++;
  1078. return;
  1079. }
  1080. skb->dev = dev;
  1081. if (!rx_in_place) {
  1082. skb_reserve(skb, 2); /* 16 byte align */
  1083. skb_put(skb, pkt_len); /* Make room */
  1084. pci_dma_sync_single_for_cpu(lp->pci_dev,
  1085. lp->rx_dma_addr[entry],
  1086. pkt_len,
  1087. PCI_DMA_FROMDEVICE);
  1088. skb_copy_to_linear_data(skb,
  1089. (unsigned char *)(lp->rx_skbuff[entry]->data),
  1090. pkt_len);
  1091. pci_dma_sync_single_for_device(lp->pci_dev,
  1092. lp->rx_dma_addr[entry],
  1093. pkt_len,
  1094. PCI_DMA_FROMDEVICE);
  1095. }
  1096. lp->stats.rx_bytes += skb->len;
  1097. skb->protocol = eth_type_trans(skb, dev);
  1098. #ifdef CONFIG_PCNET32_NAPI
  1099. netif_receive_skb(skb);
  1100. #else
  1101. netif_rx(skb);
  1102. #endif
  1103. dev->last_rx = jiffies;
  1104. lp->stats.rx_packets++;
  1105. return;
  1106. }
  1107. static int pcnet32_rx(struct net_device *dev, int budget)
  1108. {
  1109. struct pcnet32_private *lp = netdev_priv(dev);
  1110. int entry = lp->cur_rx & lp->rx_mod_mask;
  1111. struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
  1112. int npackets = 0;
  1113. /* If we own the next entry, it's a new packet. Send it up. */
  1114. while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
  1115. pcnet32_rx_entry(dev, lp, rxp, entry);
  1116. npackets += 1;
  1117. /*
  1118. * The docs say that the buffer length isn't touched, but Andrew
  1119. * Boyd of QNX reports that some revs of the 79C965 clear it.
  1120. */
  1121. rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
  1122. wmb(); /* Make sure owner changes after others are visible */
  1123. rxp->status = le16_to_cpu(0x8000);
  1124. entry = (++lp->cur_rx) & lp->rx_mod_mask;
  1125. rxp = &lp->rx_ring[entry];
  1126. }
  1127. return npackets;
  1128. }
  1129. static int pcnet32_tx(struct net_device *dev)
  1130. {
  1131. struct pcnet32_private *lp = netdev_priv(dev);
  1132. unsigned int dirty_tx = lp->dirty_tx;
  1133. int delta;
  1134. int must_restart = 0;
  1135. while (dirty_tx != lp->cur_tx) {
  1136. int entry = dirty_tx & lp->tx_mod_mask;
  1137. int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
  1138. if (status < 0)
  1139. break; /* It still hasn't been Txed */
  1140. lp->tx_ring[entry].base = 0;
  1141. if (status & 0x4000) {
  1142. /* There was a major error, log it. */
  1143. int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
  1144. lp->stats.tx_errors++;
  1145. if (netif_msg_tx_err(lp))
  1146. printk(KERN_ERR
  1147. "%s: Tx error status=%04x err_status=%08x\n",
  1148. dev->name, status,
  1149. err_status);
  1150. if (err_status & 0x04000000)
  1151. lp->stats.tx_aborted_errors++;
  1152. if (err_status & 0x08000000)
  1153. lp->stats.tx_carrier_errors++;
  1154. if (err_status & 0x10000000)
  1155. lp->stats.tx_window_errors++;
  1156. #ifndef DO_DXSUFLO
  1157. if (err_status & 0x40000000) {
  1158. lp->stats.tx_fifo_errors++;
  1159. /* Ackk! On FIFO errors the Tx unit is turned off! */
  1160. /* Remove this verbosity later! */
  1161. if (netif_msg_tx_err(lp))
  1162. printk(KERN_ERR
  1163. "%s: Tx FIFO error!\n",
  1164. dev->name);
  1165. must_restart = 1;
  1166. }
  1167. #else
  1168. if (err_status & 0x40000000) {
  1169. lp->stats.tx_fifo_errors++;
  1170. if (!lp->dxsuflo) { /* If controller doesn't recover ... */
  1171. /* Ackk! On FIFO errors the Tx unit is turned off! */
  1172. /* Remove this verbosity later! */
  1173. if (netif_msg_tx_err(lp))
  1174. printk(KERN_ERR
  1175. "%s: Tx FIFO error!\n",
  1176. dev->name);
  1177. must_restart = 1;
  1178. }
  1179. }
  1180. #endif
  1181. } else {
  1182. if (status & 0x1800)
  1183. lp->stats.collisions++;
  1184. lp->stats.tx_packets++;
  1185. }
  1186. /* We must free the original skb */
  1187. if (lp->tx_skbuff[entry]) {
  1188. pci_unmap_single(lp->pci_dev,
  1189. lp->tx_dma_addr[entry],
  1190. lp->tx_skbuff[entry]->
  1191. len, PCI_DMA_TODEVICE);
  1192. dev_kfree_skb_any(lp->tx_skbuff[entry]);
  1193. lp->tx_skbuff[entry] = NULL;
  1194. lp->tx_dma_addr[entry] = 0;
  1195. }
  1196. dirty_tx++;
  1197. }
  1198. delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
  1199. if (delta > lp->tx_ring_size) {
  1200. if (netif_msg_drv(lp))
  1201. printk(KERN_ERR
  1202. "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
  1203. dev->name, dirty_tx, lp->cur_tx,
  1204. lp->tx_full);
  1205. dirty_tx += lp->tx_ring_size;
  1206. delta -= lp->tx_ring_size;
  1207. }
  1208. if (lp->tx_full &&
  1209. netif_queue_stopped(dev) &&
  1210. delta < lp->tx_ring_size - 2) {
  1211. /* The ring is no longer full, clear tbusy. */
  1212. lp->tx_full = 0;
  1213. netif_wake_queue(dev);
  1214. }
  1215. lp->dirty_tx = dirty_tx;
  1216. return must_restart;
  1217. }
  1218. #ifdef CONFIG_PCNET32_NAPI
  1219. static int pcnet32_poll(struct napi_struct *napi, int budget)
  1220. {
  1221. struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
  1222. struct net_device *dev = lp->dev;
  1223. unsigned long ioaddr = dev->base_addr;
  1224. unsigned long flags;
  1225. int work_done;
  1226. u16 val;
  1227. work_done = pcnet32_rx(dev, budget);
  1228. spin_lock_irqsave(&lp->lock, flags);
  1229. if (pcnet32_tx(dev)) {
  1230. /* reset the chip to clear the error condition, then restart */
  1231. lp->a.reset(ioaddr);
  1232. lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
  1233. pcnet32_restart(dev, CSR0_START);
  1234. netif_wake_queue(dev);
  1235. }
  1236. spin_unlock_irqrestore(&lp->lock, flags);
  1237. if (work_done < budget) {
  1238. spin_lock_irqsave(&lp->lock, flags);
  1239. __netif_rx_complete(dev, napi);
  1240. /* clear interrupt masks */
  1241. val = lp->a.read_csr(ioaddr, CSR3);
  1242. val &= 0x00ff;
  1243. lp->a.write_csr(ioaddr, CSR3, val);
  1244. /* Set interrupt enable. */
  1245. lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
  1246. mmiowb();
  1247. spin_unlock_irqrestore(&lp->lock, flags);
  1248. }
  1249. return work_done;
  1250. }
  1251. #endif
  1252. #define PCNET32_REGS_PER_PHY 32
  1253. #define PCNET32_MAX_PHYS 32
  1254. static int pcnet32_get_regs_len(struct net_device *dev)
  1255. {
  1256. struct pcnet32_private *lp = netdev_priv(dev);
  1257. int j = lp->phycount * PCNET32_REGS_PER_PHY;
  1258. return ((PCNET32_NUM_REGS + j) * sizeof(u16));
  1259. }
  1260. static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  1261. void *ptr)
  1262. {
  1263. int i, csr0;
  1264. u16 *buff = ptr;
  1265. struct pcnet32_private *lp = netdev_priv(dev);
  1266. struct pcnet32_access *a = &lp->a;
  1267. ulong ioaddr = dev->base_addr;
  1268. unsigned long flags;
  1269. spin_lock_irqsave(&lp->lock, flags);
  1270. csr0 = a->read_csr(ioaddr, CSR0);
  1271. if (!(csr0 & CSR0_STOP)) /* If not stopped */
  1272. pcnet32_suspend(dev, &flags, 1);
  1273. /* read address PROM */
  1274. for (i = 0; i < 16; i += 2)
  1275. *buff++ = inw(ioaddr + i);
  1276. /* read control and status registers */
  1277. for (i = 0; i < 90; i++) {
  1278. *buff++ = a->read_csr(ioaddr, i);
  1279. }
  1280. *buff++ = a->read_csr(ioaddr, 112);
  1281. *buff++ = a->read_csr(ioaddr, 114);
  1282. /* read bus configuration registers */
  1283. for (i = 0; i < 30; i++) {
  1284. *buff++ = a->read_bcr(ioaddr, i);
  1285. }
  1286. *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
  1287. for (i = 31; i < 36; i++) {
  1288. *buff++ = a->read_bcr(ioaddr, i);
  1289. }
  1290. /* read mii phy registers */
  1291. if (lp->mii) {
  1292. int j;
  1293. for (j = 0; j < PCNET32_MAX_PHYS; j++) {
  1294. if (lp->phymask & (1 << j)) {
  1295. for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
  1296. lp->a.write_bcr(ioaddr, 33,
  1297. (j << 5) | i);
  1298. *buff++ = lp->a.read_bcr(ioaddr, 34);
  1299. }
  1300. }
  1301. }
  1302. }
  1303. if (!(csr0 & CSR0_STOP)) { /* If not stopped */
  1304. int csr5;
  1305. /* clear SUSPEND (SPND) - CSR5 bit 0 */
  1306. csr5 = a->read_csr(ioaddr, CSR5);
  1307. a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
  1308. }
  1309. spin_unlock_irqrestore(&lp->lock, flags);
  1310. }
  1311. static const struct ethtool_ops pcnet32_ethtool_ops = {
  1312. .get_settings = pcnet32_get_settings,
  1313. .set_settings = pcnet32_set_settings,
  1314. .get_drvinfo = pcnet32_get_drvinfo,
  1315. .get_msglevel = pcnet32_get_msglevel,
  1316. .set_msglevel = pcnet32_set_msglevel,
  1317. .nway_reset = pcnet32_nway_reset,
  1318. .get_link = pcnet32_get_link,
  1319. .get_ringparam = pcnet32_get_ringparam,
  1320. .set_ringparam = pcnet32_set_ringparam,
  1321. .get_strings = pcnet32_get_strings,
  1322. .self_test_count = pcnet32_self_test_count,
  1323. .self_test = pcnet32_ethtool_test,
  1324. .phys_id = pcnet32_phys_id,
  1325. .get_regs_len = pcnet32_get_regs_len,
  1326. .get_regs = pcnet32_get_regs,
  1327. };
  1328. /* only probes for non-PCI devices, the rest are handled by
  1329. * pci_register_driver via pcnet32_probe_pci */
  1330. static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
  1331. {
  1332. unsigned int *port, ioaddr;
  1333. /* search for PCnet32 VLB cards at known addresses */
  1334. for (port = pcnet32_portlist; (ioaddr = *port); port++) {
  1335. if (request_region
  1336. (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
  1337. /* check if there is really a pcnet chip on that ioaddr */
  1338. if ((inb(ioaddr + 14) == 0x57)
  1339. && (inb(ioaddr + 15) == 0x57)) {
  1340. pcnet32_probe1(ioaddr, 0, NULL);
  1341. } else {
  1342. release_region(ioaddr, PCNET32_TOTAL_SIZE);
  1343. }
  1344. }
  1345. }
  1346. }
  1347. static int __devinit
  1348. pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
  1349. {
  1350. unsigned long ioaddr;
  1351. int err;
  1352. err = pci_enable_device(pdev);
  1353. if (err < 0) {
  1354. if (pcnet32_debug & NETIF_MSG_PROBE)
  1355. printk(KERN_ERR PFX
  1356. "failed to enable device -- err=%d\n", err);
  1357. return err;
  1358. }
  1359. pci_set_master(pdev);
  1360. ioaddr = pci_resource_start(pdev, 0);
  1361. if (!ioaddr) {
  1362. if (pcnet32_debug & NETIF_MSG_PROBE)
  1363. printk(KERN_ERR PFX
  1364. "card has no PCI IO resources, aborting\n");
  1365. return -ENODEV;
  1366. }
  1367. if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
  1368. if (pcnet32_debug & NETIF_MSG_PROBE)
  1369. printk(KERN_ERR PFX
  1370. "architecture does not support 32bit PCI busmaster DMA\n");
  1371. return -ENODEV;
  1372. }
  1373. if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
  1374. NULL) {
  1375. if (pcnet32_debug & NETIF_MSG_PROBE)
  1376. printk(KERN_ERR PFX
  1377. "io address range already allocated\n");
  1378. return -EBUSY;
  1379. }
  1380. err = pcnet32_probe1(ioaddr, 1, pdev);
  1381. if (err < 0) {
  1382. pci_disable_device(pdev);
  1383. }
  1384. return err;
  1385. }
  1386. /* pcnet32_probe1
  1387. * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
  1388. * pdev will be NULL when called from pcnet32_probe_vlbus.
  1389. */
  1390. static int __devinit
  1391. pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
  1392. {
  1393. struct pcnet32_private *lp;
  1394. int i, media;
  1395. int fdx, mii, fset, dxsuflo;
  1396. int chip_version;
  1397. char *chipname;
  1398. struct net_device *dev;
  1399. struct pcnet32_access *a = NULL;
  1400. u8 promaddr[6];
  1401. int ret = -ENODEV;
  1402. /* reset the chip */
  1403. pcnet32_wio_reset(ioaddr);
  1404. /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
  1405. if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
  1406. a = &pcnet32_wio;
  1407. } else {
  1408. pcnet32_dwio_reset(ioaddr);
  1409. if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
  1410. && pcnet32_dwio_check(ioaddr)) {
  1411. a = &pcnet32_dwio;
  1412. } else
  1413. goto err_release_region;
  1414. }
  1415. chip_version =
  1416. a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
  1417. if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
  1418. printk(KERN_INFO " PCnet chip version is %#x.\n",
  1419. chip_version);
  1420. if ((chip_version & 0xfff) != 0x003) {
  1421. if (pcnet32_debug & NETIF_MSG_PROBE)
  1422. printk(KERN_INFO PFX "Unsupported chip version.\n");
  1423. goto err_release_region;
  1424. }
  1425. /* initialize variables */
  1426. fdx = mii = fset = dxsuflo = 0;
  1427. chip_version = (chip_version >> 12) & 0xffff;
  1428. switch (chip_version) {
  1429. case 0x2420:
  1430. chipname = "PCnet/PCI 79C970"; /* PCI */
  1431. break;
  1432. case 0x2430:
  1433. if (shared)
  1434. chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
  1435. else
  1436. chipname = "PCnet/32 79C965"; /* 486/VL bus */
  1437. break;
  1438. case 0x2621:
  1439. chipname = "PCnet/PCI II 79C970A"; /* PCI */
  1440. fdx = 1;
  1441. break;
  1442. case 0x2623:
  1443. chipname = "PCnet/FAST 79C971"; /* PCI */
  1444. fdx = 1;
  1445. mii = 1;
  1446. fset = 1;
  1447. break;
  1448. case 0x2624:
  1449. chipname = "PCnet/FAST+ 79C972"; /* PCI */
  1450. fdx = 1;
  1451. mii = 1;
  1452. fset = 1;
  1453. break;
  1454. case 0x2625:
  1455. chipname = "PCnet/FAST III 79C973"; /* PCI */
  1456. fdx = 1;
  1457. mii = 1;
  1458. break;
  1459. case 0x2626:
  1460. chipname = "PCnet/Home 79C978"; /* PCI */
  1461. fdx = 1;
  1462. /*
  1463. * This is based on specs published at www.amd.com. This section
  1464. * assumes that a card with a 79C978 wants to go into standard
  1465. * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
  1466. * and the module option homepna=1 can select this instead.
  1467. */
  1468. media = a->read_bcr(ioaddr, 49);
  1469. media &= ~3; /* default to 10Mb ethernet */
  1470. if (cards_found < MAX_UNITS && homepna[cards_found])
  1471. media |= 1; /* switch to home wiring mode */
  1472. if (pcnet32_debug & NETIF_MSG_PROBE)
  1473. printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
  1474. (media & 1) ? "1" : "10");
  1475. a->write_bcr(ioaddr, 49, media);
  1476. break;
  1477. case 0x2627:
  1478. chipname = "PCnet/FAST III 79C975"; /* PCI */
  1479. fdx = 1;
  1480. mii = 1;
  1481. break;
  1482. case 0x2628:
  1483. chipname = "PCnet/PRO 79C976";
  1484. fdx = 1;
  1485. mii = 1;
  1486. break;
  1487. default:
  1488. if (pcnet32_debug & NETIF_MSG_PROBE)
  1489. printk(KERN_INFO PFX
  1490. "PCnet version %#x, no PCnet32 chip.\n",
  1491. chip_version);
  1492. goto err_release_region;
  1493. }
  1494. /*
  1495. * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
  1496. * starting until the packet is loaded. Strike one for reliability, lose
  1497. * one for latency - although on PCI this isnt a big loss. Older chips
  1498. * have FIFO's smaller than a packet, so you can't do this.
  1499. * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
  1500. */
  1501. if (fset) {
  1502. a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
  1503. a->write_csr(ioaddr, 80,
  1504. (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
  1505. dxsuflo = 1;
  1506. }
  1507. dev = alloc_etherdev(sizeof(*lp));
  1508. if (!dev) {
  1509. if (pcnet32_debug & NETIF_MSG_PROBE)
  1510. printk(KERN_ERR PFX "Memory allocation failed.\n");
  1511. ret = -ENOMEM;
  1512. goto err_release_region;
  1513. }
  1514. SET_NETDEV_DEV(dev, &pdev->dev);
  1515. if (pcnet32_debug & NETIF_MSG_PROBE)
  1516. printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
  1517. /* In most chips, after a chip reset, the ethernet address is read from the
  1518. * station address PROM at the base address and programmed into the
  1519. * "Physical Address Registers" CSR12-14.
  1520. * As a precautionary measure, we read the PROM values and complain if
  1521. * they disagree with the CSRs. If they miscompare, and the PROM addr
  1522. * is valid, then the PROM addr is used.
  1523. */
  1524. for (i = 0; i < 3; i++) {
  1525. unsigned int val;
  1526. val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
  1527. /* There may be endianness issues here. */
  1528. dev->dev_addr[2 * i] = val & 0x0ff;
  1529. dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
  1530. }
  1531. /* read PROM address and compare with CSR address */
  1532. for (i = 0; i < 6; i++)
  1533. promaddr[i] = inb(ioaddr + i);
  1534. if (memcmp(promaddr, dev->dev_addr, 6)
  1535. || !is_valid_ether_addr(dev->dev_addr)) {
  1536. if (is_valid_ether_addr(promaddr)) {
  1537. if (pcnet32_debug & NETIF_MSG_PROBE) {
  1538. printk(" warning: CSR address invalid,\n");
  1539. printk(KERN_INFO
  1540. " using instead PROM address of");
  1541. }
  1542. memcpy(dev->dev_addr, promaddr, 6);
  1543. }
  1544. }
  1545. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  1546. /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
  1547. if (!is_valid_ether_addr(dev->perm_addr))
  1548. memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
  1549. if (pcnet32_debug & NETIF_MSG_PROBE) {
  1550. for (i = 0; i < 6; i++)
  1551. printk(" %2.2x", dev->dev_addr[i]);
  1552. /* Version 0x2623 and 0x2624 */
  1553. if (((chip_version + 1) & 0xfffe) == 0x2624) {
  1554. i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
  1555. printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
  1556. switch (i >> 10) {
  1557. case 0:
  1558. printk(" 20 bytes,");
  1559. break;
  1560. case 1:
  1561. printk(" 64 bytes,");
  1562. break;
  1563. case 2:
  1564. printk(" 128 bytes,");
  1565. break;
  1566. case 3:
  1567. printk("~220 bytes,");
  1568. break;
  1569. }
  1570. i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
  1571. printk(" BCR18(%x):", i & 0xffff);
  1572. if (i & (1 << 5))
  1573. printk("BurstWrEn ");
  1574. if (i & (1 << 6))
  1575. printk("BurstRdEn ");
  1576. if (i & (1 << 7))
  1577. printk("DWordIO ");
  1578. if (i & (1 << 11))
  1579. printk("NoUFlow ");
  1580. i = a->read_bcr(ioaddr, 25);
  1581. printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
  1582. i = a->read_bcr(ioaddr, 26);
  1583. printk(" SRAM_BND=0x%04x,", i << 8);
  1584. i = a->read_bcr(ioaddr, 27);
  1585. if (i & (1 << 14))
  1586. printk("LowLatRx");
  1587. }
  1588. }
  1589. dev->base_addr = ioaddr;
  1590. lp = netdev_priv(dev);
  1591. /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
  1592. if ((lp->init_block =
  1593. pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
  1594. if (pcnet32_debug & NETIF_MSG_PROBE)
  1595. printk(KERN_ERR PFX
  1596. "Consistent memory allocation failed.\n");
  1597. ret = -ENOMEM;
  1598. goto err_free_netdev;
  1599. }
  1600. lp->pci_dev = pdev;
  1601. lp->dev = dev;
  1602. spin_lock_init(&lp->lock);
  1603. SET_NETDEV_DEV(dev, &pdev->dev);
  1604. lp->name = chipname;
  1605. lp->shared_irq = shared;
  1606. lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
  1607. lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
  1608. lp->tx_mod_mask = lp->tx_ring_size - 1;
  1609. lp->rx_mod_mask = lp->rx_ring_size - 1;
  1610. lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
  1611. lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
  1612. lp->mii_if.full_duplex = fdx;
  1613. lp->mii_if.phy_id_mask = 0x1f;
  1614. lp->mii_if.reg_num_mask = 0x1f;
  1615. lp->dxsuflo = dxsuflo;
  1616. lp->mii = mii;
  1617. lp->chip_version = chip_version;
  1618. lp->msg_enable = pcnet32_debug;
  1619. if ((cards_found >= MAX_UNITS)
  1620. || (options[cards_found] > sizeof(options_mapping)))
  1621. lp->options = PCNET32_PORT_ASEL;
  1622. else
  1623. lp->options = options_mapping[options[cards_found]];
  1624. lp->mii_if.dev = dev;
  1625. lp->mii_if.mdio_read = mdio_read;
  1626. lp->mii_if.mdio_write = mdio_write;
  1627. #ifdef CONFIG_PCNET32_NAPI
  1628. netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
  1629. #endif
  1630. if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
  1631. ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
  1632. lp->options |= PCNET32_PORT_FD;
  1633. if (!a) {
  1634. if (pcnet32_debug & NETIF_MSG_PROBE)
  1635. printk(KERN_ERR PFX "No access methods\n");
  1636. ret = -ENODEV;
  1637. goto err_free_consistent;
  1638. }
  1639. lp->a = *a;
  1640. /* prior to register_netdev, dev->name is not yet correct */
  1641. if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
  1642. ret = -ENOMEM;
  1643. goto err_free_ring;
  1644. }
  1645. /* detect special T1/E1 WAN card by checking for MAC address */
  1646. if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
  1647. && dev->dev_addr[2] == 0x75)
  1648. lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
  1649. lp->init_block->mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
  1650. lp->init_block->tlen_rlen =
  1651. le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
  1652. for (i = 0; i < 6; i++)
  1653. lp->init_block->phys_addr[i] = dev->dev_addr[i];
  1654. lp->init_block->filter[0] = 0x00000000;
  1655. lp->init_block->filter[1] = 0x00000000;
  1656. lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
  1657. lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
  1658. /* switch pcnet32 to 32bit mode */
  1659. a->write_bcr(ioaddr, 20, 2);
  1660. a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
  1661. a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
  1662. if (pdev) { /* use the IRQ provided by PCI */
  1663. dev->irq = pdev->irq;
  1664. if (pcnet32_debug & NETIF_MSG_PROBE)
  1665. printk(" assigned IRQ %d.\n", dev->irq);
  1666. } else {
  1667. unsigned long irq_mask = probe_irq_on();
  1668. /*
  1669. * To auto-IRQ we enable the initialization-done and DMA error
  1670. * interrupts. For ISA boards we get a DMA error, but VLB and PCI
  1671. * boards will work.
  1672. */
  1673. /* Trigger an initialization just for the interrupt. */
  1674. a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
  1675. mdelay(1);
  1676. dev->irq = probe_irq_off(irq_mask);
  1677. if (!dev->irq) {
  1678. if (pcnet32_debug & NETIF_MSG_PROBE)
  1679. printk(", failed to detect IRQ line.\n");
  1680. ret = -ENODEV;
  1681. goto err_free_ring;
  1682. }
  1683. if (pcnet32_debug & NETIF_MSG_PROBE)
  1684. printk(", probed IRQ %d.\n", dev->irq);
  1685. }
  1686. /* Set the mii phy_id so that we can query the link state */
  1687. if (lp->mii) {
  1688. /* lp->phycount and lp->phymask are set to 0 by memset above */
  1689. lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
  1690. /* scan for PHYs */
  1691. for (i = 0; i < PCNET32_MAX_PHYS; i++) {
  1692. unsigned short id1, id2;
  1693. id1 = mdio_read(dev, i, MII_PHYSID1);
  1694. if (id1 == 0xffff)
  1695. continue;
  1696. id2 = mdio_read(dev, i, MII_PHYSID2);
  1697. if (id2 == 0xffff)
  1698. continue;
  1699. if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
  1700. continue; /* 79C971 & 79C972 have phantom phy at id 31 */
  1701. lp->phycount++;
  1702. lp->phymask |= (1 << i);
  1703. lp->mii_if.phy_id = i;
  1704. if (pcnet32_debug & NETIF_MSG_PROBE)
  1705. printk(KERN_INFO PFX
  1706. "Found PHY %04x:%04x at address %d.\n",
  1707. id1, id2, i);
  1708. }
  1709. lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
  1710. if (lp->phycount > 1) {
  1711. lp->options |= PCNET32_PORT_MII;
  1712. }
  1713. }
  1714. init_timer(&lp->watchdog_timer);
  1715. lp->watchdog_timer.data = (unsigned long)dev;
  1716. lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
  1717. /* The PCNET32-specific entries in the device structure. */
  1718. dev->open = &pcnet32_open;
  1719. dev->hard_start_xmit = &pcnet32_start_xmit;
  1720. dev->stop = &pcnet32_close;
  1721. dev->get_stats = &pcnet32_get_stats;
  1722. dev->set_multicast_list = &pcnet32_set_multicast_list;
  1723. dev->do_ioctl = &pcnet32_ioctl;
  1724. dev->ethtool_ops = &pcnet32_ethtool_ops;
  1725. dev->tx_timeout = pcnet32_tx_timeout;
  1726. dev->watchdog_timeo = (5 * HZ);
  1727. #ifdef CONFIG_NET_POLL_CONTROLLER
  1728. dev->poll_controller = pcnet32_poll_controller;
  1729. #endif
  1730. /* Fill in the generic fields of the device structure. */
  1731. if (register_netdev(dev))
  1732. goto err_free_ring;
  1733. if (pdev) {
  1734. pci_set_drvdata(pdev, dev);
  1735. } else {
  1736. lp->next = pcnet32_dev;
  1737. pcnet32_dev = dev;
  1738. }
  1739. if (pcnet32_debug & NETIF_MSG_PROBE)
  1740. printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
  1741. cards_found++;
  1742. /* enable LED writes */
  1743. a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
  1744. return 0;
  1745. err_free_ring:
  1746. pcnet32_free_ring(dev);
  1747. err_free_consistent:
  1748. pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
  1749. lp->init_block, lp->init_dma_addr);
  1750. err_free_netdev:
  1751. free_netdev(dev);
  1752. err_release_region:
  1753. release_region(ioaddr, PCNET32_TOTAL_SIZE);
  1754. return ret;
  1755. }
  1756. /* if any allocation fails, caller must also call pcnet32_free_ring */
  1757. static int pcnet32_alloc_ring(struct net_device *dev, char *name)
  1758. {
  1759. struct pcnet32_private *lp = netdev_priv(dev);
  1760. lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
  1761. sizeof(struct pcnet32_tx_head) *
  1762. lp->tx_ring_size,
  1763. &lp->tx_ring_dma_addr);
  1764. if (lp->tx_ring == NULL) {
  1765. if (netif_msg_drv(lp))
  1766. printk("\n" KERN_ERR PFX
  1767. "%s: Consistent memory allocation failed.\n",
  1768. name);
  1769. return -ENOMEM;
  1770. }
  1771. lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
  1772. sizeof(struct pcnet32_rx_head) *
  1773. lp->rx_ring_size,
  1774. &lp->rx_ring_dma_addr);
  1775. if (lp->rx_ring == NULL) {
  1776. if (netif_msg_drv(lp))
  1777. printk("\n" KERN_ERR PFX
  1778. "%s: Consistent memory allocation failed.\n",
  1779. name);
  1780. return -ENOMEM;
  1781. }
  1782. lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
  1783. GFP_ATOMIC);
  1784. if (!lp->tx_dma_addr) {
  1785. if (netif_msg_drv(lp))
  1786. printk("\n" KERN_ERR PFX
  1787. "%s: Memory allocation failed.\n", name);
  1788. return -ENOMEM;
  1789. }
  1790. lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
  1791. GFP_ATOMIC);
  1792. if (!lp->rx_dma_addr) {
  1793. if (netif_msg_drv(lp))
  1794. printk("\n" KERN_ERR PFX
  1795. "%s: Memory allocation failed.\n", name);
  1796. return -ENOMEM;
  1797. }
  1798. lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
  1799. GFP_ATOMIC);
  1800. if (!lp->tx_skbuff) {
  1801. if (netif_msg_drv(lp))
  1802. printk("\n" KERN_ERR PFX
  1803. "%s: Memory allocation failed.\n", name);
  1804. return -ENOMEM;
  1805. }
  1806. lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
  1807. GFP_ATOMIC);
  1808. if (!lp->rx_skbuff) {
  1809. if (netif_msg_drv(lp))
  1810. printk("\n" KERN_ERR PFX
  1811. "%s: Memory allocation failed.\n", name);
  1812. return -ENOMEM;
  1813. }
  1814. return 0;
  1815. }
  1816. static void pcnet32_free_ring(struct net_device *dev)
  1817. {
  1818. struct pcnet32_private *lp = netdev_priv(dev);
  1819. kfree(lp->tx_skbuff);
  1820. lp->tx_skbuff = NULL;
  1821. kfree(lp->rx_skbuff);
  1822. lp->rx_skbuff = NULL;
  1823. kfree(lp->tx_dma_addr);
  1824. lp->tx_dma_addr = NULL;
  1825. kfree(lp->rx_dma_addr);
  1826. lp->rx_dma_addr = NULL;
  1827. if (lp->tx_ring) {
  1828. pci_free_consistent(lp->pci_dev,
  1829. sizeof(struct pcnet32_tx_head) *
  1830. lp->tx_ring_size, lp->tx_ring,
  1831. lp->tx_ring_dma_addr);
  1832. lp->tx_ring = NULL;
  1833. }
  1834. if (lp->rx_ring) {
  1835. pci_free_consistent(lp->pci_dev,
  1836. sizeof(struct pcnet32_rx_head) *
  1837. lp->rx_ring_size, lp->rx_ring,
  1838. lp->rx_ring_dma_addr);
  1839. lp->rx_ring = NULL;
  1840. }
  1841. }
  1842. static int pcnet32_open(struct net_device *dev)
  1843. {
  1844. struct pcnet32_private *lp = netdev_priv(dev);
  1845. unsigned long ioaddr = dev->base_addr;
  1846. u16 val;
  1847. int i;
  1848. int rc;
  1849. unsigned long flags;
  1850. if (request_irq(dev->irq, &pcnet32_interrupt,
  1851. lp->shared_irq ? IRQF_SHARED : 0, dev->name,
  1852. (void *)dev)) {
  1853. return -EAGAIN;
  1854. }
  1855. spin_lock_irqsave(&lp->lock, flags);
  1856. /* Check for a valid station address */
  1857. if (!is_valid_ether_addr(dev->dev_addr)) {
  1858. rc = -EINVAL;
  1859. goto err_free_irq;
  1860. }
  1861. /* Reset the PCNET32 */
  1862. lp->a.reset(ioaddr);
  1863. /* switch pcnet32 to 32bit mode */
  1864. lp->a.write_bcr(ioaddr, 20, 2);
  1865. if (netif_msg_ifup(lp))
  1866. printk(KERN_DEBUG
  1867. "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
  1868. dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
  1869. (u32) (lp->rx_ring_dma_addr),
  1870. (u32) (lp->init_dma_addr));
  1871. /* set/reset autoselect bit */
  1872. val = lp->a.read_bcr(ioaddr, 2) & ~2;
  1873. if (lp->options & PCNET32_PORT_ASEL)
  1874. val |= 2;
  1875. lp->a.write_bcr(ioaddr, 2, val);
  1876. /* handle full duplex setting */
  1877. if (lp->mii_if.full_duplex) {
  1878. val = lp->a.read_bcr(ioaddr, 9) & ~3;
  1879. if (lp->options & PCNET32_PORT_FD) {
  1880. val |= 1;
  1881. if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
  1882. val |= 2;
  1883. } else if (lp->options & PCNET32_PORT_ASEL) {
  1884. /* workaround of xSeries250, turn on for 79C975 only */
  1885. if (lp->chip_version == 0x2627)
  1886. val |= 3;
  1887. }
  1888. lp->a.write_bcr(ioaddr, 9, val);
  1889. }
  1890. /* set/reset GPSI bit in test register */
  1891. val = lp->a.read_csr(ioaddr, 124) & ~0x10;
  1892. if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
  1893. val |= 0x10;
  1894. lp->a.write_csr(ioaddr, 124, val);
  1895. /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
  1896. if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
  1897. (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
  1898. lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
  1899. if (lp->options & PCNET32_PORT_ASEL) {
  1900. lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
  1901. if (netif_msg_link(lp))
  1902. printk(KERN_DEBUG
  1903. "%s: Setting 100Mb-Full Duplex.\n",
  1904. dev->name);
  1905. }
  1906. }
  1907. if (lp->phycount < 2) {
  1908. /*
  1909. * 24 Jun 2004 according AMD, in order to change the PHY,
  1910. * DANAS (or DISPM for 79C976) must be set; then select the speed,
  1911. * duplex, and/or enable auto negotiation, and clear DANAS
  1912. */
  1913. if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
  1914. lp->a.write_bcr(ioaddr, 32,
  1915. lp->a.read_bcr(ioaddr, 32) | 0x0080);
  1916. /* disable Auto Negotiation, set 10Mpbs, HD */
  1917. val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
  1918. if (lp->options & PCNET32_PORT_FD)
  1919. val |= 0x10;
  1920. if (lp->options & PCNET32_PORT_100)
  1921. val |= 0x08;
  1922. lp->a.write_bcr(ioaddr, 32, val);
  1923. } else {
  1924. if (lp->options & PCNET32_PORT_ASEL) {
  1925. lp->a.write_bcr(ioaddr, 32,
  1926. lp->a.read_bcr(ioaddr,
  1927. 32) | 0x0080);
  1928. /* enable auto negotiate, setup, disable fd */
  1929. val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
  1930. val |= 0x20;
  1931. lp->a.write_bcr(ioaddr, 32, val);
  1932. }
  1933. }
  1934. } else {
  1935. int first_phy = -1;
  1936. u16 bmcr;
  1937. u32 bcr9;
  1938. struct ethtool_cmd ecmd;
  1939. /*
  1940. * There is really no good other way to handle multiple PHYs
  1941. * other than turning off all automatics
  1942. */
  1943. val = lp->a.read_bcr(ioaddr, 2);
  1944. lp->a.write_bcr(ioaddr, 2, val & ~2);
  1945. val = lp->a.read_bcr(ioaddr, 32);
  1946. lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
  1947. if (!(lp->options & PCNET32_PORT_ASEL)) {
  1948. /* setup ecmd */
  1949. ecmd.port = PORT_MII;
  1950. ecmd.transceiver = XCVR_INTERNAL;
  1951. ecmd.autoneg = AUTONEG_DISABLE;
  1952. ecmd.speed =
  1953. lp->
  1954. options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
  1955. bcr9 = lp->a.read_bcr(ioaddr, 9);
  1956. if (lp->options & PCNET32_PORT_FD) {
  1957. ecmd.duplex = DUPLEX_FULL;
  1958. bcr9 |= (1 << 0);
  1959. } else {
  1960. ecmd.duplex = DUPLEX_HALF;
  1961. bcr9 |= ~(1 << 0);
  1962. }
  1963. lp->a.write_bcr(ioaddr, 9, bcr9);
  1964. }
  1965. for (i = 0; i < PCNET32_MAX_PHYS; i++) {
  1966. if (lp->phymask & (1 << i)) {
  1967. /* isolate all but the first PHY */
  1968. bmcr = mdio_read(dev, i, MII_BMCR);
  1969. if (first_phy == -1) {
  1970. first_phy = i;
  1971. mdio_write(dev, i, MII_BMCR,
  1972. bmcr & ~BMCR_ISOLATE);
  1973. } else {
  1974. mdio_write(dev, i, MII_BMCR,
  1975. bmcr | BMCR_ISOLATE);
  1976. }
  1977. /* use mii_ethtool_sset to setup PHY */
  1978. lp->mii_if.phy_id = i;
  1979. ecmd.phy_address = i;
  1980. if (lp->options & PCNET32_PORT_ASEL) {
  1981. mii_ethtool_gset(&lp->mii_if, &ecmd);
  1982. ecmd.autoneg = AUTONEG_ENABLE;
  1983. }
  1984. mii_ethtool_sset(&lp->mii_if, &ecmd);
  1985. }
  1986. }
  1987. lp->mii_if.phy_id = first_phy;
  1988. if (netif_msg_link(lp))
  1989. printk(KERN_INFO "%s: Using PHY number %d.\n",
  1990. dev->name, first_phy);
  1991. }
  1992. #ifdef DO_DXSUFLO
  1993. if (lp->dxsuflo) { /* Disable transmit stop on underflow */
  1994. val = lp->a.read_csr(ioaddr, CSR3);
  1995. val |= 0x40;
  1996. lp->a.write_csr(ioaddr, CSR3, val);
  1997. }
  1998. #endif
  1999. lp->init_block->mode =
  2000. le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
  2001. pcnet32_load_multicast(dev);
  2002. if (pcnet32_init_ring(dev)) {
  2003. rc = -ENOMEM;
  2004. goto err_free_ring;
  2005. }
  2006. #ifdef CONFIG_PCNET32_NAPI
  2007. napi_enable(&lp->napi);
  2008. #endif
  2009. /* Re-initialize the PCNET32, and start it when done. */
  2010. lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
  2011. lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
  2012. lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
  2013. lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
  2014. netif_start_queue(dev);
  2015. if (lp->chip_version >= PCNET32_79C970A) {
  2016. /* Print the link status and start the watchdog */
  2017. pcnet32_check_media(dev, 1);
  2018. mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
  2019. }
  2020. i = 0;
  2021. while (i++ < 100)
  2022. if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
  2023. break;
  2024. /*
  2025. * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
  2026. * reports that doing so triggers a bug in the '974.
  2027. */
  2028. lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
  2029. if (netif_msg_ifup(lp))
  2030. printk(KERN_DEBUG
  2031. "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
  2032. dev->name, i,
  2033. (u32) (lp->init_dma_addr),
  2034. lp->a.read_csr(ioaddr, CSR0));
  2035. spin_unlock_irqrestore(&lp->lock, flags);
  2036. return 0; /* Always succeed */
  2037. err_free_ring:
  2038. /* free any allocated skbuffs */
  2039. pcnet32_purge_rx_ring(dev);
  2040. /*
  2041. * Switch back to 16bit mode to avoid problems with dumb
  2042. * DOS packet driver after a warm reboot
  2043. */
  2044. lp->a.write_bcr(ioaddr, 20, 4);
  2045. err_free_irq:
  2046. spin_unlock_irqrestore(&lp->lock, flags);
  2047. free_irq(dev->irq, dev);
  2048. return rc;
  2049. }
  2050. /*
  2051. * The LANCE has been halted for one reason or another (busmaster memory
  2052. * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
  2053. * etc.). Modern LANCE variants always reload their ring-buffer
  2054. * configuration when restarted, so we must reinitialize our ring
  2055. * context before restarting. As part of this reinitialization,
  2056. * find all packets still on the Tx ring and pretend that they had been
  2057. * sent (in effect, drop the packets on the floor) - the higher-level
  2058. * protocols will time out and retransmit. It'd be better to shuffle
  2059. * these skbs to a temp list and then actually re-Tx them after
  2060. * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
  2061. */
  2062. static void pcnet32_purge_tx_ring(struct net_device *dev)
  2063. {
  2064. struct pcnet32_private *lp = netdev_priv(dev);
  2065. int i;
  2066. for (i = 0; i < lp->tx_ring_size; i++) {
  2067. lp->tx_ring[i].status = 0; /* CPU owns buffer */
  2068. wmb(); /* Make sure adapter sees owner change */
  2069. if (lp->tx_skbuff[i]) {
  2070. pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
  2071. lp->tx_skbuff[i]->len,
  2072. PCI_DMA_TODEVICE);
  2073. dev_kfree_skb_any(lp->tx_skbuff[i]);
  2074. }
  2075. lp->tx_skbuff[i] = NULL;
  2076. lp->tx_dma_addr[i] = 0;
  2077. }
  2078. }
  2079. /* Initialize the PCNET32 Rx and Tx rings. */
  2080. static int pcnet32_init_ring(struct net_device *dev)
  2081. {
  2082. struct pcnet32_private *lp = netdev_priv(dev);
  2083. int i;
  2084. lp->tx_full = 0;
  2085. lp->cur_rx = lp->cur_tx = 0;
  2086. lp->dirty_rx = lp->dirty_tx = 0;
  2087. for (i = 0; i < lp->rx_ring_size; i++) {
  2088. struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
  2089. if (rx_skbuff == NULL) {
  2090. if (!
  2091. (rx_skbuff = lp->rx_skbuff[i] =
  2092. dev_alloc_skb(PKT_BUF_SZ))) {
  2093. /* there is not much, we can do at this point */
  2094. if (netif_msg_drv(lp))
  2095. printk(KERN_ERR
  2096. "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
  2097. dev->name);
  2098. return -1;
  2099. }
  2100. skb_reserve(rx_skbuff, 2);
  2101. }
  2102. rmb();
  2103. if (lp->rx_dma_addr[i] == 0)
  2104. lp->rx_dma_addr[i] =
  2105. pci_map_single(lp->pci_dev, rx_skbuff->data,
  2106. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  2107. lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
  2108. lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
  2109. wmb(); /* Make sure owner changes after all others are visible */
  2110. lp->rx_ring[i].status = le16_to_cpu(0x8000);
  2111. }
  2112. /* The Tx buffer address is filled in as needed, but we do need to clear
  2113. * the upper ownership bit. */
  2114. for (i = 0; i < lp->tx_ring_size; i++) {
  2115. lp->tx_ring[i].status = 0; /* CPU owns buffer */
  2116. wmb(); /* Make sure adapter sees owner change */
  2117. lp->tx_ring[i].base = 0;
  2118. lp->tx_dma_addr[i] = 0;
  2119. }
  2120. lp->init_block->tlen_rlen =
  2121. le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
  2122. for (i = 0; i < 6; i++)
  2123. lp->init_block->phys_addr[i] = dev->dev_addr[i];
  2124. lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
  2125. lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
  2126. wmb(); /* Make sure all changes are visible */
  2127. return 0;
  2128. }
  2129. /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
  2130. * then flush the pending transmit operations, re-initialize the ring,
  2131. * and tell the chip to initialize.
  2132. */
  2133. static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
  2134. {
  2135. struct pcnet32_private *lp = netdev_priv(dev);
  2136. unsigned long ioaddr = dev->base_addr;
  2137. int i;
  2138. /* wait for stop */
  2139. for (i = 0; i < 100; i++)
  2140. if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
  2141. break;
  2142. if (i >= 100 && netif_msg_drv(lp))
  2143. printk(KERN_ERR
  2144. "%s: pcnet32_restart timed out waiting for stop.\n",
  2145. dev->name);
  2146. pcnet32_purge_tx_ring(dev);
  2147. if (pcnet32_init_ring(dev))
  2148. return;
  2149. /* ReInit Ring */
  2150. lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
  2151. i = 0;
  2152. while (i++ < 1000)
  2153. if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
  2154. break;
  2155. lp->a.write_csr(ioaddr, CSR0, csr0_bits);
  2156. }
  2157. static void pcnet32_tx_timeout(struct net_device *dev)
  2158. {
  2159. struct pcnet32_private *lp = netdev_priv(dev);
  2160. unsigned long ioaddr = dev->base_addr, flags;
  2161. spin_lock_irqsave(&lp->lock, flags);
  2162. /* Transmitter timeout, serious problems. */
  2163. if (pcnet32_debug & NETIF_MSG_DRV)
  2164. printk(KERN_ERR
  2165. "%s: transmit timed out, status %4.4x, resetting.\n",
  2166. dev->name, lp->a.read_csr(ioaddr, CSR0));
  2167. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
  2168. lp->stats.tx_errors++;
  2169. if (netif_msg_tx_err(lp)) {
  2170. int i;
  2171. printk(KERN_DEBUG
  2172. " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
  2173. lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
  2174. lp->cur_rx);
  2175. for (i = 0; i < lp->rx_ring_size; i++)
  2176. printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
  2177. le32_to_cpu(lp->rx_ring[i].base),
  2178. (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
  2179. 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
  2180. le16_to_cpu(lp->rx_ring[i].status));
  2181. for (i = 0; i < lp->tx_ring_size; i++)
  2182. printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
  2183. le32_to_cpu(lp->tx_ring[i].base),
  2184. (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
  2185. le32_to_cpu(lp->tx_ring[i].misc),
  2186. le16_to_cpu(lp->tx_ring[i].status));
  2187. printk("\n");
  2188. }
  2189. pcnet32_restart(dev, CSR0_NORMAL);
  2190. dev->trans_start = jiffies;
  2191. netif_wake_queue(dev);
  2192. spin_unlock_irqrestore(&lp->lock, flags);
  2193. }
  2194. static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2195. {
  2196. struct pcnet32_private *lp = netdev_priv(dev);
  2197. unsigned long ioaddr = dev->base_addr;
  2198. u16 status;
  2199. int entry;
  2200. unsigned long flags;
  2201. spin_lock_irqsave(&lp->lock, flags);
  2202. if (netif_msg_tx_queued(lp)) {
  2203. printk(KERN_DEBUG
  2204. "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
  2205. dev->name, lp->a.read_csr(ioaddr, CSR0));
  2206. }
  2207. /* Default status -- will not enable Successful-TxDone
  2208. * interrupt when that option is available to us.
  2209. */
  2210. status = 0x8300;
  2211. /* Fill in a Tx ring entry */
  2212. /* Mask to ring buffer boundary. */
  2213. entry = lp->cur_tx & lp->tx_mod_mask;
  2214. /* Caution: the write order is important here, set the status
  2215. * with the "ownership" bits last. */
  2216. lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
  2217. lp->tx_ring[entry].misc = 0x00000000;
  2218. lp->tx_skbuff[entry] = skb;
  2219. lp->tx_dma_addr[entry] =
  2220. pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
  2221. lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
  2222. wmb(); /* Make sure owner changes after all others are visible */
  2223. lp->tx_ring[entry].status = le16_to_cpu(status);
  2224. lp->cur_tx++;
  2225. lp->stats.tx_bytes += skb->len;
  2226. /* Trigger an immediate send poll. */
  2227. lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
  2228. dev->trans_start = jiffies;
  2229. if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
  2230. lp->tx_full = 1;
  2231. netif_stop_queue(dev);
  2232. }
  2233. spin_unlock_irqrestore(&lp->lock, flags);
  2234. return 0;
  2235. }
  2236. /* The PCNET32 interrupt handler. */
  2237. static irqreturn_t
  2238. pcnet32_interrupt(int irq, void *dev_id)
  2239. {
  2240. struct net_device *dev = dev_id;
  2241. struct pcnet32_private *lp;
  2242. unsigned long ioaddr;
  2243. u16 csr0;
  2244. int boguscnt = max_interrupt_work;
  2245. ioaddr = dev->base_addr;
  2246. lp = netdev_priv(dev);
  2247. spin_lock(&lp->lock);
  2248. csr0 = lp->a.read_csr(ioaddr, CSR0);
  2249. while ((csr0 & 0x8f00) && --boguscnt >= 0) {
  2250. if (csr0 == 0xffff) {
  2251. break; /* PCMCIA remove happened */
  2252. }
  2253. /* Acknowledge all of the current interrupt sources ASAP. */
  2254. lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
  2255. if (netif_msg_intr(lp))
  2256. printk(KERN_DEBUG
  2257. "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
  2258. dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
  2259. /* Log misc errors. */
  2260. if (csr0 & 0x4000)
  2261. lp->stats.tx_errors++; /* Tx babble. */
  2262. if (csr0 & 0x1000) {
  2263. /*
  2264. * This happens when our receive ring is full. This
  2265. * shouldn't be a problem as we will see normal rx
  2266. * interrupts for the frames in the receive ring. But
  2267. * there are some PCI chipsets (I can reproduce this
  2268. * on SP3G with Intel saturn chipset) which have
  2269. * sometimes problems and will fill up the receive
  2270. * ring with error descriptors. In this situation we
  2271. * don't get a rx interrupt, but a missed frame
  2272. * interrupt sooner or later.
  2273. */
  2274. lp->stats.rx_errors++; /* Missed a Rx frame. */
  2275. }
  2276. if (csr0 & 0x0800) {
  2277. if (netif_msg_drv(lp))
  2278. printk(KERN_ERR
  2279. "%s: Bus master arbitration failure, status %4.4x.\n",
  2280. dev->name, csr0);
  2281. /* unlike for the lance, there is no restart needed */
  2282. }
  2283. #ifdef CONFIG_PCNET32_NAPI
  2284. if (netif_rx_schedule_prep(dev, &lp->napi)) {
  2285. u16 val;
  2286. /* set interrupt masks */
  2287. val = lp->a.read_csr(ioaddr, CSR3);
  2288. val |= 0x5f00;
  2289. lp->a.write_csr(ioaddr, CSR3, val);
  2290. mmiowb();
  2291. __netif_rx_schedule(dev, &lp->napi);
  2292. break;
  2293. }
  2294. #else
  2295. pcnet32_rx(dev, lp->napi.weight);
  2296. if (pcnet32_tx(dev)) {
  2297. /* reset the chip to clear the error condition, then restart */
  2298. lp->a.reset(ioaddr);
  2299. lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
  2300. pcnet32_restart(dev, CSR0_START);
  2301. netif_wake_queue(dev);
  2302. }
  2303. #endif
  2304. csr0 = lp->a.read_csr(ioaddr, CSR0);
  2305. }
  2306. #ifndef CONFIG_PCNET32_NAPI
  2307. /* Set interrupt enable. */
  2308. lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
  2309. #endif
  2310. if (netif_msg_intr(lp))
  2311. printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
  2312. dev->name, lp->a.read_csr(ioaddr, CSR0));
  2313. spin_unlock(&lp->lock);
  2314. return IRQ_HANDLED;
  2315. }
  2316. static int pcnet32_close(struct net_device *dev)
  2317. {
  2318. unsigned long ioaddr = dev->base_addr;
  2319. struct pcnet32_private *lp = netdev_priv(dev);
  2320. unsigned long flags;
  2321. del_timer_sync(&lp->watchdog_timer);
  2322. netif_stop_queue(dev);
  2323. #ifdef CONFIG_PCNET32_NAPI
  2324. napi_disable(&lp->napi);
  2325. #endif
  2326. spin_lock_irqsave(&lp->lock, flags);
  2327. lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
  2328. if (netif_msg_ifdown(lp))
  2329. printk(KERN_DEBUG
  2330. "%s: Shutting down ethercard, status was %2.2x.\n",
  2331. dev->name, lp->a.read_csr(ioaddr, CSR0));
  2332. /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
  2333. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
  2334. /*
  2335. * Switch back to 16bit mode to avoid problems with dumb
  2336. * DOS packet driver after a warm reboot
  2337. */
  2338. lp->a.write_bcr(ioaddr, 20, 4);
  2339. spin_unlock_irqrestore(&lp->lock, flags);
  2340. free_irq(dev->irq, dev);
  2341. spin_lock_irqsave(&lp->lock, flags);
  2342. pcnet32_purge_rx_ring(dev);
  2343. pcnet32_purge_tx_ring(dev);
  2344. spin_unlock_irqrestore(&lp->lock, flags);
  2345. return 0;
  2346. }
  2347. static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
  2348. {
  2349. struct pcnet32_private *lp = netdev_priv(dev);
  2350. unsigned long ioaddr = dev->base_addr;
  2351. unsigned long flags;
  2352. spin_lock_irqsave(&lp->lock, flags);
  2353. lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
  2354. spin_unlock_irqrestore(&lp->lock, flags);
  2355. return &lp->stats;
  2356. }
  2357. /* taken from the sunlance driver, which it took from the depca driver */
  2358. static void pcnet32_load_multicast(struct net_device *dev)
  2359. {
  2360. struct pcnet32_private *lp = netdev_priv(dev);
  2361. volatile struct pcnet32_init_block *ib = lp->init_block;
  2362. volatile u16 *mcast_table = (u16 *) & ib->filter;
  2363. struct dev_mc_list *dmi = dev->mc_list;
  2364. unsigned long ioaddr = dev->base_addr;
  2365. char *addrs;
  2366. int i;
  2367. u32 crc;
  2368. /* set all multicast bits */
  2369. if (dev->flags & IFF_ALLMULTI) {
  2370. ib->filter[0] = 0xffffffff;
  2371. ib->filter[1] = 0xffffffff;
  2372. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
  2373. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
  2374. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
  2375. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
  2376. return;
  2377. }
  2378. /* clear the multicast filter */
  2379. ib->filter[0] = 0;
  2380. ib->filter[1] = 0;
  2381. /* Add addresses */
  2382. for (i = 0; i < dev->mc_count; i++) {
  2383. addrs = dmi->dmi_addr;
  2384. dmi = dmi->next;
  2385. /* multicast address? */
  2386. if (!(*addrs & 1))
  2387. continue;
  2388. crc = ether_crc_le(6, addrs);
  2389. crc = crc >> 26;
  2390. mcast_table[crc >> 4] =
  2391. le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
  2392. (1 << (crc & 0xf)));
  2393. }
  2394. for (i = 0; i < 4; i++)
  2395. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
  2396. le16_to_cpu(mcast_table[i]));
  2397. return;
  2398. }
  2399. /*
  2400. * Set or clear the multicast filter for this adaptor.
  2401. */
  2402. static void pcnet32_set_multicast_list(struct net_device *dev)
  2403. {
  2404. unsigned long ioaddr = dev->base_addr, flags;
  2405. struct pcnet32_private *lp = netdev_priv(dev);
  2406. int csr15, suspended;
  2407. spin_lock_irqsave(&lp->lock, flags);
  2408. suspended = pcnet32_suspend(dev, &flags, 0);
  2409. csr15 = lp->a.read_csr(ioaddr, CSR15);
  2410. if (dev->flags & IFF_PROMISC) {
  2411. /* Log any net taps. */
  2412. if (netif_msg_hw(lp))
  2413. printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
  2414. dev->name);
  2415. lp->init_block->mode =
  2416. le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
  2417. 7);
  2418. lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
  2419. } else {
  2420. lp->init_block->mode =
  2421. le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
  2422. lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
  2423. pcnet32_load_multicast(dev);
  2424. }
  2425. if (suspended) {
  2426. int csr5;
  2427. /* clear SUSPEND (SPND) - CSR5 bit 0 */
  2428. csr5 = lp->a.read_csr(ioaddr, CSR5);
  2429. lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
  2430. } else {
  2431. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
  2432. pcnet32_restart(dev, CSR0_NORMAL);
  2433. netif_wake_queue(dev);
  2434. }
  2435. spin_unlock_irqrestore(&lp->lock, flags);
  2436. }
  2437. /* This routine assumes that the lp->lock is held */
  2438. static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
  2439. {
  2440. struct pcnet32_private *lp = netdev_priv(dev);
  2441. unsigned long ioaddr = dev->base_addr;
  2442. u16 val_out;
  2443. if (!lp->mii)
  2444. return 0;
  2445. lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
  2446. val_out = lp->a.read_bcr(ioaddr, 34);
  2447. return val_out;
  2448. }
  2449. /* This routine assumes that the lp->lock is held */
  2450. static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
  2451. {
  2452. struct pcnet32_private *lp = netdev_priv(dev);
  2453. unsigned long ioaddr = dev->base_addr;
  2454. if (!lp->mii)
  2455. return;
  2456. lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
  2457. lp->a.write_bcr(ioaddr, 34, val);
  2458. }
  2459. static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  2460. {
  2461. struct pcnet32_private *lp = netdev_priv(dev);
  2462. int rc;
  2463. unsigned long flags;
  2464. /* SIOC[GS]MIIxxx ioctls */
  2465. if (lp->mii) {
  2466. spin_lock_irqsave(&lp->lock, flags);
  2467. rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
  2468. spin_unlock_irqrestore(&lp->lock, flags);
  2469. } else {
  2470. rc = -EOPNOTSUPP;
  2471. }
  2472. return rc;
  2473. }
  2474. static int pcnet32_check_otherphy(struct net_device *dev)
  2475. {
  2476. struct pcnet32_private *lp = netdev_priv(dev);
  2477. struct mii_if_info mii = lp->mii_if;
  2478. u16 bmcr;
  2479. int i;
  2480. for (i = 0; i < PCNET32_MAX_PHYS; i++) {
  2481. if (i == lp->mii_if.phy_id)
  2482. continue; /* skip active phy */
  2483. if (lp->phymask & (1 << i)) {
  2484. mii.phy_id = i;
  2485. if (mii_link_ok(&mii)) {
  2486. /* found PHY with active link */
  2487. if (netif_msg_link(lp))
  2488. printk(KERN_INFO
  2489. "%s: Using PHY number %d.\n",
  2490. dev->name, i);
  2491. /* isolate inactive phy */
  2492. bmcr =
  2493. mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
  2494. mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
  2495. bmcr | BMCR_ISOLATE);
  2496. /* de-isolate new phy */
  2497. bmcr = mdio_read(dev, i, MII_BMCR);
  2498. mdio_write(dev, i, MII_BMCR,
  2499. bmcr & ~BMCR_ISOLATE);
  2500. /* set new phy address */
  2501. lp->mii_if.phy_id = i;
  2502. return 1;
  2503. }
  2504. }
  2505. }
  2506. return 0;
  2507. }
  2508. /*
  2509. * Show the status of the media. Similar to mii_check_media however it
  2510. * correctly shows the link speed for all (tested) pcnet32 variants.
  2511. * Devices with no mii just report link state without speed.
  2512. *
  2513. * Caller is assumed to hold and release the lp->lock.
  2514. */
  2515. static void pcnet32_check_media(struct net_device *dev, int verbose)
  2516. {
  2517. struct pcnet32_private *lp = netdev_priv(dev);
  2518. int curr_link;
  2519. int prev_link = netif_carrier_ok(dev) ? 1 : 0;
  2520. u32 bcr9;
  2521. if (lp->mii) {
  2522. curr_link = mii_link_ok(&lp->mii_if);
  2523. } else {
  2524. ulong ioaddr = dev->base_addr; /* card base I/O address */
  2525. curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
  2526. }
  2527. if (!curr_link) {
  2528. if (prev_link || verbose) {
  2529. netif_carrier_off(dev);
  2530. if (netif_msg_link(lp))
  2531. printk(KERN_INFO "%s: link down\n", dev->name);
  2532. }
  2533. if (lp->phycount > 1) {
  2534. curr_link = pcnet32_check_otherphy(dev);
  2535. prev_link = 0;
  2536. }
  2537. } else if (verbose || !prev_link) {
  2538. netif_carrier_on(dev);
  2539. if (lp->mii) {
  2540. if (netif_msg_link(lp)) {
  2541. struct ethtool_cmd ecmd;
  2542. mii_ethtool_gset(&lp->mii_if, &ecmd);
  2543. printk(KERN_INFO
  2544. "%s: link up, %sMbps, %s-duplex\n",
  2545. dev->name,
  2546. (ecmd.speed == SPEED_100) ? "100" : "10",
  2547. (ecmd.duplex ==
  2548. DUPLEX_FULL) ? "full" : "half");
  2549. }
  2550. bcr9 = lp->a.read_bcr(dev->base_addr, 9);
  2551. if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
  2552. if (lp->mii_if.full_duplex)
  2553. bcr9 |= (1 << 0);
  2554. else
  2555. bcr9 &= ~(1 << 0);
  2556. lp->a.write_bcr(dev->base_addr, 9, bcr9);
  2557. }
  2558. } else {
  2559. if (netif_msg_link(lp))
  2560. printk(KERN_INFO "%s: link up\n", dev->name);
  2561. }
  2562. }
  2563. }
  2564. /*
  2565. * Check for loss of link and link establishment.
  2566. * Can not use mii_check_media because it does nothing if mode is forced.
  2567. */
  2568. static void pcnet32_watchdog(struct net_device *dev)
  2569. {
  2570. struct pcnet32_private *lp = netdev_priv(dev);
  2571. unsigned long flags;
  2572. /* Print the link status if it has changed */
  2573. spin_lock_irqsave(&lp->lock, flags);
  2574. pcnet32_check_media(dev, 0);
  2575. spin_unlock_irqrestore(&lp->lock, flags);
  2576. mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
  2577. }
  2578. static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
  2579. {
  2580. struct net_device *dev = pci_get_drvdata(pdev);
  2581. if (netif_running(dev)) {
  2582. netif_device_detach(dev);
  2583. pcnet32_close(dev);
  2584. }
  2585. pci_save_state(pdev);
  2586. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2587. return 0;
  2588. }
  2589. static int pcnet32_pm_resume(struct pci_dev *pdev)
  2590. {
  2591. struct net_device *dev = pci_get_drvdata(pdev);
  2592. pci_set_power_state(pdev, PCI_D0);
  2593. pci_restore_state(pdev);
  2594. if (netif_running(dev)) {
  2595. pcnet32_open(dev);
  2596. netif_device_attach(dev);
  2597. }
  2598. return 0;
  2599. }
  2600. static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
  2601. {
  2602. struct net_device *dev = pci_get_drvdata(pdev);
  2603. if (dev) {
  2604. struct pcnet32_private *lp = netdev_priv(dev);
  2605. unregister_netdev(dev);
  2606. pcnet32_free_ring(dev);
  2607. release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
  2608. pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
  2609. lp->init_block, lp->init_dma_addr);
  2610. free_netdev(dev);
  2611. pci_disable_device(pdev);
  2612. pci_set_drvdata(pdev, NULL);
  2613. }
  2614. }
  2615. static struct pci_driver pcnet32_driver = {
  2616. .name = DRV_NAME,
  2617. .probe = pcnet32_probe_pci,
  2618. .remove = __devexit_p(pcnet32_remove_one),
  2619. .id_table = pcnet32_pci_tbl,
  2620. .suspend = pcnet32_pm_suspend,
  2621. .resume = pcnet32_pm_resume,
  2622. };
  2623. /* An additional parameter that may be passed in... */
  2624. static int debug = -1;
  2625. static int tx_start_pt = -1;
  2626. static int pcnet32_have_pci;
  2627. module_param(debug, int, 0);
  2628. MODULE_PARM_DESC(debug, DRV_NAME " debug level");
  2629. module_param(max_interrupt_work, int, 0);
  2630. MODULE_PARM_DESC(max_interrupt_work,
  2631. DRV_NAME " maximum events handled per interrupt");
  2632. module_param(rx_copybreak, int, 0);
  2633. MODULE_PARM_DESC(rx_copybreak,
  2634. DRV_NAME " copy breakpoint for copy-only-tiny-frames");
  2635. module_param(tx_start_pt, int, 0);
  2636. MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
  2637. module_param(pcnet32vlb, int, 0);
  2638. MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
  2639. module_param_array(options, int, NULL, 0);
  2640. MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
  2641. module_param_array(full_duplex, int, NULL, 0);
  2642. MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
  2643. /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
  2644. module_param_array(homepna, int, NULL, 0);
  2645. MODULE_PARM_DESC(homepna,
  2646. DRV_NAME
  2647. " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
  2648. MODULE_AUTHOR("Thomas Bogendoerfer");
  2649. MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
  2650. MODULE_LICENSE("GPL");
  2651. #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  2652. static int __init pcnet32_init_module(void)
  2653. {
  2654. printk(KERN_INFO "%s", version);
  2655. pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
  2656. if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
  2657. tx_start = tx_start_pt;
  2658. /* find the PCI devices */
  2659. if (!pci_register_driver(&pcnet32_driver))
  2660. pcnet32_have_pci = 1;
  2661. /* should we find any remaining VLbus devices ? */
  2662. if (pcnet32vlb)
  2663. pcnet32_probe_vlbus(pcnet32_portlist);
  2664. if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
  2665. printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
  2666. return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
  2667. }
  2668. static void __exit pcnet32_cleanup_module(void)
  2669. {
  2670. struct net_device *next_dev;
  2671. while (pcnet32_dev) {
  2672. struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
  2673. next_dev = lp->next;
  2674. unregister_netdev(pcnet32_dev);
  2675. pcnet32_free_ring(pcnet32_dev);
  2676. release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
  2677. pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
  2678. lp->init_block, lp->init_dma_addr);
  2679. free_netdev(pcnet32_dev);
  2680. pcnet32_dev = next_dev;
  2681. }
  2682. if (pcnet32_have_pci)
  2683. pci_unregister_driver(&pcnet32_driver);
  2684. }
  2685. module_init(pcnet32_init_module);
  2686. module_exit(pcnet32_cleanup_module);
  2687. /*
  2688. * Local variables:
  2689. * c-indent-level: 4
  2690. * tab-width: 8
  2691. * End:
  2692. */