mv_sas.c 60 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
  7. *
  8. * This file is licensed under GPLv2.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; version 2 of the
  13. * License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23. * USA
  24. */
  25. #include "mv_sas.h"
  26. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  27. {
  28. if (task->lldd_task) {
  29. struct mvs_slot_info *slot;
  30. slot = task->lldd_task;
  31. *tag = slot->slot_tag;
  32. return 1;
  33. }
  34. return 0;
  35. }
  36. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  37. {
  38. void *bitmap = &mvi->tags;
  39. clear_bit(tag, bitmap);
  40. }
  41. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  42. {
  43. mvs_tag_clear(mvi, tag);
  44. }
  45. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  46. {
  47. void *bitmap = &mvi->tags;
  48. set_bit(tag, bitmap);
  49. }
  50. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  51. {
  52. unsigned int index, tag;
  53. void *bitmap = &mvi->tags;
  54. index = find_first_zero_bit(bitmap, mvi->tags_num);
  55. tag = index;
  56. if (tag >= mvi->tags_num)
  57. return -SAS_QUEUE_FULL;
  58. mvs_tag_set(mvi, tag);
  59. *tag_out = tag;
  60. return 0;
  61. }
  62. void mvs_tag_init(struct mvs_info *mvi)
  63. {
  64. int i;
  65. for (i = 0; i < mvi->tags_num; ++i)
  66. mvs_tag_clear(mvi, i);
  67. }
  68. void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
  69. {
  70. u32 i;
  71. u32 run;
  72. u32 offset;
  73. offset = 0;
  74. while (size) {
  75. printk(KERN_DEBUG"%08X : ", baseaddr + offset);
  76. if (size >= 16)
  77. run = 16;
  78. else
  79. run = size;
  80. size -= run;
  81. for (i = 0; i < 16; i++) {
  82. if (i < run)
  83. printk(KERN_DEBUG"%02X ", (u32)data[i]);
  84. else
  85. printk(KERN_DEBUG" ");
  86. }
  87. printk(KERN_DEBUG": ");
  88. for (i = 0; i < run; i++)
  89. printk(KERN_DEBUG"%c",
  90. isalnum(data[i]) ? data[i] : '.');
  91. printk(KERN_DEBUG"\n");
  92. data = &data[16];
  93. offset += run;
  94. }
  95. printk(KERN_DEBUG"\n");
  96. }
  97. #if (_MV_DUMP > 1)
  98. static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
  99. enum sas_protocol proto)
  100. {
  101. u32 offset;
  102. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  103. offset = slot->cmd_size + MVS_OAF_SZ +
  104. MVS_CHIP_DISP->prd_size() * slot->n_elem;
  105. dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
  106. tag);
  107. mvs_hexdump(32, (u8 *) slot->response,
  108. (u32) slot->buf_dma + offset);
  109. }
  110. #endif
  111. static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
  112. enum sas_protocol proto)
  113. {
  114. #if (_MV_DUMP > 1)
  115. u32 sz, w_ptr;
  116. u64 addr;
  117. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  118. /*Delivery Queue */
  119. sz = MVS_CHIP_SLOT_SZ;
  120. w_ptr = slot->tx;
  121. addr = mvi->tx_dma;
  122. dev_printk(KERN_DEBUG, mvi->dev,
  123. "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
  124. dev_printk(KERN_DEBUG, mvi->dev,
  125. "Delivery Queue Base Address=0x%llX (PA)"
  126. "(tx_dma=0x%llX), Entry=%04d\n",
  127. addr, (unsigned long long)mvi->tx_dma, w_ptr);
  128. mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
  129. (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
  130. /*Command List */
  131. addr = mvi->slot_dma;
  132. dev_printk(KERN_DEBUG, mvi->dev,
  133. "Command List Base Address=0x%llX (PA)"
  134. "(slot_dma=0x%llX), Header=%03d\n",
  135. addr, (unsigned long long)slot->buf_dma, tag);
  136. dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
  137. /*mvs_cmd_hdr */
  138. mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
  139. (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
  140. /*1.command table area */
  141. dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
  142. mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
  143. /*2.open address frame area */
  144. dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
  145. mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
  146. (u32) slot->buf_dma + slot->cmd_size);
  147. /*3.status buffer */
  148. mvs_hba_sb_dump(mvi, tag, proto);
  149. /*4.PRD table */
  150. dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
  151. mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
  152. (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
  153. (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
  154. #endif
  155. }
  156. static void mvs_hba_cq_dump(struct mvs_info *mvi)
  157. {
  158. #if (_MV_DUMP > 2)
  159. u64 addr;
  160. void __iomem *regs = mvi->regs;
  161. u32 entry = mvi->rx_cons + 1;
  162. u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
  163. /*Completion Queue */
  164. addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
  165. dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
  166. mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
  167. dev_printk(KERN_DEBUG, mvi->dev,
  168. "Completion List Base Address=0x%llX (PA), "
  169. "CQ_Entry=%04d, CQ_WP=0x%08X\n",
  170. addr, entry - 1, mvi->rx[0]);
  171. mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
  172. mvi->rx_dma + sizeof(u32) * entry);
  173. #endif
  174. }
  175. void mvs_get_sas_addr(void *buf, u32 buflen)
  176. {
  177. /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
  178. }
  179. struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  180. {
  181. unsigned long i = 0, j = 0, hi = 0;
  182. struct sas_ha_struct *sha = dev->port->ha;
  183. struct mvs_info *mvi = NULL;
  184. struct asd_sas_phy *phy;
  185. while (sha->sas_port[i]) {
  186. if (sha->sas_port[i] == dev->port) {
  187. phy = container_of(sha->sas_port[i]->phy_list.next,
  188. struct asd_sas_phy, port_phy_el);
  189. j = 0;
  190. while (sha->sas_phy[j]) {
  191. if (sha->sas_phy[j] == phy)
  192. break;
  193. j++;
  194. }
  195. break;
  196. }
  197. i++;
  198. }
  199. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  200. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  201. return mvi;
  202. }
  203. /* FIXME */
  204. int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  205. {
  206. unsigned long i = 0, j = 0, n = 0, num = 0;
  207. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  208. struct mvs_info *mvi = mvi_dev->mvi_info;
  209. struct sas_ha_struct *sha = dev->port->ha;
  210. while (sha->sas_port[i]) {
  211. if (sha->sas_port[i] == dev->port) {
  212. struct asd_sas_phy *phy;
  213. list_for_each_entry(phy,
  214. &sha->sas_port[i]->phy_list, port_phy_el) {
  215. j = 0;
  216. while (sha->sas_phy[j]) {
  217. if (sha->sas_phy[j] == phy)
  218. break;
  219. j++;
  220. }
  221. phyno[n] = (j >= mvi->chip->n_phy) ?
  222. (j - mvi->chip->n_phy) : j;
  223. num++;
  224. n++;
  225. }
  226. break;
  227. }
  228. i++;
  229. }
  230. return num;
  231. }
  232. struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
  233. u8 reg_set)
  234. {
  235. u32 dev_no;
  236. for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
  237. if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
  238. continue;
  239. if (mvi->devices[dev_no].taskfileset == reg_set)
  240. return &mvi->devices[dev_no];
  241. }
  242. return NULL;
  243. }
  244. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  245. struct mvs_device *dev)
  246. {
  247. if (!dev) {
  248. mv_printk("device has been free.\n");
  249. return;
  250. }
  251. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  252. return;
  253. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  254. }
  255. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  256. struct mvs_device *dev)
  257. {
  258. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  259. return 0;
  260. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  261. }
  262. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  263. {
  264. u32 no;
  265. for_each_phy(phy_mask, phy_mask, no) {
  266. if (!(phy_mask & 1))
  267. continue;
  268. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  269. }
  270. }
  271. /* FIXME: locking? */
  272. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  273. void *funcdata)
  274. {
  275. int rc = 0, phy_id = sas_phy->id;
  276. u32 tmp, i = 0, hi;
  277. struct sas_ha_struct *sha = sas_phy->ha;
  278. struct mvs_info *mvi = NULL;
  279. while (sha->sas_phy[i]) {
  280. if (sha->sas_phy[i] == sas_phy)
  281. break;
  282. i++;
  283. }
  284. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  285. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  286. switch (func) {
  287. case PHY_FUNC_SET_LINK_RATE:
  288. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  289. break;
  290. case PHY_FUNC_HARD_RESET:
  291. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  292. if (tmp & PHY_RST_HARD)
  293. break;
  294. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
  295. break;
  296. case PHY_FUNC_LINK_RESET:
  297. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  298. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
  299. break;
  300. case PHY_FUNC_DISABLE:
  301. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  302. break;
  303. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  304. default:
  305. rc = -EOPNOTSUPP;
  306. }
  307. msleep(200);
  308. return rc;
  309. }
  310. void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
  311. u32 off_lo, u32 off_hi, u64 sas_addr)
  312. {
  313. u32 lo = (u32)sas_addr;
  314. u32 hi = (u32)(sas_addr>>32);
  315. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  316. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  317. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  318. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  319. }
  320. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  321. {
  322. struct mvs_phy *phy = &mvi->phy[i];
  323. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  324. struct sas_ha_struct *sas_ha;
  325. if (!phy->phy_attached)
  326. return;
  327. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  328. && phy->phy_type & PORT_TYPE_SAS) {
  329. return;
  330. }
  331. sas_ha = mvi->sas;
  332. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  333. if (sas_phy->phy) {
  334. struct sas_phy *sphy = sas_phy->phy;
  335. sphy->negotiated_linkrate = sas_phy->linkrate;
  336. sphy->minimum_linkrate = phy->minimum_linkrate;
  337. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  338. sphy->maximum_linkrate = phy->maximum_linkrate;
  339. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  340. }
  341. if (phy->phy_type & PORT_TYPE_SAS) {
  342. struct sas_identify_frame *id;
  343. id = (struct sas_identify_frame *)phy->frame_rcvd;
  344. id->dev_type = phy->identify.device_type;
  345. id->initiator_bits = SAS_PROTOCOL_ALL;
  346. id->target_bits = phy->identify.target_port_protocols;
  347. } else if (phy->phy_type & PORT_TYPE_SATA) {
  348. /*Nothing*/
  349. }
  350. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  351. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  352. mvi->sas->notify_port_event(sas_phy,
  353. PORTE_BYTES_DMAED);
  354. }
  355. int mvs_slave_alloc(struct scsi_device *scsi_dev)
  356. {
  357. struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
  358. if (dev_is_sata(dev)) {
  359. /* We don't need to rescan targets
  360. * if REPORT_LUNS request is failed
  361. */
  362. if (scsi_dev->lun > 0)
  363. return -ENXIO;
  364. scsi_dev->tagged_supported = 1;
  365. }
  366. return sas_slave_alloc(scsi_dev);
  367. }
  368. int mvs_slave_configure(struct scsi_device *sdev)
  369. {
  370. struct domain_device *dev = sdev_to_domain_dev(sdev);
  371. int ret = sas_slave_configure(sdev);
  372. if (ret)
  373. return ret;
  374. if (dev_is_sata(dev)) {
  375. /* may set PIO mode */
  376. #if MV_DISABLE_NCQ
  377. struct ata_port *ap = dev->sata_dev.ap;
  378. struct ata_device *adev = ap->link.device;
  379. adev->flags |= ATA_DFLAG_NCQ_OFF;
  380. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
  381. #endif
  382. }
  383. return 0;
  384. }
  385. void mvs_scan_start(struct Scsi_Host *shost)
  386. {
  387. int i, j;
  388. unsigned short core_nr;
  389. struct mvs_info *mvi;
  390. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  391. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  392. for (j = 0; j < core_nr; j++) {
  393. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  394. for (i = 0; i < mvi->chip->n_phy; ++i)
  395. mvs_bytes_dmaed(mvi, i);
  396. }
  397. }
  398. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  399. {
  400. /* give the phy enabling interrupt event time to come in (1s
  401. * is empirically about all it takes) */
  402. if (time < HZ)
  403. return 0;
  404. /* Wait for discovery to finish */
  405. scsi_flush_work(shost);
  406. return 1;
  407. }
  408. static int mvs_task_prep_smp(struct mvs_info *mvi,
  409. struct mvs_task_exec_info *tei)
  410. {
  411. int elem, rc, i;
  412. struct sas_task *task = tei->task;
  413. struct mvs_cmd_hdr *hdr = tei->hdr;
  414. struct domain_device *dev = task->dev;
  415. struct asd_sas_port *sas_port = dev->port;
  416. struct scatterlist *sg_req, *sg_resp;
  417. u32 req_len, resp_len, tag = tei->tag;
  418. void *buf_tmp;
  419. u8 *buf_oaf;
  420. dma_addr_t buf_tmp_dma;
  421. void *buf_prd;
  422. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  423. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  424. #if _MV_DUMP
  425. u8 *buf_cmd;
  426. void *from;
  427. #endif
  428. /*
  429. * DMA-map SMP request, response buffers
  430. */
  431. sg_req = &task->smp_task.smp_req;
  432. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  433. if (!elem)
  434. return -ENOMEM;
  435. req_len = sg_dma_len(sg_req);
  436. sg_resp = &task->smp_task.smp_resp;
  437. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  438. if (!elem) {
  439. rc = -ENOMEM;
  440. goto err_out;
  441. }
  442. resp_len = SB_RFB_MAX;
  443. /* must be in dwords */
  444. if ((req_len & 0x3) || (resp_len & 0x3)) {
  445. rc = -EINVAL;
  446. goto err_out_2;
  447. }
  448. /*
  449. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  450. */
  451. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  452. buf_tmp = slot->buf;
  453. buf_tmp_dma = slot->buf_dma;
  454. #if _MV_DUMP
  455. buf_cmd = buf_tmp;
  456. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  457. buf_tmp += req_len;
  458. buf_tmp_dma += req_len;
  459. slot->cmd_size = req_len;
  460. #else
  461. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  462. #endif
  463. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  464. buf_oaf = buf_tmp;
  465. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  466. buf_tmp += MVS_OAF_SZ;
  467. buf_tmp_dma += MVS_OAF_SZ;
  468. /* region 3: PRD table *********************************** */
  469. buf_prd = buf_tmp;
  470. if (tei->n_elem)
  471. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  472. else
  473. hdr->prd_tbl = 0;
  474. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  475. buf_tmp += i;
  476. buf_tmp_dma += i;
  477. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  478. slot->response = buf_tmp;
  479. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  480. if (mvi->flags & MVF_FLAG_SOC)
  481. hdr->reserved[0] = 0;
  482. /*
  483. * Fill in TX ring and command slot header
  484. */
  485. slot->tx = mvi->tx_prod;
  486. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  487. TXQ_MODE_I | tag |
  488. (sas_port->phy_mask << TXQ_PHY_SHIFT));
  489. hdr->flags |= flags;
  490. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  491. hdr->tags = cpu_to_le32(tag);
  492. hdr->data_len = 0;
  493. /* generate open address frame hdr (first 12 bytes) */
  494. /* initiator, SMP, ftype 1h */
  495. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  496. buf_oaf[1] = dev->linkrate & 0xf;
  497. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  498. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  499. /* fill in PRD (scatter/gather) table, if any */
  500. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  501. #if _MV_DUMP
  502. /* copy cmd table */
  503. from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
  504. memcpy(buf_cmd, from + sg_req->offset, req_len);
  505. kunmap_atomic(from, KM_IRQ0);
  506. #endif
  507. return 0;
  508. err_out_2:
  509. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  510. PCI_DMA_FROMDEVICE);
  511. err_out:
  512. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  513. PCI_DMA_TODEVICE);
  514. return rc;
  515. }
  516. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  517. {
  518. struct ata_queued_cmd *qc = task->uldd_task;
  519. if (qc) {
  520. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  521. qc->tf.command == ATA_CMD_FPDMA_READ) {
  522. *tag = qc->tag;
  523. return 1;
  524. }
  525. }
  526. return 0;
  527. }
  528. static int mvs_task_prep_ata(struct mvs_info *mvi,
  529. struct mvs_task_exec_info *tei)
  530. {
  531. struct sas_task *task = tei->task;
  532. struct domain_device *dev = task->dev;
  533. struct mvs_device *mvi_dev = dev->lldd_dev;
  534. struct mvs_cmd_hdr *hdr = tei->hdr;
  535. struct asd_sas_port *sas_port = dev->port;
  536. struct mvs_slot_info *slot;
  537. void *buf_prd;
  538. u32 tag = tei->tag, hdr_tag;
  539. u32 flags, del_q;
  540. void *buf_tmp;
  541. u8 *buf_cmd, *buf_oaf;
  542. dma_addr_t buf_tmp_dma;
  543. u32 i, req_len, resp_len;
  544. const u32 max_resp_len = SB_RFB_MAX;
  545. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  546. mv_dprintk("Have not enough regiset for dev %d.\n",
  547. mvi_dev->device_id);
  548. return -EBUSY;
  549. }
  550. slot = &mvi->slot_info[tag];
  551. slot->tx = mvi->tx_prod;
  552. del_q = TXQ_MODE_I | tag |
  553. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  554. (sas_port->phy_mask << TXQ_PHY_SHIFT) |
  555. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  556. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  557. if (task->data_dir == DMA_FROM_DEVICE)
  558. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  559. else
  560. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  561. if (task->ata_task.use_ncq)
  562. flags |= MCH_FPDMA;
  563. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
  564. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  565. flags |= MCH_ATAPI;
  566. }
  567. /* FIXME: fill in port multiplier number */
  568. hdr->flags = cpu_to_le32(flags);
  569. /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
  570. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  571. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  572. else
  573. hdr_tag = tag;
  574. hdr->tags = cpu_to_le32(hdr_tag);
  575. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  576. /*
  577. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  578. */
  579. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  580. buf_cmd = buf_tmp = slot->buf;
  581. buf_tmp_dma = slot->buf_dma;
  582. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  583. buf_tmp += MVS_ATA_CMD_SZ;
  584. buf_tmp_dma += MVS_ATA_CMD_SZ;
  585. #if _MV_DUMP
  586. slot->cmd_size = MVS_ATA_CMD_SZ;
  587. #endif
  588. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  589. /* used for STP. unused for SATA? */
  590. buf_oaf = buf_tmp;
  591. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  592. buf_tmp += MVS_OAF_SZ;
  593. buf_tmp_dma += MVS_OAF_SZ;
  594. /* region 3: PRD table ********************************************* */
  595. buf_prd = buf_tmp;
  596. if (tei->n_elem)
  597. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  598. else
  599. hdr->prd_tbl = 0;
  600. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  601. buf_tmp += i;
  602. buf_tmp_dma += i;
  603. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  604. /* FIXME: probably unused, for SATA. kept here just in case
  605. * we get a STP/SATA error information record
  606. */
  607. slot->response = buf_tmp;
  608. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  609. if (mvi->flags & MVF_FLAG_SOC)
  610. hdr->reserved[0] = 0;
  611. req_len = sizeof(struct host_to_dev_fis);
  612. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  613. sizeof(struct mvs_err_info) - i;
  614. /* request, response lengths */
  615. resp_len = min(resp_len, max_resp_len);
  616. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  617. if (likely(!task->ata_task.device_control_reg_update))
  618. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  619. /* fill in command FIS and ATAPI CDB */
  620. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  621. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
  622. memcpy(buf_cmd + STP_ATAPI_CMD,
  623. task->ata_task.atapi_packet, 16);
  624. /* generate open address frame hdr (first 12 bytes) */
  625. /* initiator, STP, ftype 1h */
  626. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  627. buf_oaf[1] = dev->linkrate & 0xf;
  628. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  629. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  630. /* fill in PRD (scatter/gather) table, if any */
  631. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  632. if (task->data_dir == DMA_FROM_DEVICE)
  633. MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
  634. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  635. return 0;
  636. }
  637. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  638. struct mvs_task_exec_info *tei, int is_tmf,
  639. struct mvs_tmf_task *tmf)
  640. {
  641. struct sas_task *task = tei->task;
  642. struct mvs_cmd_hdr *hdr = tei->hdr;
  643. struct mvs_port *port = tei->port;
  644. struct domain_device *dev = task->dev;
  645. struct mvs_device *mvi_dev = dev->lldd_dev;
  646. struct asd_sas_port *sas_port = dev->port;
  647. struct mvs_slot_info *slot;
  648. void *buf_prd;
  649. struct ssp_frame_hdr *ssp_hdr;
  650. void *buf_tmp;
  651. u8 *buf_cmd, *buf_oaf, fburst = 0;
  652. dma_addr_t buf_tmp_dma;
  653. u32 flags;
  654. u32 resp_len, req_len, i, tag = tei->tag;
  655. const u32 max_resp_len = SB_RFB_MAX;
  656. u32 phy_mask;
  657. slot = &mvi->slot_info[tag];
  658. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  659. sas_port->phy_mask) & TXQ_PHY_MASK;
  660. slot->tx = mvi->tx_prod;
  661. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  662. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  663. (phy_mask << TXQ_PHY_SHIFT));
  664. flags = MCH_RETRY;
  665. if (task->ssp_task.enable_first_burst) {
  666. flags |= MCH_FBURST;
  667. fburst = (1 << 7);
  668. }
  669. if (is_tmf)
  670. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  671. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  672. hdr->tags = cpu_to_le32(tag);
  673. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  674. /*
  675. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  676. */
  677. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  678. buf_cmd = buf_tmp = slot->buf;
  679. buf_tmp_dma = slot->buf_dma;
  680. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  681. buf_tmp += MVS_SSP_CMD_SZ;
  682. buf_tmp_dma += MVS_SSP_CMD_SZ;
  683. #if _MV_DUMP
  684. slot->cmd_size = MVS_SSP_CMD_SZ;
  685. #endif
  686. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  687. buf_oaf = buf_tmp;
  688. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  689. buf_tmp += MVS_OAF_SZ;
  690. buf_tmp_dma += MVS_OAF_SZ;
  691. /* region 3: PRD table ********************************************* */
  692. buf_prd = buf_tmp;
  693. if (tei->n_elem)
  694. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  695. else
  696. hdr->prd_tbl = 0;
  697. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  698. buf_tmp += i;
  699. buf_tmp_dma += i;
  700. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  701. slot->response = buf_tmp;
  702. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  703. if (mvi->flags & MVF_FLAG_SOC)
  704. hdr->reserved[0] = 0;
  705. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  706. sizeof(struct mvs_err_info) - i;
  707. resp_len = min(resp_len, max_resp_len);
  708. req_len = sizeof(struct ssp_frame_hdr) + 28;
  709. /* request, response lengths */
  710. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  711. /* generate open address frame hdr (first 12 bytes) */
  712. /* initiator, SSP, ftype 1h */
  713. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  714. buf_oaf[1] = dev->linkrate & 0xf;
  715. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  716. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  717. /* fill in SSP frame header (Command Table.SSP frame header) */
  718. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  719. if (is_tmf)
  720. ssp_hdr->frame_type = SSP_TASK;
  721. else
  722. ssp_hdr->frame_type = SSP_COMMAND;
  723. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  724. HASHED_SAS_ADDR_SIZE);
  725. memcpy(ssp_hdr->hashed_src_addr,
  726. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  727. ssp_hdr->tag = cpu_to_be16(tag);
  728. /* fill in IU for TASK and Command Frame */
  729. buf_cmd += sizeof(*ssp_hdr);
  730. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  731. if (ssp_hdr->frame_type != SSP_TASK) {
  732. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  733. (task->ssp_task.task_prio << 3);
  734. memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
  735. } else{
  736. buf_cmd[10] = tmf->tmf;
  737. switch (tmf->tmf) {
  738. case TMF_ABORT_TASK:
  739. case TMF_QUERY_TASK:
  740. buf_cmd[12] =
  741. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  742. buf_cmd[13] =
  743. tmf->tag_of_task_to_be_managed & 0xff;
  744. break;
  745. default:
  746. break;
  747. }
  748. }
  749. /* fill in PRD (scatter/gather) table, if any */
  750. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  751. return 0;
  752. }
  753. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
  754. static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
  755. struct mvs_tmf_task *tmf, int *pass)
  756. {
  757. struct domain_device *dev = task->dev;
  758. struct mvs_device *mvi_dev = dev->lldd_dev;
  759. struct mvs_task_exec_info tei;
  760. struct mvs_slot_info *slot;
  761. u32 tag = 0xdeadbeef, n_elem = 0;
  762. int rc = 0;
  763. if (!dev->port) {
  764. struct task_status_struct *tsm = &task->task_status;
  765. tsm->resp = SAS_TASK_UNDELIVERED;
  766. tsm->stat = SAS_PHY_DOWN;
  767. /*
  768. * libsas will use dev->port, should
  769. * not call task_done for sata
  770. */
  771. if (dev->dev_type != SATA_DEV)
  772. task->task_done(task);
  773. return rc;
  774. }
  775. if (DEV_IS_GONE(mvi_dev)) {
  776. if (mvi_dev)
  777. mv_dprintk("device %d not ready.\n",
  778. mvi_dev->device_id);
  779. else
  780. mv_dprintk("device %016llx not ready.\n",
  781. SAS_ADDR(dev->sas_addr));
  782. rc = SAS_PHY_DOWN;
  783. return rc;
  784. }
  785. tei.port = dev->port->lldd_port;
  786. if (tei.port && !tei.port->port_attached && !tmf) {
  787. if (sas_protocol_ata(task->task_proto)) {
  788. struct task_status_struct *ts = &task->task_status;
  789. mv_dprintk("SATA/STP port %d does not attach"
  790. "device.\n", dev->port->id);
  791. ts->resp = SAS_TASK_COMPLETE;
  792. ts->stat = SAS_PHY_DOWN;
  793. task->task_done(task);
  794. } else {
  795. struct task_status_struct *ts = &task->task_status;
  796. mv_dprintk("SAS port %d does not attach"
  797. "device.\n", dev->port->id);
  798. ts->resp = SAS_TASK_UNDELIVERED;
  799. ts->stat = SAS_PHY_DOWN;
  800. task->task_done(task);
  801. }
  802. return rc;
  803. }
  804. if (!sas_protocol_ata(task->task_proto)) {
  805. if (task->num_scatter) {
  806. n_elem = dma_map_sg(mvi->dev,
  807. task->scatter,
  808. task->num_scatter,
  809. task->data_dir);
  810. if (!n_elem) {
  811. rc = -ENOMEM;
  812. goto prep_out;
  813. }
  814. }
  815. } else {
  816. n_elem = task->num_scatter;
  817. }
  818. rc = mvs_tag_alloc(mvi, &tag);
  819. if (rc)
  820. goto err_out;
  821. slot = &mvi->slot_info[tag];
  822. task->lldd_task = NULL;
  823. slot->n_elem = n_elem;
  824. slot->slot_tag = tag;
  825. slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
  826. if (!slot->buf)
  827. goto err_out_tag;
  828. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  829. tei.task = task;
  830. tei.hdr = &mvi->slot[tag];
  831. tei.tag = tag;
  832. tei.n_elem = n_elem;
  833. switch (task->task_proto) {
  834. case SAS_PROTOCOL_SMP:
  835. rc = mvs_task_prep_smp(mvi, &tei);
  836. break;
  837. case SAS_PROTOCOL_SSP:
  838. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  839. break;
  840. case SAS_PROTOCOL_SATA:
  841. case SAS_PROTOCOL_STP:
  842. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  843. rc = mvs_task_prep_ata(mvi, &tei);
  844. break;
  845. default:
  846. dev_printk(KERN_ERR, mvi->dev,
  847. "unknown sas_task proto: 0x%x\n",
  848. task->task_proto);
  849. rc = -EINVAL;
  850. break;
  851. }
  852. if (rc) {
  853. mv_dprintk("rc is %x\n", rc);
  854. goto err_out_slot_buf;
  855. }
  856. slot->task = task;
  857. slot->port = tei.port;
  858. task->lldd_task = slot;
  859. list_add_tail(&slot->entry, &tei.port->list);
  860. spin_lock(&task->task_state_lock);
  861. task->task_state_flags |= SAS_TASK_AT_INITIATOR;
  862. spin_unlock(&task->task_state_lock);
  863. mvs_hba_memory_dump(mvi, tag, task->task_proto);
  864. mvi_dev->running_req++;
  865. ++(*pass);
  866. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  867. return rc;
  868. err_out_slot_buf:
  869. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  870. err_out_tag:
  871. mvs_tag_free(mvi, tag);
  872. err_out:
  873. dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
  874. if (!sas_protocol_ata(task->task_proto))
  875. if (n_elem)
  876. dma_unmap_sg(mvi->dev, task->scatter, n_elem,
  877. task->data_dir);
  878. prep_out:
  879. return rc;
  880. }
  881. static struct mvs_task_list *mvs_task_alloc_list(int *num, gfp_t gfp_flags)
  882. {
  883. struct mvs_task_list *first = NULL;
  884. for (; *num > 0; --*num) {
  885. struct mvs_task_list *mvs_list = kmem_cache_zalloc(mvs_task_list_cache, gfp_flags);
  886. if (!mvs_list)
  887. break;
  888. INIT_LIST_HEAD(&mvs_list->list);
  889. if (!first)
  890. first = mvs_list;
  891. else
  892. list_add_tail(&mvs_list->list, &first->list);
  893. }
  894. return first;
  895. }
  896. static inline void mvs_task_free_list(struct mvs_task_list *mvs_list)
  897. {
  898. LIST_HEAD(list);
  899. struct list_head *pos, *a;
  900. struct mvs_task_list *mlist = NULL;
  901. __list_add(&list, mvs_list->list.prev, &mvs_list->list);
  902. list_for_each_safe(pos, a, &list) {
  903. list_del_init(pos);
  904. mlist = list_entry(pos, struct mvs_task_list, list);
  905. kmem_cache_free(mvs_task_list_cache, mlist);
  906. }
  907. }
  908. static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  909. struct completion *completion, int is_tmf,
  910. struct mvs_tmf_task *tmf)
  911. {
  912. struct domain_device *dev = task->dev;
  913. struct mvs_info *mvi = NULL;
  914. u32 rc = 0;
  915. u32 pass = 0;
  916. unsigned long flags = 0;
  917. mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
  918. if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
  919. spin_unlock_irq(dev->sata_dev.ap->lock);
  920. spin_lock_irqsave(&mvi->lock, flags);
  921. rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
  922. if (rc)
  923. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  924. if (likely(pass))
  925. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  926. (MVS_CHIP_SLOT_SZ - 1));
  927. spin_unlock_irqrestore(&mvi->lock, flags);
  928. if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
  929. spin_lock_irq(dev->sata_dev.ap->lock);
  930. return rc;
  931. }
  932. static int mvs_collector_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  933. struct completion *completion, int is_tmf,
  934. struct mvs_tmf_task *tmf)
  935. {
  936. struct domain_device *dev = task->dev;
  937. struct mvs_prv_info *mpi = dev->port->ha->lldd_ha;
  938. struct mvs_info *mvi = NULL;
  939. struct sas_task *t = task;
  940. struct mvs_task_list *mvs_list = NULL, *a;
  941. LIST_HEAD(q);
  942. int pass[2] = {0};
  943. u32 rc = 0;
  944. u32 n = num;
  945. unsigned long flags = 0;
  946. mvs_list = mvs_task_alloc_list(&n, gfp_flags);
  947. if (n) {
  948. printk(KERN_ERR "%s: mvs alloc list failed.\n", __func__);
  949. rc = -ENOMEM;
  950. goto free_list;
  951. }
  952. __list_add(&q, mvs_list->list.prev, &mvs_list->list);
  953. list_for_each_entry(a, &q, list) {
  954. a->task = t;
  955. t = list_entry(t->list.next, struct sas_task, list);
  956. }
  957. list_for_each_entry(a, &q , list) {
  958. t = a->task;
  959. mvi = ((struct mvs_device *)t->dev->lldd_dev)->mvi_info;
  960. spin_lock_irqsave(&mvi->lock, flags);
  961. rc = mvs_task_prep(t, mvi, is_tmf, tmf, &pass[mvi->id]);
  962. if (rc)
  963. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  964. spin_unlock_irqrestore(&mvi->lock, flags);
  965. }
  966. if (likely(pass[0]))
  967. MVS_CHIP_DISP->start_delivery(mpi->mvi[0],
  968. (mpi->mvi[0]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  969. if (likely(pass[1]))
  970. MVS_CHIP_DISP->start_delivery(mpi->mvi[1],
  971. (mpi->mvi[1]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  972. list_del_init(&q);
  973. free_list:
  974. if (mvs_list)
  975. mvs_task_free_list(mvs_list);
  976. return rc;
  977. }
  978. int mvs_queue_command(struct sas_task *task, const int num,
  979. gfp_t gfp_flags)
  980. {
  981. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  982. struct sas_ha_struct *sas = mvi_dev->mvi_info->sas;
  983. if (sas->lldd_max_execute_num < 2)
  984. return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  985. else
  986. return mvs_collector_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  987. }
  988. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  989. {
  990. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  991. mvs_tag_clear(mvi, slot_idx);
  992. }
  993. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  994. struct mvs_slot_info *slot, u32 slot_idx)
  995. {
  996. if (!slot->task)
  997. return;
  998. if (!sas_protocol_ata(task->task_proto))
  999. if (slot->n_elem)
  1000. dma_unmap_sg(mvi->dev, task->scatter,
  1001. slot->n_elem, task->data_dir);
  1002. switch (task->task_proto) {
  1003. case SAS_PROTOCOL_SMP:
  1004. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  1005. PCI_DMA_FROMDEVICE);
  1006. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  1007. PCI_DMA_TODEVICE);
  1008. break;
  1009. case SAS_PROTOCOL_SATA:
  1010. case SAS_PROTOCOL_STP:
  1011. case SAS_PROTOCOL_SSP:
  1012. default:
  1013. /* do nothing */
  1014. break;
  1015. }
  1016. if (slot->buf) {
  1017. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  1018. slot->buf = NULL;
  1019. }
  1020. list_del_init(&slot->entry);
  1021. task->lldd_task = NULL;
  1022. slot->task = NULL;
  1023. slot->port = NULL;
  1024. slot->slot_tag = 0xFFFFFFFF;
  1025. mvs_slot_free(mvi, slot_idx);
  1026. }
  1027. static void mvs_update_wideport(struct mvs_info *mvi, int i)
  1028. {
  1029. struct mvs_phy *phy = &mvi->phy[i];
  1030. struct mvs_port *port = phy->port;
  1031. int j, no;
  1032. for_each_phy(port->wide_port_phymap, j, no) {
  1033. if (j & 1) {
  1034. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  1035. PHYR_WIDE_PORT);
  1036. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  1037. port->wide_port_phymap);
  1038. } else {
  1039. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  1040. PHYR_WIDE_PORT);
  1041. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  1042. 0);
  1043. }
  1044. }
  1045. }
  1046. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  1047. {
  1048. u32 tmp;
  1049. struct mvs_phy *phy = &mvi->phy[i];
  1050. struct mvs_port *port = phy->port;
  1051. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  1052. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  1053. if (!port)
  1054. phy->phy_attached = 1;
  1055. return tmp;
  1056. }
  1057. if (port) {
  1058. if (phy->phy_type & PORT_TYPE_SAS) {
  1059. port->wide_port_phymap &= ~(1U << i);
  1060. if (!port->wide_port_phymap)
  1061. port->port_attached = 0;
  1062. mvs_update_wideport(mvi, i);
  1063. } else if (phy->phy_type & PORT_TYPE_SATA)
  1064. port->port_attached = 0;
  1065. phy->port = NULL;
  1066. phy->phy_attached = 0;
  1067. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  1068. }
  1069. return 0;
  1070. }
  1071. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  1072. {
  1073. u32 *s = (u32 *) buf;
  1074. if (!s)
  1075. return NULL;
  1076. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  1077. s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  1078. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  1079. s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  1080. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  1081. s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  1082. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  1083. s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  1084. /* Workaround: take some ATAPI devices for ATA */
  1085. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  1086. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  1087. return s;
  1088. }
  1089. static u32 mvs_is_sig_fis_received(u32 irq_status)
  1090. {
  1091. return irq_status & PHYEV_SIG_FIS;
  1092. }
  1093. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  1094. {
  1095. if (phy->timer.function)
  1096. del_timer(&phy->timer);
  1097. phy->timer.function = NULL;
  1098. }
  1099. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  1100. {
  1101. struct mvs_phy *phy = &mvi->phy[i];
  1102. struct sas_identify_frame *id;
  1103. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1104. if (get_st) {
  1105. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  1106. phy->phy_status = mvs_is_phy_ready(mvi, i);
  1107. }
  1108. if (phy->phy_status) {
  1109. int oob_done = 0;
  1110. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  1111. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  1112. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  1113. if (phy->phy_type & PORT_TYPE_SATA) {
  1114. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  1115. if (mvs_is_sig_fis_received(phy->irq_status)) {
  1116. mvs_sig_remove_timer(phy);
  1117. phy->phy_attached = 1;
  1118. phy->att_dev_sas_addr =
  1119. i + mvi->id * mvi->chip->n_phy;
  1120. if (oob_done)
  1121. sas_phy->oob_mode = SATA_OOB_MODE;
  1122. phy->frame_rcvd_size =
  1123. sizeof(struct dev_to_host_fis);
  1124. mvs_get_d2h_reg(mvi, i, id);
  1125. } else {
  1126. u32 tmp;
  1127. dev_printk(KERN_DEBUG, mvi->dev,
  1128. "Phy%d : No sig fis\n", i);
  1129. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  1130. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  1131. tmp | PHYEV_SIG_FIS);
  1132. phy->phy_attached = 0;
  1133. phy->phy_type &= ~PORT_TYPE_SATA;
  1134. goto out_done;
  1135. }
  1136. } else if (phy->phy_type & PORT_TYPE_SAS
  1137. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  1138. phy->phy_attached = 1;
  1139. phy->identify.device_type =
  1140. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  1141. if (phy->identify.device_type == SAS_END_DEV)
  1142. phy->identify.target_port_protocols =
  1143. SAS_PROTOCOL_SSP;
  1144. else if (phy->identify.device_type != NO_DEVICE)
  1145. phy->identify.target_port_protocols =
  1146. SAS_PROTOCOL_SMP;
  1147. if (oob_done)
  1148. sas_phy->oob_mode = SAS_OOB_MODE;
  1149. phy->frame_rcvd_size =
  1150. sizeof(struct sas_identify_frame);
  1151. }
  1152. memcpy(sas_phy->attached_sas_addr,
  1153. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  1154. if (MVS_CHIP_DISP->phy_work_around)
  1155. MVS_CHIP_DISP->phy_work_around(mvi, i);
  1156. }
  1157. mv_dprintk("port %d attach dev info is %x\n",
  1158. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  1159. mv_dprintk("port %d attach sas addr is %llx\n",
  1160. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  1161. out_done:
  1162. if (get_st)
  1163. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  1164. }
  1165. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  1166. {
  1167. struct sas_ha_struct *sas_ha = sas_phy->ha;
  1168. struct mvs_info *mvi = NULL; int i = 0, hi;
  1169. struct mvs_phy *phy = sas_phy->lldd_phy;
  1170. struct asd_sas_port *sas_port = sas_phy->port;
  1171. struct mvs_port *port;
  1172. unsigned long flags = 0;
  1173. if (!sas_port)
  1174. return;
  1175. while (sas_ha->sas_phy[i]) {
  1176. if (sas_ha->sas_phy[i] == sas_phy)
  1177. break;
  1178. i++;
  1179. }
  1180. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  1181. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  1182. if (sas_port->id >= mvi->chip->n_phy)
  1183. port = &mvi->port[sas_port->id - mvi->chip->n_phy];
  1184. else
  1185. port = &mvi->port[sas_port->id];
  1186. if (lock)
  1187. spin_lock_irqsave(&mvi->lock, flags);
  1188. port->port_attached = 1;
  1189. phy->port = port;
  1190. sas_port->lldd_port = port;
  1191. if (phy->phy_type & PORT_TYPE_SAS) {
  1192. port->wide_port_phymap = sas_port->phy_mask;
  1193. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  1194. mvs_update_wideport(mvi, sas_phy->id);
  1195. }
  1196. if (lock)
  1197. spin_unlock_irqrestore(&mvi->lock, flags);
  1198. }
  1199. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  1200. {
  1201. struct domain_device *dev;
  1202. struct mvs_phy *phy = sas_phy->lldd_phy;
  1203. struct mvs_info *mvi = phy->mvi;
  1204. struct asd_sas_port *port = sas_phy->port;
  1205. int phy_no = 0;
  1206. while (phy != &mvi->phy[phy_no]) {
  1207. phy_no++;
  1208. if (phy_no >= MVS_MAX_PHYS)
  1209. return;
  1210. }
  1211. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  1212. mvs_do_release_task(phy->mvi, phy_no, NULL);
  1213. }
  1214. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  1215. {
  1216. mvs_port_notify_formed(sas_phy, 1);
  1217. }
  1218. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  1219. {
  1220. mvs_port_notify_deformed(sas_phy, 1);
  1221. }
  1222. struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  1223. {
  1224. u32 dev;
  1225. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  1226. if (mvi->devices[dev].dev_type == NO_DEVICE) {
  1227. mvi->devices[dev].device_id = dev;
  1228. return &mvi->devices[dev];
  1229. }
  1230. }
  1231. if (dev == MVS_MAX_DEVICES)
  1232. mv_printk("max support %d devices, ignore ..\n",
  1233. MVS_MAX_DEVICES);
  1234. return NULL;
  1235. }
  1236. void mvs_free_dev(struct mvs_device *mvi_dev)
  1237. {
  1238. u32 id = mvi_dev->device_id;
  1239. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1240. mvi_dev->device_id = id;
  1241. mvi_dev->dev_type = NO_DEVICE;
  1242. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1243. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1244. }
  1245. int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1246. {
  1247. unsigned long flags = 0;
  1248. int res = 0;
  1249. struct mvs_info *mvi = NULL;
  1250. struct domain_device *parent_dev = dev->parent;
  1251. struct mvs_device *mvi_device;
  1252. mvi = mvs_find_dev_mvi(dev);
  1253. if (lock)
  1254. spin_lock_irqsave(&mvi->lock, flags);
  1255. mvi_device = mvs_alloc_dev(mvi);
  1256. if (!mvi_device) {
  1257. res = -1;
  1258. goto found_out;
  1259. }
  1260. dev->lldd_dev = mvi_device;
  1261. mvi_device->dev_status = MVS_DEV_NORMAL;
  1262. mvi_device->dev_type = dev->dev_type;
  1263. mvi_device->mvi_info = mvi;
  1264. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1265. int phy_id;
  1266. u8 phy_num = parent_dev->ex_dev.num_phys;
  1267. struct ex_phy *phy;
  1268. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1269. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1270. if (SAS_ADDR(phy->attached_sas_addr) ==
  1271. SAS_ADDR(dev->sas_addr)) {
  1272. mvi_device->attached_phy = phy_id;
  1273. break;
  1274. }
  1275. }
  1276. if (phy_id == phy_num) {
  1277. mv_printk("Error: no attached dev:%016llx"
  1278. "at ex:%016llx.\n",
  1279. SAS_ADDR(dev->sas_addr),
  1280. SAS_ADDR(parent_dev->sas_addr));
  1281. res = -1;
  1282. }
  1283. }
  1284. found_out:
  1285. if (lock)
  1286. spin_unlock_irqrestore(&mvi->lock, flags);
  1287. return res;
  1288. }
  1289. int mvs_dev_found(struct domain_device *dev)
  1290. {
  1291. return mvs_dev_found_notify(dev, 1);
  1292. }
  1293. void mvs_dev_gone_notify(struct domain_device *dev)
  1294. {
  1295. unsigned long flags = 0;
  1296. struct mvs_device *mvi_dev = dev->lldd_dev;
  1297. struct mvs_info *mvi = mvi_dev->mvi_info;
  1298. spin_lock_irqsave(&mvi->lock, flags);
  1299. if (mvi_dev) {
  1300. mv_dprintk("found dev[%d:%x] is gone.\n",
  1301. mvi_dev->device_id, mvi_dev->dev_type);
  1302. mvs_release_task(mvi, dev);
  1303. mvs_free_reg_set(mvi, mvi_dev);
  1304. mvs_free_dev(mvi_dev);
  1305. } else {
  1306. mv_dprintk("found dev has gone.\n");
  1307. }
  1308. dev->lldd_dev = NULL;
  1309. spin_unlock_irqrestore(&mvi->lock, flags);
  1310. }
  1311. void mvs_dev_gone(struct domain_device *dev)
  1312. {
  1313. mvs_dev_gone_notify(dev);
  1314. }
  1315. static struct sas_task *mvs_alloc_task(void)
  1316. {
  1317. struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
  1318. if (task) {
  1319. INIT_LIST_HEAD(&task->list);
  1320. spin_lock_init(&task->task_state_lock);
  1321. task->task_state_flags = SAS_TASK_STATE_PENDING;
  1322. init_timer(&task->timer);
  1323. init_completion(&task->completion);
  1324. }
  1325. return task;
  1326. }
  1327. static void mvs_free_task(struct sas_task *task)
  1328. {
  1329. if (task) {
  1330. BUG_ON(!list_empty(&task->list));
  1331. kfree(task);
  1332. }
  1333. }
  1334. static void mvs_task_done(struct sas_task *task)
  1335. {
  1336. if (!del_timer(&task->timer))
  1337. return;
  1338. complete(&task->completion);
  1339. }
  1340. static void mvs_tmf_timedout(unsigned long data)
  1341. {
  1342. struct sas_task *task = (struct sas_task *)data;
  1343. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1344. complete(&task->completion);
  1345. }
  1346. /* XXX */
  1347. #define MVS_TASK_TIMEOUT 20
  1348. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1349. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1350. {
  1351. int res, retry;
  1352. struct sas_task *task = NULL;
  1353. for (retry = 0; retry < 3; retry++) {
  1354. task = mvs_alloc_task();
  1355. if (!task)
  1356. return -ENOMEM;
  1357. task->dev = dev;
  1358. task->task_proto = dev->tproto;
  1359. memcpy(&task->ssp_task, parameter, para_len);
  1360. task->task_done = mvs_task_done;
  1361. task->timer.data = (unsigned long) task;
  1362. task->timer.function = mvs_tmf_timedout;
  1363. task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1364. add_timer(&task->timer);
  1365. res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
  1366. if (res) {
  1367. del_timer(&task->timer);
  1368. mv_printk("executing internel task failed:%d\n", res);
  1369. goto ex_err;
  1370. }
  1371. wait_for_completion(&task->completion);
  1372. res = -TMF_RESP_FUNC_FAILED;
  1373. /* Even TMF timed out, return direct. */
  1374. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1375. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1376. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1377. goto ex_err;
  1378. }
  1379. }
  1380. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1381. task->task_status.stat == SAM_STAT_GOOD) {
  1382. res = TMF_RESP_FUNC_COMPLETE;
  1383. break;
  1384. }
  1385. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1386. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1387. /* no error, but return the number of bytes of
  1388. * underrun */
  1389. res = task->task_status.residual;
  1390. break;
  1391. }
  1392. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1393. task->task_status.stat == SAS_DATA_OVERRUN) {
  1394. mv_dprintk("blocked task error.\n");
  1395. res = -EMSGSIZE;
  1396. break;
  1397. } else {
  1398. mv_dprintk(" task to dev %016llx response: 0x%x "
  1399. "status 0x%x\n",
  1400. SAS_ADDR(dev->sas_addr),
  1401. task->task_status.resp,
  1402. task->task_status.stat);
  1403. mvs_free_task(task);
  1404. task = NULL;
  1405. }
  1406. }
  1407. ex_err:
  1408. BUG_ON(retry == 3 && task != NULL);
  1409. if (task != NULL)
  1410. mvs_free_task(task);
  1411. return res;
  1412. }
  1413. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1414. u8 *lun, struct mvs_tmf_task *tmf)
  1415. {
  1416. struct sas_ssp_task ssp_task;
  1417. DECLARE_COMPLETION_ONSTACK(completion);
  1418. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1419. return TMF_RESP_FUNC_ESUPP;
  1420. strncpy((u8 *)&ssp_task.LUN, lun, 8);
  1421. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1422. sizeof(ssp_task), tmf);
  1423. }
  1424. /* Standard mandates link reset for ATA (type 0)
  1425. and hard reset for SSP (type 1) , only for RECOVERY */
  1426. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1427. {
  1428. int rc;
  1429. struct sas_phy *phy = sas_find_local_phy(dev);
  1430. int reset_type = (dev->dev_type == SATA_DEV ||
  1431. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1432. rc = sas_phy_reset(phy, reset_type);
  1433. msleep(2000);
  1434. return rc;
  1435. }
  1436. /* mandatory SAM-3 */
  1437. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1438. {
  1439. unsigned long flags;
  1440. int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
  1441. struct mvs_tmf_task tmf_task;
  1442. struct mvs_device * mvi_dev = dev->lldd_dev;
  1443. struct mvs_info *mvi = mvi_dev->mvi_info;
  1444. tmf_task.tmf = TMF_LU_RESET;
  1445. mvi_dev->dev_status = MVS_DEV_EH;
  1446. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1447. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1448. num = mvs_find_dev_phyno(dev, phyno);
  1449. spin_lock_irqsave(&mvi->lock, flags);
  1450. for (i = 0; i < num; i++)
  1451. mvs_release_task(mvi, dev);
  1452. spin_unlock_irqrestore(&mvi->lock, flags);
  1453. }
  1454. /* If failed, fall-through I_T_Nexus reset */
  1455. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1456. mvi_dev->device_id, rc);
  1457. return rc;
  1458. }
  1459. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1460. {
  1461. unsigned long flags;
  1462. int rc = TMF_RESP_FUNC_FAILED;
  1463. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1464. struct mvs_info *mvi = mvi_dev->mvi_info;
  1465. if (mvi_dev->dev_status != MVS_DEV_EH)
  1466. return TMF_RESP_FUNC_COMPLETE;
  1467. rc = mvs_debug_I_T_nexus_reset(dev);
  1468. mv_printk("%s for device[%x]:rc= %d\n",
  1469. __func__, mvi_dev->device_id, rc);
  1470. /* housekeeper */
  1471. spin_lock_irqsave(&mvi->lock, flags);
  1472. mvs_release_task(mvi, dev);
  1473. spin_unlock_irqrestore(&mvi->lock, flags);
  1474. return rc;
  1475. }
  1476. /* optional SAM-3 */
  1477. int mvs_query_task(struct sas_task *task)
  1478. {
  1479. u32 tag;
  1480. struct scsi_lun lun;
  1481. struct mvs_tmf_task tmf_task;
  1482. int rc = TMF_RESP_FUNC_FAILED;
  1483. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1484. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1485. struct domain_device *dev = task->dev;
  1486. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1487. struct mvs_info *mvi = mvi_dev->mvi_info;
  1488. int_to_scsilun(cmnd->device->lun, &lun);
  1489. rc = mvs_find_tag(mvi, task, &tag);
  1490. if (rc == 0) {
  1491. rc = TMF_RESP_FUNC_FAILED;
  1492. return rc;
  1493. }
  1494. tmf_task.tmf = TMF_QUERY_TASK;
  1495. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1496. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1497. switch (rc) {
  1498. /* The task is still in Lun, release it then */
  1499. case TMF_RESP_FUNC_SUCC:
  1500. /* The task is not in Lun or failed, reset the phy */
  1501. case TMF_RESP_FUNC_FAILED:
  1502. case TMF_RESP_FUNC_COMPLETE:
  1503. break;
  1504. default:
  1505. rc = TMF_RESP_FUNC_COMPLETE;
  1506. break;
  1507. }
  1508. }
  1509. mv_printk("%s:rc= %d\n", __func__, rc);
  1510. return rc;
  1511. }
  1512. /* mandatory SAM-3, still need free task/slot info */
  1513. int mvs_abort_task(struct sas_task *task)
  1514. {
  1515. struct scsi_lun lun;
  1516. struct mvs_tmf_task tmf_task;
  1517. struct domain_device *dev = task->dev;
  1518. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1519. struct mvs_info *mvi;
  1520. int rc = TMF_RESP_FUNC_FAILED;
  1521. unsigned long flags;
  1522. u32 tag;
  1523. if (!mvi_dev) {
  1524. mv_printk("%s:%d TMF_RESP_FUNC_FAILED\n", __func__, __LINE__);
  1525. rc = TMF_RESP_FUNC_FAILED;
  1526. }
  1527. mvi = mvi_dev->mvi_info;
  1528. spin_lock_irqsave(&task->task_state_lock, flags);
  1529. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1530. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1531. rc = TMF_RESP_FUNC_COMPLETE;
  1532. goto out;
  1533. }
  1534. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1535. mvi_dev->dev_status = MVS_DEV_EH;
  1536. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1537. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1538. int_to_scsilun(cmnd->device->lun, &lun);
  1539. rc = mvs_find_tag(mvi, task, &tag);
  1540. if (rc == 0) {
  1541. mv_printk("No such tag in %s\n", __func__);
  1542. rc = TMF_RESP_FUNC_FAILED;
  1543. return rc;
  1544. }
  1545. tmf_task.tmf = TMF_ABORT_TASK;
  1546. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1547. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1548. /* if successful, clear the task and callback forwards.*/
  1549. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1550. u32 slot_no;
  1551. struct mvs_slot_info *slot;
  1552. if (task->lldd_task) {
  1553. slot = task->lldd_task;
  1554. slot_no = (u32) (slot - mvi->slot_info);
  1555. spin_lock_irqsave(&mvi->lock, flags);
  1556. mvs_slot_complete(mvi, slot_no, 1);
  1557. spin_unlock_irqrestore(&mvi->lock, flags);
  1558. }
  1559. }
  1560. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1561. task->task_proto & SAS_PROTOCOL_STP) {
  1562. /* to do free register_set */
  1563. if (SATA_DEV == dev->dev_type) {
  1564. struct mvs_slot_info *slot = task->lldd_task;
  1565. struct task_status_struct *tstat;
  1566. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1567. tstat = &task->task_status;
  1568. mv_dprintk(KERN_DEBUG "mv_abort_task() mvi=%p task=%p "
  1569. "slot=%p slot_idx=x%x\n",
  1570. mvi, task, slot, slot_idx);
  1571. tstat->stat = SAS_ABORTED_TASK;
  1572. if (mvi_dev && mvi_dev->running_req)
  1573. mvi_dev->running_req--;
  1574. if (sas_protocol_ata(task->task_proto))
  1575. mvs_free_reg_set(mvi, mvi_dev);
  1576. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1577. return -1;
  1578. }
  1579. } else {
  1580. /* SMP */
  1581. }
  1582. out:
  1583. if (rc != TMF_RESP_FUNC_COMPLETE)
  1584. mv_printk("%s:rc= %d\n", __func__, rc);
  1585. return rc;
  1586. }
  1587. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1588. {
  1589. int rc = TMF_RESP_FUNC_FAILED;
  1590. struct mvs_tmf_task tmf_task;
  1591. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1592. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1593. return rc;
  1594. }
  1595. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1596. {
  1597. int rc = TMF_RESP_FUNC_FAILED;
  1598. struct mvs_tmf_task tmf_task;
  1599. tmf_task.tmf = TMF_CLEAR_ACA;
  1600. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1601. return rc;
  1602. }
  1603. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1604. {
  1605. int rc = TMF_RESP_FUNC_FAILED;
  1606. struct mvs_tmf_task tmf_task;
  1607. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1608. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1609. return rc;
  1610. }
  1611. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1612. u32 slot_idx, int err)
  1613. {
  1614. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1615. struct task_status_struct *tstat = &task->task_status;
  1616. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1617. int stat = SAM_STAT_GOOD;
  1618. resp->frame_len = sizeof(struct dev_to_host_fis);
  1619. memcpy(&resp->ending_fis[0],
  1620. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1621. sizeof(struct dev_to_host_fis));
  1622. tstat->buf_valid_size = sizeof(*resp);
  1623. if (unlikely(err)) {
  1624. if (unlikely(err & CMD_ISS_STPD))
  1625. stat = SAS_OPEN_REJECT;
  1626. else
  1627. stat = SAS_PROTO_RESPONSE;
  1628. }
  1629. return stat;
  1630. }
  1631. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1632. u32 slot_idx)
  1633. {
  1634. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1635. int stat;
  1636. u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
  1637. u32 tfs = 0;
  1638. enum mvs_port_type type = PORT_TYPE_SAS;
  1639. if (err_dw0 & CMD_ISS_STPD)
  1640. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1641. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1642. stat = SAM_STAT_CHECK_CONDITION;
  1643. switch (task->task_proto) {
  1644. case SAS_PROTOCOL_SSP:
  1645. stat = SAS_ABORTED_TASK;
  1646. break;
  1647. case SAS_PROTOCOL_SMP:
  1648. stat = SAM_STAT_CHECK_CONDITION;
  1649. break;
  1650. case SAS_PROTOCOL_SATA:
  1651. case SAS_PROTOCOL_STP:
  1652. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1653. {
  1654. if (err_dw0 == 0x80400002)
  1655. mv_printk("find reserved error, why?\n");
  1656. task->ata_task.use_ncq = 0;
  1657. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1658. }
  1659. break;
  1660. default:
  1661. break;
  1662. }
  1663. return stat;
  1664. }
  1665. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1666. {
  1667. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1668. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1669. struct sas_task *task = slot->task;
  1670. struct mvs_device *mvi_dev = NULL;
  1671. struct task_status_struct *tstat;
  1672. struct domain_device *dev;
  1673. u32 aborted;
  1674. void *to;
  1675. enum exec_status sts;
  1676. if (mvi->exp_req)
  1677. mvi->exp_req--;
  1678. if (unlikely(!task || !task->lldd_task || !task->dev))
  1679. return -1;
  1680. tstat = &task->task_status;
  1681. dev = task->dev;
  1682. mvi_dev = dev->lldd_dev;
  1683. mvs_hba_cq_dump(mvi);
  1684. spin_lock(&task->task_state_lock);
  1685. task->task_state_flags &=
  1686. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1687. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1688. /* race condition*/
  1689. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1690. spin_unlock(&task->task_state_lock);
  1691. memset(tstat, 0, sizeof(*tstat));
  1692. tstat->resp = SAS_TASK_COMPLETE;
  1693. if (unlikely(aborted)) {
  1694. tstat->stat = SAS_ABORTED_TASK;
  1695. if (mvi_dev && mvi_dev->running_req)
  1696. mvi_dev->running_req--;
  1697. if (sas_protocol_ata(task->task_proto))
  1698. mvs_free_reg_set(mvi, mvi_dev);
  1699. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1700. return -1;
  1701. }
  1702. if (unlikely(!mvi_dev || flags)) {
  1703. if (!mvi_dev)
  1704. mv_dprintk("port has not device.\n");
  1705. tstat->stat = SAS_PHY_DOWN;
  1706. goto out;
  1707. }
  1708. /* error info record present */
  1709. if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
  1710. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1711. tstat->resp = SAS_TASK_COMPLETE;
  1712. goto out;
  1713. }
  1714. switch (task->task_proto) {
  1715. case SAS_PROTOCOL_SSP:
  1716. /* hw says status == 0, datapres == 0 */
  1717. if (rx_desc & RXQ_GOOD) {
  1718. tstat->stat = SAM_STAT_GOOD;
  1719. tstat->resp = SAS_TASK_COMPLETE;
  1720. }
  1721. /* response frame present */
  1722. else if (rx_desc & RXQ_RSP) {
  1723. struct ssp_response_iu *iu = slot->response +
  1724. sizeof(struct mvs_err_info);
  1725. sas_ssp_task_response(mvi->dev, task, iu);
  1726. } else
  1727. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1728. break;
  1729. case SAS_PROTOCOL_SMP: {
  1730. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1731. tstat->stat = SAM_STAT_GOOD;
  1732. to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
  1733. memcpy(to + sg_resp->offset,
  1734. slot->response + sizeof(struct mvs_err_info),
  1735. sg_dma_len(sg_resp));
  1736. kunmap_atomic(to, KM_IRQ0);
  1737. break;
  1738. }
  1739. case SAS_PROTOCOL_SATA:
  1740. case SAS_PROTOCOL_STP:
  1741. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1742. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1743. break;
  1744. }
  1745. default:
  1746. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1747. break;
  1748. }
  1749. if (!slot->port->port_attached) {
  1750. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1751. tstat->stat = SAS_PHY_DOWN;
  1752. }
  1753. out:
  1754. if (mvi_dev && mvi_dev->running_req) {
  1755. mvi_dev->running_req--;
  1756. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1757. mvs_free_reg_set(mvi, mvi_dev);
  1758. }
  1759. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1760. sts = tstat->stat;
  1761. spin_unlock(&mvi->lock);
  1762. if (task->task_done)
  1763. task->task_done(task);
  1764. else
  1765. mv_dprintk("why has not task_done.\n");
  1766. spin_lock(&mvi->lock);
  1767. return sts;
  1768. }
  1769. void mvs_do_release_task(struct mvs_info *mvi,
  1770. int phy_no, struct domain_device *dev)
  1771. {
  1772. u32 slot_idx;
  1773. struct mvs_phy *phy;
  1774. struct mvs_port *port;
  1775. struct mvs_slot_info *slot, *slot2;
  1776. phy = &mvi->phy[phy_no];
  1777. port = phy->port;
  1778. if (!port)
  1779. return;
  1780. /* clean cmpl queue in case request is already finished */
  1781. mvs_int_rx(mvi, false);
  1782. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1783. struct sas_task *task;
  1784. slot_idx = (u32) (slot - mvi->slot_info);
  1785. task = slot->task;
  1786. if (dev && task->dev != dev)
  1787. continue;
  1788. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1789. slot_idx, slot->slot_tag, task);
  1790. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1791. mvs_slot_complete(mvi, slot_idx, 1);
  1792. }
  1793. }
  1794. void mvs_release_task(struct mvs_info *mvi,
  1795. struct domain_device *dev)
  1796. {
  1797. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1798. /* housekeeper */
  1799. num = mvs_find_dev_phyno(dev, phyno);
  1800. for (i = 0; i < num; i++)
  1801. mvs_do_release_task(mvi, phyno[i], dev);
  1802. }
  1803. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1804. {
  1805. phy->phy_attached = 0;
  1806. phy->att_dev_info = 0;
  1807. phy->att_dev_sas_addr = 0;
  1808. }
  1809. static void mvs_work_queue(struct work_struct *work)
  1810. {
  1811. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1812. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1813. struct mvs_info *mvi = mwq->mvi;
  1814. unsigned long flags;
  1815. spin_lock_irqsave(&mvi->lock, flags);
  1816. if (mwq->handler & PHY_PLUG_EVENT) {
  1817. u32 phy_no = (unsigned long) mwq->data;
  1818. struct sas_ha_struct *sas_ha = mvi->sas;
  1819. struct mvs_phy *phy = &mvi->phy[phy_no];
  1820. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1821. if (phy->phy_event & PHY_PLUG_OUT) {
  1822. u32 tmp;
  1823. struct sas_identify_frame *id;
  1824. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1825. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1826. phy->phy_event &= ~PHY_PLUG_OUT;
  1827. if (!(tmp & PHY_READY_MASK)) {
  1828. sas_phy_disconnected(sas_phy);
  1829. mvs_phy_disconnected(phy);
  1830. sas_ha->notify_phy_event(sas_phy,
  1831. PHYE_LOSS_OF_SIGNAL);
  1832. mv_dprintk("phy%d Removed Device\n", phy_no);
  1833. } else {
  1834. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1835. mvs_update_phyinfo(mvi, phy_no, 1);
  1836. mvs_bytes_dmaed(mvi, phy_no);
  1837. mvs_port_notify_formed(sas_phy, 0);
  1838. mv_dprintk("phy%d Attached Device\n", phy_no);
  1839. }
  1840. }
  1841. }
  1842. list_del(&mwq->entry);
  1843. spin_unlock_irqrestore(&mvi->lock, flags);
  1844. kfree(mwq);
  1845. }
  1846. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1847. {
  1848. struct mvs_wq *mwq;
  1849. int ret = 0;
  1850. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1851. if (mwq) {
  1852. mwq->mvi = mvi;
  1853. mwq->data = data;
  1854. mwq->handler = handler;
  1855. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1856. list_add_tail(&mwq->entry, &mvi->wq_list);
  1857. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1858. } else
  1859. ret = -ENOMEM;
  1860. return ret;
  1861. }
  1862. static void mvs_sig_time_out(unsigned long tphy)
  1863. {
  1864. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1865. struct mvs_info *mvi = phy->mvi;
  1866. u8 phy_no;
  1867. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1868. if (&mvi->phy[phy_no] == phy) {
  1869. mv_dprintk("Get signature time out, reset phy %d\n",
  1870. phy_no+mvi->id*mvi->chip->n_phy);
  1871. MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
  1872. }
  1873. }
  1874. }
  1875. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1876. {
  1877. u32 tmp;
  1878. struct sas_ha_struct *sas_ha = mvi->sas;
  1879. struct mvs_phy *phy = &mvi->phy[phy_no];
  1880. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1881. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1882. mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1883. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1884. mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1885. phy->irq_status);
  1886. /*
  1887. * events is port event now ,
  1888. * we need check the interrupt status which belongs to per port.
  1889. */
  1890. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1891. mv_dprintk("port %d STP decoding error.\n",
  1892. phy_no + mvi->id*mvi->chip->n_phy);
  1893. }
  1894. if (phy->irq_status & PHYEV_POOF) {
  1895. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1896. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1897. int ready;
  1898. mvs_do_release_task(mvi, phy_no, NULL);
  1899. phy->phy_event |= PHY_PLUG_OUT;
  1900. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1901. mvs_handle_event(mvi,
  1902. (void *)(unsigned long)phy_no,
  1903. PHY_PLUG_EVENT);
  1904. ready = mvs_is_phy_ready(mvi, phy_no);
  1905. if (!ready)
  1906. mv_dprintk("phy%d Unplug Notice\n",
  1907. phy_no +
  1908. mvi->id * mvi->chip->n_phy);
  1909. if (ready || dev_sata) {
  1910. if (MVS_CHIP_DISP->stp_reset)
  1911. MVS_CHIP_DISP->stp_reset(mvi,
  1912. phy_no);
  1913. else
  1914. MVS_CHIP_DISP->phy_reset(mvi,
  1915. phy_no, 0);
  1916. return;
  1917. }
  1918. }
  1919. }
  1920. if (phy->irq_status & PHYEV_COMWAKE) {
  1921. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1922. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1923. tmp | PHYEV_SIG_FIS);
  1924. if (phy->timer.function == NULL) {
  1925. phy->timer.data = (unsigned long)phy;
  1926. phy->timer.function = mvs_sig_time_out;
  1927. phy->timer.expires = jiffies + 10*HZ;
  1928. add_timer(&phy->timer);
  1929. }
  1930. }
  1931. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1932. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1933. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1934. if (phy->phy_status) {
  1935. mdelay(10);
  1936. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1937. if (phy->phy_type & PORT_TYPE_SATA) {
  1938. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1939. mvi, phy_no);
  1940. tmp &= ~PHYEV_SIG_FIS;
  1941. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1942. phy_no, tmp);
  1943. }
  1944. mvs_update_phyinfo(mvi, phy_no, 0);
  1945. if (phy->phy_type & PORT_TYPE_SAS) {
  1946. MVS_CHIP_DISP->phy_reset(mvi, phy_no, 2);
  1947. mdelay(10);
  1948. }
  1949. mvs_bytes_dmaed(mvi, phy_no);
  1950. /* whether driver is going to handle hot plug */
  1951. if (phy->phy_event & PHY_PLUG_OUT) {
  1952. mvs_port_notify_formed(sas_phy, 0);
  1953. phy->phy_event &= ~PHY_PLUG_OUT;
  1954. }
  1955. } else {
  1956. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1957. phy_no + mvi->id*mvi->chip->n_phy);
  1958. }
  1959. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1960. mv_dprintk("port %d broadcast change.\n",
  1961. phy_no + mvi->id*mvi->chip->n_phy);
  1962. /* exception for Samsung disk drive*/
  1963. mdelay(1000);
  1964. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  1965. }
  1966. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1967. }
  1968. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1969. {
  1970. u32 rx_prod_idx, rx_desc;
  1971. bool attn = false;
  1972. /* the first dword in the RX ring is special: it contains
  1973. * a mirror of the hardware's RX producer index, so that
  1974. * we don't have to stall the CPU reading that register.
  1975. * The actual RX ring is offset by one dword, due to this.
  1976. */
  1977. rx_prod_idx = mvi->rx_cons;
  1978. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1979. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1980. return 0;
  1981. /* The CMPL_Q may come late, read from register and try again
  1982. * note: if coalescing is enabled,
  1983. * it will need to read from register every time for sure
  1984. */
  1985. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1986. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1987. if (mvi->rx_cons == rx_prod_idx)
  1988. return 0;
  1989. while (mvi->rx_cons != rx_prod_idx) {
  1990. /* increment our internal RX consumer pointer */
  1991. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1992. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1993. if (likely(rx_desc & RXQ_DONE))
  1994. mvs_slot_complete(mvi, rx_desc, 0);
  1995. if (rx_desc & RXQ_ATTN) {
  1996. attn = true;
  1997. } else if (rx_desc & RXQ_ERR) {
  1998. if (!(rx_desc & RXQ_DONE))
  1999. mvs_slot_complete(mvi, rx_desc, 0);
  2000. } else if (rx_desc & RXQ_SLOT_RESET) {
  2001. mvs_slot_free(mvi, rx_desc);
  2002. }
  2003. }
  2004. if (attn && self_clear)
  2005. MVS_CHIP_DISP->int_full(mvi);
  2006. return 0;
  2007. }