gdth.c 179 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: Command priority
  87. * buffer: phys. DMA sense buffer
  88. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  89. * buffers_residual: Timeout value
  90. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  91. * Message: Additional info (gdth_do_cmd()), DMA direction
  92. * have_data_in: Flag for gdth_wait_completion()
  93. * sent_command: Opcode special command
  94. * phase: Service/parameter/return code special command
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #ifdef GDTH_RTC
  117. #include <linux/mc146818rtc.h>
  118. #endif
  119. #include <linux/reboot.h>
  120. #include <asm/dma.h>
  121. #include <asm/system.h>
  122. #include <asm/io.h>
  123. #include <asm/uaccess.h>
  124. #include <linux/spinlock.h>
  125. #include <linux/blkdev.h>
  126. #include "scsi.h"
  127. #include <scsi/scsi_host.h>
  128. #include "gdth.h"
  129. static void gdth_delay(int milliseconds);
  130. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  131. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  132. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
  133. int gdth_from_wait, int* pIndex);
  134. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  135. Scsi_Cmnd *scp);
  136. static int gdth_async_event(gdth_ha_str *ha);
  137. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  138. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  139. static void gdth_next(gdth_ha_str *ha);
  140. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  141. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  142. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  143. ushort idx, gdth_evt_data *evt);
  144. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  145. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  146. gdth_evt_str *estr);
  147. static void gdth_clear_events(void);
  148. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  149. char *buffer,ushort count);
  150. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  151. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  152. static void gdth_enable_int(gdth_ha_str *ha);
  153. static unchar gdth_get_status(gdth_ha_str *ha, int irq);
  154. static int gdth_test_busy(gdth_ha_str *ha);
  155. static int gdth_get_cmd_index(gdth_ha_str *ha);
  156. static void gdth_release_event(gdth_ha_str *ha);
  157. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  158. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  159. ulong32 p1, ulong64 p2,ulong64 p3);
  160. static int gdth_search_drives(gdth_ha_str *ha);
  161. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  162. static const char *gdth_ctr_name(gdth_ha_str *ha);
  163. static int gdth_open(struct inode *inode, struct file *filep);
  164. static int gdth_close(struct inode *inode, struct file *filep);
  165. static int gdth_ioctl(struct inode *inode, struct file *filep,
  166. unsigned int cmd, unsigned long arg);
  167. static void gdth_flush(gdth_ha_str *ha);
  168. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  169. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  170. static void gdth_scsi_done(struct scsi_cmnd *scp);
  171. #ifdef DEBUG_GDTH
  172. static unchar DebugState = DEBUG_GDTH;
  173. #ifdef __SERIAL__
  174. #define MAX_SERBUF 160
  175. static void ser_init(void);
  176. static void ser_puts(char *str);
  177. static void ser_putc(char c);
  178. static int ser_printk(const char *fmt, ...);
  179. static char strbuf[MAX_SERBUF+1];
  180. #ifdef __COM2__
  181. #define COM_BASE 0x2f8
  182. #else
  183. #define COM_BASE 0x3f8
  184. #endif
  185. static void ser_init()
  186. {
  187. unsigned port=COM_BASE;
  188. outb(0x80,port+3);
  189. outb(0,port+1);
  190. /* 19200 Baud, if 9600: outb(12,port) */
  191. outb(6, port);
  192. outb(3,port+3);
  193. outb(0,port+1);
  194. /*
  195. ser_putc('I');
  196. ser_putc(' ');
  197. */
  198. }
  199. static void ser_puts(char *str)
  200. {
  201. char *ptr;
  202. ser_init();
  203. for (ptr=str;*ptr;++ptr)
  204. ser_putc(*ptr);
  205. }
  206. static void ser_putc(char c)
  207. {
  208. unsigned port=COM_BASE;
  209. while ((inb(port+5) & 0x20)==0);
  210. outb(c,port);
  211. if (c==0x0a)
  212. {
  213. while ((inb(port+5) & 0x20)==0);
  214. outb(0x0d,port);
  215. }
  216. }
  217. static int ser_printk(const char *fmt, ...)
  218. {
  219. va_list args;
  220. int i;
  221. va_start(args,fmt);
  222. i = vsprintf(strbuf,fmt,args);
  223. ser_puts(strbuf);
  224. va_end(args);
  225. return i;
  226. }
  227. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  228. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  229. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  230. #else /* !__SERIAL__ */
  231. #define TRACE(a) {if (DebugState==1) {printk a;}}
  232. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  233. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  234. #endif
  235. #else /* !DEBUG */
  236. #define TRACE(a)
  237. #define TRACE2(a)
  238. #define TRACE3(a)
  239. #endif
  240. #ifdef GDTH_STATISTICS
  241. static ulong32 max_rq=0, max_index=0, max_sg=0;
  242. #ifdef INT_COAL
  243. static ulong32 max_int_coal=0;
  244. #endif
  245. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  246. static struct timer_list gdth_timer;
  247. #endif
  248. #define PTR2USHORT(a) (ushort)(ulong)(a)
  249. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  250. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  251. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  252. #ifdef CONFIG_ISA
  253. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  254. #endif
  255. #ifdef CONFIG_EISA
  256. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  257. #endif
  258. static unchar gdth_polling; /* polling if TRUE */
  259. static int gdth_ctr_count = 0; /* controller count */
  260. static LIST_HEAD(gdth_instances); /* controller list */
  261. static unchar gdth_write_through = FALSE; /* write through */
  262. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  263. static int elastidx;
  264. static int eoldidx;
  265. static int major;
  266. #define DIN 1 /* IN data direction */
  267. #define DOU 2 /* OUT data direction */
  268. #define DNO DIN /* no data transfer */
  269. #define DUN DIN /* unknown data direction */
  270. static unchar gdth_direction_tab[0x100] = {
  271. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  272. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  273. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  274. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  275. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  276. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  277. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  278. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  282. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  283. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  284. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  285. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  287. };
  288. /* LILO and modprobe/insmod parameters */
  289. /* IRQ list for GDT3000/3020 EISA controllers */
  290. static int irq[MAXHA] __initdata =
  291. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  292. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  293. /* disable driver flag */
  294. static int disable __initdata = 0;
  295. /* reserve flag */
  296. static int reserve_mode = 1;
  297. /* reserve list */
  298. static int reserve_list[MAX_RES_ARGS] =
  299. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  300. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  301. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  302. /* scan order for PCI controllers */
  303. static int reverse_scan = 0;
  304. /* virtual channel for the host drives */
  305. static int hdr_channel = 0;
  306. /* max. IDs per channel */
  307. static int max_ids = MAXID;
  308. /* rescan all IDs */
  309. static int rescan = 0;
  310. /* shared access */
  311. static int shared_access = 1;
  312. /* enable support for EISA and ISA controllers */
  313. static int probe_eisa_isa = 0;
  314. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  315. static int force_dma32 = 0;
  316. /* parameters for modprobe/insmod */
  317. module_param_array(irq, int, NULL, 0);
  318. module_param(disable, int, 0);
  319. module_param(reserve_mode, int, 0);
  320. module_param_array(reserve_list, int, NULL, 0);
  321. module_param(reverse_scan, int, 0);
  322. module_param(hdr_channel, int, 0);
  323. module_param(max_ids, int, 0);
  324. module_param(rescan, int, 0);
  325. module_param(shared_access, int, 0);
  326. module_param(probe_eisa_isa, int, 0);
  327. module_param(force_dma32, int, 0);
  328. MODULE_AUTHOR("Achim Leubner");
  329. MODULE_LICENSE("GPL");
  330. /* ioctl interface */
  331. static const struct file_operations gdth_fops = {
  332. .ioctl = gdth_ioctl,
  333. .open = gdth_open,
  334. .release = gdth_close,
  335. };
  336. #define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
  337. #define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
  338. #include "gdth_proc.h"
  339. #include "gdth_proc.c"
  340. /* notifier block to get a notify on system shutdown/halt/reboot */
  341. static struct notifier_block gdth_notifier = {
  342. gdth_halt, NULL, 0
  343. };
  344. static int notifier_disabled = 0;
  345. static gdth_ha_str *gdth_find_ha(int hanum)
  346. {
  347. gdth_ha_str *ha;
  348. list_for_each_entry(ha, &gdth_instances, list)
  349. if (hanum == ha->hanum)
  350. return ha;
  351. return NULL;
  352. }
  353. static void gdth_delay(int milliseconds)
  354. {
  355. if (milliseconds == 0) {
  356. udelay(1);
  357. } else {
  358. mdelay(milliseconds);
  359. }
  360. }
  361. static void gdth_scsi_done(struct scsi_cmnd *scp)
  362. {
  363. TRACE2(("gdth_scsi_done()\n"));
  364. if (IS_GDTH_INTERNAL_CMD(scp))
  365. complete((struct completion *)scp->request);
  366. else
  367. scp->scsi_done(scp);
  368. }
  369. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  370. int timeout, u32 *info)
  371. {
  372. Scsi_Cmnd *scp;
  373. DECLARE_COMPLETION_ONSTACK(wait);
  374. int rval;
  375. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  376. if (!scp)
  377. return -ENOMEM;
  378. scp->device = sdev;
  379. /* use request field to save the ptr. to completion struct. */
  380. scp->request = (struct request *)&wait;
  381. scp->timeout_per_command = timeout*HZ;
  382. scp->request_buffer = gdtcmd;
  383. scp->cmd_len = 12;
  384. memcpy(scp->cmnd, cmnd, 12);
  385. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  386. scp->underflow = GDTH_MAGIC;
  387. gdth_queuecommand(scp, NULL);
  388. wait_for_completion(&wait);
  389. rval = scp->SCp.Status;
  390. if (info)
  391. *info = scp->SCp.Message;
  392. kfree(scp);
  393. return rval;
  394. }
  395. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  396. int timeout, u32 *info)
  397. {
  398. struct scsi_device *sdev = scsi_get_host_dev(shost);
  399. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  400. scsi_free_host_dev(sdev);
  401. return rval;
  402. }
  403. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  404. {
  405. *cyls = size /HEADS/SECS;
  406. if (*cyls <= MAXCYLS) {
  407. *heads = HEADS;
  408. *secs = SECS;
  409. } else { /* too high for 64*32 */
  410. *cyls = size /MEDHEADS/MEDSECS;
  411. if (*cyls <= MAXCYLS) {
  412. *heads = MEDHEADS;
  413. *secs = MEDSECS;
  414. } else { /* too high for 127*63 */
  415. *cyls = size /BIGHEADS/BIGSECS;
  416. *heads = BIGHEADS;
  417. *secs = BIGSECS;
  418. }
  419. }
  420. }
  421. /* controller search and initialization functions */
  422. #ifdef CONFIG_EISA
  423. static int __init gdth_search_eisa(ushort eisa_adr)
  424. {
  425. ulong32 id;
  426. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  427. id = inl(eisa_adr+ID0REG);
  428. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  429. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  430. return 0; /* not EISA configured */
  431. return 1;
  432. }
  433. if (id == GDT3_ID) /* GDT3000 */
  434. return 1;
  435. return 0;
  436. }
  437. #endif /* CONFIG_EISA */
  438. #ifdef CONFIG_ISA
  439. static int __init gdth_search_isa(ulong32 bios_adr)
  440. {
  441. void __iomem *addr;
  442. ulong32 id;
  443. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  444. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  445. id = readl(addr);
  446. iounmap(addr);
  447. if (id == GDT2_ID) /* GDT2000 */
  448. return 1;
  449. }
  450. return 0;
  451. }
  452. #endif /* CONFIG_ISA */
  453. #ifdef CONFIG_PCI
  454. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  455. ushort vendor, ushort dev);
  456. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  457. {
  458. ushort device, cnt;
  459. TRACE(("gdth_search_pci()\n"));
  460. cnt = 0;
  461. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  462. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  463. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  464. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  465. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  466. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  467. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  468. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  469. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  470. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  471. PCI_DEVICE_ID_INTEL_SRC);
  472. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  473. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  474. return cnt;
  475. }
  476. /* Vortex only makes RAID controllers.
  477. * We do not really want to specify all 550 ids here, so wildcard match.
  478. */
  479. static struct pci_device_id gdthtable[] __maybe_unused = {
  480. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  481. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  482. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  483. {0}
  484. };
  485. MODULE_DEVICE_TABLE(pci,gdthtable);
  486. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  487. ushort vendor, ushort device)
  488. {
  489. ulong base0, base1, base2;
  490. struct pci_dev *pdev;
  491. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  492. *cnt, vendor, device));
  493. pdev = NULL;
  494. while ((pdev = pci_find_device(vendor, device, pdev))
  495. != NULL) {
  496. if (pci_enable_device(pdev))
  497. continue;
  498. if (*cnt >= MAXHA)
  499. return;
  500. /* GDT PCI controller found, resources are already in pdev */
  501. pcistr[*cnt].pdev = pdev;
  502. pcistr[*cnt].irq = pdev->irq;
  503. base0 = pci_resource_flags(pdev, 0);
  504. base1 = pci_resource_flags(pdev, 1);
  505. base2 = pci_resource_flags(pdev, 2);
  506. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  507. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  508. if (!(base0 & IORESOURCE_MEM))
  509. continue;
  510. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  511. } else { /* GDT6110, GDT6120, .. */
  512. if (!(base0 & IORESOURCE_MEM) ||
  513. !(base2 & IORESOURCE_MEM) ||
  514. !(base1 & IORESOURCE_IO))
  515. continue;
  516. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  517. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  518. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  519. }
  520. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  521. pcistr[*cnt].pdev->bus->number,
  522. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  523. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  524. (*cnt)++;
  525. }
  526. }
  527. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  528. {
  529. gdth_pci_str temp;
  530. int i, changed;
  531. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  532. if (cnt == 0)
  533. return;
  534. do {
  535. changed = FALSE;
  536. for (i = 0; i < cnt-1; ++i) {
  537. if (!reverse_scan) {
  538. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  539. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  540. PCI_SLOT(pcistr[i].pdev->devfn) >
  541. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  542. temp = pcistr[i];
  543. pcistr[i] = pcistr[i+1];
  544. pcistr[i+1] = temp;
  545. changed = TRUE;
  546. }
  547. } else {
  548. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  549. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  550. PCI_SLOT(pcistr[i].pdev->devfn) <
  551. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  552. temp = pcistr[i];
  553. pcistr[i] = pcistr[i+1];
  554. pcistr[i+1] = temp;
  555. changed = TRUE;
  556. }
  557. }
  558. }
  559. } while (changed);
  560. }
  561. #endif /* CONFIG_PCI */
  562. #ifdef CONFIG_EISA
  563. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  564. {
  565. ulong32 retries,id;
  566. unchar prot_ver,eisacf,i,irq_found;
  567. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  568. /* disable board interrupts, deinitialize services */
  569. outb(0xff,eisa_adr+EDOORREG);
  570. outb(0x00,eisa_adr+EDENABREG);
  571. outb(0x00,eisa_adr+EINTENABREG);
  572. outb(0xff,eisa_adr+LDOORREG);
  573. retries = INIT_RETRIES;
  574. gdth_delay(20);
  575. while (inb(eisa_adr+EDOORREG) != 0xff) {
  576. if (--retries == 0) {
  577. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  578. return 0;
  579. }
  580. gdth_delay(1);
  581. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  582. }
  583. prot_ver = inb(eisa_adr+MAILBOXREG);
  584. outb(0xff,eisa_adr+EDOORREG);
  585. if (prot_ver != PROTOCOL_VERSION) {
  586. printk("GDT-EISA: Illegal protocol version\n");
  587. return 0;
  588. }
  589. ha->bmic = eisa_adr;
  590. ha->brd_phys = (ulong32)eisa_adr >> 12;
  591. outl(0,eisa_adr+MAILBOXREG);
  592. outl(0,eisa_adr+MAILBOXREG+4);
  593. outl(0,eisa_adr+MAILBOXREG+8);
  594. outl(0,eisa_adr+MAILBOXREG+12);
  595. /* detect IRQ */
  596. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  597. ha->oem_id = OEM_ID_ICP;
  598. ha->type = GDT_EISA;
  599. ha->stype = id;
  600. outl(1,eisa_adr+MAILBOXREG+8);
  601. outb(0xfe,eisa_adr+LDOORREG);
  602. retries = INIT_RETRIES;
  603. gdth_delay(20);
  604. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  605. if (--retries == 0) {
  606. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  607. return 0;
  608. }
  609. gdth_delay(1);
  610. }
  611. ha->irq = inb(eisa_adr+MAILBOXREG);
  612. outb(0xff,eisa_adr+EDOORREG);
  613. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  614. /* check the result */
  615. if (ha->irq == 0) {
  616. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  617. for (i = 0, irq_found = FALSE;
  618. i < MAXHA && irq[i] != 0xff; ++i) {
  619. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  620. irq_found = TRUE;
  621. break;
  622. }
  623. }
  624. if (irq_found) {
  625. ha->irq = irq[i];
  626. irq[i] = 0;
  627. printk("GDT-EISA: Can not detect controller IRQ,\n");
  628. printk("Use IRQ setting from command line (IRQ = %d)\n",
  629. ha->irq);
  630. } else {
  631. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  632. printk("the controller BIOS or use command line parameters\n");
  633. return 0;
  634. }
  635. }
  636. } else {
  637. eisacf = inb(eisa_adr+EISAREG) & 7;
  638. if (eisacf > 4) /* level triggered */
  639. eisacf -= 4;
  640. ha->irq = gdth_irq_tab[eisacf];
  641. ha->oem_id = OEM_ID_ICP;
  642. ha->type = GDT_EISA;
  643. ha->stype = id;
  644. }
  645. ha->dma64_support = 0;
  646. return 1;
  647. }
  648. #endif /* CONFIG_EISA */
  649. #ifdef CONFIG_ISA
  650. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  651. {
  652. register gdt2_dpram_str __iomem *dp2_ptr;
  653. int i;
  654. unchar irq_drq,prot_ver;
  655. ulong32 retries;
  656. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  657. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  658. if (ha->brd == NULL) {
  659. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  660. return 0;
  661. }
  662. dp2_ptr = ha->brd;
  663. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  664. /* reset interface area */
  665. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  666. if (readl(&dp2_ptr->u) != 0) {
  667. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  668. iounmap(ha->brd);
  669. return 0;
  670. }
  671. /* disable board interrupts, read DRQ and IRQ */
  672. writeb(0xff, &dp2_ptr->io.irqdel);
  673. writeb(0x00, &dp2_ptr->io.irqen);
  674. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  675. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  676. irq_drq = readb(&dp2_ptr->io.rq);
  677. for (i=0; i<3; ++i) {
  678. if ((irq_drq & 1)==0)
  679. break;
  680. irq_drq >>= 1;
  681. }
  682. ha->drq = gdth_drq_tab[i];
  683. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  684. for (i=1; i<5; ++i) {
  685. if ((irq_drq & 1)==0)
  686. break;
  687. irq_drq >>= 1;
  688. }
  689. ha->irq = gdth_irq_tab[i];
  690. /* deinitialize services */
  691. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  692. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  693. writeb(0, &dp2_ptr->io.event);
  694. retries = INIT_RETRIES;
  695. gdth_delay(20);
  696. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  697. if (--retries == 0) {
  698. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  699. iounmap(ha->brd);
  700. return 0;
  701. }
  702. gdth_delay(1);
  703. }
  704. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  705. writeb(0, &dp2_ptr->u.ic.Status);
  706. writeb(0xff, &dp2_ptr->io.irqdel);
  707. if (prot_ver != PROTOCOL_VERSION) {
  708. printk("GDT-ISA: Illegal protocol version\n");
  709. iounmap(ha->brd);
  710. return 0;
  711. }
  712. ha->oem_id = OEM_ID_ICP;
  713. ha->type = GDT_ISA;
  714. ha->ic_all_size = sizeof(dp2_ptr->u);
  715. ha->stype= GDT2_ID;
  716. ha->brd_phys = bios_adr >> 4;
  717. /* special request to controller BIOS */
  718. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  719. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  720. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  721. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  722. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  723. writeb(0, &dp2_ptr->io.event);
  724. retries = INIT_RETRIES;
  725. gdth_delay(20);
  726. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  727. if (--retries == 0) {
  728. printk("GDT-ISA: Initialization error\n");
  729. iounmap(ha->brd);
  730. return 0;
  731. }
  732. gdth_delay(1);
  733. }
  734. writeb(0, &dp2_ptr->u.ic.Status);
  735. writeb(0xff, &dp2_ptr->io.irqdel);
  736. ha->dma64_support = 0;
  737. return 1;
  738. }
  739. #endif /* CONFIG_ISA */
  740. #ifdef CONFIG_PCI
  741. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  742. {
  743. register gdt6_dpram_str __iomem *dp6_ptr;
  744. register gdt6c_dpram_str __iomem *dp6c_ptr;
  745. register gdt6m_dpram_str __iomem *dp6m_ptr;
  746. ulong32 retries;
  747. unchar prot_ver;
  748. ushort command;
  749. int i, found = FALSE;
  750. TRACE(("gdth_init_pci()\n"));
  751. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  752. ha->oem_id = OEM_ID_INTEL;
  753. else
  754. ha->oem_id = OEM_ID_ICP;
  755. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  756. ha->stype = (ulong32)pcistr->pdev->device;
  757. ha->irq = pcistr->irq;
  758. ha->pdev = pcistr->pdev;
  759. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  760. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  761. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  762. if (ha->brd == NULL) {
  763. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  764. return 0;
  765. }
  766. /* check and reset interface area */
  767. dp6_ptr = ha->brd;
  768. writel(DPMEM_MAGIC, &dp6_ptr->u);
  769. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  770. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  771. pcistr->dpmem);
  772. found = FALSE;
  773. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  774. iounmap(ha->brd);
  775. ha->brd = ioremap(i, sizeof(ushort));
  776. if (ha->brd == NULL) {
  777. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  778. return 0;
  779. }
  780. if (readw(ha->brd) != 0xffff) {
  781. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  782. continue;
  783. }
  784. iounmap(ha->brd);
  785. pci_write_config_dword(pcistr->pdev,
  786. PCI_BASE_ADDRESS_0, i);
  787. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  788. if (ha->brd == NULL) {
  789. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  790. return 0;
  791. }
  792. dp6_ptr = ha->brd;
  793. writel(DPMEM_MAGIC, &dp6_ptr->u);
  794. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  795. printk("GDT-PCI: Use free address at 0x%x\n", i);
  796. found = TRUE;
  797. break;
  798. }
  799. }
  800. if (!found) {
  801. printk("GDT-PCI: No free address found!\n");
  802. iounmap(ha->brd);
  803. return 0;
  804. }
  805. }
  806. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  807. if (readl(&dp6_ptr->u) != 0) {
  808. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  809. iounmap(ha->brd);
  810. return 0;
  811. }
  812. /* disable board interrupts, deinit services */
  813. writeb(0xff, &dp6_ptr->io.irqdel);
  814. writeb(0x00, &dp6_ptr->io.irqen);
  815. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  816. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  817. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  818. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  819. writeb(0, &dp6_ptr->io.event);
  820. retries = INIT_RETRIES;
  821. gdth_delay(20);
  822. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  823. if (--retries == 0) {
  824. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  825. iounmap(ha->brd);
  826. return 0;
  827. }
  828. gdth_delay(1);
  829. }
  830. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  831. writeb(0, &dp6_ptr->u.ic.S_Status);
  832. writeb(0xff, &dp6_ptr->io.irqdel);
  833. if (prot_ver != PROTOCOL_VERSION) {
  834. printk("GDT-PCI: Illegal protocol version\n");
  835. iounmap(ha->brd);
  836. return 0;
  837. }
  838. ha->type = GDT_PCI;
  839. ha->ic_all_size = sizeof(dp6_ptr->u);
  840. /* special command to controller BIOS */
  841. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  842. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  843. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  844. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  845. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  846. writeb(0, &dp6_ptr->io.event);
  847. retries = INIT_RETRIES;
  848. gdth_delay(20);
  849. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  850. if (--retries == 0) {
  851. printk("GDT-PCI: Initialization error\n");
  852. iounmap(ha->brd);
  853. return 0;
  854. }
  855. gdth_delay(1);
  856. }
  857. writeb(0, &dp6_ptr->u.ic.S_Status);
  858. writeb(0xff, &dp6_ptr->io.irqdel);
  859. ha->dma64_support = 0;
  860. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  861. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  862. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  863. pcistr->dpmem,ha->irq));
  864. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  865. if (ha->brd == NULL) {
  866. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  867. iounmap(ha->brd);
  868. return 0;
  869. }
  870. /* check and reset interface area */
  871. dp6c_ptr = ha->brd;
  872. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  873. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  874. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  875. pcistr->dpmem);
  876. found = FALSE;
  877. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  878. iounmap(ha->brd);
  879. ha->brd = ioremap(i, sizeof(ushort));
  880. if (ha->brd == NULL) {
  881. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  882. return 0;
  883. }
  884. if (readw(ha->brd) != 0xffff) {
  885. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  886. continue;
  887. }
  888. iounmap(ha->brd);
  889. pci_write_config_dword(pcistr->pdev,
  890. PCI_BASE_ADDRESS_2, i);
  891. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  892. if (ha->brd == NULL) {
  893. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  894. return 0;
  895. }
  896. dp6c_ptr = ha->brd;
  897. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  898. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  899. printk("GDT-PCI: Use free address at 0x%x\n", i);
  900. found = TRUE;
  901. break;
  902. }
  903. }
  904. if (!found) {
  905. printk("GDT-PCI: No free address found!\n");
  906. iounmap(ha->brd);
  907. return 0;
  908. }
  909. }
  910. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  911. if (readl(&dp6c_ptr->u) != 0) {
  912. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  913. iounmap(ha->brd);
  914. return 0;
  915. }
  916. /* disable board interrupts, deinit services */
  917. outb(0x00,PTR2USHORT(&ha->plx->control1));
  918. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  919. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  920. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  921. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  922. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  923. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  924. retries = INIT_RETRIES;
  925. gdth_delay(20);
  926. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  927. if (--retries == 0) {
  928. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  929. iounmap(ha->brd);
  930. return 0;
  931. }
  932. gdth_delay(1);
  933. }
  934. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  935. writeb(0, &dp6c_ptr->u.ic.Status);
  936. if (prot_ver != PROTOCOL_VERSION) {
  937. printk("GDT-PCI: Illegal protocol version\n");
  938. iounmap(ha->brd);
  939. return 0;
  940. }
  941. ha->type = GDT_PCINEW;
  942. ha->ic_all_size = sizeof(dp6c_ptr->u);
  943. /* special command to controller BIOS */
  944. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  945. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  946. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  947. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  948. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  949. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  950. retries = INIT_RETRIES;
  951. gdth_delay(20);
  952. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  953. if (--retries == 0) {
  954. printk("GDT-PCI: Initialization error\n");
  955. iounmap(ha->brd);
  956. return 0;
  957. }
  958. gdth_delay(1);
  959. }
  960. writeb(0, &dp6c_ptr->u.ic.S_Status);
  961. ha->dma64_support = 0;
  962. } else { /* MPR */
  963. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  964. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  965. if (ha->brd == NULL) {
  966. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  967. return 0;
  968. }
  969. /* manipulate config. space to enable DPMEM, start RP controller */
  970. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  971. command |= 6;
  972. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  973. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  974. pci_resource_start(pcistr->pdev, 8) = 0UL;
  975. i = 0xFEFF0001UL;
  976. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  977. gdth_delay(1);
  978. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  979. pci_resource_start(pcistr->pdev, 8));
  980. dp6m_ptr = ha->brd;
  981. /* Ensure that it is safe to access the non HW portions of DPMEM.
  982. * Aditional check needed for Xscale based RAID controllers */
  983. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  984. gdth_delay(1);
  985. /* check and reset interface area */
  986. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  987. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  988. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  989. pcistr->dpmem);
  990. found = FALSE;
  991. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  992. iounmap(ha->brd);
  993. ha->brd = ioremap(i, sizeof(ushort));
  994. if (ha->brd == NULL) {
  995. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  996. return 0;
  997. }
  998. if (readw(ha->brd) != 0xffff) {
  999. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1000. continue;
  1001. }
  1002. iounmap(ha->brd);
  1003. pci_write_config_dword(pcistr->pdev,
  1004. PCI_BASE_ADDRESS_0, i);
  1005. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1006. if (ha->brd == NULL) {
  1007. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1008. return 0;
  1009. }
  1010. dp6m_ptr = ha->brd;
  1011. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1012. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1013. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1014. found = TRUE;
  1015. break;
  1016. }
  1017. }
  1018. if (!found) {
  1019. printk("GDT-PCI: No free address found!\n");
  1020. iounmap(ha->brd);
  1021. return 0;
  1022. }
  1023. }
  1024. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1025. /* disable board interrupts, deinit services */
  1026. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1027. &dp6m_ptr->i960r.edoor_en_reg);
  1028. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1029. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1030. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1031. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1032. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1033. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1034. retries = INIT_RETRIES;
  1035. gdth_delay(20);
  1036. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1037. if (--retries == 0) {
  1038. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1039. iounmap(ha->brd);
  1040. return 0;
  1041. }
  1042. gdth_delay(1);
  1043. }
  1044. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1045. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1046. if (prot_ver != PROTOCOL_VERSION) {
  1047. printk("GDT-PCI: Illegal protocol version\n");
  1048. iounmap(ha->brd);
  1049. return 0;
  1050. }
  1051. ha->type = GDT_PCIMPR;
  1052. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1053. /* special command to controller BIOS */
  1054. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1055. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1056. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1057. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1058. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1059. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1060. retries = INIT_RETRIES;
  1061. gdth_delay(20);
  1062. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1063. if (--retries == 0) {
  1064. printk("GDT-PCI: Initialization error\n");
  1065. iounmap(ha->brd);
  1066. return 0;
  1067. }
  1068. gdth_delay(1);
  1069. }
  1070. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1071. /* read FW version to detect 64-bit DMA support */
  1072. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1073. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1074. retries = INIT_RETRIES;
  1075. gdth_delay(20);
  1076. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1077. if (--retries == 0) {
  1078. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1079. iounmap(ha->brd);
  1080. return 0;
  1081. }
  1082. gdth_delay(1);
  1083. }
  1084. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1085. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1086. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1087. ha->dma64_support = 0;
  1088. else
  1089. ha->dma64_support = 1;
  1090. }
  1091. return 1;
  1092. }
  1093. #endif /* CONFIG_PCI */
  1094. /* controller protocol functions */
  1095. static void __init gdth_enable_int(gdth_ha_str *ha)
  1096. {
  1097. ulong flags;
  1098. gdt2_dpram_str __iomem *dp2_ptr;
  1099. gdt6_dpram_str __iomem *dp6_ptr;
  1100. gdt6m_dpram_str __iomem *dp6m_ptr;
  1101. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1102. spin_lock_irqsave(&ha->smp_lock, flags);
  1103. if (ha->type == GDT_EISA) {
  1104. outb(0xff, ha->bmic + EDOORREG);
  1105. outb(0xff, ha->bmic + EDENABREG);
  1106. outb(0x01, ha->bmic + EINTENABREG);
  1107. } else if (ha->type == GDT_ISA) {
  1108. dp2_ptr = ha->brd;
  1109. writeb(1, &dp2_ptr->io.irqdel);
  1110. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1111. writeb(1, &dp2_ptr->io.irqen);
  1112. } else if (ha->type == GDT_PCI) {
  1113. dp6_ptr = ha->brd;
  1114. writeb(1, &dp6_ptr->io.irqdel);
  1115. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1116. writeb(1, &dp6_ptr->io.irqen);
  1117. } else if (ha->type == GDT_PCINEW) {
  1118. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1119. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1120. } else if (ha->type == GDT_PCIMPR) {
  1121. dp6m_ptr = ha->brd;
  1122. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1123. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1124. &dp6m_ptr->i960r.edoor_en_reg);
  1125. }
  1126. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1127. }
  1128. /* return IStatus if interrupt was from this card else 0 */
  1129. static unchar gdth_get_status(gdth_ha_str *ha, int irq)
  1130. {
  1131. unchar IStatus = 0;
  1132. TRACE(("gdth_get_status() irq %d ctr_count %d\n", irq, gdth_ctr_count));
  1133. if (ha->irq != (unchar)irq) /* check IRQ */
  1134. return false;
  1135. if (ha->type == GDT_EISA)
  1136. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1137. else if (ha->type == GDT_ISA)
  1138. IStatus =
  1139. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1140. else if (ha->type == GDT_PCI)
  1141. IStatus =
  1142. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1143. else if (ha->type == GDT_PCINEW)
  1144. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1145. else if (ha->type == GDT_PCIMPR)
  1146. IStatus =
  1147. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1148. return IStatus;
  1149. }
  1150. static int gdth_test_busy(gdth_ha_str *ha)
  1151. {
  1152. register int gdtsema0 = 0;
  1153. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1154. if (ha->type == GDT_EISA)
  1155. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1156. else if (ha->type == GDT_ISA)
  1157. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1158. else if (ha->type == GDT_PCI)
  1159. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1160. else if (ha->type == GDT_PCINEW)
  1161. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1162. else if (ha->type == GDT_PCIMPR)
  1163. gdtsema0 =
  1164. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1165. return (gdtsema0 & 1);
  1166. }
  1167. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1168. {
  1169. int i;
  1170. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1171. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1172. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1173. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1174. ha->cmd_tab[i].service = ha->pccb->Service;
  1175. ha->pccb->CommandIndex = (ulong32)i+2;
  1176. return (i+2);
  1177. }
  1178. }
  1179. return 0;
  1180. }
  1181. static void gdth_set_sema0(gdth_ha_str *ha)
  1182. {
  1183. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1184. if (ha->type == GDT_EISA) {
  1185. outb(1, ha->bmic + SEMA0REG);
  1186. } else if (ha->type == GDT_ISA) {
  1187. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1188. } else if (ha->type == GDT_PCI) {
  1189. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1190. } else if (ha->type == GDT_PCINEW) {
  1191. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1192. } else if (ha->type == GDT_PCIMPR) {
  1193. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1194. }
  1195. }
  1196. static void gdth_copy_command(gdth_ha_str *ha)
  1197. {
  1198. register gdth_cmd_str *cmd_ptr;
  1199. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1200. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1201. gdt6_dpram_str __iomem *dp6_ptr;
  1202. gdt2_dpram_str __iomem *dp2_ptr;
  1203. ushort cp_count,dp_offset,cmd_no;
  1204. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1205. cp_count = ha->cmd_len;
  1206. dp_offset= ha->cmd_offs_dpmem;
  1207. cmd_no = ha->cmd_cnt;
  1208. cmd_ptr = ha->pccb;
  1209. ++ha->cmd_cnt;
  1210. if (ha->type == GDT_EISA)
  1211. return; /* no DPMEM, no copy */
  1212. /* set cpcount dword aligned */
  1213. if (cp_count & 3)
  1214. cp_count += (4 - (cp_count & 3));
  1215. ha->cmd_offs_dpmem += cp_count;
  1216. /* set offset and service, copy command to DPMEM */
  1217. if (ha->type == GDT_ISA) {
  1218. dp2_ptr = ha->brd;
  1219. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1220. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1221. writew((ushort)cmd_ptr->Service,
  1222. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1223. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1224. } else if (ha->type == GDT_PCI) {
  1225. dp6_ptr = ha->brd;
  1226. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1227. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1228. writew((ushort)cmd_ptr->Service,
  1229. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1230. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1231. } else if (ha->type == GDT_PCINEW) {
  1232. dp6c_ptr = ha->brd;
  1233. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1234. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1235. writew((ushort)cmd_ptr->Service,
  1236. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1237. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1238. } else if (ha->type == GDT_PCIMPR) {
  1239. dp6m_ptr = ha->brd;
  1240. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1241. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1242. writew((ushort)cmd_ptr->Service,
  1243. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1244. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1245. }
  1246. }
  1247. static void gdth_release_event(gdth_ha_str *ha)
  1248. {
  1249. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1250. #ifdef GDTH_STATISTICS
  1251. {
  1252. ulong32 i,j;
  1253. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1254. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1255. ++i;
  1256. }
  1257. if (max_index < i) {
  1258. max_index = i;
  1259. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1260. }
  1261. }
  1262. #endif
  1263. if (ha->pccb->OpCode == GDT_INIT)
  1264. ha->pccb->Service |= 0x80;
  1265. if (ha->type == GDT_EISA) {
  1266. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1267. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1268. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1269. } else if (ha->type == GDT_ISA) {
  1270. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1271. } else if (ha->type == GDT_PCI) {
  1272. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1273. } else if (ha->type == GDT_PCINEW) {
  1274. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1275. } else if (ha->type == GDT_PCIMPR) {
  1276. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1277. }
  1278. }
  1279. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1280. {
  1281. int answer_found = FALSE;
  1282. int wait_index = 0;
  1283. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1284. if (index == 0)
  1285. return 1; /* no wait required */
  1286. do {
  1287. __gdth_interrupt(ha, (int)ha->irq, true, &wait_index);
  1288. if (wait_index == index) {
  1289. answer_found = TRUE;
  1290. break;
  1291. }
  1292. gdth_delay(1);
  1293. } while (--time);
  1294. while (gdth_test_busy(ha))
  1295. gdth_delay(0);
  1296. return (answer_found);
  1297. }
  1298. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1299. ulong32 p1, ulong64 p2, ulong64 p3)
  1300. {
  1301. register gdth_cmd_str *cmd_ptr;
  1302. int retries,index;
  1303. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1304. cmd_ptr = ha->pccb;
  1305. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1306. /* make command */
  1307. for (retries = INIT_RETRIES;;) {
  1308. cmd_ptr->Service = service;
  1309. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1310. if (!(index=gdth_get_cmd_index(ha))) {
  1311. TRACE(("GDT: No free command index found\n"));
  1312. return 0;
  1313. }
  1314. gdth_set_sema0(ha);
  1315. cmd_ptr->OpCode = opcode;
  1316. cmd_ptr->BoardNode = LOCALBOARD;
  1317. if (service == CACHESERVICE) {
  1318. if (opcode == GDT_IOCTL) {
  1319. cmd_ptr->u.ioctl.subfunc = p1;
  1320. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1321. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1322. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1323. } else {
  1324. if (ha->cache_feat & GDT_64BIT) {
  1325. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1326. cmd_ptr->u.cache64.BlockNo = p2;
  1327. } else {
  1328. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1329. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1330. }
  1331. }
  1332. } else if (service == SCSIRAWSERVICE) {
  1333. if (ha->raw_feat & GDT_64BIT) {
  1334. cmd_ptr->u.raw64.direction = p1;
  1335. cmd_ptr->u.raw64.bus = (unchar)p2;
  1336. cmd_ptr->u.raw64.target = (unchar)p3;
  1337. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1338. } else {
  1339. cmd_ptr->u.raw.direction = p1;
  1340. cmd_ptr->u.raw.bus = (unchar)p2;
  1341. cmd_ptr->u.raw.target = (unchar)p3;
  1342. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1343. }
  1344. } else if (service == SCREENSERVICE) {
  1345. if (opcode == GDT_REALTIME) {
  1346. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1347. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1348. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1349. }
  1350. }
  1351. ha->cmd_len = sizeof(gdth_cmd_str);
  1352. ha->cmd_offs_dpmem = 0;
  1353. ha->cmd_cnt = 0;
  1354. gdth_copy_command(ha);
  1355. gdth_release_event(ha);
  1356. gdth_delay(20);
  1357. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1358. printk("GDT: Initialization error (timeout service %d)\n",service);
  1359. return 0;
  1360. }
  1361. if (ha->status != S_BSY || --retries == 0)
  1362. break;
  1363. gdth_delay(1);
  1364. }
  1365. return (ha->status != S_OK ? 0:1);
  1366. }
  1367. /* search for devices */
  1368. static int __init gdth_search_drives(gdth_ha_str *ha)
  1369. {
  1370. ushort cdev_cnt, i;
  1371. int ok;
  1372. ulong32 bus_no, drv_cnt, drv_no, j;
  1373. gdth_getch_str *chn;
  1374. gdth_drlist_str *drl;
  1375. gdth_iochan_str *ioc;
  1376. gdth_raw_iochan_str *iocr;
  1377. gdth_arcdl_str *alst;
  1378. gdth_alist_str *alst2;
  1379. gdth_oem_str_ioctl *oemstr;
  1380. #ifdef INT_COAL
  1381. gdth_perf_modes *pmod;
  1382. #endif
  1383. #ifdef GDTH_RTC
  1384. unchar rtc[12];
  1385. ulong flags;
  1386. #endif
  1387. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1388. ok = 0;
  1389. /* initialize controller services, at first: screen service */
  1390. ha->screen_feat = 0;
  1391. if (!force_dma32) {
  1392. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1393. if (ok)
  1394. ha->screen_feat = GDT_64BIT;
  1395. }
  1396. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1397. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1398. if (!ok) {
  1399. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1400. ha->hanum, ha->status);
  1401. return 0;
  1402. }
  1403. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1404. #ifdef GDTH_RTC
  1405. /* read realtime clock info, send to controller */
  1406. /* 1. wait for the falling edge of update flag */
  1407. spin_lock_irqsave(&rtc_lock, flags);
  1408. for (j = 0; j < 1000000; ++j)
  1409. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1410. break;
  1411. for (j = 0; j < 1000000; ++j)
  1412. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1413. break;
  1414. /* 2. read info */
  1415. do {
  1416. for (j = 0; j < 12; ++j)
  1417. rtc[j] = CMOS_READ(j);
  1418. } while (rtc[0] != CMOS_READ(0));
  1419. spin_unlock_irqrestore(&rtc_lock, flags);
  1420. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1421. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1422. /* 3. send to controller firmware */
  1423. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1424. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1425. #endif
  1426. /* unfreeze all IOs */
  1427. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1428. /* initialize cache service */
  1429. ha->cache_feat = 0;
  1430. if (!force_dma32) {
  1431. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1432. 0, 0);
  1433. if (ok)
  1434. ha->cache_feat = GDT_64BIT;
  1435. }
  1436. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1437. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1438. if (!ok) {
  1439. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1440. ha->hanum, ha->status);
  1441. return 0;
  1442. }
  1443. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1444. cdev_cnt = (ushort)ha->info;
  1445. ha->fw_vers = ha->service;
  1446. #ifdef INT_COAL
  1447. if (ha->type == GDT_PCIMPR) {
  1448. /* set perf. modes */
  1449. pmod = (gdth_perf_modes *)ha->pscratch;
  1450. pmod->version = 1;
  1451. pmod->st_mode = 1; /* enable one status buffer */
  1452. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1453. pmod->st_buff_indx1 = COALINDEX;
  1454. pmod->st_buff_addr2 = 0;
  1455. pmod->st_buff_u_addr2 = 0;
  1456. pmod->st_buff_indx2 = 0;
  1457. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1458. pmod->cmd_mode = 0; // disable all cmd buffers
  1459. pmod->cmd_buff_addr1 = 0;
  1460. pmod->cmd_buff_u_addr1 = 0;
  1461. pmod->cmd_buff_indx1 = 0;
  1462. pmod->cmd_buff_addr2 = 0;
  1463. pmod->cmd_buff_u_addr2 = 0;
  1464. pmod->cmd_buff_indx2 = 0;
  1465. pmod->cmd_buff_size = 0;
  1466. pmod->reserved1 = 0;
  1467. pmod->reserved2 = 0;
  1468. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1469. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1470. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1471. }
  1472. }
  1473. #endif
  1474. /* detect number of buses - try new IOCTL */
  1475. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1476. iocr->hdr.version = 0xffffffff;
  1477. iocr->hdr.list_entries = MAXBUS;
  1478. iocr->hdr.first_chan = 0;
  1479. iocr->hdr.last_chan = MAXBUS-1;
  1480. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1481. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1482. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1483. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1484. ha->bus_cnt = iocr->hdr.chan_count;
  1485. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1486. if (iocr->list[bus_no].proc_id < MAXID)
  1487. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1488. else
  1489. ha->bus_id[bus_no] = 0xff;
  1490. }
  1491. } else {
  1492. /* old method */
  1493. chn = (gdth_getch_str *)ha->pscratch;
  1494. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1495. chn->channel_no = bus_no;
  1496. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1497. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1498. IO_CHANNEL | INVALID_CHANNEL,
  1499. sizeof(gdth_getch_str))) {
  1500. if (bus_no == 0) {
  1501. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1502. ha->hanum, ha->status);
  1503. return 0;
  1504. }
  1505. break;
  1506. }
  1507. if (chn->siop_id < MAXID)
  1508. ha->bus_id[bus_no] = chn->siop_id;
  1509. else
  1510. ha->bus_id[bus_no] = 0xff;
  1511. }
  1512. ha->bus_cnt = (unchar)bus_no;
  1513. }
  1514. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1515. /* read cache configuration */
  1516. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1517. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1518. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1519. ha->hanum, ha->status);
  1520. return 0;
  1521. }
  1522. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1523. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1524. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1525. ha->cpar.write_back,ha->cpar.block_size));
  1526. /* read board info and features */
  1527. ha->more_proc = FALSE;
  1528. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1529. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1530. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1531. sizeof(gdth_binfo_str));
  1532. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1533. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1534. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1535. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1536. ha->more_proc = TRUE;
  1537. }
  1538. } else {
  1539. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1540. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1541. }
  1542. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1543. /* read more informations */
  1544. if (ha->more_proc) {
  1545. /* physical drives, channel addresses */
  1546. ioc = (gdth_iochan_str *)ha->pscratch;
  1547. ioc->hdr.version = 0xffffffff;
  1548. ioc->hdr.list_entries = MAXBUS;
  1549. ioc->hdr.first_chan = 0;
  1550. ioc->hdr.last_chan = MAXBUS-1;
  1551. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1552. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1553. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1554. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1555. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1556. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1557. }
  1558. } else {
  1559. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1560. ha->raw[bus_no].address = IO_CHANNEL;
  1561. ha->raw[bus_no].local_no = bus_no;
  1562. }
  1563. }
  1564. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1565. chn = (gdth_getch_str *)ha->pscratch;
  1566. chn->channel_no = ha->raw[bus_no].local_no;
  1567. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1568. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1569. ha->raw[bus_no].address | INVALID_CHANNEL,
  1570. sizeof(gdth_getch_str))) {
  1571. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1572. TRACE2(("Channel %d: %d phys. drives\n",
  1573. bus_no,chn->drive_cnt));
  1574. }
  1575. if (ha->raw[bus_no].pdev_cnt > 0) {
  1576. drl = (gdth_drlist_str *)ha->pscratch;
  1577. drl->sc_no = ha->raw[bus_no].local_no;
  1578. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1579. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1580. SCSI_DR_LIST | L_CTRL_PATTERN,
  1581. ha->raw[bus_no].address | INVALID_CHANNEL,
  1582. sizeof(gdth_drlist_str))) {
  1583. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1584. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1585. } else {
  1586. ha->raw[bus_no].pdev_cnt = 0;
  1587. }
  1588. }
  1589. }
  1590. /* logical drives */
  1591. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1592. INVALID_CHANNEL,sizeof(ulong32))) {
  1593. drv_cnt = *(ulong32 *)ha->pscratch;
  1594. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1595. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1596. for (j = 0; j < drv_cnt; ++j) {
  1597. drv_no = ((ulong32 *)ha->pscratch)[j];
  1598. if (drv_no < MAX_LDRIVES) {
  1599. ha->hdr[drv_no].is_logdrv = TRUE;
  1600. TRACE2(("Drive %d is log. drive\n",drv_no));
  1601. }
  1602. }
  1603. }
  1604. alst = (gdth_arcdl_str *)ha->pscratch;
  1605. alst->entries_avail = MAX_LDRIVES;
  1606. alst->first_entry = 0;
  1607. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1608. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1609. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1610. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1611. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1612. for (j = 0; j < alst->entries_init; ++j) {
  1613. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1614. ha->hdr[j].is_master = alst->list[j].is_master;
  1615. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1616. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1617. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1618. }
  1619. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1620. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1621. 0, 35 * sizeof(gdth_alist_str))) {
  1622. for (j = 0; j < 35; ++j) {
  1623. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1624. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1625. ha->hdr[j].is_master = alst2->is_master;
  1626. ha->hdr[j].is_parity = alst2->is_parity;
  1627. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1628. ha->hdr[j].master_no = alst2->cd_handle;
  1629. }
  1630. }
  1631. }
  1632. }
  1633. /* initialize raw service */
  1634. ha->raw_feat = 0;
  1635. if (!force_dma32) {
  1636. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1637. if (ok)
  1638. ha->raw_feat = GDT_64BIT;
  1639. }
  1640. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1641. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1642. if (!ok) {
  1643. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1644. ha->hanum, ha->status);
  1645. return 0;
  1646. }
  1647. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1648. /* set/get features raw service (scatter/gather) */
  1649. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1650. 0, 0)) {
  1651. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1652. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1653. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1654. ha->info));
  1655. ha->raw_feat |= (ushort)ha->info;
  1656. }
  1657. }
  1658. /* set/get features cache service (equal to raw service) */
  1659. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1660. SCATTER_GATHER,0)) {
  1661. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1662. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1663. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1664. ha->info));
  1665. ha->cache_feat |= (ushort)ha->info;
  1666. }
  1667. }
  1668. /* reserve drives for raw service */
  1669. if (reserve_mode != 0) {
  1670. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1671. reserve_mode == 1 ? 1 : 3, 0, 0);
  1672. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1673. ha->status));
  1674. }
  1675. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1676. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1677. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1678. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1679. reserve_list[i], reserve_list[i+1],
  1680. reserve_list[i+2], reserve_list[i+3]));
  1681. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1682. reserve_list[i+1], reserve_list[i+2] |
  1683. (reserve_list[i+3] << 8))) {
  1684. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1685. ha->hanum, ha->status);
  1686. }
  1687. }
  1688. }
  1689. /* Determine OEM string using IOCTL */
  1690. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1691. oemstr->params.ctl_version = 0x01;
  1692. oemstr->params.buffer_size = sizeof(oemstr->text);
  1693. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1694. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1695. sizeof(gdth_oem_str_ioctl))) {
  1696. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1697. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1698. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1699. /* Save the Host Drive inquiry data */
  1700. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1701. sizeof(ha->oem_name));
  1702. } else {
  1703. /* Old method, based on PCI ID */
  1704. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1705. printk("GDT-HA %d: Name: %s\n",
  1706. ha->hanum, ha->binfo.type_string);
  1707. if (ha->oem_id == OEM_ID_INTEL)
  1708. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1709. else
  1710. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1711. }
  1712. /* scanning for host drives */
  1713. for (i = 0; i < cdev_cnt; ++i)
  1714. gdth_analyse_hdrive(ha, i);
  1715. TRACE(("gdth_search_drives() OK\n"));
  1716. return 1;
  1717. }
  1718. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1719. {
  1720. ulong32 drv_cyls;
  1721. int drv_hds, drv_secs;
  1722. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1723. if (hdrive >= MAX_HDRIVES)
  1724. return 0;
  1725. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1726. return 0;
  1727. ha->hdr[hdrive].present = TRUE;
  1728. ha->hdr[hdrive].size = ha->info;
  1729. /* evaluate mapping (sectors per head, heads per cylinder) */
  1730. ha->hdr[hdrive].size &= ~SECS32;
  1731. if (ha->info2 == 0) {
  1732. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1733. } else {
  1734. drv_hds = ha->info2 & 0xff;
  1735. drv_secs = (ha->info2 >> 8) & 0xff;
  1736. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1737. }
  1738. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1739. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1740. /* round size */
  1741. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1742. if (ha->cache_feat & GDT_64BIT) {
  1743. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1744. && ha->info2 != 0) {
  1745. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1746. }
  1747. }
  1748. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1749. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1750. /* get informations about device */
  1751. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1752. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1753. hdrive,ha->info));
  1754. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1755. }
  1756. /* cluster info */
  1757. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1758. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1759. hdrive,ha->info));
  1760. if (!shared_access)
  1761. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1762. }
  1763. /* R/W attributes */
  1764. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1765. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1766. hdrive,ha->info));
  1767. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1768. }
  1769. return 1;
  1770. }
  1771. /* command queueing/sending functions */
  1772. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1773. {
  1774. register Scsi_Cmnd *pscp;
  1775. register Scsi_Cmnd *nscp;
  1776. ulong flags;
  1777. unchar b, t;
  1778. TRACE(("gdth_putq() priority %d\n",priority));
  1779. spin_lock_irqsave(&ha->smp_lock, flags);
  1780. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  1781. scp->SCp.this_residual = (int)priority;
  1782. b = scp->device->channel;
  1783. t = scp->device->id;
  1784. if (priority >= DEFAULT_PRI) {
  1785. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1786. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1787. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1788. scp->SCp.buffers_residual = gdth_update_timeout(scp, 0);
  1789. }
  1790. }
  1791. }
  1792. if (ha->req_first==NULL) {
  1793. ha->req_first = scp; /* queue was empty */
  1794. scp->SCp.ptr = NULL;
  1795. } else { /* queue not empty */
  1796. pscp = ha->req_first;
  1797. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1798. /* priority: 0-highest,..,0xff-lowest */
  1799. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  1800. pscp = nscp;
  1801. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1802. }
  1803. pscp->SCp.ptr = (char *)scp;
  1804. scp->SCp.ptr = (char *)nscp;
  1805. }
  1806. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1807. #ifdef GDTH_STATISTICS
  1808. flags = 0;
  1809. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1810. ++flags;
  1811. if (max_rq < flags) {
  1812. max_rq = flags;
  1813. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1814. }
  1815. #endif
  1816. }
  1817. static void gdth_next(gdth_ha_str *ha)
  1818. {
  1819. register Scsi_Cmnd *pscp;
  1820. register Scsi_Cmnd *nscp;
  1821. unchar b, t, l, firsttime;
  1822. unchar this_cmd, next_cmd;
  1823. ulong flags = 0;
  1824. int cmd_index;
  1825. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1826. if (!gdth_polling)
  1827. spin_lock_irqsave(&ha->smp_lock, flags);
  1828. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1829. this_cmd = firsttime = TRUE;
  1830. next_cmd = gdth_polling ? FALSE:TRUE;
  1831. cmd_index = 0;
  1832. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1833. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1834. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1835. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  1836. b = nscp->device->channel;
  1837. t = nscp->device->id;
  1838. l = nscp->device->lun;
  1839. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  1840. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1841. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1842. continue;
  1843. }
  1844. } else
  1845. b = t = l = 0;
  1846. if (firsttime) {
  1847. if (gdth_test_busy(ha)) { /* controller busy ? */
  1848. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1849. if (!gdth_polling) {
  1850. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1851. return;
  1852. }
  1853. while (gdth_test_busy(ha))
  1854. gdth_delay(1);
  1855. }
  1856. firsttime = FALSE;
  1857. }
  1858. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  1859. if (nscp->SCp.phase == -1) {
  1860. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  1861. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1862. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1863. b, t, l));
  1864. /* TEST_UNIT_READY -> set scan mode */
  1865. if ((ha->scan_mode & 0x0f) == 0) {
  1866. if (b == 0 && t == 0 && l == 0) {
  1867. ha->scan_mode |= 1;
  1868. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1869. }
  1870. } else if ((ha->scan_mode & 0x0f) == 1) {
  1871. if (b == 0 && ((t == 0 && l == 1) ||
  1872. (t == 1 && l == 0))) {
  1873. nscp->SCp.sent_command = GDT_SCAN_START;
  1874. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1875. | SCSIRAWSERVICE;
  1876. ha->scan_mode = 0x12;
  1877. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1878. ha->scan_mode));
  1879. } else {
  1880. ha->scan_mode &= 0x10;
  1881. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1882. }
  1883. } else if (ha->scan_mode == 0x12) {
  1884. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1885. nscp->SCp.phase = SCSIRAWSERVICE;
  1886. nscp->SCp.sent_command = GDT_SCAN_END;
  1887. ha->scan_mode &= 0x10;
  1888. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1889. ha->scan_mode));
  1890. }
  1891. }
  1892. }
  1893. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1894. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1895. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1896. /* always GDT_CLUST_INFO! */
  1897. nscp->SCp.sent_command = GDT_CLUST_INFO;
  1898. }
  1899. }
  1900. }
  1901. if (nscp->SCp.sent_command != -1) {
  1902. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  1903. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1904. this_cmd = FALSE;
  1905. next_cmd = FALSE;
  1906. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  1907. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1908. this_cmd = FALSE;
  1909. next_cmd = FALSE;
  1910. } else {
  1911. memset((char*)nscp->sense_buffer,0,16);
  1912. nscp->sense_buffer[0] = 0x70;
  1913. nscp->sense_buffer[2] = NOT_READY;
  1914. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1915. if (!nscp->SCp.have_data_in)
  1916. nscp->SCp.have_data_in++;
  1917. else
  1918. gdth_scsi_done(nscp);
  1919. }
  1920. } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
  1921. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1922. this_cmd = FALSE;
  1923. next_cmd = FALSE;
  1924. } else if (b != ha->virt_bus) {
  1925. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1926. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1927. this_cmd = FALSE;
  1928. else
  1929. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1930. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1931. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1932. nscp->cmnd[0], b, t, l));
  1933. nscp->result = DID_BAD_TARGET << 16;
  1934. if (!nscp->SCp.have_data_in)
  1935. nscp->SCp.have_data_in++;
  1936. else
  1937. gdth_scsi_done(nscp);
  1938. } else {
  1939. switch (nscp->cmnd[0]) {
  1940. case TEST_UNIT_READY:
  1941. case INQUIRY:
  1942. case REQUEST_SENSE:
  1943. case READ_CAPACITY:
  1944. case VERIFY:
  1945. case START_STOP:
  1946. case MODE_SENSE:
  1947. case SERVICE_ACTION_IN:
  1948. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1949. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1950. nscp->cmnd[4],nscp->cmnd[5]));
  1951. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1952. /* return UNIT_ATTENTION */
  1953. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1954. nscp->cmnd[0], t));
  1955. ha->hdr[t].media_changed = FALSE;
  1956. memset((char*)nscp->sense_buffer,0,16);
  1957. nscp->sense_buffer[0] = 0x70;
  1958. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1959. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1960. if (!nscp->SCp.have_data_in)
  1961. nscp->SCp.have_data_in++;
  1962. else
  1963. gdth_scsi_done(nscp);
  1964. } else if (gdth_internal_cache_cmd(ha, nscp))
  1965. gdth_scsi_done(nscp);
  1966. break;
  1967. case ALLOW_MEDIUM_REMOVAL:
  1968. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1969. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1970. nscp->cmnd[4],nscp->cmnd[5]));
  1971. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1972. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1973. nscp->result = DID_OK << 16;
  1974. nscp->sense_buffer[0] = 0;
  1975. if (!nscp->SCp.have_data_in)
  1976. nscp->SCp.have_data_in++;
  1977. else
  1978. gdth_scsi_done(nscp);
  1979. } else {
  1980. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1981. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1982. nscp->cmnd[4],nscp->cmnd[3]));
  1983. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1984. this_cmd = FALSE;
  1985. }
  1986. break;
  1987. case RESERVE:
  1988. case RELEASE:
  1989. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  1990. "RESERVE" : "RELEASE"));
  1991. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1992. this_cmd = FALSE;
  1993. break;
  1994. case READ_6:
  1995. case WRITE_6:
  1996. case READ_10:
  1997. case WRITE_10:
  1998. case READ_16:
  1999. case WRITE_16:
  2000. if (ha->hdr[t].media_changed) {
  2001. /* return UNIT_ATTENTION */
  2002. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2003. nscp->cmnd[0], t));
  2004. ha->hdr[t].media_changed = FALSE;
  2005. memset((char*)nscp->sense_buffer,0,16);
  2006. nscp->sense_buffer[0] = 0x70;
  2007. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2008. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2009. if (!nscp->SCp.have_data_in)
  2010. nscp->SCp.have_data_in++;
  2011. else
  2012. gdth_scsi_done(nscp);
  2013. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2014. this_cmd = FALSE;
  2015. break;
  2016. default:
  2017. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2018. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2019. nscp->cmnd[4],nscp->cmnd[5]));
  2020. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2021. ha->hanum, nscp->cmnd[0]);
  2022. nscp->result = DID_ABORT << 16;
  2023. if (!nscp->SCp.have_data_in)
  2024. nscp->SCp.have_data_in++;
  2025. else
  2026. gdth_scsi_done(nscp);
  2027. break;
  2028. }
  2029. }
  2030. if (!this_cmd)
  2031. break;
  2032. if (nscp == ha->req_first)
  2033. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2034. else
  2035. pscp->SCp.ptr = nscp->SCp.ptr;
  2036. if (!next_cmd)
  2037. break;
  2038. }
  2039. if (ha->cmd_cnt > 0) {
  2040. gdth_release_event(ha);
  2041. }
  2042. if (!gdth_polling)
  2043. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2044. if (gdth_polling && ha->cmd_cnt > 0) {
  2045. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2046. printk("GDT-HA %d: Command %d timed out !\n",
  2047. ha->hanum, cmd_index);
  2048. }
  2049. }
  2050. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2051. char *buffer,ushort count)
  2052. {
  2053. ushort cpcount,i;
  2054. ushort cpsum,cpnow;
  2055. struct scatterlist *sl;
  2056. char *address;
  2057. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2058. if (scp->use_sg) {
  2059. sl = (struct scatterlist *)scp->request_buffer;
  2060. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2061. unsigned long flags;
  2062. cpnow = (ushort)sl->length;
  2063. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2064. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2065. if (cpsum+cpnow > cpcount)
  2066. cpnow = cpcount - cpsum;
  2067. cpsum += cpnow;
  2068. if (!sl->page) {
  2069. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2070. ha->hanum);
  2071. return;
  2072. }
  2073. local_irq_save(flags);
  2074. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2075. memcpy(address,buffer,cpnow);
  2076. flush_dcache_page(sl->page);
  2077. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2078. local_irq_restore(flags);
  2079. if (cpsum == cpcount)
  2080. break;
  2081. buffer += cpnow;
  2082. }
  2083. } else {
  2084. TRACE(("copy_internal() count %d\n",cpcount));
  2085. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2086. }
  2087. }
  2088. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2089. {
  2090. unchar t;
  2091. gdth_inq_data inq;
  2092. gdth_rdcap_data rdc;
  2093. gdth_sense_data sd;
  2094. gdth_modep_data mpd;
  2095. t = scp->device->id;
  2096. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2097. scp->cmnd[0],t));
  2098. scp->result = DID_OK << 16;
  2099. scp->sense_buffer[0] = 0;
  2100. switch (scp->cmnd[0]) {
  2101. case TEST_UNIT_READY:
  2102. case VERIFY:
  2103. case START_STOP:
  2104. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2105. break;
  2106. case INQUIRY:
  2107. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2108. t,ha->hdr[t].devtype));
  2109. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2110. /* you can here set all disks to removable, if you want to do
  2111. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2112. inq.modif_rmb = 0x00;
  2113. if ((ha->hdr[t].devtype & 1) ||
  2114. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2115. inq.modif_rmb = 0x80;
  2116. inq.version = 2;
  2117. inq.resp_aenc = 2;
  2118. inq.add_length= 32;
  2119. strcpy(inq.vendor,ha->oem_name);
  2120. sprintf(inq.product,"Host Drive #%02d",t);
  2121. strcpy(inq.revision," ");
  2122. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2123. break;
  2124. case REQUEST_SENSE:
  2125. TRACE2(("Request sense hdrive %d\n",t));
  2126. sd.errorcode = 0x70;
  2127. sd.segno = 0x00;
  2128. sd.key = NO_SENSE;
  2129. sd.info = 0;
  2130. sd.add_length= 0;
  2131. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2132. break;
  2133. case MODE_SENSE:
  2134. TRACE2(("Mode sense hdrive %d\n",t));
  2135. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2136. mpd.hd.data_length = sizeof(gdth_modep_data);
  2137. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2138. mpd.hd.bd_length = sizeof(mpd.bd);
  2139. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2140. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2141. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2142. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2143. break;
  2144. case READ_CAPACITY:
  2145. TRACE2(("Read capacity hdrive %d\n",t));
  2146. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2147. rdc.last_block_no = 0xffffffff;
  2148. else
  2149. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2150. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2151. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2152. break;
  2153. case SERVICE_ACTION_IN:
  2154. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2155. (ha->cache_feat & GDT_64BIT)) {
  2156. gdth_rdcap16_data rdc16;
  2157. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2158. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2159. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2160. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2161. sizeof(gdth_rdcap16_data));
  2162. } else {
  2163. scp->result = DID_ABORT << 16;
  2164. }
  2165. break;
  2166. default:
  2167. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2168. break;
  2169. }
  2170. if (!scp->SCp.have_data_in)
  2171. scp->SCp.have_data_in++;
  2172. else
  2173. return 1;
  2174. return 0;
  2175. }
  2176. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2177. {
  2178. register gdth_cmd_str *cmdp;
  2179. struct scatterlist *sl;
  2180. ulong32 cnt, blockcnt;
  2181. ulong64 no, blockno;
  2182. dma_addr_t phys_addr;
  2183. int i, cmd_index, read_write, sgcnt, mode64;
  2184. struct page *page;
  2185. ulong offset;
  2186. cmdp = ha->pccb;
  2187. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2188. scp->cmnd[0],scp->cmd_len,hdrive));
  2189. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2190. return 0;
  2191. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2192. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2193. not required, should not occur due to error return on
  2194. READ_CAPACITY_16 */
  2195. cmdp->Service = CACHESERVICE;
  2196. cmdp->RequestBuffer = scp;
  2197. /* search free command index */
  2198. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2199. TRACE(("GDT: No free command index found\n"));
  2200. return 0;
  2201. }
  2202. /* if it's the first command, set command semaphore */
  2203. if (ha->cmd_cnt == 0)
  2204. gdth_set_sema0(ha);
  2205. /* fill command */
  2206. read_write = 0;
  2207. if (scp->SCp.sent_command != -1)
  2208. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2209. else if (scp->cmnd[0] == RESERVE)
  2210. cmdp->OpCode = GDT_RESERVE_DRV;
  2211. else if (scp->cmnd[0] == RELEASE)
  2212. cmdp->OpCode = GDT_RELEASE_DRV;
  2213. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2214. if (scp->cmnd[4] & 1) /* prevent ? */
  2215. cmdp->OpCode = GDT_MOUNT;
  2216. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2217. cmdp->OpCode = GDT_UNMOUNT;
  2218. else
  2219. cmdp->OpCode = GDT_FLUSH;
  2220. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2221. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2222. ) {
  2223. read_write = 1;
  2224. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2225. (ha->cache_feat & GDT_WR_THROUGH)))
  2226. cmdp->OpCode = GDT_WRITE_THR;
  2227. else
  2228. cmdp->OpCode = GDT_WRITE;
  2229. } else {
  2230. read_write = 2;
  2231. cmdp->OpCode = GDT_READ;
  2232. }
  2233. cmdp->BoardNode = LOCALBOARD;
  2234. if (mode64) {
  2235. cmdp->u.cache64.DeviceNo = hdrive;
  2236. cmdp->u.cache64.BlockNo = 1;
  2237. cmdp->u.cache64.sg_canz = 0;
  2238. } else {
  2239. cmdp->u.cache.DeviceNo = hdrive;
  2240. cmdp->u.cache.BlockNo = 1;
  2241. cmdp->u.cache.sg_canz = 0;
  2242. }
  2243. if (read_write) {
  2244. if (scp->cmd_len == 16) {
  2245. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2246. blockno = be64_to_cpu(no);
  2247. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2248. blockcnt = be32_to_cpu(cnt);
  2249. } else if (scp->cmd_len == 10) {
  2250. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2251. blockno = be32_to_cpu(no);
  2252. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2253. blockcnt = be16_to_cpu(cnt);
  2254. } else {
  2255. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2256. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2257. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2258. }
  2259. if (mode64) {
  2260. cmdp->u.cache64.BlockNo = blockno;
  2261. cmdp->u.cache64.BlockCnt = blockcnt;
  2262. } else {
  2263. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2264. cmdp->u.cache.BlockCnt = blockcnt;
  2265. }
  2266. if (scp->use_sg) {
  2267. sl = (struct scatterlist *)scp->request_buffer;
  2268. sgcnt = scp->use_sg;
  2269. scp->SCp.Status = GDTH_MAP_SG;
  2270. scp->SCp.Message = (read_write == 1 ?
  2271. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2272. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2273. if (mode64) {
  2274. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2275. cmdp->u.cache64.sg_canz = sgcnt;
  2276. for (i=0; i<sgcnt; ++i,++sl) {
  2277. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2278. #ifdef GDTH_DMA_STATISTICS
  2279. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2280. ha->dma64_cnt++;
  2281. else
  2282. ha->dma32_cnt++;
  2283. #endif
  2284. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2285. }
  2286. } else {
  2287. cmdp->u.cache.DestAddr= 0xffffffff;
  2288. cmdp->u.cache.sg_canz = sgcnt;
  2289. for (i=0; i<sgcnt; ++i,++sl) {
  2290. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2291. #ifdef GDTH_DMA_STATISTICS
  2292. ha->dma32_cnt++;
  2293. #endif
  2294. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2295. }
  2296. }
  2297. #ifdef GDTH_STATISTICS
  2298. if (max_sg < (ulong32)sgcnt) {
  2299. max_sg = (ulong32)sgcnt;
  2300. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2301. }
  2302. #endif
  2303. } else if (scp->request_bufflen) {
  2304. scp->SCp.Status = GDTH_MAP_SINGLE;
  2305. scp->SCp.Message = (read_write == 1 ?
  2306. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2307. page = virt_to_page(scp->request_buffer);
  2308. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2309. phys_addr = pci_map_page(ha->pdev,page,offset,
  2310. scp->request_bufflen,scp->SCp.Message);
  2311. scp->SCp.dma_handle = phys_addr;
  2312. if (mode64) {
  2313. if (ha->cache_feat & SCATTER_GATHER) {
  2314. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2315. cmdp->u.cache64.sg_canz = 1;
  2316. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2317. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2318. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2319. } else {
  2320. cmdp->u.cache64.DestAddr = phys_addr;
  2321. cmdp->u.cache64.sg_canz= 0;
  2322. }
  2323. } else {
  2324. if (ha->cache_feat & SCATTER_GATHER) {
  2325. cmdp->u.cache.DestAddr = 0xffffffff;
  2326. cmdp->u.cache.sg_canz = 1;
  2327. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2328. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2329. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2330. } else {
  2331. cmdp->u.cache.DestAddr = phys_addr;
  2332. cmdp->u.cache.sg_canz= 0;
  2333. }
  2334. }
  2335. }
  2336. }
  2337. /* evaluate command size, check space */
  2338. if (mode64) {
  2339. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2340. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2341. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2342. cmdp->u.cache64.sg_lst[0].sg_len));
  2343. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2344. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2345. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2346. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2347. } else {
  2348. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2349. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2350. cmdp->u.cache.sg_lst[0].sg_ptr,
  2351. cmdp->u.cache.sg_lst[0].sg_len));
  2352. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2353. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2354. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2355. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2356. }
  2357. if (ha->cmd_len & 3)
  2358. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2359. if (ha->cmd_cnt > 0) {
  2360. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2361. ha->ic_all_size) {
  2362. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2363. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2364. return 0;
  2365. }
  2366. }
  2367. /* copy command */
  2368. gdth_copy_command(ha);
  2369. return cmd_index;
  2370. }
  2371. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2372. {
  2373. register gdth_cmd_str *cmdp;
  2374. struct scatterlist *sl;
  2375. ushort i;
  2376. dma_addr_t phys_addr, sense_paddr;
  2377. int cmd_index, sgcnt, mode64;
  2378. unchar t,l;
  2379. struct page *page;
  2380. ulong offset;
  2381. t = scp->device->id;
  2382. l = scp->device->lun;
  2383. cmdp = ha->pccb;
  2384. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2385. scp->cmnd[0],b,t,l));
  2386. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2387. return 0;
  2388. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2389. cmdp->Service = SCSIRAWSERVICE;
  2390. cmdp->RequestBuffer = scp;
  2391. /* search free command index */
  2392. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2393. TRACE(("GDT: No free command index found\n"));
  2394. return 0;
  2395. }
  2396. /* if it's the first command, set command semaphore */
  2397. if (ha->cmd_cnt == 0)
  2398. gdth_set_sema0(ha);
  2399. /* fill command */
  2400. if (scp->SCp.sent_command != -1) {
  2401. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2402. cmdp->BoardNode = LOCALBOARD;
  2403. if (mode64) {
  2404. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2405. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2406. cmdp->OpCode, cmdp->u.raw64.direction));
  2407. /* evaluate command size */
  2408. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2409. } else {
  2410. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2411. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2412. cmdp->OpCode, cmdp->u.raw.direction));
  2413. /* evaluate command size */
  2414. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2415. }
  2416. } else {
  2417. page = virt_to_page(scp->sense_buffer);
  2418. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2419. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2420. 16,PCI_DMA_FROMDEVICE);
  2421. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2422. /* high part, if 64bit */
  2423. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2424. cmdp->OpCode = GDT_WRITE; /* always */
  2425. cmdp->BoardNode = LOCALBOARD;
  2426. if (mode64) {
  2427. cmdp->u.raw64.reserved = 0;
  2428. cmdp->u.raw64.mdisc_time = 0;
  2429. cmdp->u.raw64.mcon_time = 0;
  2430. cmdp->u.raw64.clen = scp->cmd_len;
  2431. cmdp->u.raw64.target = t;
  2432. cmdp->u.raw64.lun = l;
  2433. cmdp->u.raw64.bus = b;
  2434. cmdp->u.raw64.priority = 0;
  2435. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2436. cmdp->u.raw64.sense_len = 16;
  2437. cmdp->u.raw64.sense_data = sense_paddr;
  2438. cmdp->u.raw64.direction =
  2439. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2440. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2441. cmdp->u.raw64.sg_ranz = 0;
  2442. } else {
  2443. cmdp->u.raw.reserved = 0;
  2444. cmdp->u.raw.mdisc_time = 0;
  2445. cmdp->u.raw.mcon_time = 0;
  2446. cmdp->u.raw.clen = scp->cmd_len;
  2447. cmdp->u.raw.target = t;
  2448. cmdp->u.raw.lun = l;
  2449. cmdp->u.raw.bus = b;
  2450. cmdp->u.raw.priority = 0;
  2451. cmdp->u.raw.link_p = 0;
  2452. cmdp->u.raw.sdlen = scp->request_bufflen;
  2453. cmdp->u.raw.sense_len = 16;
  2454. cmdp->u.raw.sense_data = sense_paddr;
  2455. cmdp->u.raw.direction =
  2456. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2457. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2458. cmdp->u.raw.sg_ranz = 0;
  2459. }
  2460. if (scp->use_sg) {
  2461. sl = (struct scatterlist *)scp->request_buffer;
  2462. sgcnt = scp->use_sg;
  2463. scp->SCp.Status = GDTH_MAP_SG;
  2464. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2465. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2466. if (mode64) {
  2467. cmdp->u.raw64.sdata = (ulong64)-1;
  2468. cmdp->u.raw64.sg_ranz = sgcnt;
  2469. for (i=0; i<sgcnt; ++i,++sl) {
  2470. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2471. #ifdef GDTH_DMA_STATISTICS
  2472. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2473. ha->dma64_cnt++;
  2474. else
  2475. ha->dma32_cnt++;
  2476. #endif
  2477. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2478. }
  2479. } else {
  2480. cmdp->u.raw.sdata = 0xffffffff;
  2481. cmdp->u.raw.sg_ranz = sgcnt;
  2482. for (i=0; i<sgcnt; ++i,++sl) {
  2483. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2484. #ifdef GDTH_DMA_STATISTICS
  2485. ha->dma32_cnt++;
  2486. #endif
  2487. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2488. }
  2489. }
  2490. #ifdef GDTH_STATISTICS
  2491. if (max_sg < sgcnt) {
  2492. max_sg = sgcnt;
  2493. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2494. }
  2495. #endif
  2496. } else if (scp->request_bufflen) {
  2497. scp->SCp.Status = GDTH_MAP_SINGLE;
  2498. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2499. page = virt_to_page(scp->request_buffer);
  2500. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2501. phys_addr = pci_map_page(ha->pdev,page,offset,
  2502. scp->request_bufflen,scp->SCp.Message);
  2503. scp->SCp.dma_handle = phys_addr;
  2504. if (mode64) {
  2505. if (ha->raw_feat & SCATTER_GATHER) {
  2506. cmdp->u.raw64.sdata = (ulong64)-1;
  2507. cmdp->u.raw64.sg_ranz= 1;
  2508. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2509. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2510. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2511. } else {
  2512. cmdp->u.raw64.sdata = phys_addr;
  2513. cmdp->u.raw64.sg_ranz= 0;
  2514. }
  2515. } else {
  2516. if (ha->raw_feat & SCATTER_GATHER) {
  2517. cmdp->u.raw.sdata = 0xffffffff;
  2518. cmdp->u.raw.sg_ranz= 1;
  2519. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2520. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2521. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2522. } else {
  2523. cmdp->u.raw.sdata = phys_addr;
  2524. cmdp->u.raw.sg_ranz= 0;
  2525. }
  2526. }
  2527. }
  2528. if (mode64) {
  2529. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2530. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2531. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2532. cmdp->u.raw64.sg_lst[0].sg_len));
  2533. /* evaluate command size */
  2534. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2535. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2536. } else {
  2537. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2538. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2539. cmdp->u.raw.sg_lst[0].sg_ptr,
  2540. cmdp->u.raw.sg_lst[0].sg_len));
  2541. /* evaluate command size */
  2542. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2543. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2544. }
  2545. }
  2546. /* check space */
  2547. if (ha->cmd_len & 3)
  2548. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2549. if (ha->cmd_cnt > 0) {
  2550. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2551. ha->ic_all_size) {
  2552. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2553. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2554. return 0;
  2555. }
  2556. }
  2557. /* copy command */
  2558. gdth_copy_command(ha);
  2559. return cmd_index;
  2560. }
  2561. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2562. {
  2563. register gdth_cmd_str *cmdp;
  2564. int cmd_index;
  2565. cmdp= ha->pccb;
  2566. TRACE2(("gdth_special_cmd(): "));
  2567. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2568. return 0;
  2569. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2570. cmdp->RequestBuffer = scp;
  2571. /* search free command index */
  2572. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2573. TRACE(("GDT: No free command index found\n"));
  2574. return 0;
  2575. }
  2576. /* if it's the first command, set command semaphore */
  2577. if (ha->cmd_cnt == 0)
  2578. gdth_set_sema0(ha);
  2579. /* evaluate command size, check space */
  2580. if (cmdp->OpCode == GDT_IOCTL) {
  2581. TRACE2(("IOCTL\n"));
  2582. ha->cmd_len =
  2583. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2584. } else if (cmdp->Service == CACHESERVICE) {
  2585. TRACE2(("cache command %d\n",cmdp->OpCode));
  2586. if (ha->cache_feat & GDT_64BIT)
  2587. ha->cmd_len =
  2588. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2589. else
  2590. ha->cmd_len =
  2591. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2592. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2593. TRACE2(("raw command %d\n",cmdp->OpCode));
  2594. if (ha->raw_feat & GDT_64BIT)
  2595. ha->cmd_len =
  2596. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2597. else
  2598. ha->cmd_len =
  2599. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2600. }
  2601. if (ha->cmd_len & 3)
  2602. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2603. if (ha->cmd_cnt > 0) {
  2604. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2605. ha->ic_all_size) {
  2606. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2607. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2608. return 0;
  2609. }
  2610. }
  2611. /* copy command */
  2612. gdth_copy_command(ha);
  2613. return cmd_index;
  2614. }
  2615. /* Controller event handling functions */
  2616. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2617. ushort idx, gdth_evt_data *evt)
  2618. {
  2619. gdth_evt_str *e;
  2620. struct timeval tv;
  2621. /* no GDTH_LOCK_HA() ! */
  2622. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2623. if (source == 0) /* no source -> no event */
  2624. return NULL;
  2625. if (ebuffer[elastidx].event_source == source &&
  2626. ebuffer[elastidx].event_idx == idx &&
  2627. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2628. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2629. (char *)&evt->eu, evt->size)) ||
  2630. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2631. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2632. (char *)&evt->event_string)))) {
  2633. e = &ebuffer[elastidx];
  2634. do_gettimeofday(&tv);
  2635. e->last_stamp = tv.tv_sec;
  2636. ++e->same_count;
  2637. } else {
  2638. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2639. ++elastidx;
  2640. if (elastidx == MAX_EVENTS)
  2641. elastidx = 0;
  2642. if (elastidx == eoldidx) { /* reached mark ? */
  2643. ++eoldidx;
  2644. if (eoldidx == MAX_EVENTS)
  2645. eoldidx = 0;
  2646. }
  2647. }
  2648. e = &ebuffer[elastidx];
  2649. e->event_source = source;
  2650. e->event_idx = idx;
  2651. do_gettimeofday(&tv);
  2652. e->first_stamp = e->last_stamp = tv.tv_sec;
  2653. e->same_count = 1;
  2654. e->event_data = *evt;
  2655. e->application = 0;
  2656. }
  2657. return e;
  2658. }
  2659. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2660. {
  2661. gdth_evt_str *e;
  2662. int eindex;
  2663. ulong flags;
  2664. TRACE2(("gdth_read_event() handle %d\n", handle));
  2665. spin_lock_irqsave(&ha->smp_lock, flags);
  2666. if (handle == -1)
  2667. eindex = eoldidx;
  2668. else
  2669. eindex = handle;
  2670. estr->event_source = 0;
  2671. if (eindex >= MAX_EVENTS) {
  2672. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2673. return eindex;
  2674. }
  2675. e = &ebuffer[eindex];
  2676. if (e->event_source != 0) {
  2677. if (eindex != elastidx) {
  2678. if (++eindex == MAX_EVENTS)
  2679. eindex = 0;
  2680. } else {
  2681. eindex = -1;
  2682. }
  2683. memcpy(estr, e, sizeof(gdth_evt_str));
  2684. }
  2685. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2686. return eindex;
  2687. }
  2688. static void gdth_readapp_event(gdth_ha_str *ha,
  2689. unchar application, gdth_evt_str *estr)
  2690. {
  2691. gdth_evt_str *e;
  2692. int eindex;
  2693. ulong flags;
  2694. unchar found = FALSE;
  2695. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2696. spin_lock_irqsave(&ha->smp_lock, flags);
  2697. eindex = eoldidx;
  2698. for (;;) {
  2699. e = &ebuffer[eindex];
  2700. if (e->event_source == 0)
  2701. break;
  2702. if ((e->application & application) == 0) {
  2703. e->application |= application;
  2704. found = TRUE;
  2705. break;
  2706. }
  2707. if (eindex == elastidx)
  2708. break;
  2709. if (++eindex == MAX_EVENTS)
  2710. eindex = 0;
  2711. }
  2712. if (found)
  2713. memcpy(estr, e, sizeof(gdth_evt_str));
  2714. else
  2715. estr->event_source = 0;
  2716. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2717. }
  2718. static void gdth_clear_events(void)
  2719. {
  2720. TRACE(("gdth_clear_events()"));
  2721. eoldidx = elastidx = 0;
  2722. ebuffer[0].event_source = 0;
  2723. }
  2724. /* SCSI interface functions */
  2725. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
  2726. int gdth_from_wait, int* pIndex)
  2727. {
  2728. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2729. gdt6_dpram_str __iomem *dp6_ptr;
  2730. gdt2_dpram_str __iomem *dp2_ptr;
  2731. Scsi_Cmnd *scp;
  2732. int rval, i;
  2733. unchar IStatus;
  2734. ushort Service;
  2735. ulong flags = 0;
  2736. #ifdef INT_COAL
  2737. int coalesced = FALSE;
  2738. int next = FALSE;
  2739. gdth_coal_status *pcs = NULL;
  2740. int act_int_coal = 0;
  2741. #endif
  2742. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  2743. /* if polling and not from gdth_wait() -> return */
  2744. if (gdth_polling) {
  2745. if (!gdth_from_wait) {
  2746. return IRQ_HANDLED;
  2747. }
  2748. }
  2749. if (!gdth_polling)
  2750. spin_lock_irqsave(&ha->smp_lock, flags);
  2751. /* search controller */
  2752. if (0 == (IStatus = gdth_get_status(ha, irq))) {
  2753. /* spurious interrupt */
  2754. if (!gdth_polling)
  2755. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2756. return IRQ_HANDLED;
  2757. }
  2758. #ifdef GDTH_STATISTICS
  2759. ++act_ints;
  2760. #endif
  2761. #ifdef INT_COAL
  2762. /* See if the fw is returning coalesced status */
  2763. if (IStatus == COALINDEX) {
  2764. /* Coalesced status. Setup the initial status
  2765. buffer pointer and flags */
  2766. pcs = ha->coal_stat;
  2767. coalesced = TRUE;
  2768. next = TRUE;
  2769. }
  2770. do {
  2771. if (coalesced) {
  2772. /* For coalesced requests all status
  2773. information is found in the status buffer */
  2774. IStatus = (unchar)(pcs->status & 0xff);
  2775. }
  2776. #endif
  2777. if (ha->type == GDT_EISA) {
  2778. if (IStatus & 0x80) { /* error flag */
  2779. IStatus &= ~0x80;
  2780. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2781. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2782. } else /* no error */
  2783. ha->status = S_OK;
  2784. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2785. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2786. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2787. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2788. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2789. } else if (ha->type == GDT_ISA) {
  2790. dp2_ptr = ha->brd;
  2791. if (IStatus & 0x80) { /* error flag */
  2792. IStatus &= ~0x80;
  2793. ha->status = readw(&dp2_ptr->u.ic.Status);
  2794. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2795. } else /* no error */
  2796. ha->status = S_OK;
  2797. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2798. ha->service = readw(&dp2_ptr->u.ic.Service);
  2799. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2800. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2801. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2802. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2803. } else if (ha->type == GDT_PCI) {
  2804. dp6_ptr = ha->brd;
  2805. if (IStatus & 0x80) { /* error flag */
  2806. IStatus &= ~0x80;
  2807. ha->status = readw(&dp6_ptr->u.ic.Status);
  2808. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2809. } else /* no error */
  2810. ha->status = S_OK;
  2811. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2812. ha->service = readw(&dp6_ptr->u.ic.Service);
  2813. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2814. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2815. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2816. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2817. } else if (ha->type == GDT_PCINEW) {
  2818. if (IStatus & 0x80) { /* error flag */
  2819. IStatus &= ~0x80;
  2820. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2821. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2822. } else
  2823. ha->status = S_OK;
  2824. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2825. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2826. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2827. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2828. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2829. } else if (ha->type == GDT_PCIMPR) {
  2830. dp6m_ptr = ha->brd;
  2831. if (IStatus & 0x80) { /* error flag */
  2832. IStatus &= ~0x80;
  2833. #ifdef INT_COAL
  2834. if (coalesced)
  2835. ha->status = pcs->ext_status & 0xffff;
  2836. else
  2837. #endif
  2838. ha->status = readw(&dp6m_ptr->i960r.status);
  2839. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2840. } else /* no error */
  2841. ha->status = S_OK;
  2842. #ifdef INT_COAL
  2843. /* get information */
  2844. if (coalesced) {
  2845. ha->info = pcs->info0;
  2846. ha->info2 = pcs->info1;
  2847. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2848. } else
  2849. #endif
  2850. {
  2851. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2852. ha->service = readw(&dp6m_ptr->i960r.service);
  2853. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2854. }
  2855. /* event string */
  2856. if (IStatus == ASYNCINDEX) {
  2857. if (ha->service != SCREENSERVICE &&
  2858. (ha->fw_vers & 0xff) >= 0x1a) {
  2859. ha->dvr.severity = readb
  2860. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2861. for (i = 0; i < 256; ++i) {
  2862. ha->dvr.event_string[i] = readb
  2863. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2864. if (ha->dvr.event_string[i] == 0)
  2865. break;
  2866. }
  2867. }
  2868. }
  2869. #ifdef INT_COAL
  2870. /* Make sure that non coalesced interrupts get cleared
  2871. before being handled by gdth_async_event/gdth_sync_event */
  2872. if (!coalesced)
  2873. #endif
  2874. {
  2875. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2876. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2877. }
  2878. } else {
  2879. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2880. if (!gdth_polling)
  2881. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2882. return IRQ_HANDLED;
  2883. }
  2884. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2885. IStatus,ha->status,ha->info));
  2886. if (gdth_from_wait) {
  2887. *pIndex = (int)IStatus;
  2888. }
  2889. if (IStatus == ASYNCINDEX) {
  2890. TRACE2(("gdth_interrupt() async. event\n"));
  2891. gdth_async_event(ha);
  2892. if (!gdth_polling)
  2893. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2894. gdth_next(ha);
  2895. return IRQ_HANDLED;
  2896. }
  2897. if (IStatus == SPEZINDEX) {
  2898. TRACE2(("Service unknown or not initialized !\n"));
  2899. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2900. ha->dvr.eu.driver.ionode = ha->hanum;
  2901. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2902. if (!gdth_polling)
  2903. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2904. return IRQ_HANDLED;
  2905. }
  2906. scp = ha->cmd_tab[IStatus-2].cmnd;
  2907. Service = ha->cmd_tab[IStatus-2].service;
  2908. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2909. if (scp == UNUSED_CMND) {
  2910. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2911. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2912. ha->dvr.eu.driver.ionode = ha->hanum;
  2913. ha->dvr.eu.driver.index = IStatus;
  2914. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2915. if (!gdth_polling)
  2916. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2917. return IRQ_HANDLED;
  2918. }
  2919. if (scp == INTERNAL_CMND) {
  2920. TRACE(("gdth_interrupt() answer to internal command\n"));
  2921. if (!gdth_polling)
  2922. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2923. return IRQ_HANDLED;
  2924. }
  2925. TRACE(("gdth_interrupt() sync. status\n"));
  2926. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2927. if (!gdth_polling)
  2928. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2929. if (rval == 2) {
  2930. gdth_putq(ha, scp,scp->SCp.this_residual);
  2931. } else if (rval == 1) {
  2932. gdth_scsi_done(scp);
  2933. }
  2934. #ifdef INT_COAL
  2935. if (coalesced) {
  2936. /* go to the next status in the status buffer */
  2937. ++pcs;
  2938. #ifdef GDTH_STATISTICS
  2939. ++act_int_coal;
  2940. if (act_int_coal > max_int_coal) {
  2941. max_int_coal = act_int_coal;
  2942. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2943. }
  2944. #endif
  2945. /* see if there is another status */
  2946. if (pcs->status == 0)
  2947. /* Stop the coalesce loop */
  2948. next = FALSE;
  2949. }
  2950. } while (next);
  2951. /* coalescing only for new GDT_PCIMPR controllers available */
  2952. if (ha->type == GDT_PCIMPR && coalesced) {
  2953. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2954. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2955. }
  2956. #endif
  2957. gdth_next(ha);
  2958. return IRQ_HANDLED;
  2959. }
  2960. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2961. {
  2962. gdth_ha_str *ha = (gdth_ha_str *)dev_id;
  2963. return __gdth_interrupt(ha, irq, false, NULL);
  2964. }
  2965. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2966. Scsi_Cmnd *scp)
  2967. {
  2968. gdth_msg_str *msg;
  2969. gdth_cmd_str *cmdp;
  2970. unchar b, t;
  2971. cmdp = ha->pccb;
  2972. TRACE(("gdth_sync_event() serv %d status %d\n",
  2973. service,ha->status));
  2974. if (service == SCREENSERVICE) {
  2975. msg = ha->pmsg;
  2976. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2977. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2978. if (msg->msg_len > MSGLEN+1)
  2979. msg->msg_len = MSGLEN+1;
  2980. if (msg->msg_len)
  2981. if (!(msg->msg_answer && msg->msg_ext)) {
  2982. msg->msg_text[msg->msg_len] = '\0';
  2983. printk("%s",msg->msg_text);
  2984. }
  2985. if (msg->msg_ext && !msg->msg_answer) {
  2986. while (gdth_test_busy(ha))
  2987. gdth_delay(0);
  2988. cmdp->Service = SCREENSERVICE;
  2989. cmdp->RequestBuffer = SCREEN_CMND;
  2990. gdth_get_cmd_index(ha);
  2991. gdth_set_sema0(ha);
  2992. cmdp->OpCode = GDT_READ;
  2993. cmdp->BoardNode = LOCALBOARD;
  2994. cmdp->u.screen.reserved = 0;
  2995. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2996. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2997. ha->cmd_offs_dpmem = 0;
  2998. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2999. + sizeof(ulong64);
  3000. ha->cmd_cnt = 0;
  3001. gdth_copy_command(ha);
  3002. gdth_release_event(ha);
  3003. return 0;
  3004. }
  3005. if (msg->msg_answer && msg->msg_alen) {
  3006. /* default answers (getchar() not possible) */
  3007. if (msg->msg_alen == 1) {
  3008. msg->msg_alen = 0;
  3009. msg->msg_len = 1;
  3010. msg->msg_text[0] = 0;
  3011. } else {
  3012. msg->msg_alen -= 2;
  3013. msg->msg_len = 2;
  3014. msg->msg_text[0] = 1;
  3015. msg->msg_text[1] = 0;
  3016. }
  3017. msg->msg_ext = 0;
  3018. msg->msg_answer = 0;
  3019. while (gdth_test_busy(ha))
  3020. gdth_delay(0);
  3021. cmdp->Service = SCREENSERVICE;
  3022. cmdp->RequestBuffer = SCREEN_CMND;
  3023. gdth_get_cmd_index(ha);
  3024. gdth_set_sema0(ha);
  3025. cmdp->OpCode = GDT_WRITE;
  3026. cmdp->BoardNode = LOCALBOARD;
  3027. cmdp->u.screen.reserved = 0;
  3028. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3029. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3030. ha->cmd_offs_dpmem = 0;
  3031. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3032. + sizeof(ulong64);
  3033. ha->cmd_cnt = 0;
  3034. gdth_copy_command(ha);
  3035. gdth_release_event(ha);
  3036. return 0;
  3037. }
  3038. printk("\n");
  3039. } else {
  3040. b = scp->device->channel;
  3041. t = scp->device->id;
  3042. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3043. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3044. }
  3045. /* cache or raw service */
  3046. if (ha->status == S_BSY) {
  3047. TRACE2(("Controller busy -> retry !\n"));
  3048. if (scp->SCp.sent_command == GDT_MOUNT)
  3049. scp->SCp.sent_command = GDT_CLUST_INFO;
  3050. /* retry */
  3051. return 2;
  3052. }
  3053. if (scp->SCp.Status == GDTH_MAP_SG)
  3054. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3055. scp->use_sg,scp->SCp.Message);
  3056. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3057. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3058. scp->request_bufflen,scp->SCp.Message);
  3059. if (scp->SCp.buffer) {
  3060. dma_addr_t addr;
  3061. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3062. if (scp->host_scribble)
  3063. addr += (dma_addr_t)
  3064. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3065. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3066. }
  3067. if (ha->status == S_OK) {
  3068. scp->SCp.Status = S_OK;
  3069. scp->SCp.Message = ha->info;
  3070. if (scp->SCp.sent_command != -1) {
  3071. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3072. scp->SCp.sent_command));
  3073. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3074. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3075. ha->hdr[t].cluster_type = (unchar)ha->info;
  3076. if (!(ha->hdr[t].cluster_type &
  3077. CLUSTER_MOUNTED)) {
  3078. /* NOT MOUNTED -> MOUNT */
  3079. scp->SCp.sent_command = GDT_MOUNT;
  3080. if (ha->hdr[t].cluster_type &
  3081. CLUSTER_RESERVED) {
  3082. /* cluster drive RESERVED (on the other node) */
  3083. scp->SCp.phase = -2; /* reservation conflict */
  3084. }
  3085. } else {
  3086. scp->SCp.sent_command = -1;
  3087. }
  3088. } else {
  3089. if (scp->SCp.sent_command == GDT_MOUNT) {
  3090. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3091. ha->hdr[t].media_changed = TRUE;
  3092. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3093. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3094. ha->hdr[t].media_changed = TRUE;
  3095. }
  3096. scp->SCp.sent_command = -1;
  3097. }
  3098. /* retry */
  3099. scp->SCp.this_residual = HIGH_PRI;
  3100. return 2;
  3101. } else {
  3102. /* RESERVE/RELEASE ? */
  3103. if (scp->cmnd[0] == RESERVE) {
  3104. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3105. } else if (scp->cmnd[0] == RELEASE) {
  3106. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3107. }
  3108. scp->result = DID_OK << 16;
  3109. scp->sense_buffer[0] = 0;
  3110. }
  3111. } else {
  3112. scp->SCp.Status = ha->status;
  3113. scp->SCp.Message = ha->info;
  3114. if (scp->SCp.sent_command != -1) {
  3115. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3116. scp->SCp.sent_command, ha->status));
  3117. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3118. scp->SCp.sent_command == GDT_SCAN_END) {
  3119. scp->SCp.sent_command = -1;
  3120. /* retry */
  3121. scp->SCp.this_residual = HIGH_PRI;
  3122. return 2;
  3123. }
  3124. memset((char*)scp->sense_buffer,0,16);
  3125. scp->sense_buffer[0] = 0x70;
  3126. scp->sense_buffer[2] = NOT_READY;
  3127. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3128. } else if (service == CACHESERVICE) {
  3129. if (ha->status == S_CACHE_UNKNOWN &&
  3130. (ha->hdr[t].cluster_type &
  3131. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3132. /* bus reset -> force GDT_CLUST_INFO */
  3133. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3134. }
  3135. memset((char*)scp->sense_buffer,0,16);
  3136. if (ha->status == (ushort)S_CACHE_RESERV) {
  3137. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3138. } else {
  3139. scp->sense_buffer[0] = 0x70;
  3140. scp->sense_buffer[2] = NOT_READY;
  3141. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3142. }
  3143. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  3144. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3145. ha->dvr.eu.sync.ionode = ha->hanum;
  3146. ha->dvr.eu.sync.service = service;
  3147. ha->dvr.eu.sync.status = ha->status;
  3148. ha->dvr.eu.sync.info = ha->info;
  3149. ha->dvr.eu.sync.hostdrive = t;
  3150. if (ha->status >= 0x8000)
  3151. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3152. else
  3153. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3154. }
  3155. } else {
  3156. /* sense buffer filled from controller firmware (DMA) */
  3157. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3158. scp->result = DID_BAD_TARGET << 16;
  3159. } else {
  3160. scp->result = (DID_OK << 16) | ha->info;
  3161. }
  3162. }
  3163. }
  3164. if (!scp->SCp.have_data_in)
  3165. scp->SCp.have_data_in++;
  3166. else
  3167. return 1;
  3168. }
  3169. return 0;
  3170. }
  3171. static char *async_cache_tab[] = {
  3172. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3173. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3174. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3175. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3176. /* 2*/ "\005\000\002\006\004"
  3177. "GDT HA %u, Host Drive %lu not ready",
  3178. /* 3*/ "\005\000\002\006\004"
  3179. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3180. /* 4*/ "\005\000\002\006\004"
  3181. "GDT HA %u, mirror update on Host Drive %lu failed",
  3182. /* 5*/ "\005\000\002\006\004"
  3183. "GDT HA %u, Mirror Drive %lu failed",
  3184. /* 6*/ "\005\000\002\006\004"
  3185. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3186. /* 7*/ "\005\000\002\006\004"
  3187. "GDT HA %u, Host Drive %lu write protected",
  3188. /* 8*/ "\005\000\002\006\004"
  3189. "GDT HA %u, media changed in Host Drive %lu",
  3190. /* 9*/ "\005\000\002\006\004"
  3191. "GDT HA %u, Host Drive %lu is offline",
  3192. /*10*/ "\005\000\002\006\004"
  3193. "GDT HA %u, media change of Mirror Drive %lu",
  3194. /*11*/ "\005\000\002\006\004"
  3195. "GDT HA %u, Mirror Drive %lu is write protected",
  3196. /*12*/ "\005\000\002\006\004"
  3197. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3198. /*13*/ "\007\000\002\006\002\010\002"
  3199. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3200. /*14*/ "\005\000\002\006\002"
  3201. "GDT HA %u, Array Drive %u: FAIL state entered",
  3202. /*15*/ "\005\000\002\006\002"
  3203. "GDT HA %u, Array Drive %u: error",
  3204. /*16*/ "\007\000\002\006\002\010\002"
  3205. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3206. /*17*/ "\005\000\002\006\002"
  3207. "GDT HA %u, Array Drive %u: parity build failed",
  3208. /*18*/ "\005\000\002\006\002"
  3209. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3210. /*19*/ "\005\000\002\010\002"
  3211. "GDT HA %u, Test of Hot Fix %u failed",
  3212. /*20*/ "\005\000\002\006\002"
  3213. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3214. /*21*/ "\005\000\002\006\002"
  3215. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3216. /*22*/ "\007\000\002\006\002\010\002"
  3217. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3218. /*23*/ "\005\000\002\006\002"
  3219. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3220. /*24*/ "\005\000\002\010\002"
  3221. "GDT HA %u, mirror update on Cache Drive %u completed",
  3222. /*25*/ "\005\000\002\010\002"
  3223. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3224. /*26*/ "\005\000\002\006\002"
  3225. "GDT HA %u, Array Drive %u: drive rebuild started",
  3226. /*27*/ "\005\000\002\012\001"
  3227. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3228. /*28*/ "\005\000\002\012\001"
  3229. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3230. /*29*/ "\007\000\002\012\001\013\001"
  3231. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3232. /*30*/ "\007\000\002\012\001\013\001"
  3233. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3234. /*31*/ "\007\000\002\012\001\013\001"
  3235. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3236. /*32*/ "\007\000\002\012\001\013\001"
  3237. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3238. /*33*/ "\007\000\002\012\001\013\001"
  3239. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3240. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3241. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3242. /*35*/ "\007\000\002\012\001\013\001"
  3243. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3244. /*36*/ "\007\000\002\012\001\013\001"
  3245. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3246. /*37*/ "\007\000\002\012\001\006\004"
  3247. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3248. /*38*/ "\007\000\002\012\001\013\001"
  3249. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3250. /*39*/ "\007\000\002\012\001\013\001"
  3251. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3252. /*40*/ "\007\000\002\012\001\013\001"
  3253. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3254. /*41*/ "\007\000\002\012\001\013\001"
  3255. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3256. /*42*/ "\005\000\002\006\002"
  3257. "GDT HA %u, Array Drive %u: drive build started",
  3258. /*43*/ "\003\000\002"
  3259. "GDT HA %u, DRAM parity error detected",
  3260. /*44*/ "\005\000\002\006\002"
  3261. "GDT HA %u, Mirror Drive %u: update started",
  3262. /*45*/ "\007\000\002\006\002\010\002"
  3263. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3264. /*46*/ "\005\000\002\006\002"
  3265. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3266. /*47*/ "\005\000\002\006\002"
  3267. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3268. /*48*/ "\005\000\002\006\002"
  3269. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3270. /*49*/ "\005\000\002\006\002"
  3271. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3272. /*50*/ "\007\000\002\012\001\013\001"
  3273. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3274. /*51*/ "\005\000\002\006\002"
  3275. "GDT HA %u, Array Drive %u: expand started",
  3276. /*52*/ "\005\000\002\006\002"
  3277. "GDT HA %u, Array Drive %u: expand finished successfully",
  3278. /*53*/ "\005\000\002\006\002"
  3279. "GDT HA %u, Array Drive %u: expand failed",
  3280. /*54*/ "\003\000\002"
  3281. "GDT HA %u, CPU temperature critical",
  3282. /*55*/ "\003\000\002"
  3283. "GDT HA %u, CPU temperature OK",
  3284. /*56*/ "\005\000\002\006\004"
  3285. "GDT HA %u, Host drive %lu created",
  3286. /*57*/ "\005\000\002\006\002"
  3287. "GDT HA %u, Array Drive %u: expand restarted",
  3288. /*58*/ "\005\000\002\006\002"
  3289. "GDT HA %u, Array Drive %u: expand stopped",
  3290. /*59*/ "\005\000\002\010\002"
  3291. "GDT HA %u, Mirror Drive %u: drive build quited",
  3292. /*60*/ "\005\000\002\006\002"
  3293. "GDT HA %u, Array Drive %u: parity build quited",
  3294. /*61*/ "\005\000\002\006\002"
  3295. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3296. /*62*/ "\005\000\002\006\002"
  3297. "GDT HA %u, Array Drive %u: parity verify started",
  3298. /*63*/ "\005\000\002\006\002"
  3299. "GDT HA %u, Array Drive %u: parity verify done",
  3300. /*64*/ "\005\000\002\006\002"
  3301. "GDT HA %u, Array Drive %u: parity verify failed",
  3302. /*65*/ "\005\000\002\006\002"
  3303. "GDT HA %u, Array Drive %u: parity error detected",
  3304. /*66*/ "\005\000\002\006\002"
  3305. "GDT HA %u, Array Drive %u: parity verify quited",
  3306. /*67*/ "\005\000\002\006\002"
  3307. "GDT HA %u, Host Drive %u reserved",
  3308. /*68*/ "\005\000\002\006\002"
  3309. "GDT HA %u, Host Drive %u mounted and released",
  3310. /*69*/ "\005\000\002\006\002"
  3311. "GDT HA %u, Host Drive %u released",
  3312. /*70*/ "\003\000\002"
  3313. "GDT HA %u, DRAM error detected and corrected with ECC",
  3314. /*71*/ "\003\000\002"
  3315. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3316. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3317. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3318. /*73*/ "\005\000\002\006\002"
  3319. "GDT HA %u, Host drive %u resetted locally",
  3320. /*74*/ "\005\000\002\006\002"
  3321. "GDT HA %u, Host drive %u resetted remotely",
  3322. /*75*/ "\003\000\002"
  3323. "GDT HA %u, async. status 75 unknown",
  3324. };
  3325. static int gdth_async_event(gdth_ha_str *ha)
  3326. {
  3327. gdth_cmd_str *cmdp;
  3328. int cmd_index;
  3329. cmdp= ha->pccb;
  3330. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3331. ha->hanum, ha->service));
  3332. if (ha->service == SCREENSERVICE) {
  3333. if (ha->status == MSG_REQUEST) {
  3334. while (gdth_test_busy(ha))
  3335. gdth_delay(0);
  3336. cmdp->Service = SCREENSERVICE;
  3337. cmdp->RequestBuffer = SCREEN_CMND;
  3338. cmd_index = gdth_get_cmd_index(ha);
  3339. gdth_set_sema0(ha);
  3340. cmdp->OpCode = GDT_READ;
  3341. cmdp->BoardNode = LOCALBOARD;
  3342. cmdp->u.screen.reserved = 0;
  3343. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3344. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3345. ha->cmd_offs_dpmem = 0;
  3346. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3347. + sizeof(ulong64);
  3348. ha->cmd_cnt = 0;
  3349. gdth_copy_command(ha);
  3350. if (ha->type == GDT_EISA)
  3351. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3352. else if (ha->type == GDT_ISA)
  3353. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3354. else
  3355. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3356. (ushort)((ha->brd_phys>>3)&0x1f));
  3357. gdth_release_event(ha);
  3358. }
  3359. } else {
  3360. if (ha->type == GDT_PCIMPR &&
  3361. (ha->fw_vers & 0xff) >= 0x1a) {
  3362. ha->dvr.size = 0;
  3363. ha->dvr.eu.async.ionode = ha->hanum;
  3364. ha->dvr.eu.async.status = ha->status;
  3365. /* severity and event_string already set! */
  3366. } else {
  3367. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3368. ha->dvr.eu.async.ionode = ha->hanum;
  3369. ha->dvr.eu.async.service = ha->service;
  3370. ha->dvr.eu.async.status = ha->status;
  3371. ha->dvr.eu.async.info = ha->info;
  3372. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3373. }
  3374. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3375. gdth_log_event( &ha->dvr, NULL );
  3376. /* new host drive from expand? */
  3377. if (ha->service == CACHESERVICE && ha->status == 56) {
  3378. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3379. (ushort)ha->info));
  3380. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3381. }
  3382. }
  3383. return 1;
  3384. }
  3385. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3386. {
  3387. gdth_stackframe stack;
  3388. char *f = NULL;
  3389. int i,j;
  3390. TRACE2(("gdth_log_event()\n"));
  3391. if (dvr->size == 0) {
  3392. if (buffer == NULL) {
  3393. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3394. } else {
  3395. sprintf(buffer,"Adapter %d: %s\n",
  3396. dvr->eu.async.ionode,dvr->event_string);
  3397. }
  3398. } else if (dvr->eu.async.service == CACHESERVICE &&
  3399. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3400. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3401. dvr->eu.async.status));
  3402. f = async_cache_tab[dvr->eu.async.status];
  3403. /* i: parameter to push, j: stack element to fill */
  3404. for (j=0,i=1; i < f[0]; i+=2) {
  3405. switch (f[i+1]) {
  3406. case 4:
  3407. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3408. break;
  3409. case 2:
  3410. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3411. break;
  3412. case 1:
  3413. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3414. break;
  3415. default:
  3416. break;
  3417. }
  3418. }
  3419. if (buffer == NULL) {
  3420. printk(&f[(int)f[0]],stack);
  3421. printk("\n");
  3422. } else {
  3423. sprintf(buffer,&f[(int)f[0]],stack);
  3424. }
  3425. } else {
  3426. if (buffer == NULL) {
  3427. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3428. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3429. } else {
  3430. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3431. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3432. }
  3433. }
  3434. }
  3435. #ifdef GDTH_STATISTICS
  3436. static void gdth_timeout(ulong data)
  3437. {
  3438. ulong32 i;
  3439. Scsi_Cmnd *nscp;
  3440. gdth_ha_str *ha;
  3441. ulong flags;
  3442. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3443. spin_lock_irqsave(&ha->smp_lock, flags);
  3444. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3445. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3446. ++act_stats;
  3447. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3448. ++act_rq;
  3449. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3450. act_ints, act_ios, act_stats, act_rq));
  3451. act_ints = act_ios = 0;
  3452. gdth_timer.expires = jiffies + 30 * HZ;
  3453. add_timer(&gdth_timer);
  3454. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3455. }
  3456. #endif
  3457. static void __init internal_setup(char *str,int *ints)
  3458. {
  3459. int i, argc;
  3460. char *cur_str, *argv;
  3461. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3462. str ? str:"NULL", ints ? ints[0]:0));
  3463. /* read irq[] from ints[] */
  3464. if (ints) {
  3465. argc = ints[0];
  3466. if (argc > 0) {
  3467. if (argc > MAXHA)
  3468. argc = MAXHA;
  3469. for (i = 0; i < argc; ++i)
  3470. irq[i] = ints[i+1];
  3471. }
  3472. }
  3473. /* analyse string */
  3474. argv = str;
  3475. while (argv && (cur_str = strchr(argv, ':'))) {
  3476. int val = 0, c = *++cur_str;
  3477. if (c == 'n' || c == 'N')
  3478. val = 0;
  3479. else if (c == 'y' || c == 'Y')
  3480. val = 1;
  3481. else
  3482. val = (int)simple_strtoul(cur_str, NULL, 0);
  3483. if (!strncmp(argv, "disable:", 8))
  3484. disable = val;
  3485. else if (!strncmp(argv, "reserve_mode:", 13))
  3486. reserve_mode = val;
  3487. else if (!strncmp(argv, "reverse_scan:", 13))
  3488. reverse_scan = val;
  3489. else if (!strncmp(argv, "hdr_channel:", 12))
  3490. hdr_channel = val;
  3491. else if (!strncmp(argv, "max_ids:", 8))
  3492. max_ids = val;
  3493. else if (!strncmp(argv, "rescan:", 7))
  3494. rescan = val;
  3495. else if (!strncmp(argv, "shared_access:", 14))
  3496. shared_access = val;
  3497. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3498. probe_eisa_isa = val;
  3499. else if (!strncmp(argv, "reserve_list:", 13)) {
  3500. reserve_list[0] = val;
  3501. for (i = 1; i < MAX_RES_ARGS; i++) {
  3502. cur_str = strchr(cur_str, ',');
  3503. if (!cur_str)
  3504. break;
  3505. if (!isdigit((int)*++cur_str)) {
  3506. --cur_str;
  3507. break;
  3508. }
  3509. reserve_list[i] =
  3510. (int)simple_strtoul(cur_str, NULL, 0);
  3511. }
  3512. if (!cur_str)
  3513. break;
  3514. argv = ++cur_str;
  3515. continue;
  3516. }
  3517. if ((argv = strchr(argv, ',')))
  3518. ++argv;
  3519. }
  3520. }
  3521. int __init option_setup(char *str)
  3522. {
  3523. int ints[MAXHA];
  3524. char *cur = str;
  3525. int i = 1;
  3526. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3527. while (cur && isdigit(*cur) && i <= MAXHA) {
  3528. ints[i++] = simple_strtoul(cur, NULL, 0);
  3529. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3530. }
  3531. ints[0] = i - 1;
  3532. internal_setup(cur, ints);
  3533. return 1;
  3534. }
  3535. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3536. {
  3537. TRACE2(("gdth_ctr_name()\n"));
  3538. if (ha->type == GDT_EISA) {
  3539. switch (ha->stype) {
  3540. case GDT3_ID:
  3541. return("GDT3000/3020");
  3542. case GDT3A_ID:
  3543. return("GDT3000A/3020A/3050A");
  3544. case GDT3B_ID:
  3545. return("GDT3000B/3010A");
  3546. }
  3547. } else if (ha->type == GDT_ISA) {
  3548. return("GDT2000/2020");
  3549. } else if (ha->type == GDT_PCI) {
  3550. switch (ha->pdev->device) {
  3551. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3552. return("GDT6000/6020/6050");
  3553. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3554. return("GDT6000B/6010");
  3555. }
  3556. }
  3557. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3558. return("");
  3559. }
  3560. static const char *gdth_info(struct Scsi_Host *shp)
  3561. {
  3562. gdth_ha_str *ha = shost_priv(shp);
  3563. TRACE2(("gdth_info()\n"));
  3564. return ((const char *)ha->binfo.type_string);
  3565. }
  3566. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3567. {
  3568. gdth_ha_str *ha = shost_priv(scp->device->host);
  3569. int i;
  3570. ulong flags;
  3571. Scsi_Cmnd *cmnd;
  3572. unchar b;
  3573. TRACE2(("gdth_eh_bus_reset()\n"));
  3574. b = scp->device->channel;
  3575. /* clear command tab */
  3576. spin_lock_irqsave(&ha->smp_lock, flags);
  3577. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3578. cmnd = ha->cmd_tab[i].cmnd;
  3579. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3580. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3581. }
  3582. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3583. if (b == ha->virt_bus) {
  3584. /* host drives */
  3585. for (i = 0; i < MAX_HDRIVES; ++i) {
  3586. if (ha->hdr[i].present) {
  3587. spin_lock_irqsave(&ha->smp_lock, flags);
  3588. gdth_polling = TRUE;
  3589. while (gdth_test_busy(ha))
  3590. gdth_delay(0);
  3591. if (gdth_internal_cmd(ha, CACHESERVICE,
  3592. GDT_CLUST_RESET, i, 0, 0))
  3593. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3594. gdth_polling = FALSE;
  3595. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3596. }
  3597. }
  3598. } else {
  3599. /* raw devices */
  3600. spin_lock_irqsave(&ha->smp_lock, flags);
  3601. for (i = 0; i < MAXID; ++i)
  3602. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3603. gdth_polling = TRUE;
  3604. while (gdth_test_busy(ha))
  3605. gdth_delay(0);
  3606. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3607. BUS_L2P(ha,b), 0, 0);
  3608. gdth_polling = FALSE;
  3609. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3610. }
  3611. return SUCCESS;
  3612. }
  3613. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3614. {
  3615. unchar b, t;
  3616. gdth_ha_str *ha = shost_priv(sdev->host);
  3617. struct scsi_device *sd;
  3618. unsigned capacity;
  3619. sd = sdev;
  3620. capacity = cap;
  3621. b = sd->channel;
  3622. t = sd->id;
  3623. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3624. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3625. /* raw device or host drive without mapping information */
  3626. TRACE2(("Evaluate mapping\n"));
  3627. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3628. } else {
  3629. ip[0] = ha->hdr[t].heads;
  3630. ip[1] = ha->hdr[t].secs;
  3631. ip[2] = capacity / ip[0] / ip[1];
  3632. }
  3633. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3634. ip[0],ip[1],ip[2]));
  3635. return 0;
  3636. }
  3637. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3638. void (*done)(struct scsi_cmnd *))
  3639. {
  3640. gdth_ha_str *ha = shost_priv(scp->device->host);
  3641. int priority;
  3642. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3643. scp->scsi_done = done;
  3644. scp->SCp.have_data_in = 1;
  3645. scp->SCp.phase = -1;
  3646. scp->SCp.sent_command = -1;
  3647. scp->SCp.Status = GDTH_MAP_NONE;
  3648. scp->SCp.buffer = (struct scatterlist *)NULL;
  3649. #ifdef GDTH_STATISTICS
  3650. ++act_ios;
  3651. #endif
  3652. priority = DEFAULT_PRI;
  3653. if (IS_GDTH_INTERNAL_CMD(scp))
  3654. priority = scp->SCp.this_residual;
  3655. else
  3656. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3657. gdth_putq(ha, scp, priority);
  3658. gdth_next(ha);
  3659. return 0;
  3660. }
  3661. static int gdth_open(struct inode *inode, struct file *filep)
  3662. {
  3663. gdth_ha_str *ha;
  3664. list_for_each_entry(ha, &gdth_instances, list) {
  3665. if (!ha->sdev)
  3666. ha->sdev = scsi_get_host_dev(ha->shost);
  3667. }
  3668. TRACE(("gdth_open()\n"));
  3669. return 0;
  3670. }
  3671. static int gdth_close(struct inode *inode, struct file *filep)
  3672. {
  3673. TRACE(("gdth_close()\n"));
  3674. return 0;
  3675. }
  3676. static int ioc_event(void __user *arg)
  3677. {
  3678. gdth_ioctl_event evt;
  3679. gdth_ha_str *ha;
  3680. ulong flags;
  3681. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3682. return -EFAULT;
  3683. ha = gdth_find_ha(evt.ionode);
  3684. if (!ha)
  3685. return -EFAULT;
  3686. if (evt.erase == 0xff) {
  3687. if (evt.event.event_source == ES_TEST)
  3688. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3689. else if (evt.event.event_source == ES_DRIVER)
  3690. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3691. else if (evt.event.event_source == ES_SYNC)
  3692. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3693. else
  3694. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3695. spin_lock_irqsave(&ha->smp_lock, flags);
  3696. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3697. &evt.event.event_data);
  3698. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3699. } else if (evt.erase == 0xfe) {
  3700. gdth_clear_events();
  3701. } else if (evt.erase == 0) {
  3702. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3703. } else {
  3704. gdth_readapp_event(ha, evt.erase, &evt.event);
  3705. }
  3706. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3707. return -EFAULT;
  3708. return 0;
  3709. }
  3710. static int ioc_lockdrv(void __user *arg)
  3711. {
  3712. gdth_ioctl_lockdrv ldrv;
  3713. unchar i, j;
  3714. ulong flags;
  3715. gdth_ha_str *ha;
  3716. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3717. return -EFAULT;
  3718. ha = gdth_find_ha(ldrv.ionode);
  3719. if (!ha)
  3720. return -EFAULT;
  3721. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3722. j = ldrv.drives[i];
  3723. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3724. continue;
  3725. if (ldrv.lock) {
  3726. spin_lock_irqsave(&ha->smp_lock, flags);
  3727. ha->hdr[j].lock = 1;
  3728. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3729. gdth_wait_completion(ha, ha->bus_cnt, j);
  3730. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3731. } else {
  3732. spin_lock_irqsave(&ha->smp_lock, flags);
  3733. ha->hdr[j].lock = 0;
  3734. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3735. gdth_start_timeout(ha, ha->bus_cnt, j);
  3736. gdth_next(ha);
  3737. }
  3738. }
  3739. return 0;
  3740. }
  3741. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3742. {
  3743. gdth_ioctl_reset res;
  3744. gdth_cmd_str cmd;
  3745. gdth_ha_str *ha;
  3746. int rval;
  3747. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3748. res.number >= MAX_HDRIVES)
  3749. return -EFAULT;
  3750. ha = gdth_find_ha(res.ionode);
  3751. if (!ha)
  3752. return -EFAULT;
  3753. if (!ha->hdr[res.number].present)
  3754. return 0;
  3755. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3756. cmd.Service = CACHESERVICE;
  3757. cmd.OpCode = GDT_CLUST_RESET;
  3758. if (ha->cache_feat & GDT_64BIT)
  3759. cmd.u.cache64.DeviceNo = res.number;
  3760. else
  3761. cmd.u.cache.DeviceNo = res.number;
  3762. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3763. if (rval < 0)
  3764. return rval;
  3765. res.status = rval;
  3766. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3767. return -EFAULT;
  3768. return 0;
  3769. }
  3770. static int ioc_general(void __user *arg, char *cmnd)
  3771. {
  3772. gdth_ioctl_general gen;
  3773. char *buf = NULL;
  3774. ulong64 paddr;
  3775. gdth_ha_str *ha;
  3776. int rval;
  3777. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3778. return -EFAULT;
  3779. ha = gdth_find_ha(gen.ionode);
  3780. if (!ha)
  3781. return -EFAULT;
  3782. if (gen.data_len + gen.sense_len != 0) {
  3783. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3784. FALSE, &paddr)))
  3785. return -EFAULT;
  3786. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3787. gen.data_len + gen.sense_len)) {
  3788. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3789. return -EFAULT;
  3790. }
  3791. if (gen.command.OpCode == GDT_IOCTL) {
  3792. gen.command.u.ioctl.p_param = paddr;
  3793. } else if (gen.command.Service == CACHESERVICE) {
  3794. if (ha->cache_feat & GDT_64BIT) {
  3795. /* copy elements from 32-bit IOCTL structure */
  3796. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3797. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3798. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3799. /* addresses */
  3800. if (ha->cache_feat & SCATTER_GATHER) {
  3801. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3802. gen.command.u.cache64.sg_canz = 1;
  3803. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3804. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3805. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3806. } else {
  3807. gen.command.u.cache64.DestAddr = paddr;
  3808. gen.command.u.cache64.sg_canz = 0;
  3809. }
  3810. } else {
  3811. if (ha->cache_feat & SCATTER_GATHER) {
  3812. gen.command.u.cache.DestAddr = 0xffffffff;
  3813. gen.command.u.cache.sg_canz = 1;
  3814. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3815. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3816. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3817. } else {
  3818. gen.command.u.cache.DestAddr = paddr;
  3819. gen.command.u.cache.sg_canz = 0;
  3820. }
  3821. }
  3822. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3823. if (ha->raw_feat & GDT_64BIT) {
  3824. /* copy elements from 32-bit IOCTL structure */
  3825. char cmd[16];
  3826. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3827. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3828. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3829. gen.command.u.raw64.target = gen.command.u.raw.target;
  3830. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3831. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3832. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3833. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3834. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3835. /* addresses */
  3836. if (ha->raw_feat & SCATTER_GATHER) {
  3837. gen.command.u.raw64.sdata = (ulong64)-1;
  3838. gen.command.u.raw64.sg_ranz = 1;
  3839. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3840. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3841. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3842. } else {
  3843. gen.command.u.raw64.sdata = paddr;
  3844. gen.command.u.raw64.sg_ranz = 0;
  3845. }
  3846. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3847. } else {
  3848. if (ha->raw_feat & SCATTER_GATHER) {
  3849. gen.command.u.raw.sdata = 0xffffffff;
  3850. gen.command.u.raw.sg_ranz = 1;
  3851. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3852. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3853. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3854. } else {
  3855. gen.command.u.raw.sdata = paddr;
  3856. gen.command.u.raw.sg_ranz = 0;
  3857. }
  3858. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3859. }
  3860. } else {
  3861. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3862. return -EFAULT;
  3863. }
  3864. }
  3865. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3866. if (rval < 0)
  3867. return rval;
  3868. gen.status = rval;
  3869. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3870. gen.data_len + gen.sense_len)) {
  3871. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3872. return -EFAULT;
  3873. }
  3874. if (copy_to_user(arg, &gen,
  3875. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3876. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3877. return -EFAULT;
  3878. }
  3879. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3880. return 0;
  3881. }
  3882. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3883. {
  3884. gdth_ioctl_rescan *rsc;
  3885. gdth_cmd_str *cmd;
  3886. gdth_ha_str *ha;
  3887. unchar i;
  3888. int rc = -ENOMEM;
  3889. u32 cluster_type = 0;
  3890. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3891. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3892. if (!rsc || !cmd)
  3893. goto free_fail;
  3894. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3895. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3896. rc = -EFAULT;
  3897. goto free_fail;
  3898. }
  3899. memset(cmd, 0, sizeof(gdth_cmd_str));
  3900. for (i = 0; i < MAX_HDRIVES; ++i) {
  3901. if (!ha->hdr[i].present) {
  3902. rsc->hdr_list[i].bus = 0xff;
  3903. continue;
  3904. }
  3905. rsc->hdr_list[i].bus = ha->virt_bus;
  3906. rsc->hdr_list[i].target = i;
  3907. rsc->hdr_list[i].lun = 0;
  3908. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3909. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3910. cmd->Service = CACHESERVICE;
  3911. cmd->OpCode = GDT_CLUST_INFO;
  3912. if (ha->cache_feat & GDT_64BIT)
  3913. cmd->u.cache64.DeviceNo = i;
  3914. else
  3915. cmd->u.cache.DeviceNo = i;
  3916. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3917. rsc->hdr_list[i].cluster_type = cluster_type;
  3918. }
  3919. }
  3920. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3921. rc = -EFAULT;
  3922. else
  3923. rc = 0;
  3924. free_fail:
  3925. kfree(rsc);
  3926. kfree(cmd);
  3927. return rc;
  3928. }
  3929. static int ioc_rescan(void __user *arg, char *cmnd)
  3930. {
  3931. gdth_ioctl_rescan *rsc;
  3932. gdth_cmd_str *cmd;
  3933. ushort i, status, hdr_cnt;
  3934. ulong32 info;
  3935. int cyls, hds, secs;
  3936. int rc = -ENOMEM;
  3937. ulong flags;
  3938. gdth_ha_str *ha;
  3939. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3940. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3941. if (!cmd || !rsc)
  3942. goto free_fail;
  3943. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3944. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3945. rc = -EFAULT;
  3946. goto free_fail;
  3947. }
  3948. memset(cmd, 0, sizeof(gdth_cmd_str));
  3949. if (rsc->flag == 0) {
  3950. /* old method: re-init. cache service */
  3951. cmd->Service = CACHESERVICE;
  3952. if (ha->cache_feat & GDT_64BIT) {
  3953. cmd->OpCode = GDT_X_INIT_HOST;
  3954. cmd->u.cache64.DeviceNo = LINUX_OS;
  3955. } else {
  3956. cmd->OpCode = GDT_INIT;
  3957. cmd->u.cache.DeviceNo = LINUX_OS;
  3958. }
  3959. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3960. i = 0;
  3961. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  3962. } else {
  3963. i = rsc->hdr_no;
  3964. hdr_cnt = i + 1;
  3965. }
  3966. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3967. cmd->Service = CACHESERVICE;
  3968. cmd->OpCode = GDT_INFO;
  3969. if (ha->cache_feat & GDT_64BIT)
  3970. cmd->u.cache64.DeviceNo = i;
  3971. else
  3972. cmd->u.cache.DeviceNo = i;
  3973. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3974. spin_lock_irqsave(&ha->smp_lock, flags);
  3975. rsc->hdr_list[i].bus = ha->virt_bus;
  3976. rsc->hdr_list[i].target = i;
  3977. rsc->hdr_list[i].lun = 0;
  3978. if (status != S_OK) {
  3979. ha->hdr[i].present = FALSE;
  3980. } else {
  3981. ha->hdr[i].present = TRUE;
  3982. ha->hdr[i].size = info;
  3983. /* evaluate mapping */
  3984. ha->hdr[i].size &= ~SECS32;
  3985. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3986. ha->hdr[i].heads = hds;
  3987. ha->hdr[i].secs = secs;
  3988. /* round size */
  3989. ha->hdr[i].size = cyls * hds * secs;
  3990. }
  3991. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3992. if (status != S_OK)
  3993. continue;
  3994. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3995. /* but we need ha->info2, not yet stored in scp->SCp */
  3996. /* devtype, cluster info, R/W attribs */
  3997. cmd->Service = CACHESERVICE;
  3998. cmd->OpCode = GDT_DEVTYPE;
  3999. if (ha->cache_feat & GDT_64BIT)
  4000. cmd->u.cache64.DeviceNo = i;
  4001. else
  4002. cmd->u.cache.DeviceNo = i;
  4003. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4004. spin_lock_irqsave(&ha->smp_lock, flags);
  4005. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4006. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4007. cmd->Service = CACHESERVICE;
  4008. cmd->OpCode = GDT_CLUST_INFO;
  4009. if (ha->cache_feat & GDT_64BIT)
  4010. cmd->u.cache64.DeviceNo = i;
  4011. else
  4012. cmd->u.cache.DeviceNo = i;
  4013. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4014. spin_lock_irqsave(&ha->smp_lock, flags);
  4015. ha->hdr[i].cluster_type =
  4016. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4017. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4018. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4019. cmd->Service = CACHESERVICE;
  4020. cmd->OpCode = GDT_RW_ATTRIBS;
  4021. if (ha->cache_feat & GDT_64BIT)
  4022. cmd->u.cache64.DeviceNo = i;
  4023. else
  4024. cmd->u.cache.DeviceNo = i;
  4025. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4026. spin_lock_irqsave(&ha->smp_lock, flags);
  4027. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4028. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4029. }
  4030. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4031. rc = -EFAULT;
  4032. else
  4033. rc = 0;
  4034. free_fail:
  4035. kfree(rsc);
  4036. kfree(cmd);
  4037. return rc;
  4038. }
  4039. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4040. unsigned int cmd, unsigned long arg)
  4041. {
  4042. gdth_ha_str *ha;
  4043. Scsi_Cmnd *scp;
  4044. ulong flags;
  4045. char cmnd[MAX_COMMAND_SIZE];
  4046. void __user *argp = (void __user *)arg;
  4047. memset(cmnd, 0xff, 12);
  4048. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4049. switch (cmd) {
  4050. case GDTIOCTL_CTRCNT:
  4051. {
  4052. int cnt = gdth_ctr_count;
  4053. if (put_user(cnt, (int __user *)argp))
  4054. return -EFAULT;
  4055. break;
  4056. }
  4057. case GDTIOCTL_DRVERS:
  4058. {
  4059. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4060. if (put_user(ver, (int __user *)argp))
  4061. return -EFAULT;
  4062. break;
  4063. }
  4064. case GDTIOCTL_OSVERS:
  4065. {
  4066. gdth_ioctl_osvers osv;
  4067. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4068. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4069. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4070. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4071. return -EFAULT;
  4072. break;
  4073. }
  4074. case GDTIOCTL_CTRTYPE:
  4075. {
  4076. gdth_ioctl_ctrtype ctrt;
  4077. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4078. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4079. return -EFAULT;
  4080. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4081. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4082. } else {
  4083. if (ha->type != GDT_PCIMPR) {
  4084. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4085. } else {
  4086. ctrt.type =
  4087. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4088. if (ha->stype >= 0x300)
  4089. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4090. else
  4091. ctrt.ext_type = 0x6000 | ha->stype;
  4092. }
  4093. ctrt.device_id = ha->pdev->device;
  4094. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4095. }
  4096. ctrt.info = ha->brd_phys;
  4097. ctrt.oem_id = ha->oem_id;
  4098. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4099. return -EFAULT;
  4100. break;
  4101. }
  4102. case GDTIOCTL_GENERAL:
  4103. return ioc_general(argp, cmnd);
  4104. case GDTIOCTL_EVENT:
  4105. return ioc_event(argp);
  4106. case GDTIOCTL_LOCKDRV:
  4107. return ioc_lockdrv(argp);
  4108. case GDTIOCTL_LOCKCHN:
  4109. {
  4110. gdth_ioctl_lockchn lchn;
  4111. unchar i, j;
  4112. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4113. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4114. return -EFAULT;
  4115. i = lchn.channel;
  4116. if (i < ha->bus_cnt) {
  4117. if (lchn.lock) {
  4118. spin_lock_irqsave(&ha->smp_lock, flags);
  4119. ha->raw[i].lock = 1;
  4120. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4121. for (j = 0; j < ha->tid_cnt; ++j) {
  4122. gdth_wait_completion(ha, i, j);
  4123. gdth_stop_timeout(ha, i, j);
  4124. }
  4125. } else {
  4126. spin_lock_irqsave(&ha->smp_lock, flags);
  4127. ha->raw[i].lock = 0;
  4128. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4129. for (j = 0; j < ha->tid_cnt; ++j) {
  4130. gdth_start_timeout(ha, i, j);
  4131. gdth_next(ha);
  4132. }
  4133. }
  4134. }
  4135. break;
  4136. }
  4137. case GDTIOCTL_RESCAN:
  4138. return ioc_rescan(argp, cmnd);
  4139. case GDTIOCTL_HDRLIST:
  4140. return ioc_hdrlist(argp, cmnd);
  4141. case GDTIOCTL_RESET_BUS:
  4142. {
  4143. gdth_ioctl_reset res;
  4144. int rval;
  4145. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4146. (NULL == (ha = gdth_find_ha(res.ionode))))
  4147. return -EFAULT;
  4148. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4149. if (!scp)
  4150. return -ENOMEM;
  4151. scp->device = ha->sdev;
  4152. scp->cmd_len = 12;
  4153. scp->use_sg = 0;
  4154. scp->device->channel = res.number;
  4155. rval = gdth_eh_bus_reset(scp);
  4156. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4157. kfree(scp);
  4158. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4159. return -EFAULT;
  4160. break;
  4161. }
  4162. case GDTIOCTL_RESET_DRV:
  4163. return ioc_resetdrv(argp, cmnd);
  4164. default:
  4165. break;
  4166. }
  4167. return 0;
  4168. }
  4169. /* flush routine */
  4170. static void gdth_flush(gdth_ha_str *ha)
  4171. {
  4172. int i;
  4173. gdth_cmd_str gdtcmd;
  4174. char cmnd[MAX_COMMAND_SIZE];
  4175. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4176. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4177. for (i = 0; i < MAX_HDRIVES; ++i) {
  4178. if (ha->hdr[i].present) {
  4179. gdtcmd.BoardNode = LOCALBOARD;
  4180. gdtcmd.Service = CACHESERVICE;
  4181. gdtcmd.OpCode = GDT_FLUSH;
  4182. if (ha->cache_feat & GDT_64BIT) {
  4183. gdtcmd.u.cache64.DeviceNo = i;
  4184. gdtcmd.u.cache64.BlockNo = 1;
  4185. gdtcmd.u.cache64.sg_canz = 0;
  4186. } else {
  4187. gdtcmd.u.cache.DeviceNo = i;
  4188. gdtcmd.u.cache.BlockNo = 1;
  4189. gdtcmd.u.cache.sg_canz = 0;
  4190. }
  4191. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4192. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4193. }
  4194. }
  4195. }
  4196. /* shutdown routine */
  4197. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4198. {
  4199. gdth_ha_str *ha;
  4200. #ifndef __alpha__
  4201. gdth_cmd_str gdtcmd;
  4202. char cmnd[MAX_COMMAND_SIZE];
  4203. #endif
  4204. if (notifier_disabled)
  4205. return NOTIFY_OK;
  4206. TRACE2(("gdth_halt() event %d\n",(int)event));
  4207. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4208. return NOTIFY_DONE;
  4209. notifier_disabled = 1;
  4210. printk("GDT-HA: Flushing all host drives .. ");
  4211. list_for_each_entry(ha, &gdth_instances, list) {
  4212. gdth_flush(ha);
  4213. #ifndef __alpha__
  4214. /* controller reset */
  4215. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4216. gdtcmd.BoardNode = LOCALBOARD;
  4217. gdtcmd.Service = CACHESERVICE;
  4218. gdtcmd.OpCode = GDT_RESET;
  4219. TRACE2(("gdth_halt(): reset controller %d\n", ha->hanum));
  4220. gdth_execute(ha->shost, &gdtcmd, cmnd, 10, NULL);
  4221. #endif
  4222. }
  4223. printk("Done.\n");
  4224. #ifdef GDTH_STATISTICS
  4225. del_timer(&gdth_timer);
  4226. #endif
  4227. return NOTIFY_OK;
  4228. }
  4229. /* configure lun */
  4230. static int gdth_slave_configure(struct scsi_device *sdev)
  4231. {
  4232. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4233. sdev->skip_ms_page_3f = 1;
  4234. sdev->skip_ms_page_8 = 1;
  4235. return 0;
  4236. }
  4237. static struct scsi_host_template gdth_template = {
  4238. .name = "GDT SCSI Disk Array Controller",
  4239. .info = gdth_info,
  4240. .queuecommand = gdth_queuecommand,
  4241. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4242. .slave_configure = gdth_slave_configure,
  4243. .bios_param = gdth_bios_param,
  4244. .proc_info = gdth_proc_info,
  4245. .proc_name = "gdth",
  4246. .can_queue = GDTH_MAXCMDS,
  4247. .this_id = -1,
  4248. .sg_tablesize = GDTH_MAXSG,
  4249. .cmd_per_lun = GDTH_MAXC_P_L,
  4250. .unchecked_isa_dma = 1,
  4251. .use_clustering = ENABLE_CLUSTERING,
  4252. };
  4253. #ifdef CONFIG_ISA
  4254. static int gdth_isa_probe_one(ulong32 isa_bios)
  4255. {
  4256. struct Scsi_Host *shp;
  4257. gdth_ha_str *ha;
  4258. dma_addr_t scratch_dma_handle = 0;
  4259. int error, i;
  4260. if (!gdth_search_isa(isa_bios))
  4261. return -ENXIO;
  4262. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4263. if (!shp)
  4264. return -ENOMEM;
  4265. ha = shost_priv(shp);
  4266. error = -ENODEV;
  4267. if (!gdth_init_isa(isa_bios,ha))
  4268. goto out_host_put;
  4269. /* controller found and initialized */
  4270. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4271. isa_bios, ha->irq, ha->drq);
  4272. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4273. if (error) {
  4274. printk("GDT-ISA: Unable to allocate IRQ\n");
  4275. goto out_host_put;
  4276. }
  4277. error = request_dma(ha->drq, "gdth");
  4278. if (error) {
  4279. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4280. goto out_free_irq;
  4281. }
  4282. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4283. enable_dma(ha->drq);
  4284. shp->unchecked_isa_dma = 1;
  4285. shp->irq = ha->irq;
  4286. shp->dma_channel = ha->drq;
  4287. ha->hanum = gdth_ctr_count++;
  4288. ha->shost = shp;
  4289. ha->pccb = &ha->cmdext;
  4290. ha->ccb_phys = 0L;
  4291. ha->pdev = NULL;
  4292. error = -ENOMEM;
  4293. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4294. &scratch_dma_handle);
  4295. if (!ha->pscratch)
  4296. goto out_dec_counters;
  4297. ha->scratch_phys = scratch_dma_handle;
  4298. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4299. &scratch_dma_handle);
  4300. if (!ha->pmsg)
  4301. goto out_free_pscratch;
  4302. ha->msg_phys = scratch_dma_handle;
  4303. #ifdef INT_COAL
  4304. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4305. sizeof(gdth_coal_status) * MAXOFFSETS,
  4306. &scratch_dma_handle);
  4307. if (!ha->coal_stat)
  4308. goto out_free_pmsg;
  4309. ha->coal_stat_phys = scratch_dma_handle;
  4310. #endif
  4311. ha->scratch_busy = FALSE;
  4312. ha->req_first = NULL;
  4313. ha->tid_cnt = MAX_HDRIVES;
  4314. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4315. ha->tid_cnt = max_ids;
  4316. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4317. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4318. ha->scan_mode = rescan ? 0x10 : 0;
  4319. error = -ENODEV;
  4320. if (!gdth_search_drives(ha)) {
  4321. printk("GDT-ISA: Error during device scan\n");
  4322. goto out_free_coal_stat;
  4323. }
  4324. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4325. hdr_channel = ha->bus_cnt;
  4326. ha->virt_bus = hdr_channel;
  4327. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4328. shp->max_cmd_len = 16;
  4329. shp->max_id = ha->tid_cnt;
  4330. shp->max_lun = MAXLUN;
  4331. shp->max_channel = ha->bus_cnt;
  4332. spin_lock_init(&ha->smp_lock);
  4333. gdth_enable_int(ha);
  4334. error = scsi_add_host(shp, NULL);
  4335. if (error)
  4336. goto out_free_coal_stat;
  4337. list_add_tail(&ha->list, &gdth_instances);
  4338. return 0;
  4339. out_free_coal_stat:
  4340. #ifdef INT_COAL
  4341. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4342. ha->coal_stat, ha->coal_stat_phys);
  4343. out_free_pmsg:
  4344. #endif
  4345. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4346. ha->pmsg, ha->msg_phys);
  4347. out_free_pscratch:
  4348. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4349. ha->pscratch, ha->scratch_phys);
  4350. out_dec_counters:
  4351. gdth_ctr_count--;
  4352. out_free_irq:
  4353. free_irq(ha->irq, ha);
  4354. out_host_put:
  4355. scsi_host_put(shp);
  4356. return error;
  4357. }
  4358. #endif /* CONFIG_ISA */
  4359. #ifdef CONFIG_EISA
  4360. static int gdth_eisa_probe_one(ushort eisa_slot)
  4361. {
  4362. struct Scsi_Host *shp;
  4363. gdth_ha_str *ha;
  4364. dma_addr_t scratch_dma_handle = 0;
  4365. int error, i;
  4366. if (!gdth_search_eisa(eisa_slot))
  4367. return -ENXIO;
  4368. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4369. if (!shp)
  4370. return -ENOMEM;
  4371. ha = shost_priv(shp);
  4372. error = -ENODEV;
  4373. if (!gdth_init_eisa(eisa_slot,ha))
  4374. goto out_host_put;
  4375. /* controller found and initialized */
  4376. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4377. eisa_slot >> 12, ha->irq);
  4378. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4379. if (error) {
  4380. printk("GDT-EISA: Unable to allocate IRQ\n");
  4381. goto out_host_put;
  4382. }
  4383. shp->unchecked_isa_dma = 0;
  4384. shp->irq = ha->irq;
  4385. shp->dma_channel = 0xff;
  4386. ha->hanum = gdth_ctr_count++;
  4387. ha->shost = shp;
  4388. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4389. ha->pccb = &ha->cmdext;
  4390. ha->ccb_phys = 0L;
  4391. error = -ENOMEM;
  4392. ha->pdev = NULL;
  4393. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4394. &scratch_dma_handle);
  4395. if (!ha->pscratch)
  4396. goto out_free_irq;
  4397. ha->scratch_phys = scratch_dma_handle;
  4398. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4399. &scratch_dma_handle);
  4400. if (!ha->pmsg)
  4401. goto out_free_pscratch;
  4402. ha->msg_phys = scratch_dma_handle;
  4403. #ifdef INT_COAL
  4404. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4405. sizeof(gdth_coal_status) * MAXOFFSETS,
  4406. &scratch_dma_handle);
  4407. if (!ha->coal_stat)
  4408. goto out_free_pmsg;
  4409. ha->coal_stat_phys = scratch_dma_handle;
  4410. #endif
  4411. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4412. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4413. if (!ha->ccb_phys)
  4414. goto out_free_coal_stat;
  4415. ha->scratch_busy = FALSE;
  4416. ha->req_first = NULL;
  4417. ha->tid_cnt = MAX_HDRIVES;
  4418. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4419. ha->tid_cnt = max_ids;
  4420. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4421. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4422. ha->scan_mode = rescan ? 0x10 : 0;
  4423. if (!gdth_search_drives(ha)) {
  4424. printk("GDT-EISA: Error during device scan\n");
  4425. error = -ENODEV;
  4426. goto out_free_ccb_phys;
  4427. }
  4428. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4429. hdr_channel = ha->bus_cnt;
  4430. ha->virt_bus = hdr_channel;
  4431. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4432. shp->max_cmd_len = 16;
  4433. shp->max_id = ha->tid_cnt;
  4434. shp->max_lun = MAXLUN;
  4435. shp->max_channel = ha->bus_cnt;
  4436. spin_lock_init(&ha->smp_lock);
  4437. gdth_enable_int(ha);
  4438. error = scsi_add_host(shp, NULL);
  4439. if (error)
  4440. goto out_free_coal_stat;
  4441. list_add_tail(&ha->list, &gdth_instances);
  4442. return 0;
  4443. out_free_ccb_phys:
  4444. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4445. PCI_DMA_BIDIRECTIONAL);
  4446. out_free_coal_stat:
  4447. #ifdef INT_COAL
  4448. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4449. ha->coal_stat, ha->coal_stat_phys);
  4450. out_free_pmsg:
  4451. #endif
  4452. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4453. ha->pmsg, ha->msg_phys);
  4454. out_free_pscratch:
  4455. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4456. ha->pscratch, ha->scratch_phys);
  4457. out_free_irq:
  4458. free_irq(ha->irq, ha);
  4459. gdth_ctr_count--;
  4460. out_host_put:
  4461. scsi_host_put(shp);
  4462. return error;
  4463. }
  4464. #endif /* CONFIG_EISA */
  4465. #ifdef CONFIG_PCI
  4466. static int gdth_pci_probe_one(gdth_pci_str *pcistr, int ctr)
  4467. {
  4468. struct Scsi_Host *shp;
  4469. gdth_ha_str *ha;
  4470. dma_addr_t scratch_dma_handle = 0;
  4471. int error, i;
  4472. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4473. if (!shp)
  4474. return -ENOMEM;
  4475. ha = shost_priv(shp);
  4476. error = -ENODEV;
  4477. if (!gdth_init_pci(&pcistr[ctr],ha))
  4478. goto out_host_put;
  4479. /* controller found and initialized */
  4480. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4481. pcistr[ctr].pdev->bus->number,
  4482. PCI_SLOT(pcistr[ctr].pdev->devfn),
  4483. ha->irq);
  4484. error = request_irq(ha->irq, gdth_interrupt,
  4485. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4486. if (error) {
  4487. printk("GDT-PCI: Unable to allocate IRQ\n");
  4488. goto out_host_put;
  4489. }
  4490. shp->unchecked_isa_dma = 0;
  4491. shp->irq = ha->irq;
  4492. shp->dma_channel = 0xff;
  4493. ha->hanum = gdth_ctr_count++;
  4494. ha->shost = shp;
  4495. ha->pccb = &ha->cmdext;
  4496. ha->ccb_phys = 0L;
  4497. error = -ENOMEM;
  4498. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4499. &scratch_dma_handle);
  4500. if (!ha->pscratch)
  4501. goto out_free_irq;
  4502. ha->scratch_phys = scratch_dma_handle;
  4503. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4504. &scratch_dma_handle);
  4505. if (!ha->pmsg)
  4506. goto out_free_pscratch;
  4507. ha->msg_phys = scratch_dma_handle;
  4508. #ifdef INT_COAL
  4509. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4510. sizeof(gdth_coal_status) * MAXOFFSETS,
  4511. &scratch_dma_handle);
  4512. if (!ha->coal_stat)
  4513. goto out_free_pmsg;
  4514. ha->coal_stat_phys = scratch_dma_handle;
  4515. #endif
  4516. ha->scratch_busy = FALSE;
  4517. ha->req_first = NULL;
  4518. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4519. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4520. ha->tid_cnt = max_ids;
  4521. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4522. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4523. ha->scan_mode = rescan ? 0x10 : 0;
  4524. error = -ENODEV;
  4525. if (!gdth_search_drives(ha)) {
  4526. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4527. goto out_free_coal_stat;
  4528. }
  4529. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4530. hdr_channel = ha->bus_cnt;
  4531. ha->virt_bus = hdr_channel;
  4532. /* 64-bit DMA only supported from FW >= x.43 */
  4533. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4534. !ha->dma64_support) {
  4535. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4536. printk(KERN_WARNING "GDT-PCI %d: "
  4537. "Unable to set 32-bit DMA\n", ha->hanum);
  4538. goto out_free_coal_stat;
  4539. }
  4540. } else {
  4541. shp->max_cmd_len = 16;
  4542. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4543. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4544. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4545. printk(KERN_WARNING "GDT-PCI %d: "
  4546. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4547. goto out_free_coal_stat;
  4548. }
  4549. }
  4550. shp->max_id = ha->tid_cnt;
  4551. shp->max_lun = MAXLUN;
  4552. shp->max_channel = ha->bus_cnt;
  4553. spin_lock_init(&ha->smp_lock);
  4554. gdth_enable_int(ha);
  4555. error = scsi_add_host(shp, &pcistr[ctr].pdev->dev);
  4556. if (error)
  4557. goto out_free_coal_stat;
  4558. list_add_tail(&ha->list, &gdth_instances);
  4559. return 0;
  4560. out_free_coal_stat:
  4561. #ifdef INT_COAL
  4562. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4563. ha->coal_stat, ha->coal_stat_phys);
  4564. out_free_pmsg:
  4565. #endif
  4566. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4567. ha->pmsg, ha->msg_phys);
  4568. out_free_pscratch:
  4569. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4570. ha->pscratch, ha->scratch_phys);
  4571. out_free_irq:
  4572. free_irq(ha->irq, ha);
  4573. gdth_ctr_count--;
  4574. out_host_put:
  4575. scsi_host_put(shp);
  4576. return error;
  4577. }
  4578. #endif /* CONFIG_PCI */
  4579. static void gdth_remove_one(gdth_ha_str *ha)
  4580. {
  4581. struct Scsi_Host *shp = ha->shost;
  4582. TRACE2(("gdth_remove_one()\n"));
  4583. scsi_remove_host(shp);
  4584. if (ha->sdev) {
  4585. scsi_free_host_dev(ha->sdev);
  4586. ha->sdev = NULL;
  4587. }
  4588. gdth_flush(ha);
  4589. if (shp->irq)
  4590. free_irq(shp->irq,ha);
  4591. #ifdef CONFIG_ISA
  4592. if (shp->dma_channel != 0xff)
  4593. free_dma(shp->dma_channel);
  4594. #endif
  4595. #ifdef INT_COAL
  4596. if (ha->coal_stat)
  4597. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4598. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4599. #endif
  4600. if (ha->pscratch)
  4601. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4602. ha->pscratch, ha->scratch_phys);
  4603. if (ha->pmsg)
  4604. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4605. ha->pmsg, ha->msg_phys);
  4606. if (ha->ccb_phys)
  4607. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4608. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4609. scsi_host_put(shp);
  4610. }
  4611. static int __init gdth_init(void)
  4612. {
  4613. if (disable) {
  4614. printk("GDT-HA: Controller driver disabled from"
  4615. " command line !\n");
  4616. return 0;
  4617. }
  4618. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4619. GDTH_VERSION_STR);
  4620. /* initializations */
  4621. gdth_polling = TRUE;
  4622. gdth_clear_events();
  4623. /* As default we do not probe for EISA or ISA controllers */
  4624. if (probe_eisa_isa) {
  4625. /* scanning for controllers, at first: ISA controller */
  4626. #ifdef CONFIG_ISA
  4627. ulong32 isa_bios;
  4628. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4629. isa_bios += 0x8000UL)
  4630. gdth_isa_probe_one(isa_bios);
  4631. #endif
  4632. #ifdef CONFIG_EISA
  4633. {
  4634. ushort eisa_slot;
  4635. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4636. eisa_slot += 0x1000)
  4637. gdth_eisa_probe_one(eisa_slot);
  4638. }
  4639. #endif
  4640. }
  4641. #ifdef CONFIG_PCI
  4642. /* scanning for PCI controllers */
  4643. {
  4644. gdth_pci_str pcistr[MAXHA];
  4645. int cnt,ctr;
  4646. cnt = gdth_search_pci(pcistr);
  4647. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n", cnt);
  4648. gdth_sort_pci(pcistr,cnt);
  4649. for (ctr = 0; ctr < cnt; ++ctr)
  4650. gdth_pci_probe_one(pcistr, ctr);
  4651. }
  4652. #endif /* CONFIG_PCI */
  4653. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4654. #ifdef GDTH_STATISTICS
  4655. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4656. init_timer(&gdth_timer);
  4657. gdth_timer.expires = jiffies + HZ;
  4658. gdth_timer.data = 0L;
  4659. gdth_timer.function = gdth_timeout;
  4660. add_timer(&gdth_timer);
  4661. #endif
  4662. major = register_chrdev(0,"gdth", &gdth_fops);
  4663. notifier_disabled = 0;
  4664. register_reboot_notifier(&gdth_notifier);
  4665. gdth_polling = FALSE;
  4666. return 0;
  4667. }
  4668. static void __exit gdth_exit(void)
  4669. {
  4670. gdth_ha_str *ha;
  4671. list_for_each_entry(ha, &gdth_instances, list)
  4672. gdth_remove_one(ha);
  4673. #ifdef GDTH_STATISTICS
  4674. del_timer(&gdth_timer);
  4675. #endif
  4676. unregister_chrdev(major,"gdth");
  4677. unregister_reboot_notifier(&gdth_notifier);
  4678. }
  4679. module_init(gdth_init);
  4680. module_exit(gdth_exit);
  4681. #ifndef MODULE
  4682. __setup("gdth=", option_setup);
  4683. #endif