ptrace.h 4.2 KB

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  1. /*
  2. * Based on arch/arm/include/asm/ptrace.h
  3. *
  4. * Copyright (C) 1996-2003 Russell King
  5. * Copyright (C) 2012 ARM Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef __ASM_PTRACE_H
  20. #define __ASM_PTRACE_H
  21. #include <uapi/asm/ptrace.h>
  22. /* AArch32-specific ptrace requests */
  23. #define COMPAT_PTRACE_GETREGS 12
  24. #define COMPAT_PTRACE_SETREGS 13
  25. #define COMPAT_PTRACE_GET_THREAD_AREA 22
  26. #define COMPAT_PTRACE_SET_SYSCALL 23
  27. #define COMPAT_PTRACE_GETVFPREGS 27
  28. #define COMPAT_PTRACE_SETVFPREGS 28
  29. #define COMPAT_PTRACE_GETHBPREGS 29
  30. #define COMPAT_PTRACE_SETHBPREGS 30
  31. #define COMPAT_PSR_MODE_USR 0x00000010
  32. #define COMPAT_PSR_T_BIT 0x00000020
  33. #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
  34. /*
  35. * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
  36. * process is located in memory.
  37. */
  38. #define COMPAT_PT_TEXT_ADDR 0x10000
  39. #define COMPAT_PT_DATA_ADDR 0x10004
  40. #define COMPAT_PT_TEXT_END_ADDR 0x10008
  41. #ifndef __ASSEMBLY__
  42. /* sizeof(struct user) for AArch32 */
  43. #define COMPAT_USER_SZ 296
  44. /* Architecturally defined mapping between AArch32 and AArch64 registers */
  45. #define compat_usr(x) regs[(x)]
  46. #define compat_sp regs[13]
  47. #define compat_lr regs[14]
  48. #define compat_sp_hyp regs[15]
  49. #define compat_sp_irq regs[16]
  50. #define compat_lr_irq regs[17]
  51. #define compat_sp_svc regs[18]
  52. #define compat_lr_svc regs[19]
  53. #define compat_sp_abt regs[20]
  54. #define compat_lr_abt regs[21]
  55. #define compat_sp_und regs[22]
  56. #define compat_lr_und regs[23]
  57. #define compat_r8_fiq regs[24]
  58. #define compat_r9_fiq regs[25]
  59. #define compat_r10_fiq regs[26]
  60. #define compat_r11_fiq regs[27]
  61. #define compat_r12_fiq regs[28]
  62. #define compat_sp_fiq regs[29]
  63. #define compat_lr_fiq regs[30]
  64. /*
  65. * This struct defines the way the registers are stored on the stack during an
  66. * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
  67. * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
  68. */
  69. struct pt_regs {
  70. union {
  71. struct user_pt_regs user_regs;
  72. struct {
  73. u64 regs[31];
  74. u64 sp;
  75. u64 pc;
  76. u64 pstate;
  77. };
  78. };
  79. u64 orig_x0;
  80. u64 syscallno;
  81. };
  82. #define arch_has_single_step() (1)
  83. #ifdef CONFIG_COMPAT
  84. #define compat_thumb_mode(regs) \
  85. (((regs)->pstate & COMPAT_PSR_T_BIT))
  86. #else
  87. #define compat_thumb_mode(regs) (0)
  88. #endif
  89. #define user_mode(regs) \
  90. (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
  91. #define compat_user_mode(regs) \
  92. (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
  93. (PSR_MODE32_BIT | PSR_MODE_EL0t))
  94. #define processor_mode(regs) \
  95. ((regs)->pstate & PSR_MODE_MASK)
  96. #define interrupts_enabled(regs) \
  97. (!((regs)->pstate & PSR_I_BIT))
  98. #define fast_interrupts_enabled(regs) \
  99. (!((regs)->pstate & PSR_F_BIT))
  100. #define user_stack_pointer(regs) \
  101. ((regs)->sp)
  102. /*
  103. * Are the current registers suitable for user mode? (used to maintain
  104. * security in signal handlers)
  105. */
  106. static inline int valid_user_regs(struct user_pt_regs *regs)
  107. {
  108. if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
  109. regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);
  110. /* The T bit is reserved for AArch64 */
  111. if (!(regs->pstate & PSR_MODE32_BIT))
  112. regs->pstate &= ~COMPAT_PSR_T_BIT;
  113. return 1;
  114. }
  115. /*
  116. * Force PSR to something logical...
  117. */
  118. regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
  119. COMPAT_PSR_T_BIT | PSR_MODE32_BIT;
  120. if (!(regs->pstate & PSR_MODE32_BIT)) {
  121. regs->pstate &= ~COMPAT_PSR_T_BIT;
  122. regs->pstate |= PSR_MODE_EL0t;
  123. }
  124. return 0;
  125. }
  126. #define instruction_pointer(regs) (regs)->pc
  127. #ifdef CONFIG_SMP
  128. extern unsigned long profile_pc(struct pt_regs *regs);
  129. #else
  130. #define profile_pc(regs) instruction_pointer(regs)
  131. #endif
  132. extern int aarch32_break_trap(struct pt_regs *regs);
  133. #endif /* __ASSEMBLY__ */
  134. #endif