oxygen_lib.c 13 KB

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  1. /*
  2. * C-Media CMI8788 driver - main driver module
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/mutex.h>
  22. #include <linux/pci.h>
  23. #include <sound/ac97_codec.h>
  24. #include <sound/asoundef.h>
  25. #include <sound/core.h>
  26. #include <sound/info.h>
  27. #include <sound/mpu401.h>
  28. #include <sound/pcm.h>
  29. #include "oxygen.h"
  30. #include "cm9780.h"
  31. MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  32. MODULE_DESCRIPTION("C-Media CMI8788 helper library");
  33. MODULE_LICENSE("GPL");
  34. static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
  35. {
  36. struct oxygen *chip = dev_id;
  37. unsigned int status, clear, elapsed_streams, i;
  38. status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
  39. if (!status)
  40. return IRQ_NONE;
  41. spin_lock(&chip->reg_lock);
  42. clear = status & (OXYGEN_CHANNEL_A |
  43. OXYGEN_CHANNEL_B |
  44. OXYGEN_CHANNEL_C |
  45. OXYGEN_CHANNEL_SPDIF |
  46. OXYGEN_CHANNEL_MULTICH |
  47. OXYGEN_CHANNEL_AC97 |
  48. OXYGEN_INT_SPDIF_IN_DETECT |
  49. OXYGEN_INT_GPIO);
  50. if (clear) {
  51. if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
  52. chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
  53. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  54. chip->interrupt_mask & ~clear);
  55. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  56. chip->interrupt_mask);
  57. }
  58. elapsed_streams = status & chip->pcm_running;
  59. spin_unlock(&chip->reg_lock);
  60. for (i = 0; i < PCM_COUNT; ++i)
  61. if ((elapsed_streams & (1 << i)) && chip->streams[i])
  62. snd_pcm_period_elapsed(chip->streams[i]);
  63. if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
  64. spin_lock(&chip->reg_lock);
  65. i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
  66. if (i & OXYGEN_SPDIF_RATE_INT) {
  67. oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
  68. schedule_work(&chip->spdif_input_bits_work);
  69. }
  70. spin_unlock(&chip->reg_lock);
  71. }
  72. if (status & OXYGEN_INT_GPIO)
  73. ;
  74. if ((status & OXYGEN_INT_MIDI) && chip->midi)
  75. snd_mpu401_uart_interrupt(0, chip->midi->private_data);
  76. return IRQ_HANDLED;
  77. }
  78. static void oxygen_spdif_input_bits_changed(struct work_struct *work)
  79. {
  80. struct oxygen *chip = container_of(work, struct oxygen,
  81. spdif_input_bits_work);
  82. spin_lock_irq(&chip->reg_lock);
  83. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  84. OXYGEN_SPDIF_IN_CLOCK_96,
  85. OXYGEN_SPDIF_IN_CLOCK_MASK);
  86. spin_unlock_irq(&chip->reg_lock);
  87. msleep(1);
  88. if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
  89. & OXYGEN_SPDIF_LOCK_STATUS)) {
  90. spin_lock_irq(&chip->reg_lock);
  91. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  92. OXYGEN_SPDIF_IN_CLOCK_192,
  93. OXYGEN_SPDIF_IN_CLOCK_MASK);
  94. spin_unlock_irq(&chip->reg_lock);
  95. msleep(1);
  96. if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
  97. & OXYGEN_SPDIF_LOCK_STATUS)) {
  98. spin_lock_irq(&chip->reg_lock);
  99. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  100. OXYGEN_SPDIF_IN_CLOCK_96,
  101. OXYGEN_SPDIF_IN_CLOCK_MASK);
  102. spin_unlock_irq(&chip->reg_lock);
  103. }
  104. }
  105. if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
  106. spin_lock_irq(&chip->reg_lock);
  107. chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
  108. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  109. chip->interrupt_mask);
  110. spin_unlock_irq(&chip->reg_lock);
  111. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  112. &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
  113. }
  114. }
  115. #ifdef CONFIG_PROC_FS
  116. static void oxygen_proc_read(struct snd_info_entry *entry,
  117. struct snd_info_buffer *buffer)
  118. {
  119. struct oxygen *chip = entry->private_data;
  120. int i, j;
  121. snd_iprintf(buffer, "CMI8788\n\n");
  122. for (i = 0; i < 0x100; i += 0x10) {
  123. snd_iprintf(buffer, "%02x:", i);
  124. for (j = 0; j < 0x10; ++j)
  125. snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
  126. snd_iprintf(buffer, "\n");
  127. }
  128. if (mutex_lock_interruptible(&chip->mutex) < 0)
  129. return;
  130. if (chip->has_ac97_0) {
  131. snd_iprintf(buffer, "\nAC97\n");
  132. for (i = 0; i < 0x80; i += 0x10) {
  133. snd_iprintf(buffer, "%02x:", i);
  134. for (j = 0; j < 0x10; j += 2)
  135. snd_iprintf(buffer, " %04x",
  136. oxygen_read_ac97(chip, 0, i + j));
  137. snd_iprintf(buffer, "\n");
  138. }
  139. }
  140. if (chip->has_ac97_1) {
  141. snd_iprintf(buffer, "\nAC97 2\n");
  142. for (i = 0; i < 0x80; i += 0x10) {
  143. snd_iprintf(buffer, "%02x:", i);
  144. for (j = 0; j < 0x10; j += 2)
  145. snd_iprintf(buffer, " %04x",
  146. oxygen_read_ac97(chip, 1, i + j));
  147. snd_iprintf(buffer, "\n");
  148. }
  149. }
  150. mutex_unlock(&chip->mutex);
  151. }
  152. static void __devinit oxygen_proc_init(struct oxygen *chip)
  153. {
  154. struct snd_info_entry *entry;
  155. if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
  156. snd_info_set_text_ops(entry, chip, oxygen_proc_read);
  157. }
  158. #else
  159. #define oxygen_proc_init(chip)
  160. #endif
  161. static void __devinit oxygen_init(struct oxygen *chip)
  162. {
  163. unsigned int i;
  164. chip->dac_routing = 1;
  165. for (i = 0; i < 8; ++i)
  166. chip->dac_volume[i] = 0xff;
  167. chip->spdif_playback_enable = 1;
  168. chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
  169. (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
  170. chip->spdif_pcm_bits = chip->spdif_bits;
  171. if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
  172. chip->revision = 2;
  173. else
  174. chip->revision = 1;
  175. if (chip->revision == 1)
  176. oxygen_set_bits8(chip, OXYGEN_MISC,
  177. OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
  178. i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
  179. chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
  180. chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
  181. oxygen_set_bits8(chip, OXYGEN_FUNCTION,
  182. OXYGEN_FUNCTION_RESET_CODEC |
  183. chip->model->function_flags);
  184. oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
  185. OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
  186. OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
  187. OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
  188. oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
  189. OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
  190. OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
  191. OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
  192. oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
  193. OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
  194. OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
  195. OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
  196. oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
  197. OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
  198. OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
  199. OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
  200. oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_RATE_MASK);
  201. oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
  202. oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
  203. OXYGEN_PLAY_MULTICH_I2S_DAC | OXYGEN_PLAY_SPDIF_SPDIF |
  204. (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
  205. (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
  206. (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
  207. (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
  208. oxygen_write8(chip, OXYGEN_REC_ROUTING,
  209. OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
  210. OXYGEN_REC_B_ROUTE_AC97_1 |
  211. OXYGEN_REC_C_ROUTE_SPDIF);
  212. oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
  213. oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
  214. (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
  215. (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
  216. (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
  217. (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
  218. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
  219. oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
  220. oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
  221. if (chip->has_ac97_0) {
  222. oxygen_clear_bits16(chip, OXYGEN_AC97_OUT_CONFIG,
  223. OXYGEN_AC97_CODEC0_FRONTL |
  224. OXYGEN_AC97_CODEC0_FRONTR |
  225. OXYGEN_AC97_CODEC0_SIDEL |
  226. OXYGEN_AC97_CODEC0_SIDER |
  227. OXYGEN_AC97_CODEC0_CENTER |
  228. OXYGEN_AC97_CODEC0_BASE |
  229. OXYGEN_AC97_CODEC0_REARL |
  230. OXYGEN_AC97_CODEC0_REARR);
  231. oxygen_set_bits16(chip, OXYGEN_AC97_IN_CONFIG,
  232. OXYGEN_AC97_CODEC0_LINEL |
  233. OXYGEN_AC97_CODEC0_LINER);
  234. oxygen_write_ac97(chip, 0, AC97_RESET, 0);
  235. msleep(1);
  236. oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
  237. CM9780_GPIO0IO | CM9780_GPIO1IO);
  238. oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
  239. CM9780_BSTSEL | CM9780_STRO_MIC |
  240. CM9780_MIX2FR | CM9780_PCBSW);
  241. oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
  242. CM9780_RSOE | CM9780_CBOE |
  243. CM9780_SSOE | CM9780_FROE |
  244. CM9780_MIC2MIC | CM9780_LI2LI);
  245. oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
  246. oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
  247. oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
  248. oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
  249. oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
  250. oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
  251. oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
  252. oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
  253. oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
  254. oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
  255. oxygen_ac97_clear_bits(chip, 0,
  256. CM9780_GPIO_STATUS, CM9780_GPO0);
  257. /* power down unused ADCs and DACs */
  258. oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
  259. AC97_PD_PR0 | AC97_PD_PR1);
  260. oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
  261. AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
  262. }
  263. }
  264. static void oxygen_card_free(struct snd_card *card)
  265. {
  266. struct oxygen *chip = card->private_data;
  267. spin_lock_irq(&chip->reg_lock);
  268. chip->interrupt_mask = 0;
  269. chip->pcm_running = 0;
  270. oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
  271. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
  272. spin_unlock_irq(&chip->reg_lock);
  273. if (chip->irq >= 0) {
  274. free_irq(chip->irq, chip);
  275. synchronize_irq(chip->irq);
  276. }
  277. flush_scheduled_work();
  278. chip->model->cleanup(chip);
  279. mutex_destroy(&chip->mutex);
  280. pci_release_regions(chip->pci);
  281. pci_disable_device(chip->pci);
  282. }
  283. int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
  284. int midi, const struct oxygen_model *model)
  285. {
  286. struct snd_card *card;
  287. struct oxygen *chip;
  288. int err;
  289. card = snd_card_new(index, id, model->owner, sizeof *chip);
  290. if (!card)
  291. return -ENOMEM;
  292. chip = card->private_data;
  293. chip->card = card;
  294. chip->pci = pci;
  295. chip->irq = -1;
  296. chip->model = model;
  297. spin_lock_init(&chip->reg_lock);
  298. mutex_init(&chip->mutex);
  299. INIT_WORK(&chip->spdif_input_bits_work,
  300. oxygen_spdif_input_bits_changed);
  301. err = pci_enable_device(pci);
  302. if (err < 0)
  303. goto err_card;
  304. err = pci_request_regions(pci, model->chip);
  305. if (err < 0) {
  306. snd_printk(KERN_ERR "cannot reserve PCI resources\n");
  307. goto err_pci_enable;
  308. }
  309. if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
  310. pci_resource_len(pci, 0) < 0x100) {
  311. snd_printk(KERN_ERR "invalid PCI I/O range\n");
  312. err = -ENXIO;
  313. goto err_pci_regions;
  314. }
  315. chip->addr = pci_resource_start(pci, 0);
  316. pci_set_master(pci);
  317. snd_card_set_dev(card, &pci->dev);
  318. card->private_free = oxygen_card_free;
  319. oxygen_init(chip);
  320. model->init(chip);
  321. err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
  322. model->chip, chip);
  323. if (err < 0) {
  324. snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
  325. goto err_card;
  326. }
  327. chip->irq = pci->irq;
  328. strcpy(card->driver, model->chip);
  329. strcpy(card->shortname, model->shortname);
  330. sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
  331. model->longname, chip->revision, chip->addr, chip->irq);
  332. strcpy(card->mixername, model->chip);
  333. snd_component_add(card, model->chip);
  334. err = oxygen_pcm_init(chip);
  335. if (err < 0)
  336. goto err_card;
  337. err = oxygen_mixer_init(chip);
  338. if (err < 0)
  339. goto err_card;
  340. oxygen_write8_masked(chip, OXYGEN_MISC,
  341. midi ? OXYGEN_MISC_MIDI : 0, OXYGEN_MISC_MIDI);
  342. if (midi) {
  343. err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
  344. chip->addr + OXYGEN_MPU401,
  345. MPU401_INFO_INTEGRATED, 0, 0,
  346. &chip->midi);
  347. if (err < 0)
  348. goto err_card;
  349. }
  350. oxygen_proc_init(chip);
  351. spin_lock_irq(&chip->reg_lock);
  352. chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
  353. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  354. spin_unlock_irq(&chip->reg_lock);
  355. err = snd_card_register(card);
  356. if (err < 0)
  357. goto err_card;
  358. pci_set_drvdata(pci, card);
  359. return 0;
  360. err_pci_regions:
  361. pci_release_regions(pci);
  362. err_pci_enable:
  363. pci_disable_device(pci);
  364. err_card:
  365. snd_card_free(card);
  366. return err;
  367. }
  368. EXPORT_SYMBOL(oxygen_pci_probe);
  369. void __devexit oxygen_pci_remove(struct pci_dev *pci)
  370. {
  371. snd_card_free(pci_get_drvdata(pci));
  372. pci_set_drvdata(pci, NULL);
  373. }
  374. EXPORT_SYMBOL(oxygen_pci_remove);