cx88-dvb.c 27 KB

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  1. /*
  2. *
  3. * device driver for Conexant 2388x based TV cards
  4. * MPEG Transport Stream (DVB) routines
  5. *
  6. * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
  7. * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/device.h>
  26. #include <linux/fs.h>
  27. #include <linux/kthread.h>
  28. #include <linux/file.h>
  29. #include <linux/suspend.h>
  30. #include "cx88.h"
  31. #include "dvb-pll.h"
  32. #include <media/v4l2-common.h>
  33. #include "mt352.h"
  34. #include "mt352_priv.h"
  35. #include "cx88-vp3054-i2c.h"
  36. #include "zl10353.h"
  37. #include "cx22702.h"
  38. #include "or51132.h"
  39. #include "lgdt330x.h"
  40. #include "s5h1409.h"
  41. #include "xc5000.h"
  42. #include "nxt200x.h"
  43. #include "cx24123.h"
  44. #include "isl6421.h"
  45. #include "tuner-xc2028.h"
  46. #include "tuner-xc2028-types.h"
  47. MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
  48. MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  49. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  50. MODULE_LICENSE("GPL");
  51. static unsigned int debug;
  52. module_param(debug, int, 0644);
  53. MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
  54. #define dprintk(level,fmt, arg...) if (debug >= level) \
  55. printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
  56. /* ------------------------------------------------------------------ */
  57. static int dvb_buf_setup(struct videobuf_queue *q,
  58. unsigned int *count, unsigned int *size)
  59. {
  60. struct cx8802_dev *dev = q->priv_data;
  61. dev->ts_packet_size = 188 * 4;
  62. dev->ts_packet_count = 32;
  63. *size = dev->ts_packet_size * dev->ts_packet_count;
  64. *count = 32;
  65. return 0;
  66. }
  67. static int dvb_buf_prepare(struct videobuf_queue *q,
  68. struct videobuf_buffer *vb, enum v4l2_field field)
  69. {
  70. struct cx8802_dev *dev = q->priv_data;
  71. return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
  72. }
  73. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  74. {
  75. struct cx8802_dev *dev = q->priv_data;
  76. cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
  77. }
  78. static void dvb_buf_release(struct videobuf_queue *q,
  79. struct videobuf_buffer *vb)
  80. {
  81. cx88_free_buffer(q, (struct cx88_buffer*)vb);
  82. }
  83. static struct videobuf_queue_ops dvb_qops = {
  84. .buf_setup = dvb_buf_setup,
  85. .buf_prepare = dvb_buf_prepare,
  86. .buf_queue = dvb_buf_queue,
  87. .buf_release = dvb_buf_release,
  88. };
  89. /* ------------------------------------------------------------------ */
  90. static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
  91. {
  92. struct cx8802_dev *dev= fe->dvb->priv;
  93. struct cx8802_driver *drv = NULL;
  94. int ret = 0;
  95. drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
  96. if (drv) {
  97. if (acquire)
  98. ret = drv->request_acquire(drv);
  99. else
  100. ret = drv->request_release(drv);
  101. }
  102. return ret;
  103. }
  104. /* ------------------------------------------------------------------ */
  105. static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
  106. {
  107. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
  108. static u8 reset [] = { RESET, 0x80 };
  109. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  110. static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
  111. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  112. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  113. mt352_write(fe, clock_config, sizeof(clock_config));
  114. udelay(200);
  115. mt352_write(fe, reset, sizeof(reset));
  116. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  117. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  118. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  119. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  120. return 0;
  121. }
  122. static int dvico_dual_demod_init(struct dvb_frontend *fe)
  123. {
  124. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
  125. static u8 reset [] = { RESET, 0x80 };
  126. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  127. static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
  128. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  129. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  130. mt352_write(fe, clock_config, sizeof(clock_config));
  131. udelay(200);
  132. mt352_write(fe, reset, sizeof(reset));
  133. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  134. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  135. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  136. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  137. return 0;
  138. }
  139. static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
  140. {
  141. static u8 clock_config [] = { 0x89, 0x38, 0x39 };
  142. static u8 reset [] = { 0x50, 0x80 };
  143. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  144. static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
  145. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  146. static u8 dntv_extra[] = { 0xB5, 0x7A };
  147. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  148. mt352_write(fe, clock_config, sizeof(clock_config));
  149. udelay(2000);
  150. mt352_write(fe, reset, sizeof(reset));
  151. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  152. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  153. udelay(2000);
  154. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  155. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  156. return 0;
  157. }
  158. static struct mt352_config dvico_fusionhdtv = {
  159. .demod_address = 0x0f,
  160. .demod_init = dvico_fusionhdtv_demod_init,
  161. };
  162. static struct mt352_config dntv_live_dvbt_config = {
  163. .demod_address = 0x0f,
  164. .demod_init = dntv_live_dvbt_demod_init,
  165. };
  166. static struct mt352_config dvico_fusionhdtv_dual = {
  167. .demod_address = 0x0f,
  168. .demod_init = dvico_dual_demod_init,
  169. };
  170. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  171. static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
  172. {
  173. static u8 clock_config [] = { 0x89, 0x38, 0x38 };
  174. static u8 reset [] = { 0x50, 0x80 };
  175. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  176. static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
  177. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  178. static u8 dntv_extra[] = { 0xB5, 0x7A };
  179. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  180. mt352_write(fe, clock_config, sizeof(clock_config));
  181. udelay(2000);
  182. mt352_write(fe, reset, sizeof(reset));
  183. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  184. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  185. udelay(2000);
  186. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  187. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  188. return 0;
  189. }
  190. static struct mt352_config dntv_live_dvbt_pro_config = {
  191. .demod_address = 0x0f,
  192. .no_tuner = 1,
  193. .demod_init = dntv_live_dvbt_pro_demod_init,
  194. };
  195. #endif
  196. static struct zl10353_config dvico_fusionhdtv_hybrid = {
  197. .demod_address = 0x0f,
  198. .no_tuner = 1,
  199. };
  200. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  201. .demod_address = 0x0f,
  202. .if2 = 45600,
  203. .no_tuner = 1,
  204. };
  205. static struct mt352_config dvico_fusionhdtv_mt352_xc3028 = {
  206. .demod_address = 0x0f,
  207. .if2 = 4560,
  208. .no_tuner = 1,
  209. .demod_init = dvico_fusionhdtv_demod_init,
  210. };
  211. static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
  212. .demod_address = 0x0f,
  213. };
  214. static struct cx22702_config connexant_refboard_config = {
  215. .demod_address = 0x43,
  216. .output_mode = CX22702_SERIAL_OUTPUT,
  217. };
  218. static struct cx22702_config hauppauge_hvr_config = {
  219. .demod_address = 0x63,
  220. .output_mode = CX22702_SERIAL_OUTPUT,
  221. };
  222. static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  223. {
  224. struct cx8802_dev *dev= fe->dvb->priv;
  225. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  226. return 0;
  227. }
  228. static struct or51132_config pchdtv_hd3000 = {
  229. .demod_address = 0x15,
  230. .set_ts_params = or51132_set_ts_param,
  231. };
  232. static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
  233. {
  234. struct cx8802_dev *dev= fe->dvb->priv;
  235. struct cx88_core *core = dev->core;
  236. dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
  237. if (index == 0)
  238. cx_clear(MO_GP0_IO, 8);
  239. else
  240. cx_set(MO_GP0_IO, 8);
  241. return 0;
  242. }
  243. static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  244. {
  245. struct cx8802_dev *dev= fe->dvb->priv;
  246. if (is_punctured)
  247. dev->ts_gen_cntrl |= 0x04;
  248. else
  249. dev->ts_gen_cntrl &= ~0x04;
  250. return 0;
  251. }
  252. static struct lgdt330x_config fusionhdtv_3_gold = {
  253. .demod_address = 0x0e,
  254. .demod_chip = LGDT3302,
  255. .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
  256. .set_ts_params = lgdt330x_set_ts_param,
  257. };
  258. static struct lgdt330x_config fusionhdtv_5_gold = {
  259. .demod_address = 0x0e,
  260. .demod_chip = LGDT3303,
  261. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  262. .set_ts_params = lgdt330x_set_ts_param,
  263. };
  264. static struct lgdt330x_config pchdtv_hd5500 = {
  265. .demod_address = 0x59,
  266. .demod_chip = LGDT3303,
  267. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  268. .set_ts_params = lgdt330x_set_ts_param,
  269. };
  270. static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  271. {
  272. struct cx8802_dev *dev= fe->dvb->priv;
  273. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  274. return 0;
  275. }
  276. static struct nxt200x_config ati_hdtvwonder = {
  277. .demod_address = 0x0a,
  278. .set_ts_params = nxt200x_set_ts_param,
  279. };
  280. static int cx24123_set_ts_param(struct dvb_frontend* fe,
  281. int is_punctured)
  282. {
  283. struct cx8802_dev *dev= fe->dvb->priv;
  284. dev->ts_gen_cntrl = 0x02;
  285. return 0;
  286. }
  287. static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
  288. fe_sec_voltage_t voltage)
  289. {
  290. struct cx8802_dev *dev= fe->dvb->priv;
  291. struct cx88_core *core = dev->core;
  292. if (voltage == SEC_VOLTAGE_OFF)
  293. cx_write(MO_GP0_IO, 0x000006fb);
  294. else
  295. cx_write(MO_GP0_IO, 0x000006f9);
  296. if (core->prev_set_voltage)
  297. return core->prev_set_voltage(fe, voltage);
  298. return 0;
  299. }
  300. static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
  301. fe_sec_voltage_t voltage)
  302. {
  303. struct cx8802_dev *dev= fe->dvb->priv;
  304. struct cx88_core *core = dev->core;
  305. if (voltage == SEC_VOLTAGE_OFF) {
  306. dprintk(1,"LNB Voltage OFF\n");
  307. cx_write(MO_GP0_IO, 0x0000efff);
  308. }
  309. if (core->prev_set_voltage)
  310. return core->prev_set_voltage(fe, voltage);
  311. return 0;
  312. }
  313. static int cx88_xc3028_callback(void *ptr, int command, int arg)
  314. {
  315. struct cx88_core *core = ptr;
  316. switch (command) {
  317. case XC2028_TUNER_RESET:
  318. /* Send the tuner in then out of reset */
  319. dprintk(1, "%s: XC2028_TUNER_RESET %d\n", __FUNCTION__, arg);
  320. switch (core->boardnr) {
  321. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  322. /* GPIO-4 xc3028 tuner */
  323. cx_set(MO_GP0_IO, 0x00001000);
  324. cx_clear(MO_GP0_IO, 0x00000010);
  325. msleep(100);
  326. cx_set(MO_GP0_IO, 0x00000010);
  327. msleep(100);
  328. break;
  329. }
  330. break;
  331. case XC2028_RESET_CLK:
  332. dprintk(1, "%s: XC2028_RESET_CLK %d\n", __FUNCTION__, arg);
  333. break;
  334. default:
  335. dprintk(1, "%s: unknown command %d, arg %d\n", __FUNCTION__,
  336. command, arg);
  337. return -EINVAL;
  338. }
  339. return 0;
  340. }
  341. static struct cx24123_config geniatech_dvbs_config = {
  342. .demod_address = 0x55,
  343. .set_ts_params = cx24123_set_ts_param,
  344. };
  345. static struct cx24123_config hauppauge_novas_config = {
  346. .demod_address = 0x55,
  347. .set_ts_params = cx24123_set_ts_param,
  348. };
  349. static struct cx24123_config kworld_dvbs_100_config = {
  350. .demod_address = 0x15,
  351. .set_ts_params = cx24123_set_ts_param,
  352. .lnb_polarity = 1,
  353. };
  354. static struct s5h1409_config pinnacle_pctv_hd_800i_config = {
  355. .demod_address = 0x32 >> 1,
  356. .output_mode = S5H1409_PARALLEL_OUTPUT,
  357. .gpio = S5H1409_GPIO_ON,
  358. .qam_if = 44000,
  359. .inversion = S5H1409_INVERSION_OFF,
  360. .status_mode = S5H1409_DEMODLOCKING,
  361. .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK,
  362. };
  363. static struct s5h1409_config dvico_hdtv5_pci_nano_config = {
  364. .demod_address = 0x32 >> 1,
  365. .output_mode = S5H1409_SERIAL_OUTPUT,
  366. .gpio = S5H1409_GPIO_OFF,
  367. .inversion = S5H1409_INVERSION_OFF,
  368. .status_mode = S5H1409_DEMODLOCKING,
  369. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  370. };
  371. static struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
  372. .i2c_address = 0x64,
  373. .if_khz = 5380,
  374. .tuner_callback = cx88_tuner_callback,
  375. };
  376. static struct zl10353_config cx88_geniatech_x8000_mt = {
  377. .demod_address = (0x1e >> 1),
  378. .no_tuner = 1,
  379. };
  380. static int dvb_register(struct cx8802_dev *dev)
  381. {
  382. int attach_xc3028 = 0;
  383. /* init struct videobuf_dvb */
  384. dev->dvb.name = dev->core->name;
  385. dev->ts_gen_cntrl = 0x0c;
  386. /* init frontend */
  387. switch (dev->core->boardnr) {
  388. case CX88_BOARD_HAUPPAUGE_DVB_T1:
  389. dev->dvb.frontend = dvb_attach(cx22702_attach,
  390. &connexant_refboard_config,
  391. &dev->core->i2c_adap);
  392. if (dev->dvb.frontend != NULL) {
  393. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  394. &dev->core->i2c_adap,
  395. DVB_PLL_THOMSON_DTT759X);
  396. }
  397. break;
  398. case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
  399. case CX88_BOARD_CONEXANT_DVB_T1:
  400. case CX88_BOARD_KWORLD_DVB_T_CX22702:
  401. case CX88_BOARD_WINFAST_DTV1000:
  402. dev->dvb.frontend = dvb_attach(cx22702_attach,
  403. &connexant_refboard_config,
  404. &dev->core->i2c_adap);
  405. if (dev->dvb.frontend != NULL) {
  406. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  407. &dev->core->i2c_adap,
  408. DVB_PLL_THOMSON_DTT7579);
  409. }
  410. break;
  411. case CX88_BOARD_WINFAST_DTV2000H:
  412. case CX88_BOARD_HAUPPAUGE_HVR1100:
  413. case CX88_BOARD_HAUPPAUGE_HVR1100LP:
  414. case CX88_BOARD_HAUPPAUGE_HVR1300:
  415. case CX88_BOARD_HAUPPAUGE_HVR3000:
  416. dev->dvb.frontend = dvb_attach(cx22702_attach,
  417. &hauppauge_hvr_config,
  418. &dev->core->i2c_adap);
  419. if (dev->dvb.frontend != NULL) {
  420. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  421. &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
  422. }
  423. break;
  424. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
  425. dev->dvb.frontend = dvb_attach(mt352_attach,
  426. &dvico_fusionhdtv,
  427. &dev->core->i2c_adap);
  428. if (dev->dvb.frontend != NULL) {
  429. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  430. NULL, DVB_PLL_THOMSON_DTT7579);
  431. break;
  432. }
  433. /* ZL10353 replaces MT352 on later cards */
  434. dev->dvb.frontend = dvb_attach(zl10353_attach,
  435. &dvico_fusionhdtv_plus_v1_1,
  436. &dev->core->i2c_adap);
  437. if (dev->dvb.frontend != NULL) {
  438. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  439. NULL, DVB_PLL_THOMSON_DTT7579);
  440. }
  441. break;
  442. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
  443. /* The tin box says DEE1601, but it seems to be DTT7579
  444. * compatible, with a slightly different MT352 AGC gain. */
  445. dev->dvb.frontend = dvb_attach(mt352_attach,
  446. &dvico_fusionhdtv_dual,
  447. &dev->core->i2c_adap);
  448. if (dev->dvb.frontend != NULL) {
  449. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  450. NULL, DVB_PLL_THOMSON_DTT7579);
  451. break;
  452. }
  453. /* ZL10353 replaces MT352 on later cards */
  454. dev->dvb.frontend = dvb_attach(zl10353_attach,
  455. &dvico_fusionhdtv_plus_v1_1,
  456. &dev->core->i2c_adap);
  457. if (dev->dvb.frontend != NULL) {
  458. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  459. NULL, DVB_PLL_THOMSON_DTT7579);
  460. }
  461. break;
  462. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
  463. dev->dvb.frontend = dvb_attach(mt352_attach,
  464. &dvico_fusionhdtv,
  465. &dev->core->i2c_adap);
  466. if (dev->dvb.frontend != NULL) {
  467. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  468. NULL, DVB_PLL_LG_Z201);
  469. }
  470. break;
  471. case CX88_BOARD_KWORLD_DVB_T:
  472. case CX88_BOARD_DNTV_LIVE_DVB_T:
  473. case CX88_BOARD_ADSTECH_DVB_T_PCI:
  474. dev->dvb.frontend = dvb_attach(mt352_attach,
  475. &dntv_live_dvbt_config,
  476. &dev->core->i2c_adap);
  477. if (dev->dvb.frontend != NULL) {
  478. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  479. NULL, DVB_PLL_UNKNOWN_1);
  480. }
  481. break;
  482. case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
  483. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  484. /* MT352 is on a secondary I2C bus made from some GPIO lines */
  485. dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
  486. &dev->vp3054->adap);
  487. if (dev->dvb.frontend != NULL) {
  488. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  489. &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
  490. }
  491. #else
  492. printk(KERN_ERR "%s/2: built without vp3054 support\n", dev->core->name);
  493. #endif
  494. break;
  495. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
  496. dev->dvb.frontend = dvb_attach(zl10353_attach,
  497. &dvico_fusionhdtv_hybrid,
  498. &dev->core->i2c_adap);
  499. if (dev->dvb.frontend != NULL) {
  500. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  501. &dev->core->i2c_adap,
  502. DVB_PLL_THOMSON_FE6600);
  503. }
  504. break;
  505. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
  506. dev->dvb.frontend = dvb_attach(zl10353_attach,
  507. &dvico_fusionhdtv_xc3028,
  508. &dev->core->i2c_adap);
  509. if (dev->dvb.frontend == NULL)
  510. dev->dvb.frontend = dvb_attach(mt352_attach,
  511. &dvico_fusionhdtv_mt352_xc3028,
  512. &dev->core->i2c_adap);
  513. /*
  514. * On this board, the demod provides the I2C bus pullup.
  515. * We must not permit gate_ctrl to be performed, or
  516. * the xc3028 cannot communicate on the bus.
  517. */
  518. if (dev->dvb.frontend)
  519. dev->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  520. attach_xc3028 = 1;
  521. break;
  522. case CX88_BOARD_PCHDTV_HD3000:
  523. dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
  524. &dev->core->i2c_adap);
  525. if (dev->dvb.frontend != NULL) {
  526. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  527. &dev->core->i2c_adap,
  528. DVB_PLL_THOMSON_DTT761X);
  529. }
  530. break;
  531. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  532. dev->ts_gen_cntrl = 0x08;
  533. {
  534. /* Do a hardware reset of chip before using it. */
  535. struct cx88_core *core = dev->core;
  536. cx_clear(MO_GP0_IO, 1);
  537. mdelay(100);
  538. cx_set(MO_GP0_IO, 1);
  539. mdelay(200);
  540. /* Select RF connector callback */
  541. fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
  542. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  543. &fusionhdtv_3_gold,
  544. &dev->core->i2c_adap);
  545. if (dev->dvb.frontend != NULL) {
  546. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  547. &dev->core->i2c_adap,
  548. DVB_PLL_MICROTUNE_4042);
  549. }
  550. }
  551. break;
  552. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  553. dev->ts_gen_cntrl = 0x08;
  554. {
  555. /* Do a hardware reset of chip before using it. */
  556. struct cx88_core *core = dev->core;
  557. cx_clear(MO_GP0_IO, 1);
  558. mdelay(100);
  559. cx_set(MO_GP0_IO, 9);
  560. mdelay(200);
  561. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  562. &fusionhdtv_3_gold,
  563. &dev->core->i2c_adap);
  564. if (dev->dvb.frontend != NULL) {
  565. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  566. &dev->core->i2c_adap,
  567. DVB_PLL_THOMSON_DTT761X);
  568. }
  569. }
  570. break;
  571. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  572. dev->ts_gen_cntrl = 0x08;
  573. {
  574. /* Do a hardware reset of chip before using it. */
  575. struct cx88_core *core = dev->core;
  576. cx_clear(MO_GP0_IO, 1);
  577. mdelay(100);
  578. cx_set(MO_GP0_IO, 1);
  579. mdelay(200);
  580. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  581. &fusionhdtv_5_gold,
  582. &dev->core->i2c_adap);
  583. if (dev->dvb.frontend != NULL) {
  584. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  585. &dev->core->i2c_adap,
  586. DVB_PLL_LG_TDVS_H06XF);
  587. }
  588. }
  589. break;
  590. case CX88_BOARD_PCHDTV_HD5500:
  591. dev->ts_gen_cntrl = 0x08;
  592. {
  593. /* Do a hardware reset of chip before using it. */
  594. struct cx88_core *core = dev->core;
  595. cx_clear(MO_GP0_IO, 1);
  596. mdelay(100);
  597. cx_set(MO_GP0_IO, 1);
  598. mdelay(200);
  599. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  600. &pchdtv_hd5500,
  601. &dev->core->i2c_adap);
  602. if (dev->dvb.frontend != NULL) {
  603. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  604. &dev->core->i2c_adap,
  605. DVB_PLL_LG_TDVS_H06XF);
  606. }
  607. }
  608. break;
  609. case CX88_BOARD_ATI_HDTVWONDER:
  610. dev->dvb.frontend = dvb_attach(nxt200x_attach,
  611. &ati_hdtvwonder,
  612. &dev->core->i2c_adap);
  613. if (dev->dvb.frontend != NULL) {
  614. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  615. NULL, DVB_PLL_TUV1236D);
  616. }
  617. break;
  618. case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
  619. case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
  620. dev->dvb.frontend = dvb_attach(cx24123_attach,
  621. &hauppauge_novas_config,
  622. &dev->core->i2c_adap);
  623. if (dev->dvb.frontend) {
  624. dvb_attach(isl6421_attach, dev->dvb.frontend,
  625. &dev->core->i2c_adap, 0x08, 0x00, 0x00);
  626. }
  627. break;
  628. case CX88_BOARD_KWORLD_DVBS_100:
  629. dev->dvb.frontend = dvb_attach(cx24123_attach,
  630. &kworld_dvbs_100_config,
  631. &dev->core->i2c_adap);
  632. if (dev->dvb.frontend) {
  633. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  634. dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
  635. }
  636. break;
  637. case CX88_BOARD_GENIATECH_DVBS:
  638. dev->dvb.frontend = dvb_attach(cx24123_attach,
  639. &geniatech_dvbs_config,
  640. &dev->core->i2c_adap);
  641. if (dev->dvb.frontend) {
  642. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  643. dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
  644. }
  645. break;
  646. case CX88_BOARD_PINNACLE_PCTV_HD_800i:
  647. dev->dvb.frontend = dvb_attach(s5h1409_attach,
  648. &pinnacle_pctv_hd_800i_config,
  649. &dev->core->i2c_adap);
  650. if (dev->dvb.frontend != NULL) {
  651. /* tuner_config.video_dev must point to
  652. * i2c_adap.algo_data
  653. */
  654. pinnacle_pctv_hd_800i_tuner_config.priv =
  655. dev->core->i2c_adap.algo_data;
  656. dvb_attach(xc5000_attach, dev->dvb.frontend,
  657. &dev->core->i2c_adap,
  658. &pinnacle_pctv_hd_800i_tuner_config);
  659. }
  660. break;
  661. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  662. dev->dvb.frontend = dvb_attach(s5h1409_attach,
  663. &dvico_hdtv5_pci_nano_config,
  664. &dev->core->i2c_adap);
  665. if (dev->dvb.frontend != NULL) {
  666. struct dvb_frontend *fe;
  667. struct xc2028_config cfg = {
  668. .i2c_adap = &dev->core->i2c_adap,
  669. .i2c_addr = 0x61,
  670. .video_dev = dev->core,
  671. .callback = cx88_xc3028_callback,
  672. };
  673. static struct xc2028_ctrl ctl = {
  674. .fname = "xc3028-v27.fw",
  675. .max_len = 64,
  676. .scode_table = OREN538,
  677. };
  678. fe = dvb_attach(xc2028_attach,
  679. dev->dvb.frontend, &cfg);
  680. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  681. fe->ops.tuner_ops.set_config(fe, &ctl);
  682. }
  683. break;
  684. case CX88_BOARD_PINNACLE_HYBRID_PCTV:
  685. dev->dvb.frontend = dvb_attach(zl10353_attach,
  686. &cx88_geniatech_x8000_mt,
  687. &dev->core->i2c_adap);
  688. attach_xc3028 = 1;
  689. break;
  690. case CX88_BOARD_GENIATECH_X8000_MT:
  691. dev->ts_gen_cntrl = 0x00;
  692. dev->dvb.frontend = dvb_attach(zl10353_attach,
  693. &cx88_geniatech_x8000_mt,
  694. &dev->core->i2c_adap);
  695. attach_xc3028 = 1;
  696. break;
  697. default:
  698. printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
  699. dev->core->name);
  700. break;
  701. }
  702. if (NULL == dev->dvb.frontend) {
  703. printk(KERN_ERR
  704. "%s/2: frontend initialization failed\n",
  705. dev->core->name);
  706. return -1;
  707. }
  708. if (attach_xc3028) {
  709. struct dvb_frontend *fe;
  710. struct xc2028_config cfg = {
  711. .i2c_adap = &dev->core->i2c_adap,
  712. .i2c_addr = 0x61,
  713. .video_dev = dev->core,
  714. };
  715. fe = dvb_attach(xc2028_attach, dev->dvb.frontend, &cfg);
  716. if (!fe) {
  717. printk(KERN_ERR "%s/2: xc3028 attach failed\n",
  718. dev->core->name);
  719. dvb_frontend_detach(dev->dvb.frontend);
  720. dvb_unregister_frontend(dev->dvb.frontend);
  721. dev->dvb.frontend = NULL;
  722. return -1;
  723. }
  724. }
  725. /* Ensure all frontends negotiate bus access */
  726. dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  727. /* Put the analog decoder in standby to keep it quiet */
  728. cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
  729. /* register everything */
  730. return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
  731. }
  732. /* ----------------------------------------------------------- */
  733. /* CX8802 MPEG -> mini driver - We have been given the hardware */
  734. static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
  735. {
  736. struct cx88_core *core = drv->core;
  737. int err = 0;
  738. dprintk( 1, "%s\n", __FUNCTION__);
  739. switch (core->boardnr) {
  740. case CX88_BOARD_HAUPPAUGE_HVR1300:
  741. /* We arrive here with either the cx23416 or the cx22702
  742. * on the bus. Take the bus from the cx23416 and enable the
  743. * cx22702 demod
  744. */
  745. cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */
  746. cx_clear(MO_GP0_IO, 0x00000004);
  747. udelay(1000);
  748. break;
  749. default:
  750. err = -ENODEV;
  751. }
  752. return err;
  753. }
  754. /* CX8802 MPEG -> mini driver - We no longer have the hardware */
  755. static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
  756. {
  757. struct cx88_core *core = drv->core;
  758. int err = 0;
  759. dprintk( 1, "%s\n", __FUNCTION__);
  760. switch (core->boardnr) {
  761. case CX88_BOARD_HAUPPAUGE_HVR1300:
  762. /* Do Nothing, leave the cx22702 on the bus. */
  763. break;
  764. default:
  765. err = -ENODEV;
  766. }
  767. return err;
  768. }
  769. static int cx8802_dvb_probe(struct cx8802_driver *drv)
  770. {
  771. struct cx88_core *core = drv->core;
  772. struct cx8802_dev *dev = drv->core->dvbdev;
  773. int err;
  774. dprintk( 1, "%s\n", __FUNCTION__);
  775. dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
  776. core->boardnr,
  777. core->name,
  778. core->pci_bus,
  779. core->pci_slot);
  780. err = -ENODEV;
  781. if (!(core->board.mpeg & CX88_MPEG_DVB))
  782. goto fail_core;
  783. /* If vp3054 isn't enabled, a stub will just return 0 */
  784. err = vp3054_i2c_probe(dev);
  785. if (0 != err)
  786. goto fail_core;
  787. /* dvb stuff */
  788. printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name);
  789. videobuf_queue_sg_init(&dev->dvb.dvbq, &dvb_qops,
  790. &dev->pci->dev, &dev->slock,
  791. V4L2_BUF_TYPE_VIDEO_CAPTURE,
  792. V4L2_FIELD_TOP,
  793. sizeof(struct cx88_buffer),
  794. dev);
  795. err = dvb_register(dev);
  796. if (err != 0)
  797. printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n",
  798. core->name, err);
  799. fail_core:
  800. return err;
  801. }
  802. static int cx8802_dvb_remove(struct cx8802_driver *drv)
  803. {
  804. struct cx8802_dev *dev = drv->core->dvbdev;
  805. /* dvb */
  806. videobuf_dvb_unregister(&dev->dvb);
  807. vp3054_i2c_remove(dev);
  808. return 0;
  809. }
  810. static struct cx8802_driver cx8802_dvb_driver = {
  811. .type_id = CX88_MPEG_DVB,
  812. .hw_access = CX8802_DRVCTL_SHARED,
  813. .probe = cx8802_dvb_probe,
  814. .remove = cx8802_dvb_remove,
  815. .advise_acquire = cx8802_dvb_advise_acquire,
  816. .advise_release = cx8802_dvb_advise_release,
  817. };
  818. static int dvb_init(void)
  819. {
  820. printk(KERN_INFO "cx88/2: cx2388x dvb driver version %d.%d.%d loaded\n",
  821. (CX88_VERSION_CODE >> 16) & 0xff,
  822. (CX88_VERSION_CODE >> 8) & 0xff,
  823. CX88_VERSION_CODE & 0xff);
  824. #ifdef SNAPSHOT
  825. printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
  826. SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
  827. #endif
  828. return cx8802_register_driver(&cx8802_dvb_driver);
  829. }
  830. static void dvb_fini(void)
  831. {
  832. cx8802_unregister_driver(&cx8802_dvb_driver);
  833. }
  834. module_init(dvb_init);
  835. module_exit(dvb_fini);
  836. /*
  837. * Local variables:
  838. * c-basic-offset: 8
  839. * compile-command: "make DVB=1"
  840. * End:
  841. */