xhci-pci.c 10 KB

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  1. /*
  2. * xHCI host controller driver PCI Bus Glue.
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/pci.h>
  23. #include <linux/slab.h>
  24. #include "xhci.h"
  25. /* Device for a quirk */
  26. #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
  27. #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
  28. static const char hcd_name[] = "xhci_hcd";
  29. /* called after powerup, by probe or system-pm "wakeup" */
  30. static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  31. {
  32. /*
  33. * TODO: Implement finding debug ports later.
  34. * TODO: see if there are any quirks that need to be added to handle
  35. * new extended capabilities.
  36. */
  37. /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  38. if (!pci_set_mwi(pdev))
  39. xhci_dbg(xhci, "MWI active\n");
  40. xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  41. return 0;
  42. }
  43. /* called during probe() after chip reset completes */
  44. static int xhci_pci_setup(struct usb_hcd *hcd)
  45. {
  46. struct xhci_hcd *xhci;
  47. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  48. int retval;
  49. u32 temp;
  50. hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
  51. if (usb_hcd_is_primary_hcd(hcd)) {
  52. xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
  53. if (!xhci)
  54. return -ENOMEM;
  55. *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
  56. xhci->main_hcd = hcd;
  57. /* Mark the first roothub as being USB 2.0.
  58. * The xHCI driver will register the USB 3.0 roothub.
  59. */
  60. hcd->speed = HCD_USB2;
  61. hcd->self.root_hub->speed = USB_SPEED_HIGH;
  62. /*
  63. * USB 2.0 roothub under xHCI has an integrated TT,
  64. * (rate matching hub) as opposed to having an OHCI/UHCI
  65. * companion controller.
  66. */
  67. hcd->has_tt = 1;
  68. } else {
  69. /* xHCI private pointer was set in xhci_pci_probe for the second
  70. * registered roothub.
  71. */
  72. xhci = hcd_to_xhci(hcd);
  73. temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  74. if (HCC_64BIT_ADDR(temp)) {
  75. xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
  76. dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
  77. } else {
  78. dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
  79. }
  80. return 0;
  81. }
  82. xhci->cap_regs = hcd->regs;
  83. xhci->op_regs = hcd->regs +
  84. HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
  85. xhci->run_regs = hcd->regs +
  86. (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
  87. /* Cache read-only capability registers */
  88. xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
  89. xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
  90. xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
  91. xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
  92. xhci->hci_version = HC_VERSION(xhci->hcc_params);
  93. xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  94. xhci_print_registers(xhci);
  95. /* Look for vendor-specific quirks */
  96. if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  97. pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  98. pdev->revision == 0x0) {
  99. xhci->quirks |= XHCI_RESET_EP_QUIRK;
  100. xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
  101. " endpoint cmd after reset endpoint\n");
  102. }
  103. if (pdev->vendor == PCI_VENDOR_ID_NEC)
  104. xhci->quirks |= XHCI_NEC_HOST;
  105. /* AMD PLL quirk */
  106. if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
  107. xhci->quirks |= XHCI_AMD_PLL_FIX;
  108. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  109. pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
  110. xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
  111. xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
  112. xhci->limit_active_eps = 64;
  113. }
  114. /* Make sure the HC is halted. */
  115. retval = xhci_halt(xhci);
  116. if (retval)
  117. goto error;
  118. xhci_dbg(xhci, "Resetting HCD\n");
  119. /* Reset the internal HC memory state and registers. */
  120. retval = xhci_reset(xhci);
  121. if (retval)
  122. goto error;
  123. xhci_dbg(xhci, "Reset complete\n");
  124. temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  125. if (HCC_64BIT_ADDR(temp)) {
  126. xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
  127. dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
  128. } else {
  129. dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
  130. }
  131. xhci_dbg(xhci, "Calling HCD init\n");
  132. /* Initialize HCD and host controller data structures. */
  133. retval = xhci_init(hcd);
  134. if (retval)
  135. goto error;
  136. xhci_dbg(xhci, "Called HCD init\n");
  137. pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
  138. xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
  139. /* Find any debug ports */
  140. retval = xhci_pci_reinit(xhci, pdev);
  141. if (!retval)
  142. return retval;
  143. error:
  144. kfree(xhci);
  145. return retval;
  146. }
  147. /*
  148. * We need to register our own PCI probe function (instead of the USB core's
  149. * function) in order to create a second roothub under xHCI.
  150. */
  151. static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  152. {
  153. int retval;
  154. struct xhci_hcd *xhci;
  155. struct hc_driver *driver;
  156. struct usb_hcd *hcd;
  157. driver = (struct hc_driver *)id->driver_data;
  158. /* Register the USB 2.0 roothub.
  159. * FIXME: USB core must know to register the USB 2.0 roothub first.
  160. * This is sort of silly, because we could just set the HCD driver flags
  161. * to say USB 2.0, but I'm not sure what the implications would be in
  162. * the other parts of the HCD code.
  163. */
  164. retval = usb_hcd_pci_probe(dev, id);
  165. if (retval)
  166. return retval;
  167. /* USB 2.0 roothub is stored in the PCI device now. */
  168. hcd = dev_get_drvdata(&dev->dev);
  169. xhci = hcd_to_xhci(hcd);
  170. xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
  171. pci_name(dev), hcd);
  172. if (!xhci->shared_hcd) {
  173. retval = -ENOMEM;
  174. goto dealloc_usb2_hcd;
  175. }
  176. /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
  177. * is called by usb_add_hcd().
  178. */
  179. *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
  180. retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
  181. IRQF_DISABLED | IRQF_SHARED);
  182. if (retval)
  183. goto put_usb3_hcd;
  184. /* Roothub already marked as USB 3.0 speed */
  185. return 0;
  186. put_usb3_hcd:
  187. usb_put_hcd(xhci->shared_hcd);
  188. dealloc_usb2_hcd:
  189. usb_hcd_pci_remove(dev);
  190. return retval;
  191. }
  192. static void xhci_pci_remove(struct pci_dev *dev)
  193. {
  194. struct xhci_hcd *xhci;
  195. xhci = hcd_to_xhci(pci_get_drvdata(dev));
  196. if (xhci->shared_hcd) {
  197. usb_remove_hcd(xhci->shared_hcd);
  198. usb_put_hcd(xhci->shared_hcd);
  199. }
  200. usb_hcd_pci_remove(dev);
  201. kfree(xhci);
  202. }
  203. #ifdef CONFIG_PM
  204. static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
  205. {
  206. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  207. int retval = 0;
  208. if (hcd->state != HC_STATE_SUSPENDED ||
  209. xhci->shared_hcd->state != HC_STATE_SUSPENDED)
  210. return -EINVAL;
  211. retval = xhci_suspend(xhci);
  212. return retval;
  213. }
  214. static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
  215. {
  216. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  217. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  218. int retval = 0;
  219. /* The BIOS on systems with the Intel Panther Point chipset may or may
  220. * not support xHCI natively. That means that during system resume, it
  221. * may switch the ports back to EHCI so that users can use their
  222. * keyboard to select a kernel from GRUB after resume from hibernate.
  223. *
  224. * The BIOS is supposed to remember whether the OS had xHCI ports
  225. * enabled before resume, and switch the ports back to xHCI when the
  226. * BIOS/OS semaphore is written, but we all know we can't trust BIOS
  227. * writers.
  228. *
  229. * Unconditionally switch the ports back to xHCI after a system resume.
  230. * We can't tell whether the EHCI or xHCI controller will be resumed
  231. * first, so we have to do the port switchover in both drivers. Writing
  232. * a '1' to the port switchover registers should have no effect if the
  233. * port was already switched over.
  234. */
  235. if (usb_is_intel_switchable_xhci(pdev))
  236. usb_enable_xhci_ports(pdev);
  237. retval = xhci_resume(xhci, hibernated);
  238. return retval;
  239. }
  240. #endif /* CONFIG_PM */
  241. static const struct hc_driver xhci_pci_hc_driver = {
  242. .description = hcd_name,
  243. .product_desc = "xHCI Host Controller",
  244. .hcd_priv_size = sizeof(struct xhci_hcd *),
  245. /*
  246. * generic hardware linkage
  247. */
  248. .irq = xhci_irq,
  249. .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
  250. /*
  251. * basic lifecycle operations
  252. */
  253. .reset = xhci_pci_setup,
  254. .start = xhci_run,
  255. #ifdef CONFIG_PM
  256. .pci_suspend = xhci_pci_suspend,
  257. .pci_resume = xhci_pci_resume,
  258. #endif
  259. .stop = xhci_stop,
  260. .shutdown = xhci_shutdown,
  261. /*
  262. * managing i/o requests and associated device resources
  263. */
  264. .urb_enqueue = xhci_urb_enqueue,
  265. .urb_dequeue = xhci_urb_dequeue,
  266. .alloc_dev = xhci_alloc_dev,
  267. .free_dev = xhci_free_dev,
  268. .alloc_streams = xhci_alloc_streams,
  269. .free_streams = xhci_free_streams,
  270. .add_endpoint = xhci_add_endpoint,
  271. .drop_endpoint = xhci_drop_endpoint,
  272. .endpoint_reset = xhci_endpoint_reset,
  273. .check_bandwidth = xhci_check_bandwidth,
  274. .reset_bandwidth = xhci_reset_bandwidth,
  275. .address_device = xhci_address_device,
  276. .update_hub_device = xhci_update_hub_device,
  277. .reset_device = xhci_discover_or_reset_device,
  278. /*
  279. * scheduling support
  280. */
  281. .get_frame_number = xhci_get_frame,
  282. /* Root hub support */
  283. .hub_control = xhci_hub_control,
  284. .hub_status_data = xhci_hub_status_data,
  285. .bus_suspend = xhci_bus_suspend,
  286. .bus_resume = xhci_bus_resume,
  287. };
  288. /*-------------------------------------------------------------------------*/
  289. /* PCI driver selection metadata; PCI hotplugging uses this */
  290. static const struct pci_device_id pci_ids[] = { {
  291. /* handle any USB 3.0 xHCI controller */
  292. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
  293. .driver_data = (unsigned long) &xhci_pci_hc_driver,
  294. },
  295. { /* end: all zeroes */ }
  296. };
  297. MODULE_DEVICE_TABLE(pci, pci_ids);
  298. /* pci driver glue; this is a "new style" PCI driver module */
  299. static struct pci_driver xhci_pci_driver = {
  300. .name = (char *) hcd_name,
  301. .id_table = pci_ids,
  302. .probe = xhci_pci_probe,
  303. .remove = xhci_pci_remove,
  304. /* suspend and resume implemented later */
  305. .shutdown = usb_hcd_pci_shutdown,
  306. #ifdef CONFIG_PM_SLEEP
  307. .driver = {
  308. .pm = &usb_hcd_pci_pm_ops
  309. },
  310. #endif
  311. };
  312. int xhci_register_pci(void)
  313. {
  314. return pci_register_driver(&xhci_pci_driver);
  315. }
  316. void xhci_unregister_pci(void)
  317. {
  318. pci_unregister_driver(&xhci_pci_driver);
  319. }