iwl-agn.c 117 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/mac80211.h>
  46. #include <asm/div64.h>
  47. #define DRV_NAME "iwlagn"
  48. #include "iwl-eeprom.h"
  49. #include "iwl-dev.h"
  50. #include "iwl-core.h"
  51. #include "iwl-io.h"
  52. #include "iwl-helpers.h"
  53. #include "iwl-sta.h"
  54. #include "iwl-agn-calib.h"
  55. #include "iwl-agn.h"
  56. /******************************************************************************
  57. *
  58. * module boiler plate
  59. *
  60. ******************************************************************************/
  61. /*
  62. * module name, copyright, version, etc.
  63. */
  64. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  65. #ifdef CONFIG_IWLWIFI_DEBUG
  66. #define VD "d"
  67. #else
  68. #define VD
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. static int iwlagn_ant_coupling;
  76. static bool iwlagn_bt_ch_announce = 1;
  77. void iwl_update_chain_flags(struct iwl_priv *priv)
  78. {
  79. struct iwl_rxon_context *ctx;
  80. if (priv->cfg->ops->hcmd->set_rxon_chain) {
  81. for_each_context(priv, ctx) {
  82. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  83. if (ctx->active.rx_chain != ctx->staging.rx_chain)
  84. iwlagn_commit_rxon(priv, ctx);
  85. }
  86. }
  87. }
  88. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  89. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  90. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  91. u8 *beacon, u32 frame_size)
  92. {
  93. u16 tim_idx;
  94. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  95. /*
  96. * The index is relative to frame start but we start looking at the
  97. * variable-length part of the beacon.
  98. */
  99. tim_idx = mgmt->u.beacon.variable - beacon;
  100. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  101. while ((tim_idx < (frame_size - 2)) &&
  102. (beacon[tim_idx] != WLAN_EID_TIM))
  103. tim_idx += beacon[tim_idx+1] + 2;
  104. /* If TIM field was found, set variables */
  105. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  106. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  107. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  108. } else
  109. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  110. }
  111. int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
  112. {
  113. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  114. struct iwl_host_cmd cmd = {
  115. .id = REPLY_TX_BEACON,
  116. };
  117. u32 frame_size;
  118. u32 rate_flags;
  119. u32 rate;
  120. /*
  121. * We have to set up the TX command, the TX Beacon command, and the
  122. * beacon contents.
  123. */
  124. lockdep_assert_held(&priv->mutex);
  125. if (!priv->beacon_ctx) {
  126. IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
  127. return 0;
  128. }
  129. if (WARN_ON(!priv->beacon_skb))
  130. return -EINVAL;
  131. /* Allocate beacon command */
  132. if (!priv->beacon_cmd)
  133. priv->beacon_cmd = kzalloc(sizeof(*tx_beacon_cmd), GFP_KERNEL);
  134. tx_beacon_cmd = priv->beacon_cmd;
  135. if (!tx_beacon_cmd)
  136. return -ENOMEM;
  137. frame_size = priv->beacon_skb->len;
  138. /* Set up TX command fields */
  139. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  140. tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
  141. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  142. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  143. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  144. /* Set up TX beacon command fields */
  145. iwl_set_beacon_tim(priv, tx_beacon_cmd, priv->beacon_skb->data,
  146. frame_size);
  147. /* Set up packet rate and flags */
  148. rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
  149. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
  150. priv->hw_params.valid_tx_ant);
  151. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  152. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  153. rate_flags |= RATE_MCS_CCK_MSK;
  154. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  155. rate_flags);
  156. /* Submit command */
  157. cmd.len[0] = sizeof(*tx_beacon_cmd);
  158. cmd.data[0] = tx_beacon_cmd;
  159. cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
  160. cmd.len[1] = frame_size;
  161. cmd.data[1] = priv->beacon_skb->data;
  162. cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
  163. return iwl_send_cmd_sync(priv, &cmd);
  164. }
  165. static void iwl_bg_beacon_update(struct work_struct *work)
  166. {
  167. struct iwl_priv *priv =
  168. container_of(work, struct iwl_priv, beacon_update);
  169. struct sk_buff *beacon;
  170. mutex_lock(&priv->mutex);
  171. if (!priv->beacon_ctx) {
  172. IWL_ERR(priv, "updating beacon w/o beacon context!\n");
  173. goto out;
  174. }
  175. if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
  176. /*
  177. * The ucode will send beacon notifications even in
  178. * IBSS mode, but we don't want to process them. But
  179. * we need to defer the type check to here due to
  180. * requiring locking around the beacon_ctx access.
  181. */
  182. goto out;
  183. }
  184. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  185. beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
  186. if (!beacon) {
  187. IWL_ERR(priv, "update beacon failed -- keeping old\n");
  188. goto out;
  189. }
  190. /* new beacon skb is allocated every time; dispose previous.*/
  191. dev_kfree_skb(priv->beacon_skb);
  192. priv->beacon_skb = beacon;
  193. iwlagn_send_beacon_cmd(priv);
  194. out:
  195. mutex_unlock(&priv->mutex);
  196. }
  197. static void iwl_bg_bt_runtime_config(struct work_struct *work)
  198. {
  199. struct iwl_priv *priv =
  200. container_of(work, struct iwl_priv, bt_runtime_config);
  201. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  202. return;
  203. /* dont send host command if rf-kill is on */
  204. if (!iwl_is_ready_rf(priv))
  205. return;
  206. priv->cfg->ops->hcmd->send_bt_config(priv);
  207. }
  208. static void iwl_bg_bt_full_concurrency(struct work_struct *work)
  209. {
  210. struct iwl_priv *priv =
  211. container_of(work, struct iwl_priv, bt_full_concurrency);
  212. struct iwl_rxon_context *ctx;
  213. mutex_lock(&priv->mutex);
  214. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  215. goto out;
  216. /* dont send host command if rf-kill is on */
  217. if (!iwl_is_ready_rf(priv))
  218. goto out;
  219. IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
  220. priv->bt_full_concurrent ?
  221. "full concurrency" : "3-wire");
  222. /*
  223. * LQ & RXON updated cmds must be sent before BT Config cmd
  224. * to avoid 3-wire collisions
  225. */
  226. for_each_context(priv, ctx) {
  227. if (priv->cfg->ops->hcmd->set_rxon_chain)
  228. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  229. iwlagn_commit_rxon(priv, ctx);
  230. }
  231. priv->cfg->ops->hcmd->send_bt_config(priv);
  232. out:
  233. mutex_unlock(&priv->mutex);
  234. }
  235. /**
  236. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  237. *
  238. * This callback is provided in order to send a statistics request.
  239. *
  240. * This timer function is continually reset to execute within
  241. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  242. * was received. We need to ensure we receive the statistics in order
  243. * to update the temperature used for calibrating the TXPOWER.
  244. */
  245. static void iwl_bg_statistics_periodic(unsigned long data)
  246. {
  247. struct iwl_priv *priv = (struct iwl_priv *)data;
  248. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  249. return;
  250. /* dont send host command if rf-kill is on */
  251. if (!iwl_is_ready_rf(priv))
  252. return;
  253. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  254. }
  255. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  256. u32 start_idx, u32 num_events,
  257. u32 mode)
  258. {
  259. u32 i;
  260. u32 ptr; /* SRAM byte address of log data */
  261. u32 ev, time, data; /* event log data */
  262. unsigned long reg_flags;
  263. if (mode == 0)
  264. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  265. else
  266. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  267. /* Make sure device is powered up for SRAM reads */
  268. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  269. if (iwl_grab_nic_access(priv)) {
  270. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  271. return;
  272. }
  273. /* Set starting address; reads will auto-increment */
  274. iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
  275. rmb();
  276. /*
  277. * "time" is actually "data" for mode 0 (no timestamp).
  278. * place event id # at far right for easier visual parsing.
  279. */
  280. for (i = 0; i < num_events; i++) {
  281. ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  282. time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  283. if (mode == 0) {
  284. trace_iwlwifi_dev_ucode_cont_event(priv,
  285. 0, time, ev);
  286. } else {
  287. data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  288. trace_iwlwifi_dev_ucode_cont_event(priv,
  289. time, data, ev);
  290. }
  291. }
  292. /* Allow device to power down */
  293. iwl_release_nic_access(priv);
  294. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  295. }
  296. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  297. {
  298. u32 capacity; /* event log capacity in # entries */
  299. u32 base; /* SRAM byte address of event log header */
  300. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  301. u32 num_wraps; /* # times uCode wrapped to top of log */
  302. u32 next_entry; /* index of next entry to be written by uCode */
  303. base = priv->device_pointers.error_event_table;
  304. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  305. capacity = iwl_read_targ_mem(priv, base);
  306. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  307. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  308. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  309. } else
  310. return;
  311. if (num_wraps == priv->event_log.num_wraps) {
  312. iwl_print_cont_event_trace(priv,
  313. base, priv->event_log.next_entry,
  314. next_entry - priv->event_log.next_entry,
  315. mode);
  316. priv->event_log.non_wraps_count++;
  317. } else {
  318. if ((num_wraps - priv->event_log.num_wraps) > 1)
  319. priv->event_log.wraps_more_count++;
  320. else
  321. priv->event_log.wraps_once_count++;
  322. trace_iwlwifi_dev_ucode_wrap_event(priv,
  323. num_wraps - priv->event_log.num_wraps,
  324. next_entry, priv->event_log.next_entry);
  325. if (next_entry < priv->event_log.next_entry) {
  326. iwl_print_cont_event_trace(priv, base,
  327. priv->event_log.next_entry,
  328. capacity - priv->event_log.next_entry,
  329. mode);
  330. iwl_print_cont_event_trace(priv, base, 0,
  331. next_entry, mode);
  332. } else {
  333. iwl_print_cont_event_trace(priv, base,
  334. next_entry, capacity - next_entry,
  335. mode);
  336. iwl_print_cont_event_trace(priv, base, 0,
  337. next_entry, mode);
  338. }
  339. }
  340. priv->event_log.num_wraps = num_wraps;
  341. priv->event_log.next_entry = next_entry;
  342. }
  343. /**
  344. * iwl_bg_ucode_trace - Timer callback to log ucode event
  345. *
  346. * The timer is continually set to execute every
  347. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  348. * this function is to perform continuous uCode event logging operation
  349. * if enabled
  350. */
  351. static void iwl_bg_ucode_trace(unsigned long data)
  352. {
  353. struct iwl_priv *priv = (struct iwl_priv *)data;
  354. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  355. return;
  356. if (priv->event_log.ucode_trace) {
  357. iwl_continuous_event_trace(priv);
  358. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  359. mod_timer(&priv->ucode_trace,
  360. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  361. }
  362. }
  363. static void iwl_bg_tx_flush(struct work_struct *work)
  364. {
  365. struct iwl_priv *priv =
  366. container_of(work, struct iwl_priv, tx_flush);
  367. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  368. return;
  369. /* do nothing if rf-kill is on */
  370. if (!iwl_is_ready_rf(priv))
  371. return;
  372. if (priv->cfg->ops->lib->txfifo_flush) {
  373. IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
  374. iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
  375. }
  376. }
  377. /**
  378. * iwl_rx_handle - Main entry function for receiving responses from uCode
  379. *
  380. * Uses the priv->rx_handlers callback function array to invoke
  381. * the appropriate handlers, including command responses,
  382. * frame-received notifications, and other notifications.
  383. */
  384. static void iwl_rx_handle(struct iwl_priv *priv)
  385. {
  386. struct iwl_rx_mem_buffer *rxb;
  387. struct iwl_rx_packet *pkt;
  388. struct iwl_rx_queue *rxq = &priv->rxq;
  389. u32 r, i;
  390. int reclaim;
  391. unsigned long flags;
  392. u8 fill_rx = 0;
  393. u32 count = 8;
  394. int total_empty;
  395. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  396. * buffer that the driver may process (last buffer filled by ucode). */
  397. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  398. i = rxq->read;
  399. /* Rx interrupt, but nothing sent from uCode */
  400. if (i == r)
  401. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  402. /* calculate total frames need to be restock after handling RX */
  403. total_empty = r - rxq->write_actual;
  404. if (total_empty < 0)
  405. total_empty += RX_QUEUE_SIZE;
  406. if (total_empty > (RX_QUEUE_SIZE / 2))
  407. fill_rx = 1;
  408. while (i != r) {
  409. int len;
  410. rxb = rxq->queue[i];
  411. /* If an RXB doesn't have a Rx queue slot associated with it,
  412. * then a bug has been introduced in the queue refilling
  413. * routines -- catch it here */
  414. if (WARN_ON(rxb == NULL)) {
  415. i = (i + 1) & RX_QUEUE_MASK;
  416. continue;
  417. }
  418. rxq->queue[i] = NULL;
  419. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  420. PAGE_SIZE << priv->hw_params.rx_page_order,
  421. PCI_DMA_FROMDEVICE);
  422. pkt = rxb_addr(rxb);
  423. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  424. len += sizeof(u32); /* account for status word */
  425. trace_iwlwifi_dev_rx(priv, pkt, len);
  426. /* Reclaim a command buffer only if this packet is a response
  427. * to a (driver-originated) command.
  428. * If the packet (e.g. Rx frame) originated from uCode,
  429. * there is no command buffer to reclaim.
  430. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  431. * but apparently a few don't get set; catch them here. */
  432. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  433. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  434. (pkt->hdr.cmd != REPLY_RX) &&
  435. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  436. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  437. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  438. (pkt->hdr.cmd != REPLY_TX);
  439. /*
  440. * Do the notification wait before RX handlers so
  441. * even if the RX handler consumes the RXB we have
  442. * access to it in the notification wait entry.
  443. */
  444. if (!list_empty(&priv->_agn.notif_waits)) {
  445. struct iwl_notification_wait *w;
  446. spin_lock(&priv->_agn.notif_wait_lock);
  447. list_for_each_entry(w, &priv->_agn.notif_waits, list) {
  448. if (w->cmd == pkt->hdr.cmd) {
  449. w->triggered = true;
  450. if (w->fn)
  451. w->fn(priv, pkt, w->fn_data);
  452. }
  453. }
  454. spin_unlock(&priv->_agn.notif_wait_lock);
  455. wake_up_all(&priv->_agn.notif_waitq);
  456. }
  457. if (priv->pre_rx_handler)
  458. priv->pre_rx_handler(priv, rxb);
  459. /* Based on type of command response or notification,
  460. * handle those that need handling via function in
  461. * rx_handlers table. See iwl_setup_rx_handlers() */
  462. if (priv->rx_handlers[pkt->hdr.cmd]) {
  463. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  464. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  465. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  466. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  467. } else {
  468. /* No handling needed */
  469. IWL_DEBUG_RX(priv,
  470. "r %d i %d No handler needed for %s, 0x%02x\n",
  471. r, i, get_cmd_string(pkt->hdr.cmd),
  472. pkt->hdr.cmd);
  473. }
  474. /*
  475. * XXX: After here, we should always check rxb->page
  476. * against NULL before touching it or its virtual
  477. * memory (pkt). Because some rx_handler might have
  478. * already taken or freed the pages.
  479. */
  480. if (reclaim) {
  481. /* Invoke any callbacks, transfer the buffer to caller,
  482. * and fire off the (possibly) blocking iwl_send_cmd()
  483. * as we reclaim the driver command queue */
  484. if (rxb->page)
  485. iwl_tx_cmd_complete(priv, rxb);
  486. else
  487. IWL_WARN(priv, "Claim null rxb?\n");
  488. }
  489. /* Reuse the page if possible. For notification packets and
  490. * SKBs that fail to Rx correctly, add them back into the
  491. * rx_free list for reuse later. */
  492. spin_lock_irqsave(&rxq->lock, flags);
  493. if (rxb->page != NULL) {
  494. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  495. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  496. PCI_DMA_FROMDEVICE);
  497. list_add_tail(&rxb->list, &rxq->rx_free);
  498. rxq->free_count++;
  499. } else
  500. list_add_tail(&rxb->list, &rxq->rx_used);
  501. spin_unlock_irqrestore(&rxq->lock, flags);
  502. i = (i + 1) & RX_QUEUE_MASK;
  503. /* If there are a lot of unused frames,
  504. * restock the Rx queue so ucode wont assert. */
  505. if (fill_rx) {
  506. count++;
  507. if (count >= 8) {
  508. rxq->read = i;
  509. iwlagn_rx_replenish_now(priv);
  510. count = 0;
  511. }
  512. }
  513. }
  514. /* Backtrack one entry */
  515. rxq->read = i;
  516. if (fill_rx)
  517. iwlagn_rx_replenish_now(priv);
  518. else
  519. iwlagn_rx_queue_restock(priv);
  520. }
  521. /* tasklet for iwlagn interrupt */
  522. static void iwl_irq_tasklet(struct iwl_priv *priv)
  523. {
  524. u32 inta = 0;
  525. u32 handled = 0;
  526. unsigned long flags;
  527. u32 i;
  528. #ifdef CONFIG_IWLWIFI_DEBUG
  529. u32 inta_mask;
  530. #endif
  531. spin_lock_irqsave(&priv->lock, flags);
  532. /* Ack/clear/reset pending uCode interrupts.
  533. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  534. */
  535. /* There is a hardware bug in the interrupt mask function that some
  536. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  537. * they are disabled in the CSR_INT_MASK register. Furthermore the
  538. * ICT interrupt handling mechanism has another bug that might cause
  539. * these unmasked interrupts fail to be detected. We workaround the
  540. * hardware bugs here by ACKing all the possible interrupts so that
  541. * interrupt coalescing can still be achieved.
  542. */
  543. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  544. inta = priv->_agn.inta;
  545. #ifdef CONFIG_IWLWIFI_DEBUG
  546. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  547. /* just for debug */
  548. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  549. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  550. inta, inta_mask);
  551. }
  552. #endif
  553. spin_unlock_irqrestore(&priv->lock, flags);
  554. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  555. priv->_agn.inta = 0;
  556. /* Now service all interrupt bits discovered above. */
  557. if (inta & CSR_INT_BIT_HW_ERR) {
  558. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  559. /* Tell the device to stop sending interrupts */
  560. iwl_disable_interrupts(priv);
  561. priv->isr_stats.hw++;
  562. iwl_irq_handle_error(priv);
  563. handled |= CSR_INT_BIT_HW_ERR;
  564. return;
  565. }
  566. #ifdef CONFIG_IWLWIFI_DEBUG
  567. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  568. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  569. if (inta & CSR_INT_BIT_SCD) {
  570. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  571. "the frame/frames.\n");
  572. priv->isr_stats.sch++;
  573. }
  574. /* Alive notification via Rx interrupt will do the real work */
  575. if (inta & CSR_INT_BIT_ALIVE) {
  576. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  577. priv->isr_stats.alive++;
  578. }
  579. }
  580. #endif
  581. /* Safely ignore these bits for debug checks below */
  582. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  583. /* HW RF KILL switch toggled */
  584. if (inta & CSR_INT_BIT_RF_KILL) {
  585. int hw_rf_kill = 0;
  586. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  587. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  588. hw_rf_kill = 1;
  589. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  590. hw_rf_kill ? "disable radio" : "enable radio");
  591. priv->isr_stats.rfkill++;
  592. /* driver only loads ucode once setting the interface up.
  593. * the driver allows loading the ucode even if the radio
  594. * is killed. Hence update the killswitch state here. The
  595. * rfkill handler will care about restarting if needed.
  596. */
  597. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  598. if (hw_rf_kill)
  599. set_bit(STATUS_RF_KILL_HW, &priv->status);
  600. else
  601. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  602. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  603. }
  604. handled |= CSR_INT_BIT_RF_KILL;
  605. }
  606. /* Chip got too hot and stopped itself */
  607. if (inta & CSR_INT_BIT_CT_KILL) {
  608. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  609. priv->isr_stats.ctkill++;
  610. handled |= CSR_INT_BIT_CT_KILL;
  611. }
  612. /* Error detected by uCode */
  613. if (inta & CSR_INT_BIT_SW_ERR) {
  614. IWL_ERR(priv, "Microcode SW error detected. "
  615. " Restarting 0x%X.\n", inta);
  616. priv->isr_stats.sw++;
  617. iwl_irq_handle_error(priv);
  618. handled |= CSR_INT_BIT_SW_ERR;
  619. }
  620. /* uCode wakes up after power-down sleep */
  621. if (inta & CSR_INT_BIT_WAKEUP) {
  622. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  623. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  624. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  625. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  626. priv->isr_stats.wakeup++;
  627. handled |= CSR_INT_BIT_WAKEUP;
  628. }
  629. /* All uCode command responses, including Tx command responses,
  630. * Rx "responses" (frame-received notification), and other
  631. * notifications from uCode come through here*/
  632. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  633. CSR_INT_BIT_RX_PERIODIC)) {
  634. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  635. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  636. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  637. iwl_write32(priv, CSR_FH_INT_STATUS,
  638. CSR_FH_INT_RX_MASK);
  639. }
  640. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  641. handled |= CSR_INT_BIT_RX_PERIODIC;
  642. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  643. }
  644. /* Sending RX interrupt require many steps to be done in the
  645. * the device:
  646. * 1- write interrupt to current index in ICT table.
  647. * 2- dma RX frame.
  648. * 3- update RX shared data to indicate last write index.
  649. * 4- send interrupt.
  650. * This could lead to RX race, driver could receive RX interrupt
  651. * but the shared data changes does not reflect this;
  652. * periodic interrupt will detect any dangling Rx activity.
  653. */
  654. /* Disable periodic interrupt; we use it as just a one-shot. */
  655. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  656. CSR_INT_PERIODIC_DIS);
  657. iwl_rx_handle(priv);
  658. /*
  659. * Enable periodic interrupt in 8 msec only if we received
  660. * real RX interrupt (instead of just periodic int), to catch
  661. * any dangling Rx interrupt. If it was just the periodic
  662. * interrupt, there was no dangling Rx activity, and no need
  663. * to extend the periodic interrupt; one-shot is enough.
  664. */
  665. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  666. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  667. CSR_INT_PERIODIC_ENA);
  668. priv->isr_stats.rx++;
  669. }
  670. /* This "Tx" DMA channel is used only for loading uCode */
  671. if (inta & CSR_INT_BIT_FH_TX) {
  672. iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
  673. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  674. priv->isr_stats.tx++;
  675. handled |= CSR_INT_BIT_FH_TX;
  676. /* Wake up uCode load routine, now that load is complete */
  677. priv->ucode_write_complete = 1;
  678. wake_up_interruptible(&priv->wait_command_queue);
  679. }
  680. if (inta & ~handled) {
  681. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  682. priv->isr_stats.unhandled++;
  683. }
  684. if (inta & ~(priv->inta_mask)) {
  685. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  686. inta & ~priv->inta_mask);
  687. }
  688. /* Re-enable all interrupts */
  689. /* only Re-enable if disabled by irq */
  690. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  691. iwl_enable_interrupts(priv);
  692. /* Re-enable RF_KILL if it occurred */
  693. else if (handled & CSR_INT_BIT_RF_KILL)
  694. iwl_enable_rfkill_int(priv);
  695. }
  696. /*****************************************************************************
  697. *
  698. * sysfs attributes
  699. *
  700. *****************************************************************************/
  701. #ifdef CONFIG_IWLWIFI_DEBUG
  702. /*
  703. * The following adds a new attribute to the sysfs representation
  704. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  705. * used for controlling the debug level.
  706. *
  707. * See the level definitions in iwl for details.
  708. *
  709. * The debug_level being managed using sysfs below is a per device debug
  710. * level that is used instead of the global debug level if it (the per
  711. * device debug level) is set.
  712. */
  713. static ssize_t show_debug_level(struct device *d,
  714. struct device_attribute *attr, char *buf)
  715. {
  716. struct iwl_priv *priv = dev_get_drvdata(d);
  717. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  718. }
  719. static ssize_t store_debug_level(struct device *d,
  720. struct device_attribute *attr,
  721. const char *buf, size_t count)
  722. {
  723. struct iwl_priv *priv = dev_get_drvdata(d);
  724. unsigned long val;
  725. int ret;
  726. ret = strict_strtoul(buf, 0, &val);
  727. if (ret)
  728. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  729. else {
  730. priv->debug_level = val;
  731. if (iwl_alloc_traffic_mem(priv))
  732. IWL_ERR(priv,
  733. "Not enough memory to generate traffic log\n");
  734. }
  735. return strnlen(buf, count);
  736. }
  737. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  738. show_debug_level, store_debug_level);
  739. #endif /* CONFIG_IWLWIFI_DEBUG */
  740. static ssize_t show_temperature(struct device *d,
  741. struct device_attribute *attr, char *buf)
  742. {
  743. struct iwl_priv *priv = dev_get_drvdata(d);
  744. if (!iwl_is_alive(priv))
  745. return -EAGAIN;
  746. return sprintf(buf, "%d\n", priv->temperature);
  747. }
  748. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  749. static ssize_t show_tx_power(struct device *d,
  750. struct device_attribute *attr, char *buf)
  751. {
  752. struct iwl_priv *priv = dev_get_drvdata(d);
  753. if (!iwl_is_ready_rf(priv))
  754. return sprintf(buf, "off\n");
  755. else
  756. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  757. }
  758. static ssize_t store_tx_power(struct device *d,
  759. struct device_attribute *attr,
  760. const char *buf, size_t count)
  761. {
  762. struct iwl_priv *priv = dev_get_drvdata(d);
  763. unsigned long val;
  764. int ret;
  765. ret = strict_strtoul(buf, 10, &val);
  766. if (ret)
  767. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  768. else {
  769. ret = iwl_set_tx_power(priv, val, false);
  770. if (ret)
  771. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  772. ret);
  773. else
  774. ret = count;
  775. }
  776. return ret;
  777. }
  778. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  779. static struct attribute *iwl_sysfs_entries[] = {
  780. &dev_attr_temperature.attr,
  781. &dev_attr_tx_power.attr,
  782. #ifdef CONFIG_IWLWIFI_DEBUG
  783. &dev_attr_debug_level.attr,
  784. #endif
  785. NULL
  786. };
  787. static struct attribute_group iwl_attribute_group = {
  788. .name = NULL, /* put in device directory */
  789. .attrs = iwl_sysfs_entries,
  790. };
  791. /******************************************************************************
  792. *
  793. * uCode download functions
  794. *
  795. ******************************************************************************/
  796. static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
  797. {
  798. if (desc->v_addr)
  799. dma_free_coherent(&pci_dev->dev, desc->len,
  800. desc->v_addr, desc->p_addr);
  801. desc->v_addr = NULL;
  802. desc->len = 0;
  803. }
  804. static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img)
  805. {
  806. iwl_free_fw_desc(pci_dev, &img->code);
  807. iwl_free_fw_desc(pci_dev, &img->data);
  808. }
  809. static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
  810. const void *data, size_t len)
  811. {
  812. if (!len) {
  813. desc->v_addr = NULL;
  814. return -EINVAL;
  815. }
  816. desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len,
  817. &desc->p_addr, GFP_KERNEL);
  818. if (!desc->v_addr)
  819. return -ENOMEM;
  820. desc->len = len;
  821. memcpy(desc->v_addr, data, len);
  822. return 0;
  823. }
  824. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  825. {
  826. iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt);
  827. iwl_free_fw_img(priv->pci_dev, &priv->ucode_init);
  828. }
  829. struct iwlagn_ucode_capabilities {
  830. u32 max_probe_length;
  831. u32 standard_phy_calibration_size;
  832. u32 flags;
  833. };
  834. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  835. static int iwl_mac_setup_register(struct iwl_priv *priv,
  836. struct iwlagn_ucode_capabilities *capa);
  837. #define UCODE_EXPERIMENTAL_INDEX 100
  838. #define UCODE_EXPERIMENTAL_TAG "exp"
  839. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  840. {
  841. const char *name_pre = priv->cfg->fw_name_pre;
  842. char tag[8];
  843. if (first) {
  844. #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
  845. priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
  846. strcpy(tag, UCODE_EXPERIMENTAL_TAG);
  847. } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
  848. #endif
  849. priv->fw_index = priv->cfg->ucode_api_max;
  850. sprintf(tag, "%d", priv->fw_index);
  851. } else {
  852. priv->fw_index--;
  853. sprintf(tag, "%d", priv->fw_index);
  854. }
  855. if (priv->fw_index < priv->cfg->ucode_api_min) {
  856. IWL_ERR(priv, "no suitable firmware found!\n");
  857. return -ENOENT;
  858. }
  859. sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
  860. IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
  861. (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
  862. ? "EXPERIMENTAL " : "",
  863. priv->firmware_name);
  864. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  865. &priv->pci_dev->dev, GFP_KERNEL, priv,
  866. iwl_ucode_callback);
  867. }
  868. struct iwlagn_firmware_pieces {
  869. const void *inst, *data, *init, *init_data;
  870. size_t inst_size, data_size, init_size, init_data_size;
  871. u32 build;
  872. u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
  873. u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
  874. };
  875. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  876. const struct firmware *ucode_raw,
  877. struct iwlagn_firmware_pieces *pieces)
  878. {
  879. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  880. u32 api_ver, hdr_size;
  881. const u8 *src;
  882. priv->ucode_ver = le32_to_cpu(ucode->ver);
  883. api_ver = IWL_UCODE_API(priv->ucode_ver);
  884. switch (api_ver) {
  885. default:
  886. hdr_size = 28;
  887. if (ucode_raw->size < hdr_size) {
  888. IWL_ERR(priv, "File size too small!\n");
  889. return -EINVAL;
  890. }
  891. pieces->build = le32_to_cpu(ucode->u.v2.build);
  892. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  893. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  894. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  895. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  896. src = ucode->u.v2.data;
  897. break;
  898. case 0:
  899. case 1:
  900. case 2:
  901. hdr_size = 24;
  902. if (ucode_raw->size < hdr_size) {
  903. IWL_ERR(priv, "File size too small!\n");
  904. return -EINVAL;
  905. }
  906. pieces->build = 0;
  907. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  908. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  909. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  910. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  911. src = ucode->u.v1.data;
  912. break;
  913. }
  914. /* Verify size of file vs. image size info in file's header */
  915. if (ucode_raw->size != hdr_size + pieces->inst_size +
  916. pieces->data_size + pieces->init_size +
  917. pieces->init_data_size) {
  918. IWL_ERR(priv,
  919. "uCode file size %d does not match expected size\n",
  920. (int)ucode_raw->size);
  921. return -EINVAL;
  922. }
  923. pieces->inst = src;
  924. src += pieces->inst_size;
  925. pieces->data = src;
  926. src += pieces->data_size;
  927. pieces->init = src;
  928. src += pieces->init_size;
  929. pieces->init_data = src;
  930. src += pieces->init_data_size;
  931. return 0;
  932. }
  933. static int iwlagn_wanted_ucode_alternative = 1;
  934. static int iwlagn_load_firmware(struct iwl_priv *priv,
  935. const struct firmware *ucode_raw,
  936. struct iwlagn_firmware_pieces *pieces,
  937. struct iwlagn_ucode_capabilities *capa)
  938. {
  939. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  940. struct iwl_ucode_tlv *tlv;
  941. size_t len = ucode_raw->size;
  942. const u8 *data;
  943. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  944. u64 alternatives;
  945. u32 tlv_len;
  946. enum iwl_ucode_tlv_type tlv_type;
  947. const u8 *tlv_data;
  948. if (len < sizeof(*ucode)) {
  949. IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
  950. return -EINVAL;
  951. }
  952. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
  953. IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
  954. le32_to_cpu(ucode->magic));
  955. return -EINVAL;
  956. }
  957. /*
  958. * Check which alternatives are present, and "downgrade"
  959. * when the chosen alternative is not present, warning
  960. * the user when that happens. Some files may not have
  961. * any alternatives, so don't warn in that case.
  962. */
  963. alternatives = le64_to_cpu(ucode->alternatives);
  964. tmp = wanted_alternative;
  965. if (wanted_alternative > 63)
  966. wanted_alternative = 63;
  967. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  968. wanted_alternative--;
  969. if (wanted_alternative && wanted_alternative != tmp)
  970. IWL_WARN(priv,
  971. "uCode alternative %d not available, choosing %d\n",
  972. tmp, wanted_alternative);
  973. priv->ucode_ver = le32_to_cpu(ucode->ver);
  974. pieces->build = le32_to_cpu(ucode->build);
  975. data = ucode->data;
  976. len -= sizeof(*ucode);
  977. while (len >= sizeof(*tlv)) {
  978. u16 tlv_alt;
  979. len -= sizeof(*tlv);
  980. tlv = (void *)data;
  981. tlv_len = le32_to_cpu(tlv->length);
  982. tlv_type = le16_to_cpu(tlv->type);
  983. tlv_alt = le16_to_cpu(tlv->alternative);
  984. tlv_data = tlv->data;
  985. if (len < tlv_len) {
  986. IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
  987. len, tlv_len);
  988. return -EINVAL;
  989. }
  990. len -= ALIGN(tlv_len, 4);
  991. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  992. /*
  993. * Alternative 0 is always valid.
  994. *
  995. * Skip alternative TLVs that are not selected.
  996. */
  997. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  998. continue;
  999. switch (tlv_type) {
  1000. case IWL_UCODE_TLV_INST:
  1001. pieces->inst = tlv_data;
  1002. pieces->inst_size = tlv_len;
  1003. break;
  1004. case IWL_UCODE_TLV_DATA:
  1005. pieces->data = tlv_data;
  1006. pieces->data_size = tlv_len;
  1007. break;
  1008. case IWL_UCODE_TLV_INIT:
  1009. pieces->init = tlv_data;
  1010. pieces->init_size = tlv_len;
  1011. break;
  1012. case IWL_UCODE_TLV_INIT_DATA:
  1013. pieces->init_data = tlv_data;
  1014. pieces->init_data_size = tlv_len;
  1015. break;
  1016. case IWL_UCODE_TLV_BOOT:
  1017. IWL_ERR(priv, "Found unexpected BOOT ucode\n");
  1018. break;
  1019. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1020. if (tlv_len != sizeof(u32))
  1021. goto invalid_tlv_len;
  1022. capa->max_probe_length =
  1023. le32_to_cpup((__le32 *)tlv_data);
  1024. break;
  1025. case IWL_UCODE_TLV_PAN:
  1026. if (tlv_len)
  1027. goto invalid_tlv_len;
  1028. capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
  1029. break;
  1030. case IWL_UCODE_TLV_FLAGS:
  1031. /* must be at least one u32 */
  1032. if (tlv_len < sizeof(u32))
  1033. goto invalid_tlv_len;
  1034. /* and a proper number of u32s */
  1035. if (tlv_len % sizeof(u32))
  1036. goto invalid_tlv_len;
  1037. /*
  1038. * This driver only reads the first u32 as
  1039. * right now no more features are defined,
  1040. * if that changes then either the driver
  1041. * will not work with the new firmware, or
  1042. * it'll not take advantage of new features.
  1043. */
  1044. capa->flags = le32_to_cpup((__le32 *)tlv_data);
  1045. break;
  1046. case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
  1047. if (tlv_len != sizeof(u32))
  1048. goto invalid_tlv_len;
  1049. pieces->init_evtlog_ptr =
  1050. le32_to_cpup((__le32 *)tlv_data);
  1051. break;
  1052. case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
  1053. if (tlv_len != sizeof(u32))
  1054. goto invalid_tlv_len;
  1055. pieces->init_evtlog_size =
  1056. le32_to_cpup((__le32 *)tlv_data);
  1057. break;
  1058. case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
  1059. if (tlv_len != sizeof(u32))
  1060. goto invalid_tlv_len;
  1061. pieces->init_errlog_ptr =
  1062. le32_to_cpup((__le32 *)tlv_data);
  1063. break;
  1064. case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
  1065. if (tlv_len != sizeof(u32))
  1066. goto invalid_tlv_len;
  1067. pieces->inst_evtlog_ptr =
  1068. le32_to_cpup((__le32 *)tlv_data);
  1069. break;
  1070. case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
  1071. if (tlv_len != sizeof(u32))
  1072. goto invalid_tlv_len;
  1073. pieces->inst_evtlog_size =
  1074. le32_to_cpup((__le32 *)tlv_data);
  1075. break;
  1076. case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
  1077. if (tlv_len != sizeof(u32))
  1078. goto invalid_tlv_len;
  1079. pieces->inst_errlog_ptr =
  1080. le32_to_cpup((__le32 *)tlv_data);
  1081. break;
  1082. case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
  1083. if (tlv_len)
  1084. goto invalid_tlv_len;
  1085. priv->enhance_sensitivity_table = true;
  1086. break;
  1087. case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
  1088. if (tlv_len != sizeof(u32))
  1089. goto invalid_tlv_len;
  1090. capa->standard_phy_calibration_size =
  1091. le32_to_cpup((__le32 *)tlv_data);
  1092. break;
  1093. default:
  1094. IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
  1095. break;
  1096. }
  1097. }
  1098. if (len) {
  1099. IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
  1100. iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
  1101. return -EINVAL;
  1102. }
  1103. return 0;
  1104. invalid_tlv_len:
  1105. IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
  1106. iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
  1107. return -EINVAL;
  1108. }
  1109. /**
  1110. * iwl_ucode_callback - callback when firmware was loaded
  1111. *
  1112. * If loaded successfully, copies the firmware into buffers
  1113. * for the card to fetch (via DMA).
  1114. */
  1115. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1116. {
  1117. struct iwl_priv *priv = context;
  1118. struct iwl_ucode_header *ucode;
  1119. int err;
  1120. struct iwlagn_firmware_pieces pieces;
  1121. const unsigned int api_max = priv->cfg->ucode_api_max;
  1122. const unsigned int api_min = priv->cfg->ucode_api_min;
  1123. u32 api_ver;
  1124. char buildstr[25];
  1125. u32 build;
  1126. struct iwlagn_ucode_capabilities ucode_capa = {
  1127. .max_probe_length = 200,
  1128. .standard_phy_calibration_size =
  1129. IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
  1130. };
  1131. memset(&pieces, 0, sizeof(pieces));
  1132. if (!ucode_raw) {
  1133. if (priv->fw_index <= priv->cfg->ucode_api_max)
  1134. IWL_ERR(priv,
  1135. "request for firmware file '%s' failed.\n",
  1136. priv->firmware_name);
  1137. goto try_again;
  1138. }
  1139. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1140. priv->firmware_name, ucode_raw->size);
  1141. /* Make sure that we got at least the API version number */
  1142. if (ucode_raw->size < 4) {
  1143. IWL_ERR(priv, "File size way too small!\n");
  1144. goto try_again;
  1145. }
  1146. /* Data from ucode file: header followed by uCode images */
  1147. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1148. if (ucode->ver)
  1149. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1150. else
  1151. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1152. &ucode_capa);
  1153. if (err)
  1154. goto try_again;
  1155. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1156. build = pieces.build;
  1157. /*
  1158. * api_ver should match the api version forming part of the
  1159. * firmware filename ... but we don't check for that and only rely
  1160. * on the API version read from firmware header from here on forward
  1161. */
  1162. /* no api version check required for experimental uCode */
  1163. if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
  1164. if (api_ver < api_min || api_ver > api_max) {
  1165. IWL_ERR(priv,
  1166. "Driver unable to support your firmware API. "
  1167. "Driver supports v%u, firmware is v%u.\n",
  1168. api_max, api_ver);
  1169. goto try_again;
  1170. }
  1171. if (api_ver != api_max)
  1172. IWL_ERR(priv,
  1173. "Firmware has old API version. Expected v%u, "
  1174. "got v%u. New firmware can be obtained "
  1175. "from http://www.intellinuxwireless.org.\n",
  1176. api_max, api_ver);
  1177. }
  1178. if (build)
  1179. sprintf(buildstr, " build %u%s", build,
  1180. (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
  1181. ? " (EXP)" : "");
  1182. else
  1183. buildstr[0] = '\0';
  1184. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1185. IWL_UCODE_MAJOR(priv->ucode_ver),
  1186. IWL_UCODE_MINOR(priv->ucode_ver),
  1187. IWL_UCODE_API(priv->ucode_ver),
  1188. IWL_UCODE_SERIAL(priv->ucode_ver),
  1189. buildstr);
  1190. snprintf(priv->hw->wiphy->fw_version,
  1191. sizeof(priv->hw->wiphy->fw_version),
  1192. "%u.%u.%u.%u%s",
  1193. IWL_UCODE_MAJOR(priv->ucode_ver),
  1194. IWL_UCODE_MINOR(priv->ucode_ver),
  1195. IWL_UCODE_API(priv->ucode_ver),
  1196. IWL_UCODE_SERIAL(priv->ucode_ver),
  1197. buildstr);
  1198. /*
  1199. * For any of the failures below (before allocating pci memory)
  1200. * we will try to load a version with a smaller API -- maybe the
  1201. * user just got a corrupted version of the latest API.
  1202. */
  1203. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1204. priv->ucode_ver);
  1205. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1206. pieces.inst_size);
  1207. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1208. pieces.data_size);
  1209. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1210. pieces.init_size);
  1211. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1212. pieces.init_data_size);
  1213. /* Verify that uCode images will fit in card's SRAM */
  1214. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1215. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1216. pieces.inst_size);
  1217. goto try_again;
  1218. }
  1219. if (pieces.data_size > priv->hw_params.max_data_size) {
  1220. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1221. pieces.data_size);
  1222. goto try_again;
  1223. }
  1224. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1225. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1226. pieces.init_size);
  1227. goto try_again;
  1228. }
  1229. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1230. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1231. pieces.init_data_size);
  1232. goto try_again;
  1233. }
  1234. /* Allocate ucode buffers for card's bus-master loading ... */
  1235. /* Runtime instructions and 2 copies of data:
  1236. * 1) unmodified from disk
  1237. * 2) backup cache for save/restore during power-downs */
  1238. if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code,
  1239. pieces.inst, pieces.inst_size))
  1240. goto err_pci_alloc;
  1241. if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data,
  1242. pieces.data, pieces.data_size))
  1243. goto err_pci_alloc;
  1244. /* Initialization instructions and data */
  1245. if (pieces.init_size && pieces.init_data_size) {
  1246. if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code,
  1247. pieces.init, pieces.init_size))
  1248. goto err_pci_alloc;
  1249. if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data,
  1250. pieces.init_data, pieces.init_data_size))
  1251. goto err_pci_alloc;
  1252. }
  1253. /* Now that we can no longer fail, copy information */
  1254. /*
  1255. * The (size - 16) / 12 formula is based on the information recorded
  1256. * for each event, which is of mode 1 (including timestamp) for all
  1257. * new microcodes that include this information.
  1258. */
  1259. priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
  1260. if (pieces.init_evtlog_size)
  1261. priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
  1262. else
  1263. priv->_agn.init_evtlog_size =
  1264. priv->cfg->base_params->max_event_log_size;
  1265. priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
  1266. priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
  1267. if (pieces.inst_evtlog_size)
  1268. priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
  1269. else
  1270. priv->_agn.inst_evtlog_size =
  1271. priv->cfg->base_params->max_event_log_size;
  1272. priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
  1273. priv->new_scan_threshold_behaviour =
  1274. !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN);
  1275. if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
  1276. priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
  1277. priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
  1278. } else
  1279. priv->sta_key_max_num = STA_KEY_MAX_NUM;
  1280. if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
  1281. priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
  1282. else
  1283. priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
  1284. /*
  1285. * figure out the offset of chain noise reset and gain commands
  1286. * base on the size of standard phy calibration commands table size
  1287. */
  1288. if (ucode_capa.standard_phy_calibration_size >
  1289. IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
  1290. ucode_capa.standard_phy_calibration_size =
  1291. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
  1292. priv->_agn.phy_calib_chain_noise_reset_cmd =
  1293. ucode_capa.standard_phy_calibration_size;
  1294. priv->_agn.phy_calib_chain_noise_gain_cmd =
  1295. ucode_capa.standard_phy_calibration_size + 1;
  1296. /**************************************************
  1297. * This is still part of probe() in a sense...
  1298. *
  1299. * 9. Setup and register with mac80211 and debugfs
  1300. **************************************************/
  1301. err = iwl_mac_setup_register(priv, &ucode_capa);
  1302. if (err)
  1303. goto out_unbind;
  1304. err = iwl_dbgfs_register(priv, DRV_NAME);
  1305. if (err)
  1306. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1307. err = sysfs_create_group(&priv->pci_dev->dev.kobj,
  1308. &iwl_attribute_group);
  1309. if (err) {
  1310. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  1311. goto out_unbind;
  1312. }
  1313. /* We have our copies now, allow OS release its copies */
  1314. release_firmware(ucode_raw);
  1315. complete(&priv->_agn.firmware_loading_complete);
  1316. return;
  1317. try_again:
  1318. /* try next, if any */
  1319. if (iwl_request_firmware(priv, false))
  1320. goto out_unbind;
  1321. release_firmware(ucode_raw);
  1322. return;
  1323. err_pci_alloc:
  1324. IWL_ERR(priv, "failed to allocate pci memory\n");
  1325. iwl_dealloc_ucode_pci(priv);
  1326. out_unbind:
  1327. complete(&priv->_agn.firmware_loading_complete);
  1328. device_release_driver(&priv->pci_dev->dev);
  1329. release_firmware(ucode_raw);
  1330. }
  1331. static const char *desc_lookup_text[] = {
  1332. "OK",
  1333. "FAIL",
  1334. "BAD_PARAM",
  1335. "BAD_CHECKSUM",
  1336. "NMI_INTERRUPT_WDG",
  1337. "SYSASSERT",
  1338. "FATAL_ERROR",
  1339. "BAD_COMMAND",
  1340. "HW_ERROR_TUNE_LOCK",
  1341. "HW_ERROR_TEMPERATURE",
  1342. "ILLEGAL_CHAN_FREQ",
  1343. "VCC_NOT_STABLE",
  1344. "FH_ERROR",
  1345. "NMI_INTERRUPT_HOST",
  1346. "NMI_INTERRUPT_ACTION_PT",
  1347. "NMI_INTERRUPT_UNKNOWN",
  1348. "UCODE_VERSION_MISMATCH",
  1349. "HW_ERROR_ABS_LOCK",
  1350. "HW_ERROR_CAL_LOCK_FAIL",
  1351. "NMI_INTERRUPT_INST_ACTION_PT",
  1352. "NMI_INTERRUPT_DATA_ACTION_PT",
  1353. "NMI_TRM_HW_ER",
  1354. "NMI_INTERRUPT_TRM",
  1355. "NMI_INTERRUPT_BREAK_POINT"
  1356. "DEBUG_0",
  1357. "DEBUG_1",
  1358. "DEBUG_2",
  1359. "DEBUG_3",
  1360. };
  1361. static struct { char *name; u8 num; } advanced_lookup[] = {
  1362. { "NMI_INTERRUPT_WDG", 0x34 },
  1363. { "SYSASSERT", 0x35 },
  1364. { "UCODE_VERSION_MISMATCH", 0x37 },
  1365. { "BAD_COMMAND", 0x38 },
  1366. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  1367. { "FATAL_ERROR", 0x3D },
  1368. { "NMI_TRM_HW_ERR", 0x46 },
  1369. { "NMI_INTERRUPT_TRM", 0x4C },
  1370. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  1371. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  1372. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  1373. { "NMI_INTERRUPT_HOST", 0x66 },
  1374. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  1375. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  1376. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  1377. { "ADVANCED_SYSASSERT", 0 },
  1378. };
  1379. static const char *desc_lookup(u32 num)
  1380. {
  1381. int i;
  1382. int max = ARRAY_SIZE(desc_lookup_text);
  1383. if (num < max)
  1384. return desc_lookup_text[num];
  1385. max = ARRAY_SIZE(advanced_lookup) - 1;
  1386. for (i = 0; i < max; i++) {
  1387. if (advanced_lookup[i].num == num)
  1388. break;
  1389. }
  1390. return advanced_lookup[i].name;
  1391. }
  1392. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1393. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1394. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1395. {
  1396. u32 base;
  1397. struct iwl_error_event_table table;
  1398. base = priv->device_pointers.error_event_table;
  1399. if (priv->ucode_type == IWL_UCODE_INIT) {
  1400. if (!base)
  1401. base = priv->_agn.init_errlog_ptr;
  1402. } else {
  1403. if (!base)
  1404. base = priv->_agn.inst_errlog_ptr;
  1405. }
  1406. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1407. IWL_ERR(priv,
  1408. "Not valid error log pointer 0x%08X for %s uCode\n",
  1409. base,
  1410. (priv->ucode_type == IWL_UCODE_INIT)
  1411. ? "Init" : "RT");
  1412. return;
  1413. }
  1414. iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
  1415. if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
  1416. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1417. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1418. priv->status, table.valid);
  1419. }
  1420. priv->isr_stats.err_code = table.error_id;
  1421. trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
  1422. table.data1, table.data2, table.line,
  1423. table.blink1, table.blink2, table.ilink1,
  1424. table.ilink2, table.bcon_time, table.gp1,
  1425. table.gp2, table.gp3, table.ucode_ver,
  1426. table.hw_ver, table.brd_ver);
  1427. IWL_ERR(priv, "0x%08X | %-28s\n", table.error_id,
  1428. desc_lookup(table.error_id));
  1429. IWL_ERR(priv, "0x%08X | uPc\n", table.pc);
  1430. IWL_ERR(priv, "0x%08X | branchlink1\n", table.blink1);
  1431. IWL_ERR(priv, "0x%08X | branchlink2\n", table.blink2);
  1432. IWL_ERR(priv, "0x%08X | interruptlink1\n", table.ilink1);
  1433. IWL_ERR(priv, "0x%08X | interruptlink2\n", table.ilink2);
  1434. IWL_ERR(priv, "0x%08X | data1\n", table.data1);
  1435. IWL_ERR(priv, "0x%08X | data2\n", table.data2);
  1436. IWL_ERR(priv, "0x%08X | line\n", table.line);
  1437. IWL_ERR(priv, "0x%08X | beacon time\n", table.bcon_time);
  1438. IWL_ERR(priv, "0x%08X | tsf low\n", table.tsf_low);
  1439. IWL_ERR(priv, "0x%08X | tsf hi\n", table.tsf_hi);
  1440. IWL_ERR(priv, "0x%08X | time gp1\n", table.gp1);
  1441. IWL_ERR(priv, "0x%08X | time gp2\n", table.gp2);
  1442. IWL_ERR(priv, "0x%08X | time gp3\n", table.gp3);
  1443. IWL_ERR(priv, "0x%08X | uCode version\n", table.ucode_ver);
  1444. IWL_ERR(priv, "0x%08X | hw version\n", table.hw_ver);
  1445. IWL_ERR(priv, "0x%08X | board version\n", table.brd_ver);
  1446. IWL_ERR(priv, "0x%08X | hcmd\n", table.hcmd);
  1447. }
  1448. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1449. /**
  1450. * iwl_print_event_log - Dump error event log to syslog
  1451. *
  1452. */
  1453. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1454. u32 num_events, u32 mode,
  1455. int pos, char **buf, size_t bufsz)
  1456. {
  1457. u32 i;
  1458. u32 base; /* SRAM byte address of event log header */
  1459. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1460. u32 ptr; /* SRAM byte address of log data */
  1461. u32 ev, time, data; /* event log data */
  1462. unsigned long reg_flags;
  1463. if (num_events == 0)
  1464. return pos;
  1465. base = priv->device_pointers.log_event_table;
  1466. if (priv->ucode_type == IWL_UCODE_INIT) {
  1467. if (!base)
  1468. base = priv->_agn.init_evtlog_ptr;
  1469. } else {
  1470. if (!base)
  1471. base = priv->_agn.inst_evtlog_ptr;
  1472. }
  1473. if (mode == 0)
  1474. event_size = 2 * sizeof(u32);
  1475. else
  1476. event_size = 3 * sizeof(u32);
  1477. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1478. /* Make sure device is powered up for SRAM reads */
  1479. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1480. iwl_grab_nic_access(priv);
  1481. /* Set starting address; reads will auto-increment */
  1482. iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1483. rmb();
  1484. /* "time" is actually "data" for mode 0 (no timestamp).
  1485. * place event id # at far right for easier visual parsing. */
  1486. for (i = 0; i < num_events; i++) {
  1487. ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  1488. time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  1489. if (mode == 0) {
  1490. /* data, ev */
  1491. if (bufsz) {
  1492. pos += scnprintf(*buf + pos, bufsz - pos,
  1493. "EVT_LOG:0x%08x:%04u\n",
  1494. time, ev);
  1495. } else {
  1496. trace_iwlwifi_dev_ucode_event(priv, 0,
  1497. time, ev);
  1498. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1499. time, ev);
  1500. }
  1501. } else {
  1502. data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  1503. if (bufsz) {
  1504. pos += scnprintf(*buf + pos, bufsz - pos,
  1505. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1506. time, data, ev);
  1507. } else {
  1508. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1509. time, data, ev);
  1510. trace_iwlwifi_dev_ucode_event(priv, time,
  1511. data, ev);
  1512. }
  1513. }
  1514. }
  1515. /* Allow device to power down */
  1516. iwl_release_nic_access(priv);
  1517. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1518. return pos;
  1519. }
  1520. /**
  1521. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1522. */
  1523. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1524. u32 num_wraps, u32 next_entry,
  1525. u32 size, u32 mode,
  1526. int pos, char **buf, size_t bufsz)
  1527. {
  1528. /*
  1529. * display the newest DEFAULT_LOG_ENTRIES entries
  1530. * i.e the entries just before the next ont that uCode would fill.
  1531. */
  1532. if (num_wraps) {
  1533. if (next_entry < size) {
  1534. pos = iwl_print_event_log(priv,
  1535. capacity - (size - next_entry),
  1536. size - next_entry, mode,
  1537. pos, buf, bufsz);
  1538. pos = iwl_print_event_log(priv, 0,
  1539. next_entry, mode,
  1540. pos, buf, bufsz);
  1541. } else
  1542. pos = iwl_print_event_log(priv, next_entry - size,
  1543. size, mode, pos, buf, bufsz);
  1544. } else {
  1545. if (next_entry < size) {
  1546. pos = iwl_print_event_log(priv, 0, next_entry,
  1547. mode, pos, buf, bufsz);
  1548. } else {
  1549. pos = iwl_print_event_log(priv, next_entry - size,
  1550. size, mode, pos, buf, bufsz);
  1551. }
  1552. }
  1553. return pos;
  1554. }
  1555. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1556. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1557. char **buf, bool display)
  1558. {
  1559. u32 base; /* SRAM byte address of event log header */
  1560. u32 capacity; /* event log capacity in # entries */
  1561. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1562. u32 num_wraps; /* # times uCode wrapped to top of log */
  1563. u32 next_entry; /* index of next entry to be written by uCode */
  1564. u32 size; /* # entries that we'll print */
  1565. u32 logsize;
  1566. int pos = 0;
  1567. size_t bufsz = 0;
  1568. base = priv->device_pointers.log_event_table;
  1569. if (priv->ucode_type == IWL_UCODE_INIT) {
  1570. logsize = priv->_agn.init_evtlog_size;
  1571. if (!base)
  1572. base = priv->_agn.init_evtlog_ptr;
  1573. } else {
  1574. logsize = priv->_agn.inst_evtlog_size;
  1575. if (!base)
  1576. base = priv->_agn.inst_evtlog_ptr;
  1577. }
  1578. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1579. IWL_ERR(priv,
  1580. "Invalid event log pointer 0x%08X for %s uCode\n",
  1581. base,
  1582. (priv->ucode_type == IWL_UCODE_INIT)
  1583. ? "Init" : "RT");
  1584. return -EINVAL;
  1585. }
  1586. /* event log header */
  1587. capacity = iwl_read_targ_mem(priv, base);
  1588. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1589. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1590. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1591. if (capacity > logsize) {
  1592. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1593. capacity, logsize);
  1594. capacity = logsize;
  1595. }
  1596. if (next_entry > logsize) {
  1597. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1598. next_entry, logsize);
  1599. next_entry = logsize;
  1600. }
  1601. size = num_wraps ? capacity : next_entry;
  1602. /* bail out if nothing in log */
  1603. if (size == 0) {
  1604. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1605. return pos;
  1606. }
  1607. /* enable/disable bt channel inhibition */
  1608. priv->bt_ch_announce = iwlagn_bt_ch_announce;
  1609. #ifdef CONFIG_IWLWIFI_DEBUG
  1610. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1611. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1612. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1613. #else
  1614. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1615. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1616. #endif
  1617. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1618. size);
  1619. #ifdef CONFIG_IWLWIFI_DEBUG
  1620. if (display) {
  1621. if (full_log)
  1622. bufsz = capacity * 48;
  1623. else
  1624. bufsz = size * 48;
  1625. *buf = kmalloc(bufsz, GFP_KERNEL);
  1626. if (!*buf)
  1627. return -ENOMEM;
  1628. }
  1629. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1630. /*
  1631. * if uCode has wrapped back to top of log,
  1632. * start at the oldest entry,
  1633. * i.e the next one that uCode would fill.
  1634. */
  1635. if (num_wraps)
  1636. pos = iwl_print_event_log(priv, next_entry,
  1637. capacity - next_entry, mode,
  1638. pos, buf, bufsz);
  1639. /* (then/else) start at top of log */
  1640. pos = iwl_print_event_log(priv, 0,
  1641. next_entry, mode, pos, buf, bufsz);
  1642. } else
  1643. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1644. next_entry, size, mode,
  1645. pos, buf, bufsz);
  1646. #else
  1647. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1648. next_entry, size, mode,
  1649. pos, buf, bufsz);
  1650. #endif
  1651. return pos;
  1652. }
  1653. static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1654. {
  1655. struct iwl_ct_kill_config cmd;
  1656. struct iwl_ct_kill_throttling_config adv_cmd;
  1657. unsigned long flags;
  1658. int ret = 0;
  1659. spin_lock_irqsave(&priv->lock, flags);
  1660. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1661. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1662. spin_unlock_irqrestore(&priv->lock, flags);
  1663. priv->thermal_throttle.ct_kill_toggle = false;
  1664. if (priv->cfg->base_params->support_ct_kill_exit) {
  1665. adv_cmd.critical_temperature_enter =
  1666. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1667. adv_cmd.critical_temperature_exit =
  1668. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1669. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1670. sizeof(adv_cmd), &adv_cmd);
  1671. if (ret)
  1672. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1673. else
  1674. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1675. "succeeded, "
  1676. "critical temperature enter is %d,"
  1677. "exit is %d\n",
  1678. priv->hw_params.ct_kill_threshold,
  1679. priv->hw_params.ct_kill_exit_threshold);
  1680. } else {
  1681. cmd.critical_temperature_R =
  1682. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1683. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1684. sizeof(cmd), &cmd);
  1685. if (ret)
  1686. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1687. else
  1688. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1689. "succeeded, "
  1690. "critical temperature is %d\n",
  1691. priv->hw_params.ct_kill_threshold);
  1692. }
  1693. }
  1694. static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
  1695. {
  1696. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  1697. struct iwl_host_cmd cmd = {
  1698. .id = CALIBRATION_CFG_CMD,
  1699. .len = { sizeof(struct iwl_calib_cfg_cmd), },
  1700. .data = { &calib_cfg_cmd, },
  1701. };
  1702. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  1703. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  1704. calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
  1705. return iwl_send_cmd(priv, &cmd);
  1706. }
  1707. /**
  1708. * iwl_alive_start - called after REPLY_ALIVE notification received
  1709. * from protocol/runtime uCode (initialization uCode's
  1710. * Alive gets handled by iwl_init_alive_start()).
  1711. */
  1712. int iwl_alive_start(struct iwl_priv *priv)
  1713. {
  1714. int ret = 0;
  1715. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  1716. iwl_reset_ict(priv);
  1717. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1718. /* After the ALIVE response, we can send host commands to the uCode */
  1719. set_bit(STATUS_ALIVE, &priv->status);
  1720. /* Enable watchdog to monitor the driver tx queues */
  1721. iwl_setup_watchdog(priv);
  1722. if (iwl_is_rfkill(priv))
  1723. return -ERFKILL;
  1724. /* download priority table before any calibration request */
  1725. if (priv->cfg->bt_params &&
  1726. priv->cfg->bt_params->advanced_bt_coexist) {
  1727. /* Configure Bluetooth device coexistence support */
  1728. priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
  1729. priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
  1730. priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
  1731. priv->cfg->ops->hcmd->send_bt_config(priv);
  1732. priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
  1733. iwlagn_send_prio_tbl(priv);
  1734. /* FIXME: w/a to force change uCode BT state machine */
  1735. ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
  1736. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  1737. if (ret)
  1738. return ret;
  1739. ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
  1740. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  1741. if (ret)
  1742. return ret;
  1743. }
  1744. if (priv->hw_params.calib_rt_cfg)
  1745. iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
  1746. ieee80211_wake_queues(priv->hw);
  1747. priv->active_rate = IWL_RATES_MASK;
  1748. /* Configure Tx antenna selection based on H/W config */
  1749. if (priv->cfg->ops->hcmd->set_tx_ant)
  1750. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1751. if (iwl_is_associated_ctx(ctx)) {
  1752. struct iwl_rxon_cmd *active_rxon =
  1753. (struct iwl_rxon_cmd *)&ctx->active;
  1754. /* apply any changes in staging */
  1755. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1756. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1757. } else {
  1758. struct iwl_rxon_context *tmp;
  1759. /* Initialize our rx_config data */
  1760. for_each_context(priv, tmp)
  1761. iwl_connection_init_rx_config(priv, tmp);
  1762. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1763. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  1764. }
  1765. if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
  1766. !priv->cfg->bt_params->advanced_bt_coexist)) {
  1767. /*
  1768. * default is 2-wire BT coexexistence support
  1769. */
  1770. priv->cfg->ops->hcmd->send_bt_config(priv);
  1771. }
  1772. iwl_reset_run_time_calib(priv);
  1773. set_bit(STATUS_READY, &priv->status);
  1774. /* Configure the adapter for unassociated operation */
  1775. ret = iwlagn_commit_rxon(priv, ctx);
  1776. if (ret)
  1777. return ret;
  1778. /* At this point, the NIC is initialized and operational */
  1779. iwl_rf_kill_ct_config(priv);
  1780. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1781. return iwl_power_update_mode(priv, true);
  1782. }
  1783. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1784. static void __iwl_down(struct iwl_priv *priv)
  1785. {
  1786. int exit_pending;
  1787. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1788. iwl_scan_cancel_timeout(priv, 200);
  1789. exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
  1790. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  1791. * to prevent rearm timer */
  1792. del_timer_sync(&priv->watchdog);
  1793. iwl_clear_ucode_stations(priv, NULL);
  1794. iwl_dealloc_bcast_stations(priv);
  1795. iwl_clear_driver_stations(priv);
  1796. /* reset BT coex data */
  1797. priv->bt_status = 0;
  1798. if (priv->cfg->bt_params)
  1799. priv->bt_traffic_load =
  1800. priv->cfg->bt_params->bt_init_traffic_load;
  1801. else
  1802. priv->bt_traffic_load = 0;
  1803. priv->bt_full_concurrent = false;
  1804. priv->bt_ci_compliance = 0;
  1805. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1806. * exiting the module */
  1807. if (!exit_pending)
  1808. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1809. if (priv->mac80211_registered)
  1810. ieee80211_stop_queues(priv->hw);
  1811. /* Clear out all status bits but a few that are stable across reset */
  1812. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1813. STATUS_RF_KILL_HW |
  1814. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1815. STATUS_GEO_CONFIGURED |
  1816. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1817. STATUS_FW_ERROR |
  1818. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1819. STATUS_EXIT_PENDING;
  1820. iwlagn_stop_device(priv);
  1821. dev_kfree_skb(priv->beacon_skb);
  1822. priv->beacon_skb = NULL;
  1823. }
  1824. static void iwl_down(struct iwl_priv *priv)
  1825. {
  1826. mutex_lock(&priv->mutex);
  1827. __iwl_down(priv);
  1828. mutex_unlock(&priv->mutex);
  1829. iwl_cancel_deferred_work(priv);
  1830. }
  1831. #define HW_READY_TIMEOUT (50)
  1832. /* Note: returns poll_bit return value, which is >= 0 if success */
  1833. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1834. {
  1835. int ret;
  1836. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1837. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1838. /* See if we got it */
  1839. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1840. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1841. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1842. HW_READY_TIMEOUT);
  1843. IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
  1844. return ret;
  1845. }
  1846. /* Note: returns standard 0/-ERROR code */
  1847. int iwl_prepare_card_hw(struct iwl_priv *priv)
  1848. {
  1849. int ret;
  1850. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  1851. ret = iwl_set_hw_ready(priv);
  1852. if (ret >= 0)
  1853. return 0;
  1854. /* If HW is not ready, prepare the conditions to check again */
  1855. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1856. CSR_HW_IF_CONFIG_REG_PREPARE);
  1857. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1858. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1859. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1860. if (ret < 0)
  1861. return ret;
  1862. /* HW should be ready by now, check again. */
  1863. ret = iwl_set_hw_ready(priv);
  1864. if (ret >= 0)
  1865. return 0;
  1866. return ret;
  1867. }
  1868. #define MAX_HW_RESTARTS 5
  1869. static int __iwl_up(struct iwl_priv *priv)
  1870. {
  1871. struct iwl_rxon_context *ctx;
  1872. int ret;
  1873. lockdep_assert_held(&priv->mutex);
  1874. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1875. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1876. return -EIO;
  1877. }
  1878. for_each_context(priv, ctx) {
  1879. ret = iwlagn_alloc_bcast_station(priv, ctx);
  1880. if (ret) {
  1881. iwl_dealloc_bcast_stations(priv);
  1882. return ret;
  1883. }
  1884. }
  1885. ret = iwlagn_run_init_ucode(priv);
  1886. if (ret) {
  1887. IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret);
  1888. goto error;
  1889. }
  1890. ret = iwlagn_load_ucode_wait_alive(priv,
  1891. &priv->ucode_rt,
  1892. IWL_UCODE_REGULAR);
  1893. if (ret) {
  1894. IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
  1895. goto error;
  1896. }
  1897. ret = iwl_alive_start(priv);
  1898. if (ret)
  1899. goto error;
  1900. return 0;
  1901. error:
  1902. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1903. __iwl_down(priv);
  1904. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1905. IWL_ERR(priv, "Unable to initialize device.\n");
  1906. return ret;
  1907. }
  1908. /*****************************************************************************
  1909. *
  1910. * Workqueue callbacks
  1911. *
  1912. *****************************************************************************/
  1913. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1914. {
  1915. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1916. run_time_calib_work);
  1917. mutex_lock(&priv->mutex);
  1918. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1919. test_bit(STATUS_SCANNING, &priv->status)) {
  1920. mutex_unlock(&priv->mutex);
  1921. return;
  1922. }
  1923. if (priv->start_calib) {
  1924. iwl_chain_noise_calibration(priv);
  1925. iwl_sensitivity_calibration(priv);
  1926. }
  1927. mutex_unlock(&priv->mutex);
  1928. }
  1929. static void iwlagn_prepare_restart(struct iwl_priv *priv)
  1930. {
  1931. struct iwl_rxon_context *ctx;
  1932. bool bt_full_concurrent;
  1933. u8 bt_ci_compliance;
  1934. u8 bt_load;
  1935. u8 bt_status;
  1936. lockdep_assert_held(&priv->mutex);
  1937. for_each_context(priv, ctx)
  1938. ctx->vif = NULL;
  1939. priv->is_open = 0;
  1940. /*
  1941. * __iwl_down() will clear the BT status variables,
  1942. * which is correct, but when we restart we really
  1943. * want to keep them so restore them afterwards.
  1944. *
  1945. * The restart process will later pick them up and
  1946. * re-configure the hw when we reconfigure the BT
  1947. * command.
  1948. */
  1949. bt_full_concurrent = priv->bt_full_concurrent;
  1950. bt_ci_compliance = priv->bt_ci_compliance;
  1951. bt_load = priv->bt_traffic_load;
  1952. bt_status = priv->bt_status;
  1953. __iwl_down(priv);
  1954. priv->bt_full_concurrent = bt_full_concurrent;
  1955. priv->bt_ci_compliance = bt_ci_compliance;
  1956. priv->bt_traffic_load = bt_load;
  1957. priv->bt_status = bt_status;
  1958. }
  1959. static void iwl_bg_restart(struct work_struct *data)
  1960. {
  1961. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1962. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1963. return;
  1964. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1965. mutex_lock(&priv->mutex);
  1966. iwlagn_prepare_restart(priv);
  1967. mutex_unlock(&priv->mutex);
  1968. iwl_cancel_deferred_work(priv);
  1969. ieee80211_restart_hw(priv->hw);
  1970. } else {
  1971. WARN_ON(1);
  1972. }
  1973. }
  1974. static void iwl_bg_rx_replenish(struct work_struct *data)
  1975. {
  1976. struct iwl_priv *priv =
  1977. container_of(data, struct iwl_priv, rx_replenish);
  1978. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1979. return;
  1980. mutex_lock(&priv->mutex);
  1981. iwlagn_rx_replenish(priv);
  1982. mutex_unlock(&priv->mutex);
  1983. }
  1984. static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  1985. struct ieee80211_channel *chan,
  1986. enum nl80211_channel_type channel_type,
  1987. unsigned int wait)
  1988. {
  1989. struct iwl_priv *priv = hw->priv;
  1990. int ret;
  1991. /* Not supported if we don't have PAN */
  1992. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
  1993. ret = -EOPNOTSUPP;
  1994. goto free;
  1995. }
  1996. /* Not supported on pre-P2P firmware */
  1997. if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
  1998. BIT(NL80211_IFTYPE_P2P_CLIENT))) {
  1999. ret = -EOPNOTSUPP;
  2000. goto free;
  2001. }
  2002. mutex_lock(&priv->mutex);
  2003. if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
  2004. /*
  2005. * If the PAN context is free, use the normal
  2006. * way of doing remain-on-channel offload + TX.
  2007. */
  2008. ret = 1;
  2009. goto out;
  2010. }
  2011. /* TODO: queue up if scanning? */
  2012. if (test_bit(STATUS_SCANNING, &priv->status) ||
  2013. priv->_agn.offchan_tx_skb) {
  2014. ret = -EBUSY;
  2015. goto out;
  2016. }
  2017. /*
  2018. * max_scan_ie_len doesn't include the blank SSID or the header,
  2019. * so need to add that again here.
  2020. */
  2021. if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
  2022. ret = -ENOBUFS;
  2023. goto out;
  2024. }
  2025. priv->_agn.offchan_tx_skb = skb;
  2026. priv->_agn.offchan_tx_timeout = wait;
  2027. priv->_agn.offchan_tx_chan = chan;
  2028. ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
  2029. IWL_SCAN_OFFCH_TX, chan->band);
  2030. if (ret)
  2031. priv->_agn.offchan_tx_skb = NULL;
  2032. out:
  2033. mutex_unlock(&priv->mutex);
  2034. free:
  2035. if (ret < 0)
  2036. kfree_skb(skb);
  2037. return ret;
  2038. }
  2039. static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
  2040. {
  2041. struct iwl_priv *priv = hw->priv;
  2042. int ret;
  2043. mutex_lock(&priv->mutex);
  2044. if (!priv->_agn.offchan_tx_skb) {
  2045. ret = -EINVAL;
  2046. goto unlock;
  2047. }
  2048. priv->_agn.offchan_tx_skb = NULL;
  2049. ret = iwl_scan_cancel_timeout(priv, 200);
  2050. if (ret)
  2051. ret = -EIO;
  2052. unlock:
  2053. mutex_unlock(&priv->mutex);
  2054. return ret;
  2055. }
  2056. /*****************************************************************************
  2057. *
  2058. * mac80211 entry point functions
  2059. *
  2060. *****************************************************************************/
  2061. static const struct ieee80211_iface_limit iwlagn_sta_ap_limits[] = {
  2062. {
  2063. .max = 1,
  2064. .types = BIT(NL80211_IFTYPE_STATION),
  2065. },
  2066. {
  2067. .max = 1,
  2068. .types = BIT(NL80211_IFTYPE_AP),
  2069. },
  2070. };
  2071. static const struct ieee80211_iface_limit iwlagn_2sta_limits[] = {
  2072. {
  2073. .max = 2,
  2074. .types = BIT(NL80211_IFTYPE_STATION),
  2075. },
  2076. };
  2077. static const struct ieee80211_iface_limit iwlagn_p2p_sta_go_limits[] = {
  2078. {
  2079. .max = 1,
  2080. .types = BIT(NL80211_IFTYPE_STATION),
  2081. },
  2082. {
  2083. .max = 1,
  2084. .types = BIT(NL80211_IFTYPE_P2P_GO) |
  2085. BIT(NL80211_IFTYPE_AP),
  2086. },
  2087. };
  2088. static const struct ieee80211_iface_limit iwlagn_p2p_2sta_limits[] = {
  2089. {
  2090. .max = 2,
  2091. .types = BIT(NL80211_IFTYPE_STATION),
  2092. },
  2093. {
  2094. .max = 1,
  2095. .types = BIT(NL80211_IFTYPE_P2P_CLIENT),
  2096. },
  2097. };
  2098. static const struct ieee80211_iface_combination
  2099. iwlagn_iface_combinations_dualmode[] = {
  2100. { .num_different_channels = 1,
  2101. .max_interfaces = 2,
  2102. .beacon_int_infra_match = true,
  2103. .limits = iwlagn_sta_ap_limits,
  2104. .n_limits = ARRAY_SIZE(iwlagn_sta_ap_limits),
  2105. },
  2106. { .num_different_channels = 1,
  2107. .max_interfaces = 2,
  2108. .limits = iwlagn_2sta_limits,
  2109. .n_limits = ARRAY_SIZE(iwlagn_2sta_limits),
  2110. },
  2111. };
  2112. static const struct ieee80211_iface_combination
  2113. iwlagn_iface_combinations_p2p[] = {
  2114. { .num_different_channels = 1,
  2115. .max_interfaces = 2,
  2116. .beacon_int_infra_match = true,
  2117. .limits = iwlagn_p2p_sta_go_limits,
  2118. .n_limits = ARRAY_SIZE(iwlagn_p2p_sta_go_limits),
  2119. },
  2120. { .num_different_channels = 1,
  2121. .max_interfaces = 2,
  2122. .limits = iwlagn_p2p_2sta_limits,
  2123. .n_limits = ARRAY_SIZE(iwlagn_p2p_2sta_limits),
  2124. },
  2125. };
  2126. /*
  2127. * Not a mac80211 entry point function, but it fits in with all the
  2128. * other mac80211 functions grouped here.
  2129. */
  2130. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2131. struct iwlagn_ucode_capabilities *capa)
  2132. {
  2133. int ret;
  2134. struct ieee80211_hw *hw = priv->hw;
  2135. struct iwl_rxon_context *ctx;
  2136. hw->rate_control_algorithm = "iwl-agn-rs";
  2137. /* Tell mac80211 our characteristics */
  2138. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2139. IEEE80211_HW_AMPDU_AGGREGATION |
  2140. IEEE80211_HW_NEED_DTIM_PERIOD |
  2141. IEEE80211_HW_SPECTRUM_MGMT |
  2142. IEEE80211_HW_REPORTS_TX_ACK_STATUS;
  2143. hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
  2144. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2145. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2146. if (priv->cfg->sku & IWL_SKU_N)
  2147. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2148. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2149. if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
  2150. hw->flags |= IEEE80211_HW_MFP_CAPABLE;
  2151. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2152. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2153. for_each_context(priv, ctx) {
  2154. hw->wiphy->interface_modes |= ctx->interface_modes;
  2155. hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
  2156. }
  2157. BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
  2158. if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT)) {
  2159. hw->wiphy->iface_combinations = iwlagn_iface_combinations_p2p;
  2160. hw->wiphy->n_iface_combinations =
  2161. ARRAY_SIZE(iwlagn_iface_combinations_p2p);
  2162. } else if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_AP)) {
  2163. hw->wiphy->iface_combinations = iwlagn_iface_combinations_dualmode;
  2164. hw->wiphy->n_iface_combinations =
  2165. ARRAY_SIZE(iwlagn_iface_combinations_dualmode);
  2166. }
  2167. hw->wiphy->max_remain_on_channel_duration = 1000;
  2168. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2169. WIPHY_FLAG_DISABLE_BEACON_HINTS |
  2170. WIPHY_FLAG_IBSS_RSN;
  2171. /*
  2172. * For now, disable PS by default because it affects
  2173. * RX performance significantly.
  2174. */
  2175. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2176. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2177. /* we create the 802.11 header and a zero-length SSID element */
  2178. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2179. /* Default value; 4 EDCA QOS priorities */
  2180. hw->queues = 4;
  2181. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2182. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2183. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2184. &priv->bands[IEEE80211_BAND_2GHZ];
  2185. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2186. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2187. &priv->bands[IEEE80211_BAND_5GHZ];
  2188. iwl_leds_init(priv);
  2189. ret = ieee80211_register_hw(priv->hw);
  2190. if (ret) {
  2191. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2192. return ret;
  2193. }
  2194. priv->mac80211_registered = 1;
  2195. return 0;
  2196. }
  2197. static int iwlagn_mac_start(struct ieee80211_hw *hw)
  2198. {
  2199. struct iwl_priv *priv = hw->priv;
  2200. int ret;
  2201. IWL_DEBUG_MAC80211(priv, "enter\n");
  2202. /* we should be verifying the device is ready to be opened */
  2203. mutex_lock(&priv->mutex);
  2204. ret = __iwl_up(priv);
  2205. mutex_unlock(&priv->mutex);
  2206. if (ret)
  2207. return ret;
  2208. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2209. /* Now we should be done, and the READY bit should be set. */
  2210. if (WARN_ON(!test_bit(STATUS_READY, &priv->status)))
  2211. ret = -EIO;
  2212. iwlagn_led_enable(priv);
  2213. priv->is_open = 1;
  2214. IWL_DEBUG_MAC80211(priv, "leave\n");
  2215. return 0;
  2216. }
  2217. static void iwlagn_mac_stop(struct ieee80211_hw *hw)
  2218. {
  2219. struct iwl_priv *priv = hw->priv;
  2220. IWL_DEBUG_MAC80211(priv, "enter\n");
  2221. if (!priv->is_open)
  2222. return;
  2223. priv->is_open = 0;
  2224. iwl_down(priv);
  2225. flush_workqueue(priv->workqueue);
  2226. /* User space software may expect getting rfkill changes
  2227. * even if interface is down */
  2228. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2229. iwl_enable_rfkill_int(priv);
  2230. IWL_DEBUG_MAC80211(priv, "leave\n");
  2231. }
  2232. static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2233. {
  2234. struct iwl_priv *priv = hw->priv;
  2235. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2236. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2237. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2238. if (iwlagn_tx_skb(priv, skb))
  2239. dev_kfree_skb_any(skb);
  2240. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2241. }
  2242. static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
  2243. struct ieee80211_vif *vif,
  2244. struct ieee80211_key_conf *keyconf,
  2245. struct ieee80211_sta *sta,
  2246. u32 iv32, u16 *phase1key)
  2247. {
  2248. struct iwl_priv *priv = hw->priv;
  2249. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2250. IWL_DEBUG_MAC80211(priv, "enter\n");
  2251. iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
  2252. iv32, phase1key);
  2253. IWL_DEBUG_MAC80211(priv, "leave\n");
  2254. }
  2255. static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2256. struct ieee80211_vif *vif,
  2257. struct ieee80211_sta *sta,
  2258. struct ieee80211_key_conf *key)
  2259. {
  2260. struct iwl_priv *priv = hw->priv;
  2261. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2262. struct iwl_rxon_context *ctx = vif_priv->ctx;
  2263. int ret;
  2264. u8 sta_id;
  2265. bool is_default_wep_key = false;
  2266. IWL_DEBUG_MAC80211(priv, "enter\n");
  2267. if (iwlagn_mod_params.sw_crypto) {
  2268. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2269. return -EOPNOTSUPP;
  2270. }
  2271. /*
  2272. * To support IBSS RSN, don't program group keys in IBSS, the
  2273. * hardware will then not attempt to decrypt the frames.
  2274. */
  2275. if (vif->type == NL80211_IFTYPE_ADHOC &&
  2276. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
  2277. return -EOPNOTSUPP;
  2278. sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
  2279. if (sta_id == IWL_INVALID_STATION)
  2280. return -EINVAL;
  2281. mutex_lock(&priv->mutex);
  2282. iwl_scan_cancel_timeout(priv, 100);
  2283. /*
  2284. * If we are getting WEP group key and we didn't receive any key mapping
  2285. * so far, we are in legacy wep mode (group key only), otherwise we are
  2286. * in 1X mode.
  2287. * In legacy wep mode, we use another host command to the uCode.
  2288. */
  2289. if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  2290. key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
  2291. !sta) {
  2292. if (cmd == SET_KEY)
  2293. is_default_wep_key = !ctx->key_mapping_keys;
  2294. else
  2295. is_default_wep_key =
  2296. (key->hw_key_idx == HW_KEY_DEFAULT);
  2297. }
  2298. switch (cmd) {
  2299. case SET_KEY:
  2300. if (is_default_wep_key)
  2301. ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
  2302. else
  2303. ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
  2304. key, sta_id);
  2305. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2306. break;
  2307. case DISABLE_KEY:
  2308. if (is_default_wep_key)
  2309. ret = iwl_remove_default_wep_key(priv, ctx, key);
  2310. else
  2311. ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
  2312. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2313. break;
  2314. default:
  2315. ret = -EINVAL;
  2316. }
  2317. mutex_unlock(&priv->mutex);
  2318. IWL_DEBUG_MAC80211(priv, "leave\n");
  2319. return ret;
  2320. }
  2321. static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
  2322. struct ieee80211_vif *vif,
  2323. enum ieee80211_ampdu_mlme_action action,
  2324. struct ieee80211_sta *sta, u16 tid, u16 *ssn,
  2325. u8 buf_size)
  2326. {
  2327. struct iwl_priv *priv = hw->priv;
  2328. int ret = -EINVAL;
  2329. struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
  2330. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2331. sta->addr, tid);
  2332. if (!(priv->cfg->sku & IWL_SKU_N))
  2333. return -EACCES;
  2334. mutex_lock(&priv->mutex);
  2335. switch (action) {
  2336. case IEEE80211_AMPDU_RX_START:
  2337. IWL_DEBUG_HT(priv, "start Rx\n");
  2338. ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2339. break;
  2340. case IEEE80211_AMPDU_RX_STOP:
  2341. IWL_DEBUG_HT(priv, "stop Rx\n");
  2342. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2343. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2344. ret = 0;
  2345. break;
  2346. case IEEE80211_AMPDU_TX_START:
  2347. IWL_DEBUG_HT(priv, "start Tx\n");
  2348. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2349. if (ret == 0) {
  2350. priv->_agn.agg_tids_count++;
  2351. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2352. priv->_agn.agg_tids_count);
  2353. }
  2354. break;
  2355. case IEEE80211_AMPDU_TX_STOP:
  2356. IWL_DEBUG_HT(priv, "stop Tx\n");
  2357. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  2358. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2359. priv->_agn.agg_tids_count--;
  2360. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2361. priv->_agn.agg_tids_count);
  2362. }
  2363. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2364. ret = 0;
  2365. if (priv->cfg->ht_params &&
  2366. priv->cfg->ht_params->use_rts_for_aggregation) {
  2367. /*
  2368. * switch off RTS/CTS if it was previously enabled
  2369. */
  2370. sta_priv->lq_sta.lq.general_params.flags &=
  2371. ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2372. iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
  2373. &sta_priv->lq_sta.lq, CMD_ASYNC, false);
  2374. }
  2375. break;
  2376. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2377. buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
  2378. iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
  2379. /*
  2380. * If the limit is 0, then it wasn't initialised yet,
  2381. * use the default. We can do that since we take the
  2382. * minimum below, and we don't want to go above our
  2383. * default due to hardware restrictions.
  2384. */
  2385. if (sta_priv->max_agg_bufsize == 0)
  2386. sta_priv->max_agg_bufsize =
  2387. LINK_QUAL_AGG_FRAME_LIMIT_DEF;
  2388. /*
  2389. * Even though in theory the peer could have different
  2390. * aggregation reorder buffer sizes for different sessions,
  2391. * our ucode doesn't allow for that and has a global limit
  2392. * for each station. Therefore, use the minimum of all the
  2393. * aggregation sessions and our default value.
  2394. */
  2395. sta_priv->max_agg_bufsize =
  2396. min(sta_priv->max_agg_bufsize, buf_size);
  2397. if (priv->cfg->ht_params &&
  2398. priv->cfg->ht_params->use_rts_for_aggregation) {
  2399. /*
  2400. * switch to RTS/CTS if it is the prefer protection
  2401. * method for HT traffic
  2402. */
  2403. sta_priv->lq_sta.lq.general_params.flags |=
  2404. LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2405. }
  2406. sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
  2407. sta_priv->max_agg_bufsize;
  2408. iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
  2409. &sta_priv->lq_sta.lq, CMD_ASYNC, false);
  2410. IWL_INFO(priv, "Tx aggregation enabled on ra = %pM tid = %d\n",
  2411. sta->addr, tid);
  2412. ret = 0;
  2413. break;
  2414. }
  2415. mutex_unlock(&priv->mutex);
  2416. return ret;
  2417. }
  2418. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2419. struct ieee80211_vif *vif,
  2420. struct ieee80211_sta *sta)
  2421. {
  2422. struct iwl_priv *priv = hw->priv;
  2423. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2424. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2425. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2426. int ret;
  2427. u8 sta_id;
  2428. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2429. sta->addr);
  2430. mutex_lock(&priv->mutex);
  2431. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2432. sta->addr);
  2433. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2434. atomic_set(&sta_priv->pending_frames, 0);
  2435. if (vif->type == NL80211_IFTYPE_AP)
  2436. sta_priv->client = true;
  2437. ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
  2438. is_ap, sta, &sta_id);
  2439. if (ret) {
  2440. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2441. sta->addr, ret);
  2442. /* Should we return success if return code is EEXIST ? */
  2443. mutex_unlock(&priv->mutex);
  2444. return ret;
  2445. }
  2446. sta_priv->common.sta_id = sta_id;
  2447. /* Initialize rate scaling */
  2448. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2449. sta->addr);
  2450. iwl_rs_rate_init(priv, sta, sta_id);
  2451. mutex_unlock(&priv->mutex);
  2452. return 0;
  2453. }
  2454. static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
  2455. struct ieee80211_channel_switch *ch_switch)
  2456. {
  2457. struct iwl_priv *priv = hw->priv;
  2458. const struct iwl_channel_info *ch_info;
  2459. struct ieee80211_conf *conf = &hw->conf;
  2460. struct ieee80211_channel *channel = ch_switch->channel;
  2461. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2462. /*
  2463. * MULTI-FIXME
  2464. * When we add support for multiple interfaces, we need to
  2465. * revisit this. The channel switch command in the device
  2466. * only affects the BSS context, but what does that really
  2467. * mean? And what if we get a CSA on the second interface?
  2468. * This needs a lot of work.
  2469. */
  2470. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2471. u16 ch;
  2472. IWL_DEBUG_MAC80211(priv, "enter\n");
  2473. mutex_lock(&priv->mutex);
  2474. if (iwl_is_rfkill(priv))
  2475. goto out;
  2476. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2477. test_bit(STATUS_SCANNING, &priv->status) ||
  2478. test_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status))
  2479. goto out;
  2480. if (!iwl_is_associated_ctx(ctx))
  2481. goto out;
  2482. if (!priv->cfg->ops->lib->set_channel_switch)
  2483. goto out;
  2484. ch = channel->hw_value;
  2485. if (le16_to_cpu(ctx->active.channel) == ch)
  2486. goto out;
  2487. ch_info = iwl_get_channel_info(priv, channel->band, ch);
  2488. if (!is_channel_valid(ch_info)) {
  2489. IWL_DEBUG_MAC80211(priv, "invalid channel\n");
  2490. goto out;
  2491. }
  2492. spin_lock_irq(&priv->lock);
  2493. priv->current_ht_config.smps = conf->smps_mode;
  2494. /* Configure HT40 channels */
  2495. ctx->ht.enabled = conf_is_ht(conf);
  2496. if (ctx->ht.enabled) {
  2497. if (conf_is_ht40_minus(conf)) {
  2498. ctx->ht.extension_chan_offset =
  2499. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2500. ctx->ht.is_40mhz = true;
  2501. } else if (conf_is_ht40_plus(conf)) {
  2502. ctx->ht.extension_chan_offset =
  2503. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2504. ctx->ht.is_40mhz = true;
  2505. } else {
  2506. ctx->ht.extension_chan_offset =
  2507. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2508. ctx->ht.is_40mhz = false;
  2509. }
  2510. } else
  2511. ctx->ht.is_40mhz = false;
  2512. if ((le16_to_cpu(ctx->staging.channel) != ch))
  2513. ctx->staging.flags = 0;
  2514. iwl_set_rxon_channel(priv, channel, ctx);
  2515. iwl_set_rxon_ht(priv, ht_conf);
  2516. iwl_set_flags_for_band(priv, ctx, channel->band, ctx->vif);
  2517. spin_unlock_irq(&priv->lock);
  2518. iwl_set_rate(priv);
  2519. /*
  2520. * at this point, staging_rxon has the
  2521. * configuration for channel switch
  2522. */
  2523. set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
  2524. priv->switch_channel = cpu_to_le16(ch);
  2525. if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) {
  2526. clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
  2527. priv->switch_channel = 0;
  2528. ieee80211_chswitch_done(ctx->vif, false);
  2529. }
  2530. out:
  2531. mutex_unlock(&priv->mutex);
  2532. IWL_DEBUG_MAC80211(priv, "leave\n");
  2533. }
  2534. static void iwlagn_configure_filter(struct ieee80211_hw *hw,
  2535. unsigned int changed_flags,
  2536. unsigned int *total_flags,
  2537. u64 multicast)
  2538. {
  2539. struct iwl_priv *priv = hw->priv;
  2540. __le32 filter_or = 0, filter_nand = 0;
  2541. struct iwl_rxon_context *ctx;
  2542. #define CHK(test, flag) do { \
  2543. if (*total_flags & (test)) \
  2544. filter_or |= (flag); \
  2545. else \
  2546. filter_nand |= (flag); \
  2547. } while (0)
  2548. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2549. changed_flags, *total_flags);
  2550. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2551. /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
  2552. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
  2553. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2554. #undef CHK
  2555. mutex_lock(&priv->mutex);
  2556. for_each_context(priv, ctx) {
  2557. ctx->staging.filter_flags &= ~filter_nand;
  2558. ctx->staging.filter_flags |= filter_or;
  2559. /*
  2560. * Not committing directly because hardware can perform a scan,
  2561. * but we'll eventually commit the filter flags change anyway.
  2562. */
  2563. }
  2564. mutex_unlock(&priv->mutex);
  2565. /*
  2566. * Receiving all multicast frames is always enabled by the
  2567. * default flags setup in iwl_connection_init_rx_config()
  2568. * since we currently do not support programming multicast
  2569. * filters into the device.
  2570. */
  2571. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2572. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2573. }
  2574. static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
  2575. {
  2576. struct iwl_priv *priv = hw->priv;
  2577. mutex_lock(&priv->mutex);
  2578. IWL_DEBUG_MAC80211(priv, "enter\n");
  2579. /* do not support "flush" */
  2580. if (!priv->cfg->ops->lib->txfifo_flush)
  2581. goto done;
  2582. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2583. IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
  2584. goto done;
  2585. }
  2586. if (iwl_is_rfkill(priv)) {
  2587. IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
  2588. goto done;
  2589. }
  2590. /*
  2591. * mac80211 will not push any more frames for transmit
  2592. * until the flush is completed
  2593. */
  2594. if (drop) {
  2595. IWL_DEBUG_MAC80211(priv, "send flush command\n");
  2596. if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
  2597. IWL_ERR(priv, "flush request fail\n");
  2598. goto done;
  2599. }
  2600. }
  2601. IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
  2602. iwlagn_wait_tx_queue_empty(priv);
  2603. done:
  2604. mutex_unlock(&priv->mutex);
  2605. IWL_DEBUG_MAC80211(priv, "leave\n");
  2606. }
  2607. static void iwlagn_disable_roc(struct iwl_priv *priv)
  2608. {
  2609. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
  2610. struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
  2611. lockdep_assert_held(&priv->mutex);
  2612. if (!ctx->is_active)
  2613. return;
  2614. ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
  2615. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2616. iwl_set_rxon_channel(priv, chan, ctx);
  2617. iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
  2618. priv->_agn.hw_roc_channel = NULL;
  2619. iwlagn_commit_rxon(priv, ctx);
  2620. ctx->is_active = false;
  2621. }
  2622. static void iwlagn_bg_roc_done(struct work_struct *work)
  2623. {
  2624. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2625. _agn.hw_roc_work.work);
  2626. mutex_lock(&priv->mutex);
  2627. ieee80211_remain_on_channel_expired(priv->hw);
  2628. iwlagn_disable_roc(priv);
  2629. mutex_unlock(&priv->mutex);
  2630. }
  2631. static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
  2632. struct ieee80211_channel *channel,
  2633. enum nl80211_channel_type channel_type,
  2634. int duration)
  2635. {
  2636. struct iwl_priv *priv = hw->priv;
  2637. int err = 0;
  2638. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
  2639. return -EOPNOTSUPP;
  2640. if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
  2641. BIT(NL80211_IFTYPE_P2P_CLIENT)))
  2642. return -EOPNOTSUPP;
  2643. mutex_lock(&priv->mutex);
  2644. if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
  2645. test_bit(STATUS_SCAN_HW, &priv->status)) {
  2646. err = -EBUSY;
  2647. goto out;
  2648. }
  2649. priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
  2650. priv->_agn.hw_roc_channel = channel;
  2651. priv->_agn.hw_roc_chantype = channel_type;
  2652. priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
  2653. iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
  2654. queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
  2655. msecs_to_jiffies(duration + 20));
  2656. msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
  2657. ieee80211_ready_on_channel(priv->hw);
  2658. out:
  2659. mutex_unlock(&priv->mutex);
  2660. return err;
  2661. }
  2662. static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
  2663. {
  2664. struct iwl_priv *priv = hw->priv;
  2665. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
  2666. return -EOPNOTSUPP;
  2667. cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
  2668. mutex_lock(&priv->mutex);
  2669. iwlagn_disable_roc(priv);
  2670. mutex_unlock(&priv->mutex);
  2671. return 0;
  2672. }
  2673. /*****************************************************************************
  2674. *
  2675. * driver setup and teardown
  2676. *
  2677. *****************************************************************************/
  2678. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2679. {
  2680. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2681. init_waitqueue_head(&priv->wait_command_queue);
  2682. INIT_WORK(&priv->restart, iwl_bg_restart);
  2683. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2684. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2685. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2686. INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
  2687. INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
  2688. INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
  2689. INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
  2690. iwl_setup_scan_deferred_work(priv);
  2691. if (priv->cfg->ops->lib->setup_deferred_work)
  2692. priv->cfg->ops->lib->setup_deferred_work(priv);
  2693. init_timer(&priv->statistics_periodic);
  2694. priv->statistics_periodic.data = (unsigned long)priv;
  2695. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2696. init_timer(&priv->ucode_trace);
  2697. priv->ucode_trace.data = (unsigned long)priv;
  2698. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2699. init_timer(&priv->watchdog);
  2700. priv->watchdog.data = (unsigned long)priv;
  2701. priv->watchdog.function = iwl_bg_watchdog;
  2702. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2703. iwl_irq_tasklet, (unsigned long)priv);
  2704. }
  2705. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2706. {
  2707. if (priv->cfg->ops->lib->cancel_deferred_work)
  2708. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2709. cancel_work_sync(&priv->run_time_calib_work);
  2710. cancel_work_sync(&priv->beacon_update);
  2711. iwl_cancel_scan_deferred_work(priv);
  2712. cancel_work_sync(&priv->bt_full_concurrency);
  2713. cancel_work_sync(&priv->bt_runtime_config);
  2714. del_timer_sync(&priv->statistics_periodic);
  2715. del_timer_sync(&priv->ucode_trace);
  2716. }
  2717. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2718. struct ieee80211_rate *rates)
  2719. {
  2720. int i;
  2721. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2722. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2723. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2724. rates[i].hw_value_short = i;
  2725. rates[i].flags = 0;
  2726. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2727. /*
  2728. * If CCK != 1M then set short preamble rate flag.
  2729. */
  2730. rates[i].flags |=
  2731. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2732. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2733. }
  2734. }
  2735. }
  2736. static int iwl_init_drv(struct iwl_priv *priv)
  2737. {
  2738. int ret;
  2739. spin_lock_init(&priv->sta_lock);
  2740. spin_lock_init(&priv->hcmd_lock);
  2741. mutex_init(&priv->mutex);
  2742. priv->ieee_channels = NULL;
  2743. priv->ieee_rates = NULL;
  2744. priv->band = IEEE80211_BAND_2GHZ;
  2745. priv->iw_mode = NL80211_IFTYPE_STATION;
  2746. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2747. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2748. priv->_agn.agg_tids_count = 0;
  2749. /* initialize force reset */
  2750. priv->force_reset[IWL_RF_RESET].reset_duration =
  2751. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2752. priv->force_reset[IWL_FW_RESET].reset_duration =
  2753. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2754. priv->rx_statistics_jiffies = jiffies;
  2755. /* Choose which receivers/antennas to use */
  2756. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2757. priv->cfg->ops->hcmd->set_rxon_chain(priv,
  2758. &priv->contexts[IWL_RXON_CTX_BSS]);
  2759. iwl_init_scan_params(priv);
  2760. /* init bt coex */
  2761. if (priv->cfg->bt_params &&
  2762. priv->cfg->bt_params->advanced_bt_coexist) {
  2763. priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
  2764. priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
  2765. priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
  2766. priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
  2767. priv->bt_duration = BT_DURATION_LIMIT_DEF;
  2768. priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
  2769. }
  2770. ret = iwl_init_channel_map(priv);
  2771. if (ret) {
  2772. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2773. goto err;
  2774. }
  2775. ret = iwlcore_init_geos(priv);
  2776. if (ret) {
  2777. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2778. goto err_free_channel_map;
  2779. }
  2780. iwl_init_hw_rates(priv, priv->ieee_rates);
  2781. return 0;
  2782. err_free_channel_map:
  2783. iwl_free_channel_map(priv);
  2784. err:
  2785. return ret;
  2786. }
  2787. static void iwl_uninit_drv(struct iwl_priv *priv)
  2788. {
  2789. iwl_calib_free_results(priv);
  2790. iwlcore_free_geos(priv);
  2791. iwl_free_channel_map(priv);
  2792. kfree(priv->scan_cmd);
  2793. kfree(priv->beacon_cmd);
  2794. }
  2795. struct ieee80211_ops iwlagn_hw_ops = {
  2796. .tx = iwlagn_mac_tx,
  2797. .start = iwlagn_mac_start,
  2798. .stop = iwlagn_mac_stop,
  2799. .add_interface = iwl_mac_add_interface,
  2800. .remove_interface = iwl_mac_remove_interface,
  2801. .change_interface = iwl_mac_change_interface,
  2802. .config = iwlagn_mac_config,
  2803. .configure_filter = iwlagn_configure_filter,
  2804. .set_key = iwlagn_mac_set_key,
  2805. .update_tkip_key = iwlagn_mac_update_tkip_key,
  2806. .conf_tx = iwl_mac_conf_tx,
  2807. .bss_info_changed = iwlagn_bss_info_changed,
  2808. .ampdu_action = iwlagn_mac_ampdu_action,
  2809. .hw_scan = iwl_mac_hw_scan,
  2810. .sta_notify = iwlagn_mac_sta_notify,
  2811. .sta_add = iwlagn_mac_sta_add,
  2812. .sta_remove = iwl_mac_sta_remove,
  2813. .channel_switch = iwlagn_mac_channel_switch,
  2814. .flush = iwlagn_mac_flush,
  2815. .tx_last_beacon = iwl_mac_tx_last_beacon,
  2816. .remain_on_channel = iwl_mac_remain_on_channel,
  2817. .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
  2818. .offchannel_tx = iwl_mac_offchannel_tx,
  2819. .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
  2820. CFG80211_TESTMODE_CMD(iwl_testmode_cmd)
  2821. CFG80211_TESTMODE_DUMP(iwl_testmode_dump)
  2822. };
  2823. static u32 iwl_hw_detect(struct iwl_priv *priv)
  2824. {
  2825. u8 rev_id;
  2826. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  2827. IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
  2828. return iwl_read32(priv, CSR_HW_REV);
  2829. }
  2830. static int iwl_set_hw_params(struct iwl_priv *priv)
  2831. {
  2832. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  2833. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  2834. if (iwlagn_mod_params.amsdu_size_8K)
  2835. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  2836. else
  2837. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  2838. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  2839. if (iwlagn_mod_params.disable_11n)
  2840. priv->cfg->sku &= ~IWL_SKU_N;
  2841. /* Device-specific setup */
  2842. return priv->cfg->ops->lib->set_hw_params(priv);
  2843. }
  2844. static const u8 iwlagn_bss_ac_to_fifo[] = {
  2845. IWL_TX_FIFO_VO,
  2846. IWL_TX_FIFO_VI,
  2847. IWL_TX_FIFO_BE,
  2848. IWL_TX_FIFO_BK,
  2849. };
  2850. static const u8 iwlagn_bss_ac_to_queue[] = {
  2851. 0, 1, 2, 3,
  2852. };
  2853. static const u8 iwlagn_pan_ac_to_fifo[] = {
  2854. IWL_TX_FIFO_VO_IPAN,
  2855. IWL_TX_FIFO_VI_IPAN,
  2856. IWL_TX_FIFO_BE_IPAN,
  2857. IWL_TX_FIFO_BK_IPAN,
  2858. };
  2859. static const u8 iwlagn_pan_ac_to_queue[] = {
  2860. 7, 6, 5, 4,
  2861. };
  2862. /* This function both allocates and initializes hw and priv. */
  2863. static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
  2864. {
  2865. struct iwl_priv *priv;
  2866. /* mac80211 allocates memory for this device instance, including
  2867. * space for this driver's private structure */
  2868. struct ieee80211_hw *hw;
  2869. hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
  2870. if (hw == NULL) {
  2871. pr_err("%s: Can not allocate network device\n",
  2872. cfg->name);
  2873. goto out;
  2874. }
  2875. priv = hw->priv;
  2876. priv->hw = hw;
  2877. out:
  2878. return hw;
  2879. }
  2880. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2881. {
  2882. int err = 0, i;
  2883. struct iwl_priv *priv;
  2884. struct ieee80211_hw *hw;
  2885. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2886. unsigned long flags;
  2887. u16 pci_cmd, num_mac;
  2888. u32 hw_rev;
  2889. /************************
  2890. * 1. Allocating HW data
  2891. ************************/
  2892. hw = iwl_alloc_all(cfg);
  2893. if (!hw) {
  2894. err = -ENOMEM;
  2895. goto out;
  2896. }
  2897. priv = hw->priv;
  2898. /* At this point both hw and priv are allocated. */
  2899. /*
  2900. * The default context is always valid,
  2901. * more may be discovered when firmware
  2902. * is loaded.
  2903. */
  2904. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  2905. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  2906. priv->contexts[i].ctxid = i;
  2907. priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
  2908. priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
  2909. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  2910. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  2911. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  2912. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  2913. priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
  2914. priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
  2915. priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
  2916. priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
  2917. priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
  2918. BIT(NL80211_IFTYPE_ADHOC);
  2919. priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
  2920. BIT(NL80211_IFTYPE_STATION);
  2921. priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
  2922. priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
  2923. priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
  2924. priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
  2925. priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
  2926. priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
  2927. priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
  2928. priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
  2929. priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
  2930. priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
  2931. priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
  2932. priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
  2933. priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
  2934. priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
  2935. priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
  2936. priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
  2937. BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
  2938. #ifdef CONFIG_IWL_P2P
  2939. priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
  2940. BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
  2941. #endif
  2942. priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
  2943. priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
  2944. priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
  2945. BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
  2946. SET_IEEE80211_DEV(hw, &pdev->dev);
  2947. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2948. priv->cfg = cfg;
  2949. priv->pci_dev = pdev;
  2950. priv->inta_mask = CSR_INI_SET_MASK;
  2951. /* is antenna coupling more than 35dB ? */
  2952. priv->bt_ant_couple_ok =
  2953. (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
  2954. true : false;
  2955. /* enable/disable bt channel inhibition */
  2956. priv->bt_ch_announce = iwlagn_bt_ch_announce;
  2957. IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
  2958. (priv->bt_ch_announce) ? "On" : "Off");
  2959. if (iwl_alloc_traffic_mem(priv))
  2960. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2961. /**************************
  2962. * 2. Initializing PCI bus
  2963. **************************/
  2964. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  2965. PCIE_LINK_STATE_CLKPM);
  2966. if (pci_enable_device(pdev)) {
  2967. err = -ENODEV;
  2968. goto out_ieee80211_free_hw;
  2969. }
  2970. pci_set_master(pdev);
  2971. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2972. if (!err)
  2973. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2974. if (err) {
  2975. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2976. if (!err)
  2977. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2978. /* both attempts failed: */
  2979. if (err) {
  2980. IWL_WARN(priv, "No suitable DMA available.\n");
  2981. goto out_pci_disable_device;
  2982. }
  2983. }
  2984. err = pci_request_regions(pdev, DRV_NAME);
  2985. if (err)
  2986. goto out_pci_disable_device;
  2987. pci_set_drvdata(pdev, priv);
  2988. /***********************
  2989. * 3. Read REV register
  2990. ***********************/
  2991. priv->hw_base = pci_iomap(pdev, 0, 0);
  2992. if (!priv->hw_base) {
  2993. err = -ENODEV;
  2994. goto out_pci_release_regions;
  2995. }
  2996. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2997. (unsigned long long) pci_resource_len(pdev, 0));
  2998. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2999. /* these spin locks will be used in apm_ops.init and EEPROM access
  3000. * we should init now
  3001. */
  3002. spin_lock_init(&priv->reg_lock);
  3003. spin_lock_init(&priv->lock);
  3004. /*
  3005. * stop and reset the on-board processor just in case it is in a
  3006. * strange state ... like being left stranded by a primary kernel
  3007. * and this is now the kdump kernel trying to start up
  3008. */
  3009. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3010. hw_rev = iwl_hw_detect(priv);
  3011. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3012. priv->cfg->name, hw_rev);
  3013. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3014. * PCI Tx retries from interfering with C3 CPU state */
  3015. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3016. if (iwl_prepare_card_hw(priv)) {
  3017. IWL_WARN(priv, "Failed, HW not ready\n");
  3018. goto out_iounmap;
  3019. }
  3020. /*****************
  3021. * 4. Read EEPROM
  3022. *****************/
  3023. /* Read the EEPROM */
  3024. err = iwl_eeprom_init(priv, hw_rev);
  3025. if (err) {
  3026. IWL_ERR(priv, "Unable to init EEPROM\n");
  3027. goto out_iounmap;
  3028. }
  3029. err = iwl_eeprom_check_version(priv);
  3030. if (err)
  3031. goto out_free_eeprom;
  3032. err = iwl_eeprom_check_sku(priv);
  3033. if (err)
  3034. goto out_free_eeprom;
  3035. /* extract MAC Address */
  3036. iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
  3037. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
  3038. priv->hw->wiphy->addresses = priv->addresses;
  3039. priv->hw->wiphy->n_addresses = 1;
  3040. num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
  3041. if (num_mac > 1) {
  3042. memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
  3043. ETH_ALEN);
  3044. priv->addresses[1].addr[5]++;
  3045. priv->hw->wiphy->n_addresses++;
  3046. }
  3047. /************************
  3048. * 5. Setup HW constants
  3049. ************************/
  3050. if (iwl_set_hw_params(priv)) {
  3051. IWL_ERR(priv, "failed to set hw parameters\n");
  3052. goto out_free_eeprom;
  3053. }
  3054. /*******************
  3055. * 6. Setup priv
  3056. *******************/
  3057. err = iwl_init_drv(priv);
  3058. if (err)
  3059. goto out_free_eeprom;
  3060. /* At this point both hw and priv are initialized. */
  3061. /********************
  3062. * 7. Setup services
  3063. ********************/
  3064. spin_lock_irqsave(&priv->lock, flags);
  3065. iwl_disable_interrupts(priv);
  3066. spin_unlock_irqrestore(&priv->lock, flags);
  3067. pci_enable_msi(priv->pci_dev);
  3068. iwl_alloc_isr_ict(priv);
  3069. err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
  3070. IRQF_SHARED, DRV_NAME, priv);
  3071. if (err) {
  3072. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3073. goto out_disable_msi;
  3074. }
  3075. iwl_setup_deferred_work(priv);
  3076. iwl_setup_rx_handlers(priv);
  3077. iwl_testmode_init(priv);
  3078. /*********************************************
  3079. * 8. Enable interrupts and read RFKILL state
  3080. *********************************************/
  3081. /* enable rfkill interrupt: hw bug w/a */
  3082. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3083. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3084. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3085. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3086. }
  3087. iwl_enable_rfkill_int(priv);
  3088. /* If platform's RF_KILL switch is NOT set to KILL */
  3089. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3090. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3091. else
  3092. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3093. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3094. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3095. iwl_power_initialize(priv);
  3096. iwl_tt_initialize(priv);
  3097. init_completion(&priv->_agn.firmware_loading_complete);
  3098. err = iwl_request_firmware(priv, true);
  3099. if (err)
  3100. goto out_destroy_workqueue;
  3101. return 0;
  3102. out_destroy_workqueue:
  3103. destroy_workqueue(priv->workqueue);
  3104. priv->workqueue = NULL;
  3105. free_irq(priv->pci_dev->irq, priv);
  3106. out_disable_msi:
  3107. iwl_free_isr_ict(priv);
  3108. pci_disable_msi(priv->pci_dev);
  3109. iwl_uninit_drv(priv);
  3110. out_free_eeprom:
  3111. iwl_eeprom_free(priv);
  3112. out_iounmap:
  3113. pci_iounmap(pdev, priv->hw_base);
  3114. out_pci_release_regions:
  3115. pci_set_drvdata(pdev, NULL);
  3116. pci_release_regions(pdev);
  3117. out_pci_disable_device:
  3118. pci_disable_device(pdev);
  3119. out_ieee80211_free_hw:
  3120. iwl_free_traffic_mem(priv);
  3121. ieee80211_free_hw(priv->hw);
  3122. out:
  3123. return err;
  3124. }
  3125. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3126. {
  3127. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3128. unsigned long flags;
  3129. if (!priv)
  3130. return;
  3131. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3132. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3133. iwl_dbgfs_unregister(priv);
  3134. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3135. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3136. * to be called and iwl_down since we are removing the device
  3137. * we need to set STATUS_EXIT_PENDING bit.
  3138. */
  3139. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3140. iwl_testmode_cleanup(priv);
  3141. iwl_leds_exit(priv);
  3142. if (priv->mac80211_registered) {
  3143. ieee80211_unregister_hw(priv->hw);
  3144. priv->mac80211_registered = 0;
  3145. }
  3146. /* Reset to low power before unloading driver. */
  3147. iwl_apm_stop(priv);
  3148. iwl_tt_exit(priv);
  3149. /* make sure we flush any pending irq or
  3150. * tasklet for the driver
  3151. */
  3152. spin_lock_irqsave(&priv->lock, flags);
  3153. iwl_disable_interrupts(priv);
  3154. spin_unlock_irqrestore(&priv->lock, flags);
  3155. iwl_synchronize_irq(priv);
  3156. iwl_dealloc_ucode_pci(priv);
  3157. if (priv->rxq.bd)
  3158. iwlagn_rx_queue_free(priv, &priv->rxq);
  3159. iwlagn_hw_txq_ctx_free(priv);
  3160. iwl_eeprom_free(priv);
  3161. /*netif_stop_queue(dev); */
  3162. flush_workqueue(priv->workqueue);
  3163. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3164. * priv->workqueue... so we can't take down the workqueue
  3165. * until now... */
  3166. destroy_workqueue(priv->workqueue);
  3167. priv->workqueue = NULL;
  3168. iwl_free_traffic_mem(priv);
  3169. free_irq(priv->pci_dev->irq, priv);
  3170. pci_disable_msi(priv->pci_dev);
  3171. pci_iounmap(pdev, priv->hw_base);
  3172. pci_release_regions(pdev);
  3173. pci_disable_device(pdev);
  3174. pci_set_drvdata(pdev, NULL);
  3175. iwl_uninit_drv(priv);
  3176. iwl_free_isr_ict(priv);
  3177. dev_kfree_skb(priv->beacon_skb);
  3178. ieee80211_free_hw(priv->hw);
  3179. }
  3180. /*****************************************************************************
  3181. *
  3182. * driver and module entry point
  3183. *
  3184. *****************************************************************************/
  3185. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3186. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3187. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3188. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3189. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3190. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3191. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3192. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3193. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3194. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3195. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3196. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3197. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3198. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3199. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3200. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3201. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3202. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3203. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3204. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3205. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3206. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3207. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3208. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3209. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3210. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3211. /* 5300 Series WiFi */
  3212. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3213. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3214. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3215. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3216. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3217. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3218. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3219. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3220. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3221. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3222. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3223. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3224. /* 5350 Series WiFi/WiMax */
  3225. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3226. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3227. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3228. /* 5150 Series Wifi/WiMax */
  3229. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3230. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3231. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3232. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3233. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3234. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3235. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3236. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3237. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3238. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3239. /* 6x00 Series */
  3240. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3241. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3242. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3243. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3244. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3245. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3246. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3247. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3248. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3249. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3250. /* 6x05 Series */
  3251. {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
  3252. {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
  3253. {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
  3254. {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
  3255. {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
  3256. {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
  3257. {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
  3258. /* 6x30 Series */
  3259. {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
  3260. {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
  3261. {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
  3262. {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
  3263. {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
  3264. {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
  3265. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
  3266. {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
  3267. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
  3268. {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
  3269. {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
  3270. {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
  3271. {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
  3272. {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
  3273. {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
  3274. {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
  3275. /* 6x50 WiFi/WiMax Series */
  3276. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3277. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3278. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3279. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3280. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3281. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3282. /* 6150 WiFi/WiMax Series */
  3283. {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
  3284. {IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
  3285. {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
  3286. {IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
  3287. {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
  3288. {IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
  3289. /* 1000 Series WiFi */
  3290. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3291. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3292. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3293. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3294. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3295. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3296. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3297. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3298. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3299. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3300. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3301. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3302. /* 100 Series WiFi */
  3303. {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
  3304. {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
  3305. {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
  3306. {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
  3307. {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
  3308. {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
  3309. /* 130 Series WiFi */
  3310. {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
  3311. {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
  3312. {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
  3313. {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
  3314. {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
  3315. {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
  3316. /* 2x00 Series */
  3317. {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
  3318. {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
  3319. {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
  3320. {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
  3321. {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
  3322. {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
  3323. /* 2x30 Series */
  3324. {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
  3325. {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
  3326. {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
  3327. {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
  3328. {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
  3329. {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
  3330. /* 6x35 Series */
  3331. {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
  3332. {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
  3333. {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
  3334. {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
  3335. {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
  3336. {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
  3337. {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
  3338. {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
  3339. {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
  3340. /* 105 Series */
  3341. {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
  3342. {IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
  3343. {IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
  3344. {IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
  3345. {IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
  3346. {IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
  3347. /* 135 Series */
  3348. {IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
  3349. {IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
  3350. {IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
  3351. {IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
  3352. {IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
  3353. {IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
  3354. {0}
  3355. };
  3356. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3357. static struct pci_driver iwl_driver = {
  3358. .name = DRV_NAME,
  3359. .id_table = iwl_hw_card_ids,
  3360. .probe = iwl_pci_probe,
  3361. .remove = __devexit_p(iwl_pci_remove),
  3362. .driver.pm = IWL_PM_OPS,
  3363. };
  3364. static int __init iwl_init(void)
  3365. {
  3366. int ret;
  3367. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3368. pr_info(DRV_COPYRIGHT "\n");
  3369. ret = iwlagn_rate_control_register();
  3370. if (ret) {
  3371. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3372. return ret;
  3373. }
  3374. ret = pci_register_driver(&iwl_driver);
  3375. if (ret) {
  3376. pr_err("Unable to initialize PCI module\n");
  3377. goto error_register;
  3378. }
  3379. return ret;
  3380. error_register:
  3381. iwlagn_rate_control_unregister();
  3382. return ret;
  3383. }
  3384. static void __exit iwl_exit(void)
  3385. {
  3386. pci_unregister_driver(&iwl_driver);
  3387. iwlagn_rate_control_unregister();
  3388. }
  3389. module_exit(iwl_exit);
  3390. module_init(iwl_init);
  3391. #ifdef CONFIG_IWLWIFI_DEBUG
  3392. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3393. MODULE_PARM_DESC(debug, "debug output mask");
  3394. #endif
  3395. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3396. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3397. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3398. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3399. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3400. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3401. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3402. int, S_IRUGO);
  3403. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3404. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3405. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3406. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3407. S_IRUGO);
  3408. MODULE_PARM_DESC(ucode_alternative,
  3409. "specify ucode alternative to use from ucode file");
  3410. module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
  3411. MODULE_PARM_DESC(antenna_coupling,
  3412. "specify antenna coupling in dB (defualt: 0 dB)");
  3413. module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
  3414. MODULE_PARM_DESC(bt_ch_inhibition,
  3415. "Disable BT channel inhibition (default: enable)");
  3416. module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
  3417. MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
  3418. module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
  3419. MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
  3420. /*
  3421. * set bt_coex_active to true, uCode will do kill/defer
  3422. * every time the priority line is asserted (BT is sending signals on the
  3423. * priority line in the PCIx).
  3424. * set bt_coex_active to false, uCode will ignore the BT activity and
  3425. * perform the normal operation
  3426. *
  3427. * User might experience transmit issue on some platform due to WiFi/BT
  3428. * co-exist problem. The possible behaviors are:
  3429. * Able to scan and finding all the available AP
  3430. * Not able to associate with any AP
  3431. * On those platforms, WiFi communication can be restored by set
  3432. * "bt_coex_active" module parameter to "false"
  3433. *
  3434. * default: bt_coex_active = true (BT_COEX_ENABLE)
  3435. */
  3436. module_param_named(bt_coex_active, iwlagn_mod_params.bt_coex_active,
  3437. bool, S_IRUGO);
  3438. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bt co-exist (default: enable)");
  3439. module_param_named(led_mode, iwlagn_mod_params.led_mode, int, S_IRUGO);
  3440. MODULE_PARM_DESC(led_mode, "0=system default, "
  3441. "1=On(RF On)/Off(RF Off), 2=blinking (default: 0)");
  3442. /*
  3443. * For now, keep using power level 1 instead of automatically
  3444. * adjusting ...
  3445. */
  3446. module_param_named(no_sleep_autoadjust, iwlagn_mod_params.no_sleep_autoadjust,
  3447. bool, S_IRUGO);
  3448. MODULE_PARM_DESC(no_sleep_autoadjust,
  3449. "don't automatically adjust sleep level "
  3450. "according to maximum network latency (default: true)");