cryp_core.c 44 KB

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  1. /**
  2. * Copyright (C) ST-Ericsson SA 2010
  3. * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
  4. * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
  5. * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
  6. * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
  7. * Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
  8. * Author: Andreas Westin <andreas.westin@stericsson.com> for ST-Ericsson.
  9. * License terms: GNU General Public License (GPL) version 2
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/completion.h>
  13. #include <linux/crypto.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/err.h>
  16. #include <linux/errno.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/irqreturn.h>
  20. #include <linux/klist.h>
  21. #include <linux/module.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/semaphore.h>
  25. #include <linux/platform_data/dma-ste-dma40.h>
  26. #include <crypto/aes.h>
  27. #include <crypto/algapi.h>
  28. #include <crypto/ctr.h>
  29. #include <crypto/des.h>
  30. #include <crypto/scatterwalk.h>
  31. #include <linux/platform_data/crypto-ux500.h>
  32. #include "cryp_p.h"
  33. #include "cryp.h"
  34. #define CRYP_MAX_KEY_SIZE 32
  35. #define BYTES_PER_WORD 4
  36. static int cryp_mode;
  37. static atomic_t session_id;
  38. static struct stedma40_chan_cfg *mem_to_engine;
  39. static struct stedma40_chan_cfg *engine_to_mem;
  40. /**
  41. * struct cryp_driver_data - data specific to the driver.
  42. *
  43. * @device_list: A list of registered devices to choose from.
  44. * @device_allocation: A semaphore initialized with number of devices.
  45. */
  46. struct cryp_driver_data {
  47. struct klist device_list;
  48. struct semaphore device_allocation;
  49. };
  50. /**
  51. * struct cryp_ctx - Crypto context
  52. * @config: Crypto mode.
  53. * @key[CRYP_MAX_KEY_SIZE]: Key.
  54. * @keylen: Length of key.
  55. * @iv: Pointer to initialization vector.
  56. * @indata: Pointer to indata.
  57. * @outdata: Pointer to outdata.
  58. * @datalen: Length of indata.
  59. * @outlen: Length of outdata.
  60. * @blocksize: Size of blocks.
  61. * @updated: Updated flag.
  62. * @dev_ctx: Device dependent context.
  63. * @device: Pointer to the device.
  64. */
  65. struct cryp_ctx {
  66. struct cryp_config config;
  67. u8 key[CRYP_MAX_KEY_SIZE];
  68. u32 keylen;
  69. u8 *iv;
  70. const u8 *indata;
  71. u8 *outdata;
  72. u32 datalen;
  73. u32 outlen;
  74. u32 blocksize;
  75. u8 updated;
  76. struct cryp_device_context dev_ctx;
  77. struct cryp_device_data *device;
  78. u32 session_id;
  79. };
  80. static struct cryp_driver_data driver_data;
  81. /**
  82. * uint8p_to_uint32_be - 4*uint8 to uint32 big endian
  83. * @in: Data to convert.
  84. */
  85. static inline u32 uint8p_to_uint32_be(u8 *in)
  86. {
  87. u32 *data = (u32 *)in;
  88. return cpu_to_be32p(data);
  89. }
  90. /**
  91. * swap_bits_in_byte - mirror the bits in a byte
  92. * @b: the byte to be mirrored
  93. *
  94. * The bits are swapped the following way:
  95. * Byte b include bits 0-7, nibble 1 (n1) include bits 0-3 and
  96. * nibble 2 (n2) bits 4-7.
  97. *
  98. * Nibble 1 (n1):
  99. * (The "old" (moved) bit is replaced with a zero)
  100. * 1. Move bit 6 and 7, 4 positions to the left.
  101. * 2. Move bit 3 and 5, 2 positions to the left.
  102. * 3. Move bit 1-4, 1 position to the left.
  103. *
  104. * Nibble 2 (n2):
  105. * 1. Move bit 0 and 1, 4 positions to the right.
  106. * 2. Move bit 2 and 4, 2 positions to the right.
  107. * 3. Move bit 3-6, 1 position to the right.
  108. *
  109. * Combine the two nibbles to a complete and swapped byte.
  110. */
  111. static inline u8 swap_bits_in_byte(u8 b)
  112. {
  113. #define R_SHIFT_4_MASK 0xc0 /* Bits 6 and 7, right shift 4 */
  114. #define R_SHIFT_2_MASK 0x28 /* (After right shift 4) Bits 3 and 5,
  115. right shift 2 */
  116. #define R_SHIFT_1_MASK 0x1e /* (After right shift 2) Bits 1-4,
  117. right shift 1 */
  118. #define L_SHIFT_4_MASK 0x03 /* Bits 0 and 1, left shift 4 */
  119. #define L_SHIFT_2_MASK 0x14 /* (After left shift 4) Bits 2 and 4,
  120. left shift 2 */
  121. #define L_SHIFT_1_MASK 0x78 /* (After left shift 1) Bits 3-6,
  122. left shift 1 */
  123. u8 n1;
  124. u8 n2;
  125. /* Swap most significant nibble */
  126. /* Right shift 4, bits 6 and 7 */
  127. n1 = ((b & R_SHIFT_4_MASK) >> 4) | (b & ~(R_SHIFT_4_MASK >> 4));
  128. /* Right shift 2, bits 3 and 5 */
  129. n1 = ((n1 & R_SHIFT_2_MASK) >> 2) | (n1 & ~(R_SHIFT_2_MASK >> 2));
  130. /* Right shift 1, bits 1-4 */
  131. n1 = (n1 & R_SHIFT_1_MASK) >> 1;
  132. /* Swap least significant nibble */
  133. /* Left shift 4, bits 0 and 1 */
  134. n2 = ((b & L_SHIFT_4_MASK) << 4) | (b & ~(L_SHIFT_4_MASK << 4));
  135. /* Left shift 2, bits 2 and 4 */
  136. n2 = ((n2 & L_SHIFT_2_MASK) << 2) | (n2 & ~(L_SHIFT_2_MASK << 2));
  137. /* Left shift 1, bits 3-6 */
  138. n2 = (n2 & L_SHIFT_1_MASK) << 1;
  139. return n1 | n2;
  140. }
  141. static inline void swap_words_in_key_and_bits_in_byte(const u8 *in,
  142. u8 *out, u32 len)
  143. {
  144. unsigned int i = 0;
  145. int j;
  146. int index = 0;
  147. j = len - BYTES_PER_WORD;
  148. while (j >= 0) {
  149. for (i = 0; i < BYTES_PER_WORD; i++) {
  150. index = len - j - BYTES_PER_WORD + i;
  151. out[j + i] =
  152. swap_bits_in_byte(in[index]);
  153. }
  154. j -= BYTES_PER_WORD;
  155. }
  156. }
  157. static void add_session_id(struct cryp_ctx *ctx)
  158. {
  159. /*
  160. * We never want 0 to be a valid value, since this is the default value
  161. * for the software context.
  162. */
  163. if (unlikely(atomic_inc_and_test(&session_id)))
  164. atomic_inc(&session_id);
  165. ctx->session_id = atomic_read(&session_id);
  166. }
  167. static irqreturn_t cryp_interrupt_handler(int irq, void *param)
  168. {
  169. struct cryp_ctx *ctx;
  170. int i;
  171. struct cryp_device_data *device_data;
  172. if (param == NULL) {
  173. BUG_ON(!param);
  174. return IRQ_HANDLED;
  175. }
  176. /* The device is coming from the one found in hw_crypt_noxts. */
  177. device_data = (struct cryp_device_data *)param;
  178. ctx = device_data->current_ctx;
  179. if (ctx == NULL) {
  180. BUG_ON(!ctx);
  181. return IRQ_HANDLED;
  182. }
  183. dev_dbg(ctx->device->dev, "[%s] (len: %d) %s, ", __func__, ctx->outlen,
  184. cryp_pending_irq_src(device_data, CRYP_IRQ_SRC_OUTPUT_FIFO) ?
  185. "out" : "in");
  186. if (cryp_pending_irq_src(device_data,
  187. CRYP_IRQ_SRC_OUTPUT_FIFO)) {
  188. if (ctx->outlen / ctx->blocksize > 0) {
  189. for (i = 0; i < ctx->blocksize / 4; i++) {
  190. *(ctx->outdata) = readl_relaxed(
  191. &device_data->base->dout);
  192. ctx->outdata += 4;
  193. ctx->outlen -= 4;
  194. }
  195. if (ctx->outlen == 0) {
  196. cryp_disable_irq_src(device_data,
  197. CRYP_IRQ_SRC_OUTPUT_FIFO);
  198. }
  199. }
  200. } else if (cryp_pending_irq_src(device_data,
  201. CRYP_IRQ_SRC_INPUT_FIFO)) {
  202. if (ctx->datalen / ctx->blocksize > 0) {
  203. for (i = 0 ; i < ctx->blocksize / 4; i++) {
  204. writel_relaxed(ctx->indata,
  205. &device_data->base->din);
  206. ctx->indata += 4;
  207. ctx->datalen -= 4;
  208. }
  209. if (ctx->datalen == 0)
  210. cryp_disable_irq_src(device_data,
  211. CRYP_IRQ_SRC_INPUT_FIFO);
  212. if (ctx->config.algomode == CRYP_ALGO_AES_XTS) {
  213. CRYP_PUT_BITS(&device_data->base->cr,
  214. CRYP_START_ENABLE,
  215. CRYP_CR_START_POS,
  216. CRYP_CR_START_MASK);
  217. cryp_wait_until_done(device_data);
  218. }
  219. }
  220. }
  221. return IRQ_HANDLED;
  222. }
  223. static int mode_is_aes(enum cryp_algo_mode mode)
  224. {
  225. return CRYP_ALGO_AES_ECB == mode ||
  226. CRYP_ALGO_AES_CBC == mode ||
  227. CRYP_ALGO_AES_CTR == mode ||
  228. CRYP_ALGO_AES_XTS == mode;
  229. }
  230. static int cfg_iv(struct cryp_device_data *device_data, u32 left, u32 right,
  231. enum cryp_init_vector_index index)
  232. {
  233. struct cryp_init_vector_value vector_value;
  234. dev_dbg(device_data->dev, "[%s]", __func__);
  235. vector_value.init_value_left = left;
  236. vector_value.init_value_right = right;
  237. return cryp_configure_init_vector(device_data,
  238. index,
  239. vector_value);
  240. }
  241. static int cfg_ivs(struct cryp_device_data *device_data, struct cryp_ctx *ctx)
  242. {
  243. int i;
  244. int status = 0;
  245. int num_of_regs = ctx->blocksize / 8;
  246. u32 iv[AES_BLOCK_SIZE / 4];
  247. dev_dbg(device_data->dev, "[%s]", __func__);
  248. /*
  249. * Since we loop on num_of_regs we need to have a check in case
  250. * someone provides an incorrect blocksize which would force calling
  251. * cfg_iv with i greater than 2 which is an error.
  252. */
  253. if (num_of_regs > 2) {
  254. dev_err(device_data->dev, "[%s] Incorrect blocksize %d",
  255. __func__, ctx->blocksize);
  256. return -EINVAL;
  257. }
  258. for (i = 0; i < ctx->blocksize / 4; i++)
  259. iv[i] = uint8p_to_uint32_be(ctx->iv + i*4);
  260. for (i = 0; i < num_of_regs; i++) {
  261. status = cfg_iv(device_data, iv[i*2], iv[i*2+1],
  262. (enum cryp_init_vector_index) i);
  263. if (status != 0)
  264. return status;
  265. }
  266. return status;
  267. }
  268. static int set_key(struct cryp_device_data *device_data,
  269. u32 left_key,
  270. u32 right_key,
  271. enum cryp_key_reg_index index)
  272. {
  273. struct cryp_key_value key_value;
  274. int cryp_error;
  275. dev_dbg(device_data->dev, "[%s]", __func__);
  276. key_value.key_value_left = left_key;
  277. key_value.key_value_right = right_key;
  278. cryp_error = cryp_configure_key_values(device_data,
  279. index,
  280. key_value);
  281. if (cryp_error != 0)
  282. dev_err(device_data->dev, "[%s]: "
  283. "cryp_configure_key_values() failed!", __func__);
  284. return cryp_error;
  285. }
  286. static int cfg_keys(struct cryp_ctx *ctx)
  287. {
  288. int i;
  289. int num_of_regs = ctx->keylen / 8;
  290. u32 swapped_key[CRYP_MAX_KEY_SIZE / 4];
  291. int cryp_error = 0;
  292. dev_dbg(ctx->device->dev, "[%s]", __func__);
  293. if (mode_is_aes(ctx->config.algomode)) {
  294. swap_words_in_key_and_bits_in_byte((u8 *)ctx->key,
  295. (u8 *)swapped_key,
  296. ctx->keylen);
  297. } else {
  298. for (i = 0; i < ctx->keylen / 4; i++)
  299. swapped_key[i] = uint8p_to_uint32_be(ctx->key + i*4);
  300. }
  301. for (i = 0; i < num_of_regs; i++) {
  302. cryp_error = set_key(ctx->device,
  303. *(((u32 *)swapped_key)+i*2),
  304. *(((u32 *)swapped_key)+i*2+1),
  305. (enum cryp_key_reg_index) i);
  306. if (cryp_error != 0) {
  307. dev_err(ctx->device->dev, "[%s]: set_key() failed!",
  308. __func__);
  309. return cryp_error;
  310. }
  311. }
  312. return cryp_error;
  313. }
  314. static int cryp_setup_context(struct cryp_ctx *ctx,
  315. struct cryp_device_data *device_data)
  316. {
  317. u32 control_register = CRYP_CR_DEFAULT;
  318. switch (cryp_mode) {
  319. case CRYP_MODE_INTERRUPT:
  320. writel_relaxed(CRYP_IMSC_DEFAULT, &device_data->base->imsc);
  321. break;
  322. case CRYP_MODE_DMA:
  323. writel_relaxed(CRYP_DMACR_DEFAULT, &device_data->base->dmacr);
  324. break;
  325. default:
  326. break;
  327. }
  328. if (ctx->updated == 0) {
  329. cryp_flush_inoutfifo(device_data);
  330. if (cfg_keys(ctx) != 0) {
  331. dev_err(ctx->device->dev, "[%s]: cfg_keys failed!",
  332. __func__);
  333. return -EINVAL;
  334. }
  335. if (ctx->iv &&
  336. CRYP_ALGO_AES_ECB != ctx->config.algomode &&
  337. CRYP_ALGO_DES_ECB != ctx->config.algomode &&
  338. CRYP_ALGO_TDES_ECB != ctx->config.algomode) {
  339. if (cfg_ivs(device_data, ctx) != 0)
  340. return -EPERM;
  341. }
  342. cryp_set_configuration(device_data, &ctx->config,
  343. &control_register);
  344. add_session_id(ctx);
  345. } else if (ctx->updated == 1 &&
  346. ctx->session_id != atomic_read(&session_id)) {
  347. cryp_flush_inoutfifo(device_data);
  348. cryp_restore_device_context(device_data, &ctx->dev_ctx);
  349. add_session_id(ctx);
  350. control_register = ctx->dev_ctx.cr;
  351. } else
  352. control_register = ctx->dev_ctx.cr;
  353. writel(control_register |
  354. (CRYP_CRYPEN_ENABLE << CRYP_CR_CRYPEN_POS),
  355. &device_data->base->cr);
  356. return 0;
  357. }
  358. static int cryp_get_device_data(struct cryp_ctx *ctx,
  359. struct cryp_device_data **device_data)
  360. {
  361. int ret;
  362. struct klist_iter device_iterator;
  363. struct klist_node *device_node;
  364. struct cryp_device_data *local_device_data = NULL;
  365. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  366. /* Wait until a device is available */
  367. ret = down_interruptible(&driver_data.device_allocation);
  368. if (ret)
  369. return ret; /* Interrupted */
  370. /* Select a device */
  371. klist_iter_init(&driver_data.device_list, &device_iterator);
  372. device_node = klist_next(&device_iterator);
  373. while (device_node) {
  374. local_device_data = container_of(device_node,
  375. struct cryp_device_data, list_node);
  376. spin_lock(&local_device_data->ctx_lock);
  377. /* current_ctx allocates a device, NULL = unallocated */
  378. if (local_device_data->current_ctx) {
  379. device_node = klist_next(&device_iterator);
  380. } else {
  381. local_device_data->current_ctx = ctx;
  382. ctx->device = local_device_data;
  383. spin_unlock(&local_device_data->ctx_lock);
  384. break;
  385. }
  386. spin_unlock(&local_device_data->ctx_lock);
  387. }
  388. klist_iter_exit(&device_iterator);
  389. if (!device_node) {
  390. /**
  391. * No free device found.
  392. * Since we allocated a device with down_interruptible, this
  393. * should not be able to happen.
  394. * Number of available devices, which are contained in
  395. * device_allocation, is therefore decremented by not doing
  396. * an up(device_allocation).
  397. */
  398. return -EBUSY;
  399. }
  400. *device_data = local_device_data;
  401. return 0;
  402. }
  403. static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
  404. struct device *dev)
  405. {
  406. dma_cap_zero(device_data->dma.mask);
  407. dma_cap_set(DMA_SLAVE, device_data->dma.mask);
  408. device_data->dma.cfg_mem2cryp = mem_to_engine;
  409. device_data->dma.chan_mem2cryp =
  410. dma_request_channel(device_data->dma.mask,
  411. stedma40_filter,
  412. device_data->dma.cfg_mem2cryp);
  413. device_data->dma.cfg_cryp2mem = engine_to_mem;
  414. device_data->dma.chan_cryp2mem =
  415. dma_request_channel(device_data->dma.mask,
  416. stedma40_filter,
  417. device_data->dma.cfg_cryp2mem);
  418. init_completion(&device_data->dma.cryp_dma_complete);
  419. }
  420. static void cryp_dma_out_callback(void *data)
  421. {
  422. struct cryp_ctx *ctx = (struct cryp_ctx *) data;
  423. dev_dbg(ctx->device->dev, "[%s]: ", __func__);
  424. complete(&ctx->device->dma.cryp_dma_complete);
  425. }
  426. static int cryp_set_dma_transfer(struct cryp_ctx *ctx,
  427. struct scatterlist *sg,
  428. int len,
  429. enum dma_data_direction direction)
  430. {
  431. struct dma_async_tx_descriptor *desc;
  432. struct dma_chan *channel = NULL;
  433. dma_cookie_t cookie;
  434. dev_dbg(ctx->device->dev, "[%s]: ", __func__);
  435. if (unlikely(!IS_ALIGNED((u32)sg, 4))) {
  436. dev_err(ctx->device->dev, "[%s]: Data in sg list isn't "
  437. "aligned! Addr: 0x%08x", __func__, (u32)sg);
  438. return -EFAULT;
  439. }
  440. switch (direction) {
  441. case DMA_TO_DEVICE:
  442. channel = ctx->device->dma.chan_mem2cryp;
  443. ctx->device->dma.sg_src = sg;
  444. ctx->device->dma.sg_src_len = dma_map_sg(channel->device->dev,
  445. ctx->device->dma.sg_src,
  446. ctx->device->dma.nents_src,
  447. direction);
  448. if (!ctx->device->dma.sg_src_len) {
  449. dev_dbg(ctx->device->dev,
  450. "[%s]: Could not map the sg list (TO_DEVICE)",
  451. __func__);
  452. return -EFAULT;
  453. }
  454. dev_dbg(ctx->device->dev, "[%s]: Setting up DMA for buffer "
  455. "(TO_DEVICE)", __func__);
  456. desc = channel->device->device_prep_slave_sg(channel,
  457. ctx->device->dma.sg_src,
  458. ctx->device->dma.sg_src_len,
  459. direction, DMA_CTRL_ACK, NULL);
  460. break;
  461. case DMA_FROM_DEVICE:
  462. channel = ctx->device->dma.chan_cryp2mem;
  463. ctx->device->dma.sg_dst = sg;
  464. ctx->device->dma.sg_dst_len = dma_map_sg(channel->device->dev,
  465. ctx->device->dma.sg_dst,
  466. ctx->device->dma.nents_dst,
  467. direction);
  468. if (!ctx->device->dma.sg_dst_len) {
  469. dev_dbg(ctx->device->dev,
  470. "[%s]: Could not map the sg list (FROM_DEVICE)",
  471. __func__);
  472. return -EFAULT;
  473. }
  474. dev_dbg(ctx->device->dev, "[%s]: Setting up DMA for buffer "
  475. "(FROM_DEVICE)", __func__);
  476. desc = channel->device->device_prep_slave_sg(channel,
  477. ctx->device->dma.sg_dst,
  478. ctx->device->dma.sg_dst_len,
  479. direction,
  480. DMA_CTRL_ACK |
  481. DMA_PREP_INTERRUPT, NULL);
  482. desc->callback = cryp_dma_out_callback;
  483. desc->callback_param = ctx;
  484. break;
  485. default:
  486. dev_dbg(ctx->device->dev, "[%s]: Invalid DMA direction",
  487. __func__);
  488. return -EFAULT;
  489. }
  490. cookie = desc->tx_submit(desc);
  491. dma_async_issue_pending(channel);
  492. return 0;
  493. }
  494. static void cryp_dma_done(struct cryp_ctx *ctx)
  495. {
  496. struct dma_chan *chan;
  497. dev_dbg(ctx->device->dev, "[%s]: ", __func__);
  498. chan = ctx->device->dma.chan_mem2cryp;
  499. chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
  500. dma_unmap_sg(chan->device->dev, ctx->device->dma.sg_src,
  501. ctx->device->dma.sg_src_len, DMA_TO_DEVICE);
  502. chan = ctx->device->dma.chan_cryp2mem;
  503. chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
  504. dma_unmap_sg(chan->device->dev, ctx->device->dma.sg_dst,
  505. ctx->device->dma.sg_dst_len, DMA_FROM_DEVICE);
  506. }
  507. static int cryp_dma_write(struct cryp_ctx *ctx, struct scatterlist *sg,
  508. int len)
  509. {
  510. int error = cryp_set_dma_transfer(ctx, sg, len, DMA_TO_DEVICE);
  511. dev_dbg(ctx->device->dev, "[%s]: ", __func__);
  512. if (error) {
  513. dev_dbg(ctx->device->dev, "[%s]: cryp_set_dma_transfer() "
  514. "failed", __func__);
  515. return error;
  516. }
  517. return len;
  518. }
  519. static int cryp_dma_read(struct cryp_ctx *ctx, struct scatterlist *sg, int len)
  520. {
  521. int error = cryp_set_dma_transfer(ctx, sg, len, DMA_FROM_DEVICE);
  522. if (error) {
  523. dev_dbg(ctx->device->dev, "[%s]: cryp_set_dma_transfer() "
  524. "failed", __func__);
  525. return error;
  526. }
  527. return len;
  528. }
  529. static void cryp_polling_mode(struct cryp_ctx *ctx,
  530. struct cryp_device_data *device_data)
  531. {
  532. int len = ctx->blocksize / BYTES_PER_WORD;
  533. int remaining_length = ctx->datalen;
  534. u32 *indata = (u32 *)ctx->indata;
  535. u32 *outdata = (u32 *)ctx->outdata;
  536. while (remaining_length > 0) {
  537. writesl(&device_data->base->din, indata, len);
  538. indata += len;
  539. remaining_length -= (len * BYTES_PER_WORD);
  540. cryp_wait_until_done(device_data);
  541. readsl(&device_data->base->dout, outdata, len);
  542. outdata += len;
  543. cryp_wait_until_done(device_data);
  544. }
  545. }
  546. static int cryp_disable_power(struct device *dev,
  547. struct cryp_device_data *device_data,
  548. bool save_device_context)
  549. {
  550. int ret = 0;
  551. dev_dbg(dev, "[%s]", __func__);
  552. spin_lock(&device_data->power_state_spinlock);
  553. if (!device_data->power_state)
  554. goto out;
  555. spin_lock(&device_data->ctx_lock);
  556. if (save_device_context && device_data->current_ctx) {
  557. cryp_save_device_context(device_data,
  558. &device_data->current_ctx->dev_ctx,
  559. cryp_mode);
  560. device_data->restore_dev_ctx = true;
  561. }
  562. spin_unlock(&device_data->ctx_lock);
  563. clk_disable(device_data->clk);
  564. ret = regulator_disable(device_data->pwr_regulator);
  565. if (ret)
  566. dev_err(dev, "[%s]: "
  567. "regulator_disable() failed!",
  568. __func__);
  569. device_data->power_state = false;
  570. out:
  571. spin_unlock(&device_data->power_state_spinlock);
  572. return ret;
  573. }
  574. static int cryp_enable_power(
  575. struct device *dev,
  576. struct cryp_device_data *device_data,
  577. bool restore_device_context)
  578. {
  579. int ret = 0;
  580. dev_dbg(dev, "[%s]", __func__);
  581. spin_lock(&device_data->power_state_spinlock);
  582. if (!device_data->power_state) {
  583. ret = regulator_enable(device_data->pwr_regulator);
  584. if (ret) {
  585. dev_err(dev, "[%s]: regulator_enable() failed!",
  586. __func__);
  587. goto out;
  588. }
  589. ret = clk_enable(device_data->clk);
  590. if (ret) {
  591. dev_err(dev, "[%s]: clk_enable() failed!",
  592. __func__);
  593. regulator_disable(device_data->pwr_regulator);
  594. goto out;
  595. }
  596. device_data->power_state = true;
  597. }
  598. if (device_data->restore_dev_ctx) {
  599. spin_lock(&device_data->ctx_lock);
  600. if (restore_device_context && device_data->current_ctx) {
  601. device_data->restore_dev_ctx = false;
  602. cryp_restore_device_context(device_data,
  603. &device_data->current_ctx->dev_ctx);
  604. }
  605. spin_unlock(&device_data->ctx_lock);
  606. }
  607. out:
  608. spin_unlock(&device_data->power_state_spinlock);
  609. return ret;
  610. }
  611. static int hw_crypt_noxts(struct cryp_ctx *ctx,
  612. struct cryp_device_data *device_data)
  613. {
  614. int ret = 0;
  615. const u8 *indata = ctx->indata;
  616. u8 *outdata = ctx->outdata;
  617. u32 datalen = ctx->datalen;
  618. u32 outlen = datalen;
  619. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  620. ctx->outlen = ctx->datalen;
  621. if (unlikely(!IS_ALIGNED((u32)indata, 4))) {
  622. pr_debug(DEV_DBG_NAME " [%s]: Data isn't aligned! Addr: "
  623. "0x%08x", __func__, (u32)indata);
  624. return -EINVAL;
  625. }
  626. ret = cryp_setup_context(ctx, device_data);
  627. if (ret)
  628. goto out;
  629. if (cryp_mode == CRYP_MODE_INTERRUPT) {
  630. cryp_enable_irq_src(device_data, CRYP_IRQ_SRC_INPUT_FIFO |
  631. CRYP_IRQ_SRC_OUTPUT_FIFO);
  632. /*
  633. * ctx->outlen is decremented in the cryp_interrupt_handler
  634. * function. We had to add cpu_relax() (barrier) to make sure
  635. * that gcc didn't optimze away this variable.
  636. */
  637. while (ctx->outlen > 0)
  638. cpu_relax();
  639. } else if (cryp_mode == CRYP_MODE_POLLING ||
  640. cryp_mode == CRYP_MODE_DMA) {
  641. /*
  642. * The reason for having DMA in this if case is that if we are
  643. * running cryp_mode = 2, then we separate DMA routines for
  644. * handling cipher/plaintext > blocksize, except when
  645. * running the normal CRYPTO_ALG_TYPE_CIPHER, then we still use
  646. * the polling mode. Overhead of doing DMA setup eats up the
  647. * benefits using it.
  648. */
  649. cryp_polling_mode(ctx, device_data);
  650. } else {
  651. dev_err(ctx->device->dev, "[%s]: Invalid operation mode!",
  652. __func__);
  653. ret = -EPERM;
  654. goto out;
  655. }
  656. cryp_save_device_context(device_data, &ctx->dev_ctx, cryp_mode);
  657. ctx->updated = 1;
  658. out:
  659. ctx->indata = indata;
  660. ctx->outdata = outdata;
  661. ctx->datalen = datalen;
  662. ctx->outlen = outlen;
  663. return ret;
  664. }
  665. static int get_nents(struct scatterlist *sg, int nbytes)
  666. {
  667. int nents = 0;
  668. while (nbytes > 0) {
  669. nbytes -= sg->length;
  670. sg = scatterwalk_sg_next(sg);
  671. nents++;
  672. }
  673. return nents;
  674. }
  675. static int ablk_dma_crypt(struct ablkcipher_request *areq)
  676. {
  677. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  678. struct cryp_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  679. struct cryp_device_data *device_data;
  680. int bytes_written = 0;
  681. int bytes_read = 0;
  682. int ret;
  683. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  684. ctx->datalen = areq->nbytes;
  685. ctx->outlen = areq->nbytes;
  686. ret = cryp_get_device_data(ctx, &device_data);
  687. if (ret)
  688. return ret;
  689. ret = cryp_setup_context(ctx, device_data);
  690. if (ret)
  691. goto out;
  692. /* We have the device now, so store the nents in the dma struct. */
  693. ctx->device->dma.nents_src = get_nents(areq->src, ctx->datalen);
  694. ctx->device->dma.nents_dst = get_nents(areq->dst, ctx->outlen);
  695. /* Enable DMA in- and output. */
  696. cryp_configure_for_dma(device_data, CRYP_DMA_ENABLE_BOTH_DIRECTIONS);
  697. bytes_written = cryp_dma_write(ctx, areq->src, ctx->datalen);
  698. bytes_read = cryp_dma_read(ctx, areq->dst, bytes_written);
  699. wait_for_completion(&ctx->device->dma.cryp_dma_complete);
  700. cryp_dma_done(ctx);
  701. cryp_save_device_context(device_data, &ctx->dev_ctx, cryp_mode);
  702. ctx->updated = 1;
  703. out:
  704. spin_lock(&device_data->ctx_lock);
  705. device_data->current_ctx = NULL;
  706. ctx->device = NULL;
  707. spin_unlock(&device_data->ctx_lock);
  708. /*
  709. * The down_interruptible part for this semaphore is called in
  710. * cryp_get_device_data.
  711. */
  712. up(&driver_data.device_allocation);
  713. if (unlikely(bytes_written != bytes_read))
  714. return -EPERM;
  715. return 0;
  716. }
  717. static int ablk_crypt(struct ablkcipher_request *areq)
  718. {
  719. struct ablkcipher_walk walk;
  720. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  721. struct cryp_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  722. struct cryp_device_data *device_data;
  723. unsigned long src_paddr;
  724. unsigned long dst_paddr;
  725. int ret;
  726. int nbytes;
  727. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  728. ret = cryp_get_device_data(ctx, &device_data);
  729. if (ret)
  730. goto out;
  731. ablkcipher_walk_init(&walk, areq->dst, areq->src, areq->nbytes);
  732. ret = ablkcipher_walk_phys(areq, &walk);
  733. if (ret) {
  734. pr_err(DEV_DBG_NAME "[%s]: ablkcipher_walk_phys() failed!",
  735. __func__);
  736. goto out;
  737. }
  738. while ((nbytes = walk.nbytes) > 0) {
  739. ctx->iv = walk.iv;
  740. src_paddr = (page_to_phys(walk.src.page) + walk.src.offset);
  741. ctx->indata = phys_to_virt(src_paddr);
  742. dst_paddr = (page_to_phys(walk.dst.page) + walk.dst.offset);
  743. ctx->outdata = phys_to_virt(dst_paddr);
  744. ctx->datalen = nbytes - (nbytes % ctx->blocksize);
  745. ret = hw_crypt_noxts(ctx, device_data);
  746. if (ret)
  747. goto out;
  748. nbytes -= ctx->datalen;
  749. ret = ablkcipher_walk_done(areq, &walk, nbytes);
  750. if (ret)
  751. goto out;
  752. }
  753. ablkcipher_walk_complete(&walk);
  754. out:
  755. /* Release the device */
  756. spin_lock(&device_data->ctx_lock);
  757. device_data->current_ctx = NULL;
  758. ctx->device = NULL;
  759. spin_unlock(&device_data->ctx_lock);
  760. /*
  761. * The down_interruptible part for this semaphore is called in
  762. * cryp_get_device_data.
  763. */
  764. up(&driver_data.device_allocation);
  765. return ret;
  766. }
  767. static int aes_ablkcipher_setkey(struct crypto_ablkcipher *cipher,
  768. const u8 *key, unsigned int keylen)
  769. {
  770. struct cryp_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  771. u32 *flags = &cipher->base.crt_flags;
  772. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  773. switch (keylen) {
  774. case AES_KEYSIZE_128:
  775. ctx->config.keysize = CRYP_KEY_SIZE_128;
  776. break;
  777. case AES_KEYSIZE_192:
  778. ctx->config.keysize = CRYP_KEY_SIZE_192;
  779. break;
  780. case AES_KEYSIZE_256:
  781. ctx->config.keysize = CRYP_KEY_SIZE_256;
  782. break;
  783. default:
  784. pr_err(DEV_DBG_NAME "[%s]: Unknown keylen!", __func__);
  785. *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
  786. return -EINVAL;
  787. }
  788. memcpy(ctx->key, key, keylen);
  789. ctx->keylen = keylen;
  790. ctx->updated = 0;
  791. return 0;
  792. }
  793. static int des_ablkcipher_setkey(struct crypto_ablkcipher *cipher,
  794. const u8 *key, unsigned int keylen)
  795. {
  796. struct cryp_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  797. u32 *flags = &cipher->base.crt_flags;
  798. u32 tmp[DES_EXPKEY_WORDS];
  799. int ret;
  800. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  801. if (keylen != DES_KEY_SIZE) {
  802. *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
  803. pr_debug(DEV_DBG_NAME " [%s]: CRYPTO_TFM_RES_BAD_KEY_LEN",
  804. __func__);
  805. return -EINVAL;
  806. }
  807. ret = des_ekey(tmp, key);
  808. if (unlikely(ret == 0) && (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
  809. *flags |= CRYPTO_TFM_RES_WEAK_KEY;
  810. pr_debug(DEV_DBG_NAME " [%s]: CRYPTO_TFM_REQ_WEAK_KEY",
  811. __func__);
  812. return -EINVAL;
  813. }
  814. memcpy(ctx->key, key, keylen);
  815. ctx->keylen = keylen;
  816. ctx->updated = 0;
  817. return 0;
  818. }
  819. static int des3_ablkcipher_setkey(struct crypto_ablkcipher *cipher,
  820. const u8 *key, unsigned int keylen)
  821. {
  822. struct cryp_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  823. u32 *flags = &cipher->base.crt_flags;
  824. const u32 *K = (const u32 *)key;
  825. u32 tmp[DES3_EDE_EXPKEY_WORDS];
  826. int i, ret;
  827. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  828. if (keylen != DES3_EDE_KEY_SIZE) {
  829. *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
  830. pr_debug(DEV_DBG_NAME " [%s]: CRYPTO_TFM_RES_BAD_KEY_LEN",
  831. __func__);
  832. return -EINVAL;
  833. }
  834. /* Checking key interdependency for weak key detection. */
  835. if (unlikely(!((K[0] ^ K[2]) | (K[1] ^ K[3])) ||
  836. !((K[2] ^ K[4]) | (K[3] ^ K[5]))) &&
  837. (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
  838. *flags |= CRYPTO_TFM_RES_WEAK_KEY;
  839. pr_debug(DEV_DBG_NAME " [%s]: CRYPTO_TFM_REQ_WEAK_KEY",
  840. __func__);
  841. return -EINVAL;
  842. }
  843. for (i = 0; i < 3; i++) {
  844. ret = des_ekey(tmp, key + i*DES_KEY_SIZE);
  845. if (unlikely(ret == 0) && (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
  846. *flags |= CRYPTO_TFM_RES_WEAK_KEY;
  847. pr_debug(DEV_DBG_NAME " [%s]: "
  848. "CRYPTO_TFM_REQ_WEAK_KEY", __func__);
  849. return -EINVAL;
  850. }
  851. }
  852. memcpy(ctx->key, key, keylen);
  853. ctx->keylen = keylen;
  854. ctx->updated = 0;
  855. return 0;
  856. }
  857. static int cryp_blk_encrypt(struct ablkcipher_request *areq)
  858. {
  859. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  860. struct cryp_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  861. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  862. ctx->config.algodir = CRYP_ALGORITHM_ENCRYPT;
  863. /*
  864. * DMA does not work for DES due to a hw bug */
  865. if (cryp_mode == CRYP_MODE_DMA && mode_is_aes(ctx->config.algomode))
  866. return ablk_dma_crypt(areq);
  867. /* For everything except DMA, we run the non DMA version. */
  868. return ablk_crypt(areq);
  869. }
  870. static int cryp_blk_decrypt(struct ablkcipher_request *areq)
  871. {
  872. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  873. struct cryp_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  874. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  875. ctx->config.algodir = CRYP_ALGORITHM_DECRYPT;
  876. /* DMA does not work for DES due to a hw bug */
  877. if (cryp_mode == CRYP_MODE_DMA && mode_is_aes(ctx->config.algomode))
  878. return ablk_dma_crypt(areq);
  879. /* For everything except DMA, we run the non DMA version. */
  880. return ablk_crypt(areq);
  881. }
  882. struct cryp_algo_template {
  883. enum cryp_algo_mode algomode;
  884. struct crypto_alg crypto;
  885. };
  886. static int cryp_cra_init(struct crypto_tfm *tfm)
  887. {
  888. struct cryp_ctx *ctx = crypto_tfm_ctx(tfm);
  889. struct crypto_alg *alg = tfm->__crt_alg;
  890. struct cryp_algo_template *cryp_alg = container_of(alg,
  891. struct cryp_algo_template,
  892. crypto);
  893. ctx->config.algomode = cryp_alg->algomode;
  894. ctx->blocksize = crypto_tfm_alg_blocksize(tfm);
  895. return 0;
  896. }
  897. static struct cryp_algo_template cryp_algs[] = {
  898. {
  899. .algomode = CRYP_ALGO_AES_ECB,
  900. .crypto = {
  901. .cra_name = "aes",
  902. .cra_driver_name = "aes-ux500",
  903. .cra_priority = 300,
  904. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  905. CRYPTO_ALG_ASYNC,
  906. .cra_blocksize = AES_BLOCK_SIZE,
  907. .cra_ctxsize = sizeof(struct cryp_ctx),
  908. .cra_alignmask = 3,
  909. .cra_type = &crypto_ablkcipher_type,
  910. .cra_init = cryp_cra_init,
  911. .cra_module = THIS_MODULE,
  912. .cra_u = {
  913. .ablkcipher = {
  914. .min_keysize = AES_MIN_KEY_SIZE,
  915. .max_keysize = AES_MAX_KEY_SIZE,
  916. .setkey = aes_ablkcipher_setkey,
  917. .encrypt = cryp_blk_encrypt,
  918. .decrypt = cryp_blk_decrypt
  919. }
  920. }
  921. }
  922. },
  923. {
  924. .algomode = CRYP_ALGO_AES_ECB,
  925. .crypto = {
  926. .cra_name = "ecb(aes)",
  927. .cra_driver_name = "ecb-aes-ux500",
  928. .cra_priority = 300,
  929. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  930. CRYPTO_ALG_ASYNC,
  931. .cra_blocksize = AES_BLOCK_SIZE,
  932. .cra_ctxsize = sizeof(struct cryp_ctx),
  933. .cra_alignmask = 3,
  934. .cra_type = &crypto_ablkcipher_type,
  935. .cra_init = cryp_cra_init,
  936. .cra_module = THIS_MODULE,
  937. .cra_u = {
  938. .ablkcipher = {
  939. .min_keysize = AES_MIN_KEY_SIZE,
  940. .max_keysize = AES_MAX_KEY_SIZE,
  941. .setkey = aes_ablkcipher_setkey,
  942. .encrypt = cryp_blk_encrypt,
  943. .decrypt = cryp_blk_decrypt,
  944. }
  945. }
  946. }
  947. },
  948. {
  949. .algomode = CRYP_ALGO_AES_CBC,
  950. .crypto = {
  951. .cra_name = "cbc(aes)",
  952. .cra_driver_name = "cbc-aes-ux500",
  953. .cra_priority = 300,
  954. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  955. CRYPTO_ALG_ASYNC,
  956. .cra_blocksize = AES_BLOCK_SIZE,
  957. .cra_ctxsize = sizeof(struct cryp_ctx),
  958. .cra_alignmask = 3,
  959. .cra_type = &crypto_ablkcipher_type,
  960. .cra_init = cryp_cra_init,
  961. .cra_module = THIS_MODULE,
  962. .cra_u = {
  963. .ablkcipher = {
  964. .min_keysize = AES_MIN_KEY_SIZE,
  965. .max_keysize = AES_MAX_KEY_SIZE,
  966. .setkey = aes_ablkcipher_setkey,
  967. .encrypt = cryp_blk_encrypt,
  968. .decrypt = cryp_blk_decrypt,
  969. .ivsize = AES_BLOCK_SIZE,
  970. }
  971. }
  972. }
  973. },
  974. {
  975. .algomode = CRYP_ALGO_AES_CTR,
  976. .crypto = {
  977. .cra_name = "ctr(aes)",
  978. .cra_driver_name = "ctr-aes-ux500",
  979. .cra_priority = 300,
  980. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  981. CRYPTO_ALG_ASYNC,
  982. .cra_blocksize = AES_BLOCK_SIZE,
  983. .cra_ctxsize = sizeof(struct cryp_ctx),
  984. .cra_alignmask = 3,
  985. .cra_type = &crypto_ablkcipher_type,
  986. .cra_init = cryp_cra_init,
  987. .cra_module = THIS_MODULE,
  988. .cra_u = {
  989. .ablkcipher = {
  990. .min_keysize = AES_MIN_KEY_SIZE,
  991. .max_keysize = AES_MAX_KEY_SIZE,
  992. .setkey = aes_ablkcipher_setkey,
  993. .encrypt = cryp_blk_encrypt,
  994. .decrypt = cryp_blk_decrypt,
  995. .ivsize = AES_BLOCK_SIZE,
  996. }
  997. }
  998. }
  999. },
  1000. {
  1001. .algomode = CRYP_ALGO_DES_ECB,
  1002. .crypto = {
  1003. .cra_name = "des",
  1004. .cra_driver_name = "des-ux500",
  1005. .cra_priority = 300,
  1006. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1007. CRYPTO_ALG_ASYNC,
  1008. .cra_blocksize = DES_BLOCK_SIZE,
  1009. .cra_ctxsize = sizeof(struct cryp_ctx),
  1010. .cra_alignmask = 3,
  1011. .cra_type = &crypto_ablkcipher_type,
  1012. .cra_init = cryp_cra_init,
  1013. .cra_module = THIS_MODULE,
  1014. .cra_u = {
  1015. .ablkcipher = {
  1016. .min_keysize = DES_KEY_SIZE,
  1017. .max_keysize = DES_KEY_SIZE,
  1018. .setkey = des_ablkcipher_setkey,
  1019. .encrypt = cryp_blk_encrypt,
  1020. .decrypt = cryp_blk_decrypt
  1021. }
  1022. }
  1023. }
  1024. },
  1025. {
  1026. .algomode = CRYP_ALGO_TDES_ECB,
  1027. .crypto = {
  1028. .cra_name = "des3_ede",
  1029. .cra_driver_name = "des3_ede-ux500",
  1030. .cra_priority = 300,
  1031. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1032. CRYPTO_ALG_ASYNC,
  1033. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1034. .cra_ctxsize = sizeof(struct cryp_ctx),
  1035. .cra_alignmask = 3,
  1036. .cra_type = &crypto_ablkcipher_type,
  1037. .cra_init = cryp_cra_init,
  1038. .cra_module = THIS_MODULE,
  1039. .cra_u = {
  1040. .ablkcipher = {
  1041. .min_keysize = DES3_EDE_KEY_SIZE,
  1042. .max_keysize = DES3_EDE_KEY_SIZE,
  1043. .setkey = des_ablkcipher_setkey,
  1044. .encrypt = cryp_blk_encrypt,
  1045. .decrypt = cryp_blk_decrypt
  1046. }
  1047. }
  1048. }
  1049. },
  1050. {
  1051. .algomode = CRYP_ALGO_DES_ECB,
  1052. .crypto = {
  1053. .cra_name = "ecb(des)",
  1054. .cra_driver_name = "ecb-des-ux500",
  1055. .cra_priority = 300,
  1056. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1057. CRYPTO_ALG_ASYNC,
  1058. .cra_blocksize = DES_BLOCK_SIZE,
  1059. .cra_ctxsize = sizeof(struct cryp_ctx),
  1060. .cra_alignmask = 3,
  1061. .cra_type = &crypto_ablkcipher_type,
  1062. .cra_init = cryp_cra_init,
  1063. .cra_module = THIS_MODULE,
  1064. .cra_u = {
  1065. .ablkcipher = {
  1066. .min_keysize = DES_KEY_SIZE,
  1067. .max_keysize = DES_KEY_SIZE,
  1068. .setkey = des_ablkcipher_setkey,
  1069. .encrypt = cryp_blk_encrypt,
  1070. .decrypt = cryp_blk_decrypt,
  1071. }
  1072. }
  1073. }
  1074. },
  1075. {
  1076. .algomode = CRYP_ALGO_TDES_ECB,
  1077. .crypto = {
  1078. .cra_name = "ecb(des3_ede)",
  1079. .cra_driver_name = "ecb-des3_ede-ux500",
  1080. .cra_priority = 300,
  1081. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1082. CRYPTO_ALG_ASYNC,
  1083. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1084. .cra_ctxsize = sizeof(struct cryp_ctx),
  1085. .cra_alignmask = 3,
  1086. .cra_type = &crypto_ablkcipher_type,
  1087. .cra_init = cryp_cra_init,
  1088. .cra_module = THIS_MODULE,
  1089. .cra_u = {
  1090. .ablkcipher = {
  1091. .min_keysize = DES3_EDE_KEY_SIZE,
  1092. .max_keysize = DES3_EDE_KEY_SIZE,
  1093. .setkey = des3_ablkcipher_setkey,
  1094. .encrypt = cryp_blk_encrypt,
  1095. .decrypt = cryp_blk_decrypt,
  1096. }
  1097. }
  1098. }
  1099. },
  1100. {
  1101. .algomode = CRYP_ALGO_DES_CBC,
  1102. .crypto = {
  1103. .cra_name = "cbc(des)",
  1104. .cra_driver_name = "cbc-des-ux500",
  1105. .cra_priority = 300,
  1106. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1107. CRYPTO_ALG_ASYNC,
  1108. .cra_blocksize = DES_BLOCK_SIZE,
  1109. .cra_ctxsize = sizeof(struct cryp_ctx),
  1110. .cra_alignmask = 3,
  1111. .cra_type = &crypto_ablkcipher_type,
  1112. .cra_init = cryp_cra_init,
  1113. .cra_module = THIS_MODULE,
  1114. .cra_u = {
  1115. .ablkcipher = {
  1116. .min_keysize = DES_KEY_SIZE,
  1117. .max_keysize = DES_KEY_SIZE,
  1118. .setkey = des_ablkcipher_setkey,
  1119. .encrypt = cryp_blk_encrypt,
  1120. .decrypt = cryp_blk_decrypt,
  1121. }
  1122. }
  1123. }
  1124. },
  1125. {
  1126. .algomode = CRYP_ALGO_TDES_CBC,
  1127. .crypto = {
  1128. .cra_name = "cbc(des3_ede)",
  1129. .cra_driver_name = "cbc-des3_ede-ux500",
  1130. .cra_priority = 300,
  1131. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1132. CRYPTO_ALG_ASYNC,
  1133. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1134. .cra_ctxsize = sizeof(struct cryp_ctx),
  1135. .cra_alignmask = 3,
  1136. .cra_type = &crypto_ablkcipher_type,
  1137. .cra_init = cryp_cra_init,
  1138. .cra_module = THIS_MODULE,
  1139. .cra_u = {
  1140. .ablkcipher = {
  1141. .min_keysize = DES3_EDE_KEY_SIZE,
  1142. .max_keysize = DES3_EDE_KEY_SIZE,
  1143. .setkey = des3_ablkcipher_setkey,
  1144. .encrypt = cryp_blk_encrypt,
  1145. .decrypt = cryp_blk_decrypt,
  1146. .ivsize = DES3_EDE_BLOCK_SIZE,
  1147. }
  1148. }
  1149. }
  1150. }
  1151. };
  1152. /**
  1153. * cryp_algs_register_all -
  1154. */
  1155. static int cryp_algs_register_all(void)
  1156. {
  1157. int ret;
  1158. int i;
  1159. int count;
  1160. pr_debug("[%s]", __func__);
  1161. for (i = 0; i < ARRAY_SIZE(cryp_algs); i++) {
  1162. ret = crypto_register_alg(&cryp_algs[i].crypto);
  1163. if (ret) {
  1164. count = i;
  1165. pr_err("[%s] alg registration failed",
  1166. cryp_algs[i].crypto.cra_driver_name);
  1167. goto unreg;
  1168. }
  1169. }
  1170. return 0;
  1171. unreg:
  1172. for (i = 0; i < count; i++)
  1173. crypto_unregister_alg(&cryp_algs[i].crypto);
  1174. return ret;
  1175. }
  1176. /**
  1177. * cryp_algs_unregister_all -
  1178. */
  1179. static void cryp_algs_unregister_all(void)
  1180. {
  1181. int i;
  1182. pr_debug(DEV_DBG_NAME " [%s]", __func__);
  1183. for (i = 0; i < ARRAY_SIZE(cryp_algs); i++)
  1184. crypto_unregister_alg(&cryp_algs[i].crypto);
  1185. }
  1186. static int ux500_cryp_probe(struct platform_device *pdev)
  1187. {
  1188. int ret;
  1189. int cryp_error = 0;
  1190. struct resource *res = NULL;
  1191. struct resource *res_irq = NULL;
  1192. struct cryp_device_data *device_data;
  1193. struct cryp_protection_config prot = {
  1194. .privilege_access = CRYP_STATE_ENABLE
  1195. };
  1196. struct device *dev = &pdev->dev;
  1197. dev_dbg(dev, "[%s]", __func__);
  1198. device_data = kzalloc(sizeof(struct cryp_device_data), GFP_ATOMIC);
  1199. if (!device_data) {
  1200. dev_err(dev, "[%s]: kzalloc() failed!", __func__);
  1201. ret = -ENOMEM;
  1202. goto out;
  1203. }
  1204. device_data->dev = dev;
  1205. device_data->current_ctx = NULL;
  1206. /* Grab the DMA configuration from platform data. */
  1207. mem_to_engine = &((struct cryp_platform_data *)
  1208. dev->platform_data)->mem_to_engine;
  1209. engine_to_mem = &((struct cryp_platform_data *)
  1210. dev->platform_data)->engine_to_mem;
  1211. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1212. if (!res) {
  1213. dev_err(dev, "[%s]: platform_get_resource() failed",
  1214. __func__);
  1215. ret = -ENODEV;
  1216. goto out_kfree;
  1217. }
  1218. res = request_mem_region(res->start, resource_size(res), pdev->name);
  1219. if (res == NULL) {
  1220. dev_err(dev, "[%s]: request_mem_region() failed",
  1221. __func__);
  1222. ret = -EBUSY;
  1223. goto out_kfree;
  1224. }
  1225. device_data->base = ioremap(res->start, resource_size(res));
  1226. if (!device_data->base) {
  1227. dev_err(dev, "[%s]: ioremap failed!", __func__);
  1228. ret = -ENOMEM;
  1229. goto out_free_mem;
  1230. }
  1231. spin_lock_init(&device_data->ctx_lock);
  1232. spin_lock_init(&device_data->power_state_spinlock);
  1233. /* Enable power for CRYP hardware block */
  1234. device_data->pwr_regulator = regulator_get(&pdev->dev, "v-ape");
  1235. if (IS_ERR(device_data->pwr_regulator)) {
  1236. dev_err(dev, "[%s]: could not get cryp regulator", __func__);
  1237. ret = PTR_ERR(device_data->pwr_regulator);
  1238. device_data->pwr_regulator = NULL;
  1239. goto out_unmap;
  1240. }
  1241. /* Enable the clk for CRYP hardware block */
  1242. device_data->clk = clk_get(&pdev->dev, NULL);
  1243. if (IS_ERR(device_data->clk)) {
  1244. dev_err(dev, "[%s]: clk_get() failed!", __func__);
  1245. ret = PTR_ERR(device_data->clk);
  1246. goto out_regulator;
  1247. }
  1248. ret = clk_prepare(device_data->clk);
  1249. if (ret) {
  1250. dev_err(dev, "[%s]: clk_prepare() failed!", __func__);
  1251. goto out_clk;
  1252. }
  1253. /* Enable device power (and clock) */
  1254. ret = cryp_enable_power(device_data->dev, device_data, false);
  1255. if (ret) {
  1256. dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
  1257. goto out_clk_unprepare;
  1258. }
  1259. cryp_error = cryp_check(device_data);
  1260. if (cryp_error != 0) {
  1261. dev_err(dev, "[%s]: cryp_init() failed!", __func__);
  1262. ret = -EINVAL;
  1263. goto out_power;
  1264. }
  1265. cryp_error = cryp_configure_protection(device_data, &prot);
  1266. if (cryp_error != 0) {
  1267. dev_err(dev, "[%s]: cryp_configure_protection() failed!",
  1268. __func__);
  1269. ret = -EINVAL;
  1270. goto out_power;
  1271. }
  1272. res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1273. if (!res_irq) {
  1274. dev_err(dev, "[%s]: IORESOURCE_IRQ unavailable",
  1275. __func__);
  1276. ret = -ENODEV;
  1277. goto out_power;
  1278. }
  1279. ret = request_irq(res_irq->start,
  1280. cryp_interrupt_handler,
  1281. 0,
  1282. "cryp1",
  1283. device_data);
  1284. if (ret) {
  1285. dev_err(dev, "[%s]: Unable to request IRQ", __func__);
  1286. goto out_power;
  1287. }
  1288. if (cryp_mode == CRYP_MODE_DMA)
  1289. cryp_dma_setup_channel(device_data, dev);
  1290. platform_set_drvdata(pdev, device_data);
  1291. /* Put the new device into the device list... */
  1292. klist_add_tail(&device_data->list_node, &driver_data.device_list);
  1293. /* ... and signal that a new device is available. */
  1294. up(&driver_data.device_allocation);
  1295. atomic_set(&session_id, 1);
  1296. ret = cryp_algs_register_all();
  1297. if (ret) {
  1298. dev_err(dev, "[%s]: cryp_algs_register_all() failed!",
  1299. __func__);
  1300. goto out_power;
  1301. }
  1302. return 0;
  1303. out_power:
  1304. cryp_disable_power(device_data->dev, device_data, false);
  1305. out_clk_unprepare:
  1306. clk_unprepare(device_data->clk);
  1307. out_clk:
  1308. clk_put(device_data->clk);
  1309. out_regulator:
  1310. regulator_put(device_data->pwr_regulator);
  1311. out_unmap:
  1312. iounmap(device_data->base);
  1313. out_free_mem:
  1314. release_mem_region(res->start, resource_size(res));
  1315. out_kfree:
  1316. kfree(device_data);
  1317. out:
  1318. return ret;
  1319. }
  1320. static int ux500_cryp_remove(struct platform_device *pdev)
  1321. {
  1322. struct resource *res = NULL;
  1323. struct resource *res_irq = NULL;
  1324. struct cryp_device_data *device_data;
  1325. dev_dbg(&pdev->dev, "[%s]", __func__);
  1326. device_data = platform_get_drvdata(pdev);
  1327. if (!device_data) {
  1328. dev_err(&pdev->dev, "[%s]: platform_get_drvdata() failed!",
  1329. __func__);
  1330. return -ENOMEM;
  1331. }
  1332. /* Try to decrease the number of available devices. */
  1333. if (down_trylock(&driver_data.device_allocation))
  1334. return -EBUSY;
  1335. /* Check that the device is free */
  1336. spin_lock(&device_data->ctx_lock);
  1337. /* current_ctx allocates a device, NULL = unallocated */
  1338. if (device_data->current_ctx) {
  1339. /* The device is busy */
  1340. spin_unlock(&device_data->ctx_lock);
  1341. /* Return the device to the pool. */
  1342. up(&driver_data.device_allocation);
  1343. return -EBUSY;
  1344. }
  1345. spin_unlock(&device_data->ctx_lock);
  1346. /* Remove the device from the list */
  1347. if (klist_node_attached(&device_data->list_node))
  1348. klist_remove(&device_data->list_node);
  1349. /* If this was the last device, remove the services */
  1350. if (list_empty(&driver_data.device_list.k_list))
  1351. cryp_algs_unregister_all();
  1352. res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1353. if (!res_irq)
  1354. dev_err(&pdev->dev, "[%s]: IORESOURCE_IRQ, unavailable",
  1355. __func__);
  1356. else {
  1357. disable_irq(res_irq->start);
  1358. free_irq(res_irq->start, device_data);
  1359. }
  1360. if (cryp_disable_power(&pdev->dev, device_data, false))
  1361. dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
  1362. __func__);
  1363. clk_unprepare(device_data->clk);
  1364. clk_put(device_data->clk);
  1365. regulator_put(device_data->pwr_regulator);
  1366. iounmap(device_data->base);
  1367. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1368. if (res)
  1369. release_mem_region(res->start, res->end - res->start + 1);
  1370. kfree(device_data);
  1371. return 0;
  1372. }
  1373. static void ux500_cryp_shutdown(struct platform_device *pdev)
  1374. {
  1375. struct resource *res_irq = NULL;
  1376. struct cryp_device_data *device_data;
  1377. dev_dbg(&pdev->dev, "[%s]", __func__);
  1378. device_data = platform_get_drvdata(pdev);
  1379. if (!device_data) {
  1380. dev_err(&pdev->dev, "[%s]: platform_get_drvdata() failed!",
  1381. __func__);
  1382. return;
  1383. }
  1384. /* Check that the device is free */
  1385. spin_lock(&device_data->ctx_lock);
  1386. /* current_ctx allocates a device, NULL = unallocated */
  1387. if (!device_data->current_ctx) {
  1388. if (down_trylock(&driver_data.device_allocation))
  1389. dev_dbg(&pdev->dev, "[%s]: Cryp still in use!"
  1390. "Shutting down anyway...", __func__);
  1391. /**
  1392. * (Allocate the device)
  1393. * Need to set this to non-null (dummy) value,
  1394. * to avoid usage if context switching.
  1395. */
  1396. device_data->current_ctx++;
  1397. }
  1398. spin_unlock(&device_data->ctx_lock);
  1399. /* Remove the device from the list */
  1400. if (klist_node_attached(&device_data->list_node))
  1401. klist_remove(&device_data->list_node);
  1402. /* If this was the last device, remove the services */
  1403. if (list_empty(&driver_data.device_list.k_list))
  1404. cryp_algs_unregister_all();
  1405. res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1406. if (!res_irq)
  1407. dev_err(&pdev->dev, "[%s]: IORESOURCE_IRQ, unavailable",
  1408. __func__);
  1409. else {
  1410. disable_irq(res_irq->start);
  1411. free_irq(res_irq->start, device_data);
  1412. }
  1413. if (cryp_disable_power(&pdev->dev, device_data, false))
  1414. dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
  1415. __func__);
  1416. }
  1417. static int ux500_cryp_suspend(struct device *dev)
  1418. {
  1419. int ret;
  1420. struct platform_device *pdev = to_platform_device(dev);
  1421. struct cryp_device_data *device_data;
  1422. struct resource *res_irq;
  1423. struct cryp_ctx *temp_ctx = NULL;
  1424. dev_dbg(dev, "[%s]", __func__);
  1425. /* Handle state? */
  1426. device_data = platform_get_drvdata(pdev);
  1427. if (!device_data) {
  1428. dev_err(dev, "[%s]: platform_get_drvdata() failed!", __func__);
  1429. return -ENOMEM;
  1430. }
  1431. res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1432. if (!res_irq)
  1433. dev_err(dev, "[%s]: IORESOURCE_IRQ, unavailable", __func__);
  1434. else
  1435. disable_irq(res_irq->start);
  1436. spin_lock(&device_data->ctx_lock);
  1437. if (!device_data->current_ctx)
  1438. device_data->current_ctx++;
  1439. spin_unlock(&device_data->ctx_lock);
  1440. if (device_data->current_ctx == ++temp_ctx) {
  1441. if (down_interruptible(&driver_data.device_allocation))
  1442. dev_dbg(dev, "[%s]: down_interruptible() failed",
  1443. __func__);
  1444. ret = cryp_disable_power(dev, device_data, false);
  1445. } else
  1446. ret = cryp_disable_power(dev, device_data, true);
  1447. if (ret)
  1448. dev_err(dev, "[%s]: cryp_disable_power()", __func__);
  1449. return ret;
  1450. }
  1451. static int ux500_cryp_resume(struct device *dev)
  1452. {
  1453. int ret = 0;
  1454. struct platform_device *pdev = to_platform_device(dev);
  1455. struct cryp_device_data *device_data;
  1456. struct resource *res_irq;
  1457. struct cryp_ctx *temp_ctx = NULL;
  1458. dev_dbg(dev, "[%s]", __func__);
  1459. device_data = platform_get_drvdata(pdev);
  1460. if (!device_data) {
  1461. dev_err(dev, "[%s]: platform_get_drvdata() failed!", __func__);
  1462. return -ENOMEM;
  1463. }
  1464. spin_lock(&device_data->ctx_lock);
  1465. if (device_data->current_ctx == ++temp_ctx)
  1466. device_data->current_ctx = NULL;
  1467. spin_unlock(&device_data->ctx_lock);
  1468. if (!device_data->current_ctx)
  1469. up(&driver_data.device_allocation);
  1470. else
  1471. ret = cryp_enable_power(dev, device_data, true);
  1472. if (ret)
  1473. dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
  1474. else {
  1475. res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1476. if (res_irq)
  1477. enable_irq(res_irq->start);
  1478. }
  1479. return ret;
  1480. }
  1481. static SIMPLE_DEV_PM_OPS(ux500_cryp_pm, ux500_cryp_suspend, ux500_cryp_resume);
  1482. static struct platform_driver cryp_driver = {
  1483. .probe = ux500_cryp_probe,
  1484. .remove = ux500_cryp_remove,
  1485. .shutdown = ux500_cryp_shutdown,
  1486. .driver = {
  1487. .owner = THIS_MODULE,
  1488. .name = "cryp1",
  1489. .pm = &ux500_cryp_pm,
  1490. }
  1491. };
  1492. static int __init ux500_cryp_mod_init(void)
  1493. {
  1494. pr_debug("[%s] is called!", __func__);
  1495. klist_init(&driver_data.device_list, NULL, NULL);
  1496. /* Initialize the semaphore to 0 devices (locked state) */
  1497. sema_init(&driver_data.device_allocation, 0);
  1498. return platform_driver_register(&cryp_driver);
  1499. }
  1500. static void __exit ux500_cryp_mod_fini(void)
  1501. {
  1502. pr_debug("[%s] is called!", __func__);
  1503. platform_driver_unregister(&cryp_driver);
  1504. return;
  1505. }
  1506. module_init(ux500_cryp_mod_init);
  1507. module_exit(ux500_cryp_mod_fini);
  1508. module_param(cryp_mode, int, 0);
  1509. MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 CRYP crypto engine.");
  1510. MODULE_ALIAS("aes-all");
  1511. MODULE_ALIAS("des-all");
  1512. MODULE_LICENSE("GPL");