nv50_sor.c 14 KB

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  1. /*
  2. * Copyright (C) 2008 Maarten Maathuis.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "drmP.h"
  27. #include "drm_crtc_helper.h"
  28. #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  29. #include "nouveau_reg.h"
  30. #include "nouveau_drv.h"
  31. #include "nouveau_dma.h"
  32. #include "nouveau_encoder.h"
  33. #include "nouveau_connector.h"
  34. #include "nouveau_crtc.h"
  35. #include "nv50_display.h"
  36. static u32
  37. nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane)
  38. {
  39. struct drm_nouveau_private *dev_priv = dev->dev_private;
  40. static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
  41. static const u8 nv50[] = { 16, 8, 0, 24 };
  42. if (dev_priv->card_type == 0xaf)
  43. return nvaf[lane];
  44. return nv50[lane];
  45. }
  46. static void
  47. nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern)
  48. {
  49. u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
  50. nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24);
  51. }
  52. static void
  53. nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb,
  54. u8 lane, u8 swing, u8 preem)
  55. {
  56. u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
  57. u32 shift = nv50_sor_dp_lane_map(dev, dcb, lane);
  58. u32 mask = 0x000000ff << shift;
  59. u8 *table, *entry, *config;
  60. table = nouveau_dp_bios_data(dev, dcb, &entry);
  61. if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
  62. NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
  63. return;
  64. }
  65. config = entry + table[4];
  66. while (config[0] != swing || config[1] != preem) {
  67. config += table[5];
  68. if (config >= entry + table[4] + entry[4] * table[5])
  69. return;
  70. }
  71. nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, config[2] << shift);
  72. nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, config[3] << shift);
  73. nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff00, config[4] << 8);
  74. }
  75. static void
  76. nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc,
  77. int link_nr, u32 link_bw, bool enhframe)
  78. {
  79. u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
  80. u32 dpctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)) & ~0x001f4000;
  81. u32 clksor = nv_rd32(dev, 0x614300 + (or * 0x800)) & ~0x000c0000;
  82. u8 *table, *entry, mask;
  83. int i;
  84. table = nouveau_dp_bios_data(dev, dcb, &entry);
  85. if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
  86. NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
  87. return;
  88. }
  89. entry = ROMPTR(dev, entry[10]);
  90. if (entry) {
  91. while (link_bw < ROM16(entry[0]) * 10)
  92. entry += 4;
  93. nouveau_bios_run_init_table(dev, ROM16(entry[2]), dcb, crtc);
  94. }
  95. dpctrl |= ((1 << link_nr) - 1) << 16;
  96. if (enhframe)
  97. dpctrl |= 0x00004000;
  98. if (link_bw > 162000)
  99. clksor |= 0x00040000;
  100. nv_wr32(dev, 0x614300 + (or * 0x800), clksor);
  101. nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), dpctrl);
  102. mask = 0;
  103. for (i = 0; i < link_nr; i++)
  104. mask |= 1 << (nv50_sor_dp_lane_map(dev, dcb, i) >> 3);
  105. nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000000f, mask);
  106. }
  107. static void
  108. nv50_sor_dp_link_get(struct drm_device *dev, u32 or, u32 link, u32 *nr, u32 *bw)
  109. {
  110. u32 dpctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)) & 0x000f0000;
  111. u32 clksor = nv_rd32(dev, 0x614300 + (or * 0x800));
  112. if (clksor & 0x000c0000)
  113. *bw = 270000;
  114. else
  115. *bw = 162000;
  116. if (dpctrl > 0x00030000) *nr = 4;
  117. else if (dpctrl > 0x00010000) *nr = 2;
  118. else *nr = 1;
  119. }
  120. void
  121. nv50_sor_dp_calc_tu(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
  122. {
  123. const u32 symbol = 100000;
  124. int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
  125. int TU, VTUi, VTUf, VTUa;
  126. u64 link_data_rate, link_ratio, unk;
  127. u32 best_diff = 64 * symbol;
  128. u32 link_nr, link_bw, r;
  129. /* calculate packed data rate for each lane */
  130. nv50_sor_dp_link_get(dev, or, link, &link_nr, &link_bw);
  131. link_data_rate = (clk * bpp / 8) / link_nr;
  132. /* calculate ratio of packed data rate to link symbol rate */
  133. link_ratio = link_data_rate * symbol;
  134. r = do_div(link_ratio, link_bw);
  135. for (TU = 64; TU >= 32; TU--) {
  136. /* calculate average number of valid symbols in each TU */
  137. u32 tu_valid = link_ratio * TU;
  138. u32 calc, diff;
  139. /* find a hw representation for the fraction.. */
  140. VTUi = tu_valid / symbol;
  141. calc = VTUi * symbol;
  142. diff = tu_valid - calc;
  143. if (diff) {
  144. if (diff >= (symbol / 2)) {
  145. VTUf = symbol / (symbol - diff);
  146. if (symbol - (VTUf * diff))
  147. VTUf++;
  148. if (VTUf <= 15) {
  149. VTUa = 1;
  150. calc += symbol - (symbol / VTUf);
  151. } else {
  152. VTUa = 0;
  153. VTUf = 1;
  154. calc += symbol;
  155. }
  156. } else {
  157. VTUa = 0;
  158. VTUf = min((int)(symbol / diff), 15);
  159. calc += symbol / VTUf;
  160. }
  161. diff = calc - tu_valid;
  162. } else {
  163. /* no remainder, but the hw doesn't like the fractional
  164. * part to be zero. decrement the integer part and
  165. * have the fraction add a whole symbol back
  166. */
  167. VTUa = 0;
  168. VTUf = 1;
  169. VTUi--;
  170. }
  171. if (diff < best_diff) {
  172. best_diff = diff;
  173. bestTU = TU;
  174. bestVTUa = VTUa;
  175. bestVTUf = VTUf;
  176. bestVTUi = VTUi;
  177. if (diff == 0)
  178. break;
  179. }
  180. }
  181. if (!bestTU) {
  182. NV_ERROR(dev, "DP: unable to find suitable config\n");
  183. return;
  184. }
  185. /* XXX close to vbios numbers, but not right */
  186. unk = (symbol - link_ratio) * bestTU;
  187. unk *= link_ratio;
  188. r = do_div(unk, symbol);
  189. r = do_div(unk, symbol);
  190. unk += 6;
  191. nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
  192. nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
  193. bestVTUf << 16 |
  194. bestVTUi << 8 |
  195. unk);
  196. }
  197. static void
  198. nv50_sor_disconnect(struct drm_encoder *encoder)
  199. {
  200. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  201. struct drm_device *dev = encoder->dev;
  202. struct nouveau_channel *evo = nv50_display(dev)->master;
  203. int ret;
  204. if (!nv_encoder->crtc)
  205. return;
  206. nv50_crtc_blank(nouveau_crtc(nv_encoder->crtc), true);
  207. NV_DEBUG_KMS(dev, "Disconnecting SOR %d\n", nv_encoder->or);
  208. ret = RING_SPACE(evo, 4);
  209. if (ret) {
  210. NV_ERROR(dev, "no space while disconnecting SOR\n");
  211. return;
  212. }
  213. BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
  214. OUT_RING (evo, 0);
  215. BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
  216. OUT_RING (evo, 0);
  217. nouveau_hdmi_mode_set(encoder, NULL);
  218. nv_encoder->crtc = NULL;
  219. nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
  220. }
  221. static void
  222. nv50_sor_dpms(struct drm_encoder *encoder, int mode)
  223. {
  224. struct drm_device *dev = encoder->dev;
  225. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  226. struct drm_encoder *enc;
  227. uint32_t val;
  228. int or = nv_encoder->or;
  229. NV_DEBUG_KMS(dev, "or %d type %d mode %d\n", or, nv_encoder->dcb->type, mode);
  230. nv_encoder->last_dpms = mode;
  231. list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
  232. struct nouveau_encoder *nvenc = nouveau_encoder(enc);
  233. if (nvenc == nv_encoder ||
  234. (nvenc->dcb->type != OUTPUT_TMDS &&
  235. nvenc->dcb->type != OUTPUT_LVDS &&
  236. nvenc->dcb->type != OUTPUT_DP) ||
  237. nvenc->dcb->or != nv_encoder->dcb->or)
  238. continue;
  239. if (nvenc->last_dpms == DRM_MODE_DPMS_ON)
  240. return;
  241. }
  242. /* wait for it to be done */
  243. if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or),
  244. NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) {
  245. NV_ERROR(dev, "timeout: SOR_DPMS_CTRL_PENDING(%d) == 0\n", or);
  246. NV_ERROR(dev, "SOR_DPMS_CTRL(%d) = 0x%08x\n", or,
  247. nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or)));
  248. }
  249. val = nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or));
  250. if (mode == DRM_MODE_DPMS_ON)
  251. val |= NV50_PDISPLAY_SOR_DPMS_CTRL_ON;
  252. else
  253. val &= ~NV50_PDISPLAY_SOR_DPMS_CTRL_ON;
  254. nv_wr32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or), val |
  255. NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING);
  256. if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(or),
  257. NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
  258. NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", or);
  259. NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", or,
  260. nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(or)));
  261. }
  262. if (nv_encoder->dcb->type == OUTPUT_DP) {
  263. struct nouveau_i2c_chan *auxch;
  264. auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
  265. if (!auxch)
  266. return;
  267. if (mode == DRM_MODE_DPMS_ON) {
  268. struct dp_train_func func = {
  269. .link_set = nv50_sor_dp_link_set,
  270. .train_set = nv50_sor_dp_train_set,
  271. .train_adj = nv50_sor_dp_train_adj
  272. };
  273. u32 rate = nv_encoder->dp.datarate;
  274. u8 status = DP_SET_POWER_D0;
  275. nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
  276. nouveau_dp_link_train(encoder, rate, &func);
  277. } else {
  278. u8 status = DP_SET_POWER_D3;
  279. nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
  280. }
  281. }
  282. }
  283. static void
  284. nv50_sor_save(struct drm_encoder *encoder)
  285. {
  286. NV_ERROR(encoder->dev, "!!\n");
  287. }
  288. static void
  289. nv50_sor_restore(struct drm_encoder *encoder)
  290. {
  291. NV_ERROR(encoder->dev, "!!\n");
  292. }
  293. static bool
  294. nv50_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
  295. struct drm_display_mode *adjusted_mode)
  296. {
  297. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  298. struct nouveau_connector *connector;
  299. NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or);
  300. connector = nouveau_encoder_connector_get(nv_encoder);
  301. if (!connector) {
  302. NV_ERROR(encoder->dev, "Encoder has no connector\n");
  303. return false;
  304. }
  305. if (connector->scaling_mode != DRM_MODE_SCALE_NONE &&
  306. connector->native_mode) {
  307. int id = adjusted_mode->base.id;
  308. *adjusted_mode = *connector->native_mode;
  309. adjusted_mode->base.id = id;
  310. }
  311. return true;
  312. }
  313. static void
  314. nv50_sor_prepare(struct drm_encoder *encoder)
  315. {
  316. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  317. nv50_sor_disconnect(encoder);
  318. if (nv_encoder->dcb->type == OUTPUT_DP) {
  319. /* avoid race between link training and supervisor intr */
  320. nv50_display_sync(encoder->dev);
  321. }
  322. }
  323. static void
  324. nv50_sor_commit(struct drm_encoder *encoder)
  325. {
  326. }
  327. static void
  328. nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
  329. struct drm_display_mode *mode)
  330. {
  331. struct nouveau_channel *evo = nv50_display(encoder->dev)->master;
  332. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  333. struct drm_device *dev = encoder->dev;
  334. struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc);
  335. struct nouveau_connector *nv_connector;
  336. uint32_t mode_ctl = 0;
  337. int ret;
  338. NV_DEBUG_KMS(dev, "or %d type %d -> crtc %d\n",
  339. nv_encoder->or, nv_encoder->dcb->type, crtc->index);
  340. nv_encoder->crtc = encoder->crtc;
  341. switch (nv_encoder->dcb->type) {
  342. case OUTPUT_TMDS:
  343. if (nv_encoder->dcb->sorconf.link & 1) {
  344. if (mode->clock < 165000)
  345. mode_ctl = 0x0100;
  346. else
  347. mode_ctl = 0x0500;
  348. } else
  349. mode_ctl = 0x0200;
  350. nouveau_hdmi_mode_set(encoder, mode);
  351. break;
  352. case OUTPUT_DP:
  353. nv_connector = nouveau_encoder_connector_get(nv_encoder);
  354. if (nv_connector && nv_connector->base.display_info.bpc == 6) {
  355. nv_encoder->dp.datarate = mode->clock * 18 / 8;
  356. mode_ctl |= 0x00020000;
  357. } else {
  358. nv_encoder->dp.datarate = mode->clock * 24 / 8;
  359. mode_ctl |= 0x00050000;
  360. }
  361. if (nv_encoder->dcb->sorconf.link & 1)
  362. mode_ctl |= 0x00000800;
  363. else
  364. mode_ctl |= 0x00000900;
  365. break;
  366. default:
  367. break;
  368. }
  369. if (crtc->index == 1)
  370. mode_ctl |= NV50_EVO_SOR_MODE_CTRL_CRTC1;
  371. else
  372. mode_ctl |= NV50_EVO_SOR_MODE_CTRL_CRTC0;
  373. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  374. mode_ctl |= NV50_EVO_SOR_MODE_CTRL_NHSYNC;
  375. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  376. mode_ctl |= NV50_EVO_SOR_MODE_CTRL_NVSYNC;
  377. nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
  378. ret = RING_SPACE(evo, 2);
  379. if (ret) {
  380. NV_ERROR(dev, "no space while connecting SOR\n");
  381. nv_encoder->crtc = NULL;
  382. return;
  383. }
  384. BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
  385. OUT_RING(evo, mode_ctl);
  386. }
  387. static struct drm_crtc *
  388. nv50_sor_crtc_get(struct drm_encoder *encoder)
  389. {
  390. return nouveau_encoder(encoder)->crtc;
  391. }
  392. static const struct drm_encoder_helper_funcs nv50_sor_helper_funcs = {
  393. .dpms = nv50_sor_dpms,
  394. .save = nv50_sor_save,
  395. .restore = nv50_sor_restore,
  396. .mode_fixup = nv50_sor_mode_fixup,
  397. .prepare = nv50_sor_prepare,
  398. .commit = nv50_sor_commit,
  399. .mode_set = nv50_sor_mode_set,
  400. .get_crtc = nv50_sor_crtc_get,
  401. .detect = NULL,
  402. .disable = nv50_sor_disconnect
  403. };
  404. static void
  405. nv50_sor_destroy(struct drm_encoder *encoder)
  406. {
  407. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  408. if (!encoder)
  409. return;
  410. NV_DEBUG_KMS(encoder->dev, "\n");
  411. drm_encoder_cleanup(encoder);
  412. kfree(nv_encoder);
  413. }
  414. static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
  415. .destroy = nv50_sor_destroy,
  416. };
  417. int
  418. nv50_sor_create(struct drm_connector *connector, struct dcb_entry *entry)
  419. {
  420. struct nouveau_encoder *nv_encoder = NULL;
  421. struct drm_device *dev = connector->dev;
  422. struct drm_encoder *encoder;
  423. int type;
  424. NV_DEBUG_KMS(dev, "\n");
  425. switch (entry->type) {
  426. case OUTPUT_TMDS:
  427. case OUTPUT_DP:
  428. type = DRM_MODE_ENCODER_TMDS;
  429. break;
  430. case OUTPUT_LVDS:
  431. type = DRM_MODE_ENCODER_LVDS;
  432. break;
  433. default:
  434. return -EINVAL;
  435. }
  436. nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
  437. if (!nv_encoder)
  438. return -ENOMEM;
  439. encoder = to_drm_encoder(nv_encoder);
  440. nv_encoder->dcb = entry;
  441. nv_encoder->or = ffs(entry->or) - 1;
  442. nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
  443. drm_encoder_init(dev, encoder, &nv50_sor_encoder_funcs, type);
  444. drm_encoder_helper_add(encoder, &nv50_sor_helper_funcs);
  445. encoder->possible_crtcs = entry->heads;
  446. encoder->possible_clones = 0;
  447. drm_mode_connector_attach_encoder(connector, encoder);
  448. return 0;
  449. }