perf_counter.h 2.1 KB

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  1. #ifndef _ASM_X86_PERF_COUNTER_H
  2. #define _ASM_X86_PERF_COUNTER_H
  3. /*
  4. * Performance counter hw details:
  5. */
  6. #define X86_PMC_MAX_GENERIC 8
  7. #define X86_PMC_MAX_FIXED 3
  8. #define X86_PMC_IDX_GENERIC 0
  9. #define X86_PMC_IDX_FIXED 32
  10. #define X86_PMC_IDX_MAX 64
  11. #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
  12. #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
  13. #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
  14. #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
  15. #define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22)
  16. #define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
  17. #define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
  18. #define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
  19. #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
  20. #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
  21. #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
  22. #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
  23. (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
  24. #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
  25. /*
  26. * Intel "Architectural Performance Monitoring" CPUID
  27. * detection/enumeration details:
  28. */
  29. union cpuid10_eax {
  30. struct {
  31. unsigned int version_id:8;
  32. unsigned int num_counters:8;
  33. unsigned int bit_width:8;
  34. unsigned int mask_length:8;
  35. } split;
  36. unsigned int full;
  37. };
  38. union cpuid10_edx {
  39. struct {
  40. unsigned int num_counters_fixed:4;
  41. unsigned int reserved:28;
  42. } split;
  43. unsigned int full;
  44. };
  45. /*
  46. * Fixed-purpose performance counters:
  47. */
  48. /*
  49. * All 3 fixed-mode PMCs are configured via this single MSR:
  50. */
  51. #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
  52. /*
  53. * The counts are available in three separate MSRs:
  54. */
  55. /* Instr_Retired.Any: */
  56. #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
  57. /* CPU_CLK_Unhalted.Core: */
  58. #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
  59. /* CPU_CLK_Unhalted.Ref: */
  60. #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
  61. #ifdef CONFIG_PERF_COUNTERS
  62. extern void init_hw_perf_counters(void);
  63. extern void perf_counters_lapic_init(int nmi);
  64. #else
  65. static inline void init_hw_perf_counters(void) { }
  66. static inline void perf_counters_lapic_init(int nmi) { }
  67. #endif
  68. #endif /* _ASM_X86_PERF_COUNTER_H */