ci13xxx_udc.c 67 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/interrupt.h>
  58. #include <linux/io.h>
  59. #include <linux/irq.h>
  60. #include <linux/kernel.h>
  61. #include <linux/slab.h>
  62. #include <linux/pm_runtime.h>
  63. #include <linux/usb/ch9.h>
  64. #include <linux/usb/gadget.h>
  65. #include <linux/usb/otg.h>
  66. #include "ci13xxx_udc.h"
  67. /******************************************************************************
  68. * DEFINE
  69. *****************************************************************************/
  70. /* ctrl register bank access */
  71. static DEFINE_SPINLOCK(udc_lock);
  72. /* control endpoint description */
  73. static const struct usb_endpoint_descriptor
  74. ctrl_endpt_out_desc = {
  75. .bLength = USB_DT_ENDPOINT_SIZE,
  76. .bDescriptorType = USB_DT_ENDPOINT,
  77. .bEndpointAddress = USB_DIR_OUT,
  78. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  79. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  80. };
  81. static const struct usb_endpoint_descriptor
  82. ctrl_endpt_in_desc = {
  83. .bLength = USB_DT_ENDPOINT_SIZE,
  84. .bDescriptorType = USB_DT_ENDPOINT,
  85. .bEndpointAddress = USB_DIR_IN,
  86. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  87. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  88. };
  89. /* UDC descriptor */
  90. static struct ci13xxx *_udc;
  91. /* Interrupt statistics */
  92. #define ISR_MASK 0x1F
  93. static struct {
  94. u32 test;
  95. u32 ui;
  96. u32 uei;
  97. u32 pci;
  98. u32 uri;
  99. u32 sli;
  100. u32 none;
  101. struct {
  102. u32 cnt;
  103. u32 buf[ISR_MASK+1];
  104. u32 idx;
  105. } hndl;
  106. } isr_statistics;
  107. /**
  108. * ffs_nr: find first (least significant) bit set
  109. * @x: the word to search
  110. *
  111. * This function returns bit number (instead of position)
  112. */
  113. static int ffs_nr(u32 x)
  114. {
  115. int n = ffs(x);
  116. return n ? n-1 : 32;
  117. }
  118. /******************************************************************************
  119. * HW block
  120. *****************************************************************************/
  121. /* register bank descriptor */
  122. static struct {
  123. unsigned lpm; /* is LPM? */
  124. void __iomem *abs; /* bus map offset */
  125. void __iomem *cap; /* bus map offset + CAP offset + CAP data */
  126. size_t size; /* bank size */
  127. } hw_bank;
  128. /* MSM specific */
  129. #define ABS_AHBBURST (0x0090UL)
  130. #define ABS_AHBMODE (0x0098UL)
  131. /* UDC register map */
  132. #define ABS_CAPLENGTH (0x100UL)
  133. #define ABS_HCCPARAMS (0x108UL)
  134. #define ABS_DCCPARAMS (0x124UL)
  135. #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
  136. /* offset to CAPLENTGH (addr + data) */
  137. #define CAP_USBCMD (0x000UL)
  138. #define CAP_USBSTS (0x004UL)
  139. #define CAP_USBINTR (0x008UL)
  140. #define CAP_DEVICEADDR (0x014UL)
  141. #define CAP_ENDPTLISTADDR (0x018UL)
  142. #define CAP_PORTSC (0x044UL)
  143. #define CAP_DEVLC (0x084UL)
  144. #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
  145. #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
  146. #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
  147. #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
  148. #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
  149. #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
  150. #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
  151. #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
  152. /* maximum number of enpoints: valid only after hw_device_reset() */
  153. static unsigned hw_ep_max;
  154. /**
  155. * hw_ep_bit: calculates the bit number
  156. * @num: endpoint number
  157. * @dir: endpoint direction
  158. *
  159. * This function returns bit number
  160. */
  161. static inline int hw_ep_bit(int num, int dir)
  162. {
  163. return num + (dir ? 16 : 0);
  164. }
  165. /**
  166. * hw_aread: reads from register bitfield
  167. * @addr: address relative to bus map
  168. * @mask: bitfield mask
  169. *
  170. * This function returns register bitfield data
  171. */
  172. static u32 hw_aread(u32 addr, u32 mask)
  173. {
  174. return ioread32(addr + hw_bank.abs) & mask;
  175. }
  176. /**
  177. * hw_awrite: writes to register bitfield
  178. * @addr: address relative to bus map
  179. * @mask: bitfield mask
  180. * @data: new data
  181. */
  182. static void hw_awrite(u32 addr, u32 mask, u32 data)
  183. {
  184. iowrite32(hw_aread(addr, ~mask) | (data & mask),
  185. addr + hw_bank.abs);
  186. }
  187. /**
  188. * hw_cread: reads from register bitfield
  189. * @addr: address relative to CAP offset plus content
  190. * @mask: bitfield mask
  191. *
  192. * This function returns register bitfield data
  193. */
  194. static u32 hw_cread(u32 addr, u32 mask)
  195. {
  196. return ioread32(addr + hw_bank.cap) & mask;
  197. }
  198. /**
  199. * hw_cwrite: writes to register bitfield
  200. * @addr: address relative to CAP offset plus content
  201. * @mask: bitfield mask
  202. * @data: new data
  203. */
  204. static void hw_cwrite(u32 addr, u32 mask, u32 data)
  205. {
  206. iowrite32(hw_cread(addr, ~mask) | (data & mask),
  207. addr + hw_bank.cap);
  208. }
  209. /**
  210. * hw_ctest_and_clear: tests & clears register bitfield
  211. * @addr: address relative to CAP offset plus content
  212. * @mask: bitfield mask
  213. *
  214. * This function returns register bitfield data
  215. */
  216. static u32 hw_ctest_and_clear(u32 addr, u32 mask)
  217. {
  218. u32 reg = hw_cread(addr, mask);
  219. iowrite32(reg, addr + hw_bank.cap);
  220. return reg;
  221. }
  222. /**
  223. * hw_ctest_and_write: tests & writes register bitfield
  224. * @addr: address relative to CAP offset plus content
  225. * @mask: bitfield mask
  226. * @data: new data
  227. *
  228. * This function returns register bitfield data
  229. */
  230. static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
  231. {
  232. u32 reg = hw_cread(addr, ~0);
  233. iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
  234. return (reg & mask) >> ffs_nr(mask);
  235. }
  236. static int hw_device_init(void __iomem *base)
  237. {
  238. u32 reg;
  239. /* bank is a module variable */
  240. hw_bank.abs = base;
  241. hw_bank.cap = hw_bank.abs;
  242. hw_bank.cap += ABS_CAPLENGTH;
  243. hw_bank.cap += ioread8(hw_bank.cap);
  244. reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
  245. hw_bank.lpm = reg;
  246. hw_bank.size = hw_bank.cap - hw_bank.abs;
  247. hw_bank.size += CAP_LAST;
  248. hw_bank.size /= sizeof(u32);
  249. reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
  250. hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  251. if (hw_ep_max == 0 || hw_ep_max > ENDPT_MAX)
  252. return -ENODEV;
  253. /* setup lock mode ? */
  254. /* ENDPTSETUPSTAT is '0' by default */
  255. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  256. return 0;
  257. }
  258. /**
  259. * hw_device_reset: resets chip (execute without interruption)
  260. * @base: register base address
  261. *
  262. * This function returns an error code
  263. */
  264. static int hw_device_reset(struct ci13xxx *udc)
  265. {
  266. /* should flush & stop before reset */
  267. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
  268. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  269. hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
  270. while (hw_cread(CAP_USBCMD, USBCMD_RST))
  271. udelay(10); /* not RTOS friendly */
  272. if (udc->udc_driver->notify_event)
  273. udc->udc_driver->notify_event(udc,
  274. CI13XXX_CONTROLLER_RESET_EVENT);
  275. if (udc->udc_driver->flags && CI13XXX_DISABLE_STREAMING)
  276. hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  277. /* USBMODE should be configured step by step */
  278. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  279. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  280. hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
  281. if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  282. pr_err("cannot enter in device mode");
  283. pr_err("lpm = %i", hw_bank.lpm);
  284. return -ENODEV;
  285. }
  286. return 0;
  287. }
  288. /**
  289. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  290. * without interruption)
  291. * @dma: 0 => disable, !0 => enable and set dma engine
  292. *
  293. * This function returns an error code
  294. */
  295. static int hw_device_state(u32 dma)
  296. {
  297. if (dma) {
  298. hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
  299. /* interrupt, error, port change, reset, sleep/suspend */
  300. hw_cwrite(CAP_USBINTR, ~0,
  301. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  302. hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
  303. } else {
  304. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  305. hw_cwrite(CAP_USBINTR, ~0, 0);
  306. }
  307. return 0;
  308. }
  309. /**
  310. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  311. * @num: endpoint number
  312. * @dir: endpoint direction
  313. *
  314. * This function returns an error code
  315. */
  316. static int hw_ep_flush(int num, int dir)
  317. {
  318. int n = hw_ep_bit(num, dir);
  319. do {
  320. /* flush any pending transfer */
  321. hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
  322. while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
  323. cpu_relax();
  324. } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
  325. return 0;
  326. }
  327. /**
  328. * hw_ep_disable: disables endpoint (execute without interruption)
  329. * @num: endpoint number
  330. * @dir: endpoint direction
  331. *
  332. * This function returns an error code
  333. */
  334. static int hw_ep_disable(int num, int dir)
  335. {
  336. hw_ep_flush(num, dir);
  337. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
  338. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  339. return 0;
  340. }
  341. /**
  342. * hw_ep_enable: enables endpoint (execute without interruption)
  343. * @num: endpoint number
  344. * @dir: endpoint direction
  345. * @type: endpoint type
  346. *
  347. * This function returns an error code
  348. */
  349. static int hw_ep_enable(int num, int dir, int type)
  350. {
  351. u32 mask, data;
  352. if (dir) {
  353. mask = ENDPTCTRL_TXT; /* type */
  354. data = type << ffs_nr(mask);
  355. mask |= ENDPTCTRL_TXS; /* unstall */
  356. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  357. data |= ENDPTCTRL_TXR;
  358. mask |= ENDPTCTRL_TXE; /* enable */
  359. data |= ENDPTCTRL_TXE;
  360. } else {
  361. mask = ENDPTCTRL_RXT; /* type */
  362. data = type << ffs_nr(mask);
  363. mask |= ENDPTCTRL_RXS; /* unstall */
  364. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  365. data |= ENDPTCTRL_RXR;
  366. mask |= ENDPTCTRL_RXE; /* enable */
  367. data |= ENDPTCTRL_RXE;
  368. }
  369. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
  370. return 0;
  371. }
  372. /**
  373. * hw_ep_get_halt: return endpoint halt status
  374. * @num: endpoint number
  375. * @dir: endpoint direction
  376. *
  377. * This function returns 1 if endpoint halted
  378. */
  379. static int hw_ep_get_halt(int num, int dir)
  380. {
  381. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  382. return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
  383. }
  384. /**
  385. * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
  386. * @num: endpoint number
  387. * @dir: endpoint direction
  388. *
  389. * This function returns true if endpoint primed
  390. */
  391. static int hw_ep_is_primed(int num, int dir)
  392. {
  393. u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
  394. return test_bit(hw_ep_bit(num, dir), (void *)&reg);
  395. }
  396. /**
  397. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  398. * interruption)
  399. * @n: bit number (endpoint)
  400. *
  401. * This function returns setup status
  402. */
  403. static int hw_test_and_clear_setup_status(int n)
  404. {
  405. return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
  406. }
  407. /**
  408. * hw_ep_prime: primes endpoint (execute without interruption)
  409. * @num: endpoint number
  410. * @dir: endpoint direction
  411. * @is_ctrl: true if control endpoint
  412. *
  413. * This function returns an error code
  414. */
  415. static int hw_ep_prime(int num, int dir, int is_ctrl)
  416. {
  417. int n = hw_ep_bit(num, dir);
  418. /* the caller should flush first */
  419. if (hw_ep_is_primed(num, dir))
  420. return -EBUSY;
  421. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  422. return -EAGAIN;
  423. hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
  424. while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  425. cpu_relax();
  426. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  427. return -EAGAIN;
  428. /* status shoult be tested according with manual but it doesn't work */
  429. return 0;
  430. }
  431. /**
  432. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  433. * without interruption)
  434. * @num: endpoint number
  435. * @dir: endpoint direction
  436. * @value: true => stall, false => unstall
  437. *
  438. * This function returns an error code
  439. */
  440. static int hw_ep_set_halt(int num, int dir, int value)
  441. {
  442. if (value != 0 && value != 1)
  443. return -EINVAL;
  444. do {
  445. u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
  446. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  447. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  448. /* data toggle - reserved for EP0 but it's in ESS */
  449. hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
  450. } while (value != hw_ep_get_halt(num, dir));
  451. return 0;
  452. }
  453. /**
  454. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  455. * interruption)
  456. * @n: interrupt bit
  457. *
  458. * This function returns an error code
  459. */
  460. static int hw_intr_clear(int n)
  461. {
  462. if (n >= REG_BITS)
  463. return -EINVAL;
  464. hw_cwrite(CAP_USBINTR, BIT(n), 0);
  465. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  466. return 0;
  467. }
  468. /**
  469. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  470. * interruption)
  471. * @n: interrupt bit
  472. *
  473. * This function returns an error code
  474. */
  475. static int hw_intr_force(int n)
  476. {
  477. if (n >= REG_BITS)
  478. return -EINVAL;
  479. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  480. hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
  481. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  482. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
  483. return 0;
  484. }
  485. /**
  486. * hw_is_port_high_speed: test if port is high speed
  487. *
  488. * This function returns true if high speed port
  489. */
  490. static int hw_port_is_high_speed(void)
  491. {
  492. return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
  493. hw_cread(CAP_PORTSC, PORTSC_HSP);
  494. }
  495. /**
  496. * hw_port_test_get: reads port test mode value
  497. *
  498. * This function returns port test mode value
  499. */
  500. static u8 hw_port_test_get(void)
  501. {
  502. return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  503. }
  504. /**
  505. * hw_port_test_set: writes port test mode (execute without interruption)
  506. * @mode: new value
  507. *
  508. * This function returns an error code
  509. */
  510. static int hw_port_test_set(u8 mode)
  511. {
  512. const u8 TEST_MODE_MAX = 7;
  513. if (mode > TEST_MODE_MAX)
  514. return -EINVAL;
  515. hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  516. return 0;
  517. }
  518. /**
  519. * hw_read_intr_enable: returns interrupt enable register
  520. *
  521. * This function returns register data
  522. */
  523. static u32 hw_read_intr_enable(void)
  524. {
  525. return hw_cread(CAP_USBINTR, ~0);
  526. }
  527. /**
  528. * hw_read_intr_status: returns interrupt status register
  529. *
  530. * This function returns register data
  531. */
  532. static u32 hw_read_intr_status(void)
  533. {
  534. return hw_cread(CAP_USBSTS, ~0);
  535. }
  536. /**
  537. * hw_register_read: reads all device registers (execute without interruption)
  538. * @buf: destination buffer
  539. * @size: buffer size
  540. *
  541. * This function returns number of registers read
  542. */
  543. static size_t hw_register_read(u32 *buf, size_t size)
  544. {
  545. unsigned i;
  546. if (size > hw_bank.size)
  547. size = hw_bank.size;
  548. for (i = 0; i < size; i++)
  549. buf[i] = hw_aread(i * sizeof(u32), ~0);
  550. return size;
  551. }
  552. /**
  553. * hw_register_write: writes to register
  554. * @addr: register address
  555. * @data: register value
  556. *
  557. * This function returns an error code
  558. */
  559. static int hw_register_write(u16 addr, u32 data)
  560. {
  561. /* align */
  562. addr /= sizeof(u32);
  563. if (addr >= hw_bank.size)
  564. return -EINVAL;
  565. /* align */
  566. addr *= sizeof(u32);
  567. hw_awrite(addr, ~0, data);
  568. return 0;
  569. }
  570. /**
  571. * hw_test_and_clear_complete: test & clear complete status (execute without
  572. * interruption)
  573. * @n: bit number (endpoint)
  574. *
  575. * This function returns complete status
  576. */
  577. static int hw_test_and_clear_complete(int n)
  578. {
  579. return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
  580. }
  581. /**
  582. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  583. * without interruption)
  584. *
  585. * This function returns active interrutps
  586. */
  587. static u32 hw_test_and_clear_intr_active(void)
  588. {
  589. u32 reg = hw_read_intr_status() & hw_read_intr_enable();
  590. hw_cwrite(CAP_USBSTS, ~0, reg);
  591. return reg;
  592. }
  593. /**
  594. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  595. * interruption)
  596. *
  597. * This function returns guard value
  598. */
  599. static int hw_test_and_clear_setup_guard(void)
  600. {
  601. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
  602. }
  603. /**
  604. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  605. * interruption)
  606. *
  607. * This function returns guard value
  608. */
  609. static int hw_test_and_set_setup_guard(void)
  610. {
  611. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  612. }
  613. /**
  614. * hw_usb_set_address: configures USB address (execute without interruption)
  615. * @value: new USB address
  616. *
  617. * This function returns an error code
  618. */
  619. static int hw_usb_set_address(u8 value)
  620. {
  621. /* advance */
  622. hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  623. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  624. return 0;
  625. }
  626. /**
  627. * hw_usb_reset: restart device after a bus reset (execute without
  628. * interruption)
  629. *
  630. * This function returns an error code
  631. */
  632. static int hw_usb_reset(void)
  633. {
  634. hw_usb_set_address(0);
  635. /* ESS flushes only at end?!? */
  636. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
  637. /* clear setup token semaphores */
  638. hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
  639. /* clear complete status */
  640. hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
  641. /* wait until all bits cleared */
  642. while (hw_cread(CAP_ENDPTPRIME, ~0))
  643. udelay(10); /* not RTOS friendly */
  644. /* reset all endpoints ? */
  645. /* reset internal status and wait for further instructions
  646. no need to verify the port reset status (ESS does it) */
  647. return 0;
  648. }
  649. /******************************************************************************
  650. * DBG block
  651. *****************************************************************************/
  652. /**
  653. * show_device: prints information about device capabilities and status
  654. *
  655. * Check "device.h" for details
  656. */
  657. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  658. char *buf)
  659. {
  660. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  661. struct usb_gadget *gadget = &udc->gadget;
  662. int n = 0;
  663. dbg_trace("[%s] %p\n", __func__, buf);
  664. if (attr == NULL || buf == NULL) {
  665. dev_err(dev, "[%s] EINVAL\n", __func__);
  666. return 0;
  667. }
  668. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  669. gadget->speed);
  670. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  671. gadget->is_dualspeed);
  672. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  673. gadget->is_otg);
  674. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  675. gadget->is_a_peripheral);
  676. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  677. gadget->b_hnp_enable);
  678. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  679. gadget->a_hnp_support);
  680. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  681. gadget->a_alt_hnp_support);
  682. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  683. (gadget->name ? gadget->name : ""));
  684. return n;
  685. }
  686. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  687. /**
  688. * show_driver: prints information about attached gadget (if any)
  689. *
  690. * Check "device.h" for details
  691. */
  692. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  693. char *buf)
  694. {
  695. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  696. struct usb_gadget_driver *driver = udc->driver;
  697. int n = 0;
  698. dbg_trace("[%s] %p\n", __func__, buf);
  699. if (attr == NULL || buf == NULL) {
  700. dev_err(dev, "[%s] EINVAL\n", __func__);
  701. return 0;
  702. }
  703. if (driver == NULL)
  704. return scnprintf(buf, PAGE_SIZE,
  705. "There is no gadget attached!\n");
  706. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  707. (driver->function ? driver->function : ""));
  708. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  709. driver->speed);
  710. return n;
  711. }
  712. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  713. /* Maximum event message length */
  714. #define DBG_DATA_MSG 64UL
  715. /* Maximum event messages */
  716. #define DBG_DATA_MAX 128UL
  717. /* Event buffer descriptor */
  718. static struct {
  719. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  720. unsigned idx; /* index */
  721. unsigned tty; /* print to console? */
  722. rwlock_t lck; /* lock */
  723. } dbg_data = {
  724. .idx = 0,
  725. .tty = 0,
  726. .lck = __RW_LOCK_UNLOCKED(lck)
  727. };
  728. /**
  729. * dbg_dec: decrements debug event index
  730. * @idx: buffer index
  731. */
  732. static void dbg_dec(unsigned *idx)
  733. {
  734. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  735. }
  736. /**
  737. * dbg_inc: increments debug event index
  738. * @idx: buffer index
  739. */
  740. static void dbg_inc(unsigned *idx)
  741. {
  742. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  743. }
  744. /**
  745. * dbg_print: prints the common part of the event
  746. * @addr: endpoint address
  747. * @name: event name
  748. * @status: status
  749. * @extra: extra information
  750. */
  751. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  752. {
  753. struct timeval tval;
  754. unsigned int stamp;
  755. unsigned long flags;
  756. write_lock_irqsave(&dbg_data.lck, flags);
  757. do_gettimeofday(&tval);
  758. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  759. stamp = stamp * 1000000 + tval.tv_usec;
  760. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  761. "%04X\t» %02X %-7.7s %4i «\t%s\n",
  762. stamp, addr, name, status, extra);
  763. dbg_inc(&dbg_data.idx);
  764. write_unlock_irqrestore(&dbg_data.lck, flags);
  765. if (dbg_data.tty != 0)
  766. pr_notice("%04X\t» %02X %-7.7s %4i «\t%s\n",
  767. stamp, addr, name, status, extra);
  768. }
  769. /**
  770. * dbg_done: prints a DONE event
  771. * @addr: endpoint address
  772. * @td: transfer descriptor
  773. * @status: status
  774. */
  775. static void dbg_done(u8 addr, const u32 token, int status)
  776. {
  777. char msg[DBG_DATA_MSG];
  778. scnprintf(msg, sizeof(msg), "%d %02X",
  779. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  780. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  781. dbg_print(addr, "DONE", status, msg);
  782. }
  783. /**
  784. * dbg_event: prints a generic event
  785. * @addr: endpoint address
  786. * @name: event name
  787. * @status: status
  788. */
  789. static void dbg_event(u8 addr, const char *name, int status)
  790. {
  791. if (name != NULL)
  792. dbg_print(addr, name, status, "");
  793. }
  794. /*
  795. * dbg_queue: prints a QUEUE event
  796. * @addr: endpoint address
  797. * @req: USB request
  798. * @status: status
  799. */
  800. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  801. {
  802. char msg[DBG_DATA_MSG];
  803. if (req != NULL) {
  804. scnprintf(msg, sizeof(msg),
  805. "%d %d", !req->no_interrupt, req->length);
  806. dbg_print(addr, "QUEUE", status, msg);
  807. }
  808. }
  809. /**
  810. * dbg_setup: prints a SETUP event
  811. * @addr: endpoint address
  812. * @req: setup request
  813. */
  814. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  815. {
  816. char msg[DBG_DATA_MSG];
  817. if (req != NULL) {
  818. scnprintf(msg, sizeof(msg),
  819. "%02X %02X %04X %04X %d", req->bRequestType,
  820. req->bRequest, le16_to_cpu(req->wValue),
  821. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  822. dbg_print(addr, "SETUP", 0, msg);
  823. }
  824. }
  825. /**
  826. * show_events: displays the event buffer
  827. *
  828. * Check "device.h" for details
  829. */
  830. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  831. char *buf)
  832. {
  833. unsigned long flags;
  834. unsigned i, j, n = 0;
  835. dbg_trace("[%s] %p\n", __func__, buf);
  836. if (attr == NULL || buf == NULL) {
  837. dev_err(dev, "[%s] EINVAL\n", __func__);
  838. return 0;
  839. }
  840. read_lock_irqsave(&dbg_data.lck, flags);
  841. i = dbg_data.idx;
  842. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  843. n += strlen(dbg_data.buf[i]);
  844. if (n >= PAGE_SIZE) {
  845. n -= strlen(dbg_data.buf[i]);
  846. break;
  847. }
  848. }
  849. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  850. j += scnprintf(buf + j, PAGE_SIZE - j,
  851. "%s", dbg_data.buf[i]);
  852. read_unlock_irqrestore(&dbg_data.lck, flags);
  853. return n;
  854. }
  855. /**
  856. * store_events: configure if events are going to be also printed to console
  857. *
  858. * Check "device.h" for details
  859. */
  860. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  861. const char *buf, size_t count)
  862. {
  863. unsigned tty;
  864. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  865. if (attr == NULL || buf == NULL) {
  866. dev_err(dev, "[%s] EINVAL\n", __func__);
  867. goto done;
  868. }
  869. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  870. dev_err(dev, "<1|0>: enable|disable console log\n");
  871. goto done;
  872. }
  873. dbg_data.tty = tty;
  874. dev_info(dev, "tty = %u", dbg_data.tty);
  875. done:
  876. return count;
  877. }
  878. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  879. /**
  880. * show_inters: interrupt status, enable status and historic
  881. *
  882. * Check "device.h" for details
  883. */
  884. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  885. char *buf)
  886. {
  887. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  888. unsigned long flags;
  889. u32 intr;
  890. unsigned i, j, n = 0;
  891. dbg_trace("[%s] %p\n", __func__, buf);
  892. if (attr == NULL || buf == NULL) {
  893. dev_err(dev, "[%s] EINVAL\n", __func__);
  894. return 0;
  895. }
  896. spin_lock_irqsave(udc->lock, flags);
  897. n += scnprintf(buf + n, PAGE_SIZE - n,
  898. "status = %08x\n", hw_read_intr_status());
  899. n += scnprintf(buf + n, PAGE_SIZE - n,
  900. "enable = %08x\n", hw_read_intr_enable());
  901. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  902. isr_statistics.test);
  903. n += scnprintf(buf + n, PAGE_SIZE - n, "» ui = %d\n",
  904. isr_statistics.ui);
  905. n += scnprintf(buf + n, PAGE_SIZE - n, "» uei = %d\n",
  906. isr_statistics.uei);
  907. n += scnprintf(buf + n, PAGE_SIZE - n, "» pci = %d\n",
  908. isr_statistics.pci);
  909. n += scnprintf(buf + n, PAGE_SIZE - n, "» uri = %d\n",
  910. isr_statistics.uri);
  911. n += scnprintf(buf + n, PAGE_SIZE - n, "» sli = %d\n",
  912. isr_statistics.sli);
  913. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  914. isr_statistics.none);
  915. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  916. isr_statistics.hndl.cnt);
  917. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  918. i &= ISR_MASK;
  919. intr = isr_statistics.hndl.buf[i];
  920. if (USBi_UI & intr)
  921. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  922. intr &= ~USBi_UI;
  923. if (USBi_UEI & intr)
  924. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  925. intr &= ~USBi_UEI;
  926. if (USBi_PCI & intr)
  927. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  928. intr &= ~USBi_PCI;
  929. if (USBi_URI & intr)
  930. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  931. intr &= ~USBi_URI;
  932. if (USBi_SLI & intr)
  933. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  934. intr &= ~USBi_SLI;
  935. if (intr)
  936. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  937. if (isr_statistics.hndl.buf[i])
  938. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  939. }
  940. spin_unlock_irqrestore(udc->lock, flags);
  941. return n;
  942. }
  943. /**
  944. * store_inters: enable & force or disable an individual interrutps
  945. * (to be used for test purposes only)
  946. *
  947. * Check "device.h" for details
  948. */
  949. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  950. const char *buf, size_t count)
  951. {
  952. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  953. unsigned long flags;
  954. unsigned en, bit;
  955. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  956. if (attr == NULL || buf == NULL) {
  957. dev_err(dev, "[%s] EINVAL\n", __func__);
  958. goto done;
  959. }
  960. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  961. dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
  962. goto done;
  963. }
  964. spin_lock_irqsave(udc->lock, flags);
  965. if (en) {
  966. if (hw_intr_force(bit))
  967. dev_err(dev, "invalid bit number\n");
  968. else
  969. isr_statistics.test++;
  970. } else {
  971. if (hw_intr_clear(bit))
  972. dev_err(dev, "invalid bit number\n");
  973. }
  974. spin_unlock_irqrestore(udc->lock, flags);
  975. done:
  976. return count;
  977. }
  978. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  979. /**
  980. * show_port_test: reads port test mode
  981. *
  982. * Check "device.h" for details
  983. */
  984. static ssize_t show_port_test(struct device *dev,
  985. struct device_attribute *attr, char *buf)
  986. {
  987. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  988. unsigned long flags;
  989. unsigned mode;
  990. dbg_trace("[%s] %p\n", __func__, buf);
  991. if (attr == NULL || buf == NULL) {
  992. dev_err(dev, "[%s] EINVAL\n", __func__);
  993. return 0;
  994. }
  995. spin_lock_irqsave(udc->lock, flags);
  996. mode = hw_port_test_get();
  997. spin_unlock_irqrestore(udc->lock, flags);
  998. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  999. }
  1000. /**
  1001. * store_port_test: writes port test mode
  1002. *
  1003. * Check "device.h" for details
  1004. */
  1005. static ssize_t store_port_test(struct device *dev,
  1006. struct device_attribute *attr,
  1007. const char *buf, size_t count)
  1008. {
  1009. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1010. unsigned long flags;
  1011. unsigned mode;
  1012. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1013. if (attr == NULL || buf == NULL) {
  1014. dev_err(dev, "[%s] EINVAL\n", __func__);
  1015. goto done;
  1016. }
  1017. if (sscanf(buf, "%u", &mode) != 1) {
  1018. dev_err(dev, "<mode>: set port test mode");
  1019. goto done;
  1020. }
  1021. spin_lock_irqsave(udc->lock, flags);
  1022. if (hw_port_test_set(mode))
  1023. dev_err(dev, "invalid mode\n");
  1024. spin_unlock_irqrestore(udc->lock, flags);
  1025. done:
  1026. return count;
  1027. }
  1028. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1029. show_port_test, store_port_test);
  1030. /**
  1031. * show_qheads: DMA contents of all queue heads
  1032. *
  1033. * Check "device.h" for details
  1034. */
  1035. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1036. char *buf)
  1037. {
  1038. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1039. unsigned long flags;
  1040. unsigned i, j, n = 0;
  1041. dbg_trace("[%s] %p\n", __func__, buf);
  1042. if (attr == NULL || buf == NULL) {
  1043. dev_err(dev, "[%s] EINVAL\n", __func__);
  1044. return 0;
  1045. }
  1046. spin_lock_irqsave(udc->lock, flags);
  1047. for (i = 0; i < hw_ep_max/2; i++) {
  1048. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1049. struct ci13xxx_ep *mEpTx = &udc->ci13xxx_ep[i + hw_ep_max/2];
  1050. n += scnprintf(buf + n, PAGE_SIZE - n,
  1051. "EP=%02i: RX=%08X TX=%08X\n",
  1052. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1053. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1054. n += scnprintf(buf + n, PAGE_SIZE - n,
  1055. " %04X: %08X %08X\n", j,
  1056. *((u32 *)mEpRx->qh.ptr + j),
  1057. *((u32 *)mEpTx->qh.ptr + j));
  1058. }
  1059. }
  1060. spin_unlock_irqrestore(udc->lock, flags);
  1061. return n;
  1062. }
  1063. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1064. /**
  1065. * show_registers: dumps all registers
  1066. *
  1067. * Check "device.h" for details
  1068. */
  1069. static ssize_t show_registers(struct device *dev,
  1070. struct device_attribute *attr, char *buf)
  1071. {
  1072. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1073. unsigned long flags;
  1074. u32 dump[512];
  1075. unsigned i, k, n = 0;
  1076. dbg_trace("[%s] %p\n", __func__, buf);
  1077. if (attr == NULL || buf == NULL) {
  1078. dev_err(dev, "[%s] EINVAL\n", __func__);
  1079. return 0;
  1080. }
  1081. spin_lock_irqsave(udc->lock, flags);
  1082. k = hw_register_read(dump, sizeof(dump)/sizeof(u32));
  1083. spin_unlock_irqrestore(udc->lock, flags);
  1084. for (i = 0; i < k; i++) {
  1085. n += scnprintf(buf + n, PAGE_SIZE - n,
  1086. "reg[0x%04X] = 0x%08X\n",
  1087. i * (unsigned)sizeof(u32), dump[i]);
  1088. }
  1089. return n;
  1090. }
  1091. /**
  1092. * store_registers: writes value to register address
  1093. *
  1094. * Check "device.h" for details
  1095. */
  1096. static ssize_t store_registers(struct device *dev,
  1097. struct device_attribute *attr,
  1098. const char *buf, size_t count)
  1099. {
  1100. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1101. unsigned long addr, data, flags;
  1102. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1103. if (attr == NULL || buf == NULL) {
  1104. dev_err(dev, "[%s] EINVAL\n", __func__);
  1105. goto done;
  1106. }
  1107. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1108. dev_err(dev, "<addr> <data>: write data to register address");
  1109. goto done;
  1110. }
  1111. spin_lock_irqsave(udc->lock, flags);
  1112. if (hw_register_write(addr, data))
  1113. dev_err(dev, "invalid address range\n");
  1114. spin_unlock_irqrestore(udc->lock, flags);
  1115. done:
  1116. return count;
  1117. }
  1118. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1119. show_registers, store_registers);
  1120. /**
  1121. * show_requests: DMA contents of all requests currently queued (all endpts)
  1122. *
  1123. * Check "device.h" for details
  1124. */
  1125. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1126. char *buf)
  1127. {
  1128. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1129. unsigned long flags;
  1130. struct list_head *ptr = NULL;
  1131. struct ci13xxx_req *req = NULL;
  1132. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1133. dbg_trace("[%s] %p\n", __func__, buf);
  1134. if (attr == NULL || buf == NULL) {
  1135. dev_err(dev, "[%s] EINVAL\n", __func__);
  1136. return 0;
  1137. }
  1138. spin_lock_irqsave(udc->lock, flags);
  1139. for (i = 0; i < hw_ep_max; i++)
  1140. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1141. {
  1142. req = list_entry(ptr, struct ci13xxx_req, queue);
  1143. n += scnprintf(buf + n, PAGE_SIZE - n,
  1144. "EP=%02i: TD=%08X %s\n",
  1145. i % hw_ep_max/2, (u32)req->dma,
  1146. ((i < hw_ep_max/2) ? "RX" : "TX"));
  1147. for (j = 0; j < qSize; j++)
  1148. n += scnprintf(buf + n, PAGE_SIZE - n,
  1149. " %04X: %08X\n", j,
  1150. *((u32 *)req->ptr + j));
  1151. }
  1152. spin_unlock_irqrestore(udc->lock, flags);
  1153. return n;
  1154. }
  1155. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1156. /**
  1157. * dbg_create_files: initializes the attribute interface
  1158. * @dev: device
  1159. *
  1160. * This function returns an error code
  1161. */
  1162. __maybe_unused static int dbg_create_files(struct device *dev)
  1163. {
  1164. int retval = 0;
  1165. if (dev == NULL)
  1166. return -EINVAL;
  1167. retval = device_create_file(dev, &dev_attr_device);
  1168. if (retval)
  1169. goto done;
  1170. retval = device_create_file(dev, &dev_attr_driver);
  1171. if (retval)
  1172. goto rm_device;
  1173. retval = device_create_file(dev, &dev_attr_events);
  1174. if (retval)
  1175. goto rm_driver;
  1176. retval = device_create_file(dev, &dev_attr_inters);
  1177. if (retval)
  1178. goto rm_events;
  1179. retval = device_create_file(dev, &dev_attr_port_test);
  1180. if (retval)
  1181. goto rm_inters;
  1182. retval = device_create_file(dev, &dev_attr_qheads);
  1183. if (retval)
  1184. goto rm_port_test;
  1185. retval = device_create_file(dev, &dev_attr_registers);
  1186. if (retval)
  1187. goto rm_qheads;
  1188. retval = device_create_file(dev, &dev_attr_requests);
  1189. if (retval)
  1190. goto rm_registers;
  1191. return 0;
  1192. rm_registers:
  1193. device_remove_file(dev, &dev_attr_registers);
  1194. rm_qheads:
  1195. device_remove_file(dev, &dev_attr_qheads);
  1196. rm_port_test:
  1197. device_remove_file(dev, &dev_attr_port_test);
  1198. rm_inters:
  1199. device_remove_file(dev, &dev_attr_inters);
  1200. rm_events:
  1201. device_remove_file(dev, &dev_attr_events);
  1202. rm_driver:
  1203. device_remove_file(dev, &dev_attr_driver);
  1204. rm_device:
  1205. device_remove_file(dev, &dev_attr_device);
  1206. done:
  1207. return retval;
  1208. }
  1209. /**
  1210. * dbg_remove_files: destroys the attribute interface
  1211. * @dev: device
  1212. *
  1213. * This function returns an error code
  1214. */
  1215. __maybe_unused static int dbg_remove_files(struct device *dev)
  1216. {
  1217. if (dev == NULL)
  1218. return -EINVAL;
  1219. device_remove_file(dev, &dev_attr_requests);
  1220. device_remove_file(dev, &dev_attr_registers);
  1221. device_remove_file(dev, &dev_attr_qheads);
  1222. device_remove_file(dev, &dev_attr_port_test);
  1223. device_remove_file(dev, &dev_attr_inters);
  1224. device_remove_file(dev, &dev_attr_events);
  1225. device_remove_file(dev, &dev_attr_driver);
  1226. device_remove_file(dev, &dev_attr_device);
  1227. return 0;
  1228. }
  1229. /******************************************************************************
  1230. * UTIL block
  1231. *****************************************************************************/
  1232. /**
  1233. * _usb_addr: calculates endpoint address from direction & number
  1234. * @ep: endpoint
  1235. */
  1236. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1237. {
  1238. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1239. }
  1240. /**
  1241. * _hardware_queue: configures a request at hardware level
  1242. * @gadget: gadget
  1243. * @mEp: endpoint
  1244. *
  1245. * This function returns an error code
  1246. */
  1247. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1248. {
  1249. unsigned i;
  1250. trace("%p, %p", mEp, mReq);
  1251. /* don't queue twice */
  1252. if (mReq->req.status == -EALREADY)
  1253. return -EALREADY;
  1254. if (hw_ep_is_primed(mEp->num, mEp->dir))
  1255. return -EBUSY;
  1256. mReq->req.status = -EALREADY;
  1257. if (mReq->req.length && !mReq->req.dma) {
  1258. mReq->req.dma = \
  1259. dma_map_single(mEp->device, mReq->req.buf,
  1260. mReq->req.length, mEp->dir ?
  1261. DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1262. if (mReq->req.dma == 0)
  1263. return -ENOMEM;
  1264. mReq->map = 1;
  1265. }
  1266. /*
  1267. * TD configuration
  1268. * TODO - handle requests which spawns into several TDs
  1269. */
  1270. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1271. mReq->ptr->next |= TD_TERMINATE;
  1272. mReq->ptr->token = mReq->req.length << ffs_nr(TD_TOTAL_BYTES);
  1273. mReq->ptr->token &= TD_TOTAL_BYTES;
  1274. mReq->ptr->token |= TD_IOC;
  1275. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1276. mReq->ptr->page[0] = mReq->req.dma;
  1277. for (i = 1; i < 5; i++)
  1278. mReq->ptr->page[i] =
  1279. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1280. /*
  1281. * QH configuration
  1282. * At this point it's guaranteed exclusive access to qhead
  1283. * (endpt is not primed) so it's no need to use tripwire
  1284. */
  1285. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1286. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1287. if (mReq->req.zero == 0)
  1288. mEp->qh.ptr->cap |= QH_ZLT;
  1289. else
  1290. mEp->qh.ptr->cap &= ~QH_ZLT;
  1291. wmb(); /* synchronize before ep prime */
  1292. return hw_ep_prime(mEp->num, mEp->dir,
  1293. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1294. }
  1295. /**
  1296. * _hardware_dequeue: handles a request at hardware level
  1297. * @gadget: gadget
  1298. * @mEp: endpoint
  1299. *
  1300. * This function returns an error code
  1301. */
  1302. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1303. {
  1304. trace("%p, %p", mEp, mReq);
  1305. if (mReq->req.status != -EALREADY)
  1306. return -EINVAL;
  1307. if (hw_ep_is_primed(mEp->num, mEp->dir))
  1308. hw_ep_flush(mEp->num, mEp->dir);
  1309. mReq->req.status = 0;
  1310. if (mReq->map) {
  1311. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1312. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1313. mReq->req.dma = 0;
  1314. mReq->map = 0;
  1315. }
  1316. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1317. if ((TD_STATUS_ACTIVE & mReq->req.status) != 0)
  1318. mReq->req.status = -ECONNRESET;
  1319. else if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1320. mReq->req.status = -1;
  1321. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1322. mReq->req.status = -1;
  1323. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1324. mReq->req.status = -1;
  1325. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1326. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1327. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1328. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1329. return mReq->req.actual;
  1330. }
  1331. /**
  1332. * _ep_nuke: dequeues all endpoint requests
  1333. * @mEp: endpoint
  1334. *
  1335. * This function returns an error code
  1336. * Caller must hold lock
  1337. */
  1338. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1339. __releases(mEp->lock)
  1340. __acquires(mEp->lock)
  1341. {
  1342. trace("%p", mEp);
  1343. if (mEp == NULL)
  1344. return -EINVAL;
  1345. hw_ep_flush(mEp->num, mEp->dir);
  1346. while (!list_empty(&mEp->qh.queue)) {
  1347. /* pop oldest request */
  1348. struct ci13xxx_req *mReq = \
  1349. list_entry(mEp->qh.queue.next,
  1350. struct ci13xxx_req, queue);
  1351. list_del_init(&mReq->queue);
  1352. mReq->req.status = -ESHUTDOWN;
  1353. if (mReq->req.complete != NULL) {
  1354. spin_unlock(mEp->lock);
  1355. mReq->req.complete(&mEp->ep, &mReq->req);
  1356. spin_lock(mEp->lock);
  1357. }
  1358. }
  1359. return 0;
  1360. }
  1361. /**
  1362. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1363. * @gadget: gadget
  1364. *
  1365. * This function returns an error code
  1366. * Caller must hold lock
  1367. */
  1368. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1369. {
  1370. struct usb_ep *ep;
  1371. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1372. trace("%p", gadget);
  1373. if (gadget == NULL)
  1374. return -EINVAL;
  1375. /* flush all endpoints */
  1376. gadget_for_each_ep(ep, gadget) {
  1377. usb_ep_fifo_flush(ep);
  1378. }
  1379. usb_ep_fifo_flush(&udc->ep0out.ep);
  1380. usb_ep_fifo_flush(&udc->ep0in.ep);
  1381. udc->driver->disconnect(gadget);
  1382. /* make sure to disable all endpoints */
  1383. gadget_for_each_ep(ep, gadget) {
  1384. usb_ep_disable(ep);
  1385. }
  1386. usb_ep_disable(&udc->ep0out.ep);
  1387. usb_ep_disable(&udc->ep0in.ep);
  1388. if (udc->status != NULL) {
  1389. usb_ep_free_request(&udc->ep0in.ep, udc->status);
  1390. udc->status = NULL;
  1391. }
  1392. return 0;
  1393. }
  1394. /******************************************************************************
  1395. * ISR block
  1396. *****************************************************************************/
  1397. /**
  1398. * isr_reset_handler: USB reset interrupt handler
  1399. * @udc: UDC device
  1400. *
  1401. * This function resets USB engine after a bus reset occurred
  1402. */
  1403. static void isr_reset_handler(struct ci13xxx *udc)
  1404. __releases(udc->lock)
  1405. __acquires(udc->lock)
  1406. {
  1407. int retval;
  1408. trace("%p", udc);
  1409. if (udc == NULL) {
  1410. err("EINVAL");
  1411. return;
  1412. }
  1413. dbg_event(0xFF, "BUS RST", 0);
  1414. spin_unlock(udc->lock);
  1415. retval = _gadget_stop_activity(&udc->gadget);
  1416. if (retval)
  1417. goto done;
  1418. retval = hw_usb_reset();
  1419. if (retval)
  1420. goto done;
  1421. retval = usb_ep_enable(&udc->ep0out.ep, &ctrl_endpt_out_desc);
  1422. if (retval)
  1423. goto done;
  1424. retval = usb_ep_enable(&udc->ep0in.ep, &ctrl_endpt_in_desc);
  1425. if (!retval) {
  1426. udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
  1427. if (udc->status == NULL) {
  1428. usb_ep_disable(&udc->ep0out.ep);
  1429. retval = -ENOMEM;
  1430. }
  1431. }
  1432. spin_lock(udc->lock);
  1433. done:
  1434. if (retval)
  1435. err("error: %i", retval);
  1436. }
  1437. /**
  1438. * isr_get_status_complete: get_status request complete function
  1439. * @ep: endpoint
  1440. * @req: request handled
  1441. *
  1442. * Caller must release lock
  1443. */
  1444. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1445. {
  1446. trace("%p, %p", ep, req);
  1447. if (ep == NULL || req == NULL) {
  1448. err("EINVAL");
  1449. return;
  1450. }
  1451. kfree(req->buf);
  1452. usb_ep_free_request(ep, req);
  1453. }
  1454. /**
  1455. * isr_get_status_response: get_status request response
  1456. * @udc: udc struct
  1457. * @setup: setup request packet
  1458. *
  1459. * This function returns an error code
  1460. */
  1461. static int isr_get_status_response(struct ci13xxx *udc,
  1462. struct usb_ctrlrequest *setup)
  1463. __releases(mEp->lock)
  1464. __acquires(mEp->lock)
  1465. {
  1466. struct ci13xxx_ep *mEp = &udc->ep0in;
  1467. struct usb_request *req = NULL;
  1468. gfp_t gfp_flags = GFP_ATOMIC;
  1469. int dir, num, retval;
  1470. trace("%p, %p", mEp, setup);
  1471. if (mEp == NULL || setup == NULL)
  1472. return -EINVAL;
  1473. spin_unlock(mEp->lock);
  1474. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1475. spin_lock(mEp->lock);
  1476. if (req == NULL)
  1477. return -ENOMEM;
  1478. req->complete = isr_get_status_complete;
  1479. req->length = 2;
  1480. req->buf = kzalloc(req->length, gfp_flags);
  1481. if (req->buf == NULL) {
  1482. retval = -ENOMEM;
  1483. goto err_free_req;
  1484. }
  1485. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1486. /* TODO: D1 - Remote Wakeup; D0 - Self Powered */
  1487. retval = 0;
  1488. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1489. == USB_RECIP_ENDPOINT) {
  1490. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1491. TX : RX;
  1492. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1493. *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
  1494. }
  1495. /* else do nothing; reserved for future use */
  1496. spin_unlock(mEp->lock);
  1497. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1498. spin_lock(mEp->lock);
  1499. if (retval)
  1500. goto err_free_buf;
  1501. return 0;
  1502. err_free_buf:
  1503. kfree(req->buf);
  1504. err_free_req:
  1505. spin_unlock(mEp->lock);
  1506. usb_ep_free_request(&mEp->ep, req);
  1507. spin_lock(mEp->lock);
  1508. return retval;
  1509. }
  1510. /**
  1511. * isr_setup_status_phase: queues the status phase of a setup transation
  1512. * @udc: udc struct
  1513. *
  1514. * This function returns an error code
  1515. */
  1516. static int isr_setup_status_phase(struct ci13xxx *udc)
  1517. __releases(mEp->lock)
  1518. __acquires(mEp->lock)
  1519. {
  1520. int retval;
  1521. struct ci13xxx_ep *mEp;
  1522. trace("%p", udc);
  1523. mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
  1524. spin_unlock(mEp->lock);
  1525. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1526. spin_lock(mEp->lock);
  1527. return retval;
  1528. }
  1529. /**
  1530. * isr_tr_complete_low: transaction complete low level handler
  1531. * @mEp: endpoint
  1532. *
  1533. * This function returns an error code
  1534. * Caller must hold lock
  1535. */
  1536. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1537. __releases(mEp->lock)
  1538. __acquires(mEp->lock)
  1539. {
  1540. struct ci13xxx_req *mReq;
  1541. int retval;
  1542. trace("%p", mEp);
  1543. if (list_empty(&mEp->qh.queue))
  1544. return -EINVAL;
  1545. /* pop oldest request */
  1546. mReq = list_entry(mEp->qh.queue.next,
  1547. struct ci13xxx_req, queue);
  1548. list_del_init(&mReq->queue);
  1549. retval = _hardware_dequeue(mEp, mReq);
  1550. if (retval < 0) {
  1551. dbg_event(_usb_addr(mEp), "DONE", retval);
  1552. goto done;
  1553. }
  1554. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1555. if (!list_empty(&mEp->qh.queue)) {
  1556. struct ci13xxx_req* mReqEnq;
  1557. mReqEnq = list_entry(mEp->qh.queue.next,
  1558. struct ci13xxx_req, queue);
  1559. _hardware_enqueue(mEp, mReqEnq);
  1560. }
  1561. if (mReq->req.complete != NULL) {
  1562. spin_unlock(mEp->lock);
  1563. mReq->req.complete(&mEp->ep, &mReq->req);
  1564. spin_lock(mEp->lock);
  1565. }
  1566. done:
  1567. return retval;
  1568. }
  1569. /**
  1570. * isr_tr_complete_handler: transaction complete interrupt handler
  1571. * @udc: UDC descriptor
  1572. *
  1573. * This function handles traffic events
  1574. */
  1575. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1576. __releases(udc->lock)
  1577. __acquires(udc->lock)
  1578. {
  1579. unsigned i;
  1580. trace("%p", udc);
  1581. if (udc == NULL) {
  1582. err("EINVAL");
  1583. return;
  1584. }
  1585. for (i = 0; i < hw_ep_max; i++) {
  1586. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1587. int type, num, err = -EINVAL;
  1588. struct usb_ctrlrequest req;
  1589. if (mEp->desc == NULL)
  1590. continue; /* not configured */
  1591. if (hw_test_and_clear_complete(i)) {
  1592. err = isr_tr_complete_low(mEp);
  1593. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1594. if (err > 0) /* needs status phase */
  1595. err = isr_setup_status_phase(udc);
  1596. if (err < 0) {
  1597. dbg_event(_usb_addr(mEp),
  1598. "ERROR", err);
  1599. spin_unlock(udc->lock);
  1600. if (usb_ep_set_halt(&mEp->ep))
  1601. err("error: ep_set_halt");
  1602. spin_lock(udc->lock);
  1603. }
  1604. }
  1605. }
  1606. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1607. !hw_test_and_clear_setup_status(i))
  1608. continue;
  1609. if (i != 0) {
  1610. warn("ctrl traffic received at endpoint");
  1611. continue;
  1612. }
  1613. /*
  1614. * Flush data and handshake transactions of previous
  1615. * setup packet.
  1616. */
  1617. _ep_nuke(&udc->ep0out);
  1618. _ep_nuke(&udc->ep0in);
  1619. /* read_setup_packet */
  1620. do {
  1621. hw_test_and_set_setup_guard();
  1622. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1623. } while (!hw_test_and_clear_setup_guard());
  1624. type = req.bRequestType;
  1625. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1626. dbg_setup(_usb_addr(mEp), &req);
  1627. switch (req.bRequest) {
  1628. case USB_REQ_CLEAR_FEATURE:
  1629. if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1630. le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
  1631. goto delegate;
  1632. if (req.wLength != 0)
  1633. break;
  1634. num = le16_to_cpu(req.wIndex);
  1635. num &= USB_ENDPOINT_NUMBER_MASK;
  1636. if (!udc->ci13xxx_ep[num].wedge) {
  1637. spin_unlock(udc->lock);
  1638. err = usb_ep_clear_halt(
  1639. &udc->ci13xxx_ep[num].ep);
  1640. spin_lock(udc->lock);
  1641. if (err)
  1642. break;
  1643. }
  1644. err = isr_setup_status_phase(udc);
  1645. break;
  1646. case USB_REQ_GET_STATUS:
  1647. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1648. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1649. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1650. goto delegate;
  1651. if (le16_to_cpu(req.wLength) != 2 ||
  1652. le16_to_cpu(req.wValue) != 0)
  1653. break;
  1654. err = isr_get_status_response(udc, &req);
  1655. break;
  1656. case USB_REQ_SET_ADDRESS:
  1657. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1658. goto delegate;
  1659. if (le16_to_cpu(req.wLength) != 0 ||
  1660. le16_to_cpu(req.wIndex) != 0)
  1661. break;
  1662. err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
  1663. if (err)
  1664. break;
  1665. err = isr_setup_status_phase(udc);
  1666. break;
  1667. case USB_REQ_SET_FEATURE:
  1668. if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1669. le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
  1670. goto delegate;
  1671. if (req.wLength != 0)
  1672. break;
  1673. num = le16_to_cpu(req.wIndex);
  1674. num &= USB_ENDPOINT_NUMBER_MASK;
  1675. spin_unlock(udc->lock);
  1676. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1677. spin_lock(udc->lock);
  1678. if (err)
  1679. break;
  1680. err = isr_setup_status_phase(udc);
  1681. break;
  1682. default:
  1683. delegate:
  1684. if (req.wLength == 0) /* no data phase */
  1685. udc->ep0_dir = TX;
  1686. spin_unlock(udc->lock);
  1687. err = udc->driver->setup(&udc->gadget, &req);
  1688. spin_lock(udc->lock);
  1689. break;
  1690. }
  1691. if (err < 0) {
  1692. dbg_event(_usb_addr(mEp), "ERROR", err);
  1693. spin_unlock(udc->lock);
  1694. if (usb_ep_set_halt(&mEp->ep))
  1695. err("error: ep_set_halt");
  1696. spin_lock(udc->lock);
  1697. }
  1698. }
  1699. }
  1700. /******************************************************************************
  1701. * ENDPT block
  1702. *****************************************************************************/
  1703. /**
  1704. * ep_enable: configure endpoint, making it usable
  1705. *
  1706. * Check usb_ep_enable() at "usb_gadget.h" for details
  1707. */
  1708. static int ep_enable(struct usb_ep *ep,
  1709. const struct usb_endpoint_descriptor *desc)
  1710. {
  1711. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1712. int retval = 0;
  1713. unsigned long flags;
  1714. trace("%p, %p", ep, desc);
  1715. if (ep == NULL || desc == NULL)
  1716. return -EINVAL;
  1717. spin_lock_irqsave(mEp->lock, flags);
  1718. /* only internal SW should enable ctrl endpts */
  1719. mEp->desc = desc;
  1720. if (!list_empty(&mEp->qh.queue))
  1721. warn("enabling a non-empty endpoint!");
  1722. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1723. mEp->num = usb_endpoint_num(desc);
  1724. mEp->type = usb_endpoint_type(desc);
  1725. mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
  1726. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1727. mEp->qh.ptr->cap = 0;
  1728. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1729. mEp->qh.ptr->cap |= QH_IOS;
  1730. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1731. mEp->qh.ptr->cap &= ~QH_MULT;
  1732. else
  1733. mEp->qh.ptr->cap &= ~QH_ZLT;
  1734. mEp->qh.ptr->cap |=
  1735. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1736. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1737. retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
  1738. spin_unlock_irqrestore(mEp->lock, flags);
  1739. return retval;
  1740. }
  1741. /**
  1742. * ep_disable: endpoint is no longer usable
  1743. *
  1744. * Check usb_ep_disable() at "usb_gadget.h" for details
  1745. */
  1746. static int ep_disable(struct usb_ep *ep)
  1747. {
  1748. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1749. int direction, retval = 0;
  1750. unsigned long flags;
  1751. trace("%p", ep);
  1752. if (ep == NULL)
  1753. return -EINVAL;
  1754. else if (mEp->desc == NULL)
  1755. return -EBUSY;
  1756. spin_lock_irqsave(mEp->lock, flags);
  1757. /* only internal SW should disable ctrl endpts */
  1758. direction = mEp->dir;
  1759. do {
  1760. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1761. retval |= _ep_nuke(mEp);
  1762. retval |= hw_ep_disable(mEp->num, mEp->dir);
  1763. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1764. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1765. } while (mEp->dir != direction);
  1766. mEp->desc = NULL;
  1767. spin_unlock_irqrestore(mEp->lock, flags);
  1768. return retval;
  1769. }
  1770. /**
  1771. * ep_alloc_request: allocate a request object to use with this endpoint
  1772. *
  1773. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1774. */
  1775. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1776. {
  1777. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1778. struct ci13xxx_req *mReq = NULL;
  1779. trace("%p, %i", ep, gfp_flags);
  1780. if (ep == NULL) {
  1781. err("EINVAL");
  1782. return NULL;
  1783. }
  1784. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1785. if (mReq != NULL) {
  1786. INIT_LIST_HEAD(&mReq->queue);
  1787. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1788. &mReq->dma);
  1789. if (mReq->ptr == NULL) {
  1790. kfree(mReq);
  1791. mReq = NULL;
  1792. }
  1793. }
  1794. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1795. return (mReq == NULL) ? NULL : &mReq->req;
  1796. }
  1797. /**
  1798. * ep_free_request: frees a request object
  1799. *
  1800. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1801. */
  1802. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1803. {
  1804. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1805. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1806. unsigned long flags;
  1807. trace("%p, %p", ep, req);
  1808. if (ep == NULL || req == NULL) {
  1809. err("EINVAL");
  1810. return;
  1811. } else if (!list_empty(&mReq->queue)) {
  1812. err("EBUSY");
  1813. return;
  1814. }
  1815. spin_lock_irqsave(mEp->lock, flags);
  1816. if (mReq->ptr)
  1817. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1818. kfree(mReq);
  1819. dbg_event(_usb_addr(mEp), "FREE", 0);
  1820. spin_unlock_irqrestore(mEp->lock, flags);
  1821. }
  1822. /**
  1823. * ep_queue: queues (submits) an I/O request to an endpoint
  1824. *
  1825. * Check usb_ep_queue()* at usb_gadget.h" for details
  1826. */
  1827. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1828. gfp_t __maybe_unused gfp_flags)
  1829. {
  1830. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1831. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1832. int retval = 0;
  1833. unsigned long flags;
  1834. trace("%p, %p, %X", ep, req, gfp_flags);
  1835. if (ep == NULL || req == NULL || mEp->desc == NULL)
  1836. return -EINVAL;
  1837. spin_lock_irqsave(mEp->lock, flags);
  1838. if (mEp->type == USB_ENDPOINT_XFER_CONTROL &&
  1839. !list_empty(&mEp->qh.queue)) {
  1840. _ep_nuke(mEp);
  1841. retval = -EOVERFLOW;
  1842. warn("endpoint ctrl %X nuked", _usb_addr(mEp));
  1843. }
  1844. /* first nuke then test link, e.g. previous status has not sent */
  1845. if (!list_empty(&mReq->queue)) {
  1846. retval = -EBUSY;
  1847. err("request already in queue");
  1848. goto done;
  1849. }
  1850. if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
  1851. req->length = (4 * CI13XXX_PAGE_SIZE);
  1852. retval = -EMSGSIZE;
  1853. warn("request length truncated");
  1854. }
  1855. dbg_queue(_usb_addr(mEp), req, retval);
  1856. /* push request */
  1857. mReq->req.status = -EINPROGRESS;
  1858. mReq->req.actual = 0;
  1859. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1860. if (list_is_singular(&mEp->qh.queue))
  1861. retval = _hardware_enqueue(mEp, mReq);
  1862. if (retval == -EALREADY) {
  1863. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1864. retval = 0;
  1865. }
  1866. done:
  1867. spin_unlock_irqrestore(mEp->lock, flags);
  1868. return retval;
  1869. }
  1870. /**
  1871. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1872. *
  1873. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1874. */
  1875. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1876. {
  1877. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1878. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1879. unsigned long flags;
  1880. trace("%p, %p", ep, req);
  1881. if (ep == NULL || req == NULL || mEp->desc == NULL ||
  1882. list_empty(&mReq->queue) || list_empty(&mEp->qh.queue))
  1883. return -EINVAL;
  1884. spin_lock_irqsave(mEp->lock, flags);
  1885. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  1886. if (mReq->req.status == -EALREADY)
  1887. _hardware_dequeue(mEp, mReq);
  1888. /* pop request */
  1889. list_del_init(&mReq->queue);
  1890. req->status = -ECONNRESET;
  1891. if (mReq->req.complete != NULL) {
  1892. spin_unlock(mEp->lock);
  1893. mReq->req.complete(&mEp->ep, &mReq->req);
  1894. spin_lock(mEp->lock);
  1895. }
  1896. spin_unlock_irqrestore(mEp->lock, flags);
  1897. return 0;
  1898. }
  1899. /**
  1900. * ep_set_halt: sets the endpoint halt feature
  1901. *
  1902. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  1903. */
  1904. static int ep_set_halt(struct usb_ep *ep, int value)
  1905. {
  1906. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1907. int direction, retval = 0;
  1908. unsigned long flags;
  1909. trace("%p, %i", ep, value);
  1910. if (ep == NULL || mEp->desc == NULL)
  1911. return -EINVAL;
  1912. spin_lock_irqsave(mEp->lock, flags);
  1913. #ifndef STALL_IN
  1914. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  1915. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  1916. !list_empty(&mEp->qh.queue)) {
  1917. spin_unlock_irqrestore(mEp->lock, flags);
  1918. return -EAGAIN;
  1919. }
  1920. #endif
  1921. direction = mEp->dir;
  1922. do {
  1923. dbg_event(_usb_addr(mEp), "HALT", value);
  1924. retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
  1925. if (!value)
  1926. mEp->wedge = 0;
  1927. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1928. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1929. } while (mEp->dir != direction);
  1930. spin_unlock_irqrestore(mEp->lock, flags);
  1931. return retval;
  1932. }
  1933. /**
  1934. * ep_set_wedge: sets the halt feature and ignores clear requests
  1935. *
  1936. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  1937. */
  1938. static int ep_set_wedge(struct usb_ep *ep)
  1939. {
  1940. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1941. unsigned long flags;
  1942. trace("%p", ep);
  1943. if (ep == NULL || mEp->desc == NULL)
  1944. return -EINVAL;
  1945. spin_lock_irqsave(mEp->lock, flags);
  1946. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  1947. mEp->wedge = 1;
  1948. spin_unlock_irqrestore(mEp->lock, flags);
  1949. return usb_ep_set_halt(ep);
  1950. }
  1951. /**
  1952. * ep_fifo_flush: flushes contents of a fifo
  1953. *
  1954. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  1955. */
  1956. static void ep_fifo_flush(struct usb_ep *ep)
  1957. {
  1958. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1959. unsigned long flags;
  1960. trace("%p", ep);
  1961. if (ep == NULL) {
  1962. err("%02X: -EINVAL", _usb_addr(mEp));
  1963. return;
  1964. }
  1965. spin_lock_irqsave(mEp->lock, flags);
  1966. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  1967. hw_ep_flush(mEp->num, mEp->dir);
  1968. spin_unlock_irqrestore(mEp->lock, flags);
  1969. }
  1970. /**
  1971. * Endpoint-specific part of the API to the USB controller hardware
  1972. * Check "usb_gadget.h" for details
  1973. */
  1974. static const struct usb_ep_ops usb_ep_ops = {
  1975. .enable = ep_enable,
  1976. .disable = ep_disable,
  1977. .alloc_request = ep_alloc_request,
  1978. .free_request = ep_free_request,
  1979. .queue = ep_queue,
  1980. .dequeue = ep_dequeue,
  1981. .set_halt = ep_set_halt,
  1982. .set_wedge = ep_set_wedge,
  1983. .fifo_flush = ep_fifo_flush,
  1984. };
  1985. /******************************************************************************
  1986. * GADGET block
  1987. *****************************************************************************/
  1988. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  1989. {
  1990. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  1991. unsigned long flags;
  1992. int gadget_ready = 0;
  1993. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  1994. return -EOPNOTSUPP;
  1995. spin_lock_irqsave(udc->lock, flags);
  1996. udc->vbus_active = is_active;
  1997. if (udc->driver)
  1998. gadget_ready = 1;
  1999. spin_unlock_irqrestore(udc->lock, flags);
  2000. if (gadget_ready) {
  2001. if (is_active) {
  2002. pm_runtime_get_sync(&_gadget->dev);
  2003. hw_device_reset(udc);
  2004. hw_device_state(udc->ep0out.qh.dma);
  2005. } else {
  2006. hw_device_state(0);
  2007. if (udc->udc_driver->notify_event)
  2008. udc->udc_driver->notify_event(udc,
  2009. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2010. _gadget_stop_activity(&udc->gadget);
  2011. pm_runtime_put_sync(&_gadget->dev);
  2012. }
  2013. }
  2014. return 0;
  2015. }
  2016. /**
  2017. * Device operations part of the API to the USB controller hardware,
  2018. * which don't involve endpoints (or i/o)
  2019. * Check "usb_gadget.h" for details
  2020. */
  2021. static const struct usb_gadget_ops usb_gadget_ops = {
  2022. .vbus_session = ci13xxx_vbus_session,
  2023. };
  2024. /**
  2025. * usb_gadget_probe_driver: register a gadget driver
  2026. * @driver: the driver being registered
  2027. * @bind: the driver's bind callback
  2028. *
  2029. * Check usb_gadget_probe_driver() at <linux/usb/gadget.h> for details.
  2030. * Interrupts are enabled here.
  2031. */
  2032. int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
  2033. int (*bind)(struct usb_gadget *))
  2034. {
  2035. struct ci13xxx *udc = _udc;
  2036. unsigned long flags;
  2037. int i, j;
  2038. int retval = -ENOMEM;
  2039. trace("%p", driver);
  2040. if (driver == NULL ||
  2041. bind == NULL ||
  2042. driver->setup == NULL ||
  2043. driver->disconnect == NULL ||
  2044. driver->suspend == NULL ||
  2045. driver->resume == NULL)
  2046. return -EINVAL;
  2047. else if (udc == NULL)
  2048. return -ENODEV;
  2049. else if (udc->driver != NULL)
  2050. return -EBUSY;
  2051. /* alloc resources */
  2052. udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
  2053. sizeof(struct ci13xxx_qh),
  2054. 64, CI13XXX_PAGE_SIZE);
  2055. if (udc->qh_pool == NULL)
  2056. return -ENOMEM;
  2057. udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
  2058. sizeof(struct ci13xxx_td),
  2059. 64, CI13XXX_PAGE_SIZE);
  2060. if (udc->td_pool == NULL) {
  2061. dma_pool_destroy(udc->qh_pool);
  2062. udc->qh_pool = NULL;
  2063. return -ENOMEM;
  2064. }
  2065. spin_lock_irqsave(udc->lock, flags);
  2066. info("hw_ep_max = %d", hw_ep_max);
  2067. udc->gadget.dev.driver = NULL;
  2068. retval = 0;
  2069. for (i = 0; i < hw_ep_max/2; i++) {
  2070. for (j = RX; j <= TX; j++) {
  2071. int k = i + j * hw_ep_max/2;
  2072. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2073. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2074. (j == TX) ? "in" : "out");
  2075. mEp->lock = udc->lock;
  2076. mEp->device = &udc->gadget.dev;
  2077. mEp->td_pool = udc->td_pool;
  2078. mEp->ep.name = mEp->name;
  2079. mEp->ep.ops = &usb_ep_ops;
  2080. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2081. INIT_LIST_HEAD(&mEp->qh.queue);
  2082. spin_unlock_irqrestore(udc->lock, flags);
  2083. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2084. &mEp->qh.dma);
  2085. spin_lock_irqsave(udc->lock, flags);
  2086. if (mEp->qh.ptr == NULL)
  2087. retval = -ENOMEM;
  2088. else
  2089. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2090. /* skip ep0 out and in endpoints */
  2091. if (i == 0)
  2092. continue;
  2093. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2094. }
  2095. }
  2096. if (retval)
  2097. goto done;
  2098. udc->gadget.ep0 = &udc->ep0in.ep;
  2099. /* bind gadget */
  2100. driver->driver.bus = NULL;
  2101. udc->gadget.dev.driver = &driver->driver;
  2102. spin_unlock_irqrestore(udc->lock, flags);
  2103. retval = bind(&udc->gadget); /* MAY SLEEP */
  2104. spin_lock_irqsave(udc->lock, flags);
  2105. if (retval) {
  2106. udc->gadget.dev.driver = NULL;
  2107. goto done;
  2108. }
  2109. udc->driver = driver;
  2110. pm_runtime_get_sync(&udc->gadget.dev);
  2111. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2112. if (udc->vbus_active) {
  2113. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2114. hw_device_reset(udc);
  2115. } else {
  2116. pm_runtime_put_sync(&udc->gadget.dev);
  2117. goto done;
  2118. }
  2119. }
  2120. retval = hw_device_state(udc->ep0out.qh.dma);
  2121. if (retval)
  2122. pm_runtime_put_sync(&udc->gadget.dev);
  2123. done:
  2124. spin_unlock_irqrestore(udc->lock, flags);
  2125. return retval;
  2126. }
  2127. EXPORT_SYMBOL(usb_gadget_probe_driver);
  2128. /**
  2129. * usb_gadget_unregister_driver: unregister a gadget driver
  2130. *
  2131. * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
  2132. */
  2133. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  2134. {
  2135. struct ci13xxx *udc = _udc;
  2136. unsigned long i, flags;
  2137. trace("%p", driver);
  2138. if (driver == NULL ||
  2139. driver->unbind == NULL ||
  2140. driver->setup == NULL ||
  2141. driver->disconnect == NULL ||
  2142. driver->suspend == NULL ||
  2143. driver->resume == NULL ||
  2144. driver != udc->driver)
  2145. return -EINVAL;
  2146. spin_lock_irqsave(udc->lock, flags);
  2147. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2148. udc->vbus_active) {
  2149. hw_device_state(0);
  2150. if (udc->udc_driver->notify_event)
  2151. udc->udc_driver->notify_event(udc,
  2152. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2153. _gadget_stop_activity(&udc->gadget);
  2154. pm_runtime_put(&udc->gadget.dev);
  2155. }
  2156. /* unbind gadget */
  2157. spin_unlock_irqrestore(udc->lock, flags);
  2158. driver->unbind(&udc->gadget); /* MAY SLEEP */
  2159. spin_lock_irqsave(udc->lock, flags);
  2160. udc->gadget.dev.driver = NULL;
  2161. /* free resources */
  2162. for (i = 0; i < hw_ep_max; i++) {
  2163. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2164. if (!list_empty(&mEp->ep.ep_list))
  2165. list_del_init(&mEp->ep.ep_list);
  2166. if (mEp->qh.ptr != NULL)
  2167. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2168. }
  2169. udc->gadget.ep0 = NULL;
  2170. udc->driver = NULL;
  2171. spin_unlock_irqrestore(udc->lock, flags);
  2172. if (udc->td_pool != NULL) {
  2173. dma_pool_destroy(udc->td_pool);
  2174. udc->td_pool = NULL;
  2175. }
  2176. if (udc->qh_pool != NULL) {
  2177. dma_pool_destroy(udc->qh_pool);
  2178. udc->qh_pool = NULL;
  2179. }
  2180. return 0;
  2181. }
  2182. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  2183. /******************************************************************************
  2184. * BUS block
  2185. *****************************************************************************/
  2186. /**
  2187. * udc_irq: global interrupt handler
  2188. *
  2189. * This function returns IRQ_HANDLED if the IRQ has been handled
  2190. * It locks access to registers
  2191. */
  2192. static irqreturn_t udc_irq(void)
  2193. {
  2194. struct ci13xxx *udc = _udc;
  2195. irqreturn_t retval;
  2196. u32 intr;
  2197. trace();
  2198. if (udc == NULL) {
  2199. err("ENODEV");
  2200. return IRQ_HANDLED;
  2201. }
  2202. spin_lock(udc->lock);
  2203. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2204. if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
  2205. USBMODE_CM_DEVICE) {
  2206. spin_unlock(udc->lock);
  2207. return IRQ_NONE;
  2208. }
  2209. }
  2210. intr = hw_test_and_clear_intr_active();
  2211. if (intr) {
  2212. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2213. isr_statistics.hndl.idx &= ISR_MASK;
  2214. isr_statistics.hndl.cnt++;
  2215. /* order defines priority - do NOT change it */
  2216. if (USBi_URI & intr) {
  2217. isr_statistics.uri++;
  2218. isr_reset_handler(udc);
  2219. }
  2220. if (USBi_PCI & intr) {
  2221. isr_statistics.pci++;
  2222. udc->gadget.speed = hw_port_is_high_speed() ?
  2223. USB_SPEED_HIGH : USB_SPEED_FULL;
  2224. }
  2225. if (USBi_UEI & intr)
  2226. isr_statistics.uei++;
  2227. if (USBi_UI & intr) {
  2228. isr_statistics.ui++;
  2229. isr_tr_complete_handler(udc);
  2230. }
  2231. if (USBi_SLI & intr)
  2232. isr_statistics.sli++;
  2233. retval = IRQ_HANDLED;
  2234. } else {
  2235. isr_statistics.none++;
  2236. retval = IRQ_NONE;
  2237. }
  2238. spin_unlock(udc->lock);
  2239. return retval;
  2240. }
  2241. /**
  2242. * udc_release: driver release function
  2243. * @dev: device
  2244. *
  2245. * Currently does nothing
  2246. */
  2247. static void udc_release(struct device *dev)
  2248. {
  2249. trace("%p", dev);
  2250. if (dev == NULL)
  2251. err("EINVAL");
  2252. }
  2253. /**
  2254. * udc_probe: parent probe must call this to initialize UDC
  2255. * @dev: parent device
  2256. * @regs: registers base address
  2257. * @name: driver name
  2258. *
  2259. * This function returns an error code
  2260. * No interrupts active, the IRQ has not been requested yet
  2261. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2262. */
  2263. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2264. void __iomem *regs)
  2265. {
  2266. struct ci13xxx *udc;
  2267. int retval = 0;
  2268. trace("%p, %p, %p", dev, regs, name);
  2269. if (dev == NULL || regs == NULL || driver == NULL ||
  2270. driver->name == NULL)
  2271. return -EINVAL;
  2272. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2273. if (udc == NULL)
  2274. return -ENOMEM;
  2275. udc->lock = &udc_lock;
  2276. udc->regs = regs;
  2277. udc->udc_driver = driver;
  2278. udc->gadget.ops = &usb_gadget_ops;
  2279. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2280. udc->gadget.is_dualspeed = 1;
  2281. udc->gadget.is_otg = 0;
  2282. udc->gadget.name = driver->name;
  2283. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2284. udc->gadget.ep0 = NULL;
  2285. dev_set_name(&udc->gadget.dev, "gadget");
  2286. udc->gadget.dev.dma_mask = dev->dma_mask;
  2287. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2288. udc->gadget.dev.parent = dev;
  2289. udc->gadget.dev.release = udc_release;
  2290. retval = hw_device_init(regs);
  2291. if (retval < 0)
  2292. goto free_udc;
  2293. udc->transceiver = otg_get_transceiver();
  2294. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2295. if (udc->transceiver == NULL) {
  2296. retval = -ENODEV;
  2297. goto free_udc;
  2298. }
  2299. }
  2300. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2301. retval = hw_device_reset(udc);
  2302. if (retval)
  2303. goto put_transceiver;
  2304. }
  2305. retval = device_register(&udc->gadget.dev);
  2306. if (retval) {
  2307. put_device(&udc->gadget.dev);
  2308. goto put_transceiver;
  2309. }
  2310. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2311. retval = dbg_create_files(&udc->gadget.dev);
  2312. #endif
  2313. if (retval)
  2314. goto unreg_device;
  2315. if (udc->transceiver) {
  2316. retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
  2317. if (retval)
  2318. goto remove_dbg;
  2319. }
  2320. pm_runtime_no_callbacks(&udc->gadget.dev);
  2321. pm_runtime_enable(&udc->gadget.dev);
  2322. _udc = udc;
  2323. return retval;
  2324. err("error = %i", retval);
  2325. remove_dbg:
  2326. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2327. dbg_remove_files(&udc->gadget.dev);
  2328. #endif
  2329. unreg_device:
  2330. device_unregister(&udc->gadget.dev);
  2331. put_transceiver:
  2332. if (udc->transceiver)
  2333. otg_put_transceiver(udc->transceiver);
  2334. free_udc:
  2335. kfree(udc);
  2336. _udc = NULL;
  2337. return retval;
  2338. }
  2339. /**
  2340. * udc_remove: parent remove must call this to remove UDC
  2341. *
  2342. * No interrupts active, the IRQ has been released
  2343. */
  2344. static void udc_remove(void)
  2345. {
  2346. struct ci13xxx *udc = _udc;
  2347. if (udc == NULL) {
  2348. err("EINVAL");
  2349. return;
  2350. }
  2351. if (udc->transceiver) {
  2352. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2353. otg_put_transceiver(udc->transceiver);
  2354. }
  2355. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2356. dbg_remove_files(&udc->gadget.dev);
  2357. #endif
  2358. device_unregister(&udc->gadget.dev);
  2359. kfree(udc);
  2360. _udc = NULL;
  2361. }