qeth_core_main.c 130 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_MSG] = {"qeth_msg",
  31. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  32. [QETH_DBF_CTRL] = {"qeth_control",
  33. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  34. };
  35. EXPORT_SYMBOL_GPL(qeth_dbf);
  36. struct qeth_card_list_struct qeth_core_card_list;
  37. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  38. struct kmem_cache *qeth_core_header_cache;
  39. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  40. static struct device *qeth_core_root_dev;
  41. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  42. static struct lock_class_key qdio_out_skb_queue_key;
  43. static void qeth_send_control_data_cb(struct qeth_channel *,
  44. struct qeth_cmd_buffer *);
  45. static int qeth_issue_next_read(struct qeth_card *);
  46. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  47. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  48. static void qeth_free_buffer_pool(struct qeth_card *);
  49. static int qeth_qdio_establish(struct qeth_card *);
  50. static inline const char *qeth_get_cardname(struct qeth_card *card)
  51. {
  52. if (card->info.guestlan) {
  53. switch (card->info.type) {
  54. case QETH_CARD_TYPE_OSD:
  55. return " Guest LAN QDIO";
  56. case QETH_CARD_TYPE_IQD:
  57. return " Guest LAN Hiper";
  58. case QETH_CARD_TYPE_OSM:
  59. return " Guest LAN QDIO - OSM";
  60. case QETH_CARD_TYPE_OSX:
  61. return " Guest LAN QDIO - OSX";
  62. default:
  63. return " unknown";
  64. }
  65. } else {
  66. switch (card->info.type) {
  67. case QETH_CARD_TYPE_OSD:
  68. return " OSD Express";
  69. case QETH_CARD_TYPE_IQD:
  70. return " HiperSockets";
  71. case QETH_CARD_TYPE_OSN:
  72. return " OSN QDIO";
  73. case QETH_CARD_TYPE_OSM:
  74. return " OSM QDIO";
  75. case QETH_CARD_TYPE_OSX:
  76. return " OSX QDIO";
  77. default:
  78. return " unknown";
  79. }
  80. }
  81. return " n/a";
  82. }
  83. /* max length to be returned: 14 */
  84. const char *qeth_get_cardname_short(struct qeth_card *card)
  85. {
  86. if (card->info.guestlan) {
  87. switch (card->info.type) {
  88. case QETH_CARD_TYPE_OSD:
  89. return "GuestLAN QDIO";
  90. case QETH_CARD_TYPE_IQD:
  91. return "GuestLAN Hiper";
  92. case QETH_CARD_TYPE_OSM:
  93. return "GuestLAN OSM";
  94. case QETH_CARD_TYPE_OSX:
  95. return "GuestLAN OSX";
  96. default:
  97. return "unknown";
  98. }
  99. } else {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSD:
  102. switch (card->info.link_type) {
  103. case QETH_LINK_TYPE_FAST_ETH:
  104. return "OSD_100";
  105. case QETH_LINK_TYPE_HSTR:
  106. return "HSTR";
  107. case QETH_LINK_TYPE_GBIT_ETH:
  108. return "OSD_1000";
  109. case QETH_LINK_TYPE_10GBIT_ETH:
  110. return "OSD_10GIG";
  111. case QETH_LINK_TYPE_LANE_ETH100:
  112. return "OSD_FE_LANE";
  113. case QETH_LINK_TYPE_LANE_TR:
  114. return "OSD_TR_LANE";
  115. case QETH_LINK_TYPE_LANE_ETH1000:
  116. return "OSD_GbE_LANE";
  117. case QETH_LINK_TYPE_LANE:
  118. return "OSD_ATM_LANE";
  119. default:
  120. return "OSD_Express";
  121. }
  122. case QETH_CARD_TYPE_IQD:
  123. return "HiperSockets";
  124. case QETH_CARD_TYPE_OSN:
  125. return "OSN";
  126. case QETH_CARD_TYPE_OSM:
  127. return "OSM_1000";
  128. case QETH_CARD_TYPE_OSX:
  129. return "OSX_10GIG";
  130. default:
  131. return "unknown";
  132. }
  133. }
  134. return "n/a";
  135. }
  136. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  137. int clear_start_mask)
  138. {
  139. unsigned long flags;
  140. spin_lock_irqsave(&card->thread_mask_lock, flags);
  141. card->thread_allowed_mask = threads;
  142. if (clear_start_mask)
  143. card->thread_start_mask &= threads;
  144. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  145. wake_up(&card->wait_q);
  146. }
  147. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  148. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  149. {
  150. unsigned long flags;
  151. int rc = 0;
  152. spin_lock_irqsave(&card->thread_mask_lock, flags);
  153. rc = (card->thread_running_mask & threads);
  154. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  155. return rc;
  156. }
  157. EXPORT_SYMBOL_GPL(qeth_threads_running);
  158. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  159. {
  160. return wait_event_interruptible(card->wait_q,
  161. qeth_threads_running(card, threads) == 0);
  162. }
  163. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  164. void qeth_clear_working_pool_list(struct qeth_card *card)
  165. {
  166. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  167. QETH_CARD_TEXT(card, 5, "clwrklst");
  168. list_for_each_entry_safe(pool_entry, tmp,
  169. &card->qdio.in_buf_pool.entry_list, list){
  170. list_del(&pool_entry->list);
  171. }
  172. }
  173. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  174. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  175. {
  176. struct qeth_buffer_pool_entry *pool_entry;
  177. void *ptr;
  178. int i, j;
  179. QETH_CARD_TEXT(card, 5, "alocpool");
  180. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  181. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  182. if (!pool_entry) {
  183. qeth_free_buffer_pool(card);
  184. return -ENOMEM;
  185. }
  186. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  187. ptr = (void *) __get_free_page(GFP_KERNEL);
  188. if (!ptr) {
  189. while (j > 0)
  190. free_page((unsigned long)
  191. pool_entry->elements[--j]);
  192. kfree(pool_entry);
  193. qeth_free_buffer_pool(card);
  194. return -ENOMEM;
  195. }
  196. pool_entry->elements[j] = ptr;
  197. }
  198. list_add(&pool_entry->init_list,
  199. &card->qdio.init_pool.entry_list);
  200. }
  201. return 0;
  202. }
  203. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  204. {
  205. QETH_CARD_TEXT(card, 2, "realcbp");
  206. if ((card->state != CARD_STATE_DOWN) &&
  207. (card->state != CARD_STATE_RECOVER))
  208. return -EPERM;
  209. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  210. qeth_clear_working_pool_list(card);
  211. qeth_free_buffer_pool(card);
  212. card->qdio.in_buf_pool.buf_count = bufcnt;
  213. card->qdio.init_pool.buf_count = bufcnt;
  214. return qeth_alloc_buffer_pool(card);
  215. }
  216. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  217. static int qeth_issue_next_read(struct qeth_card *card)
  218. {
  219. int rc;
  220. struct qeth_cmd_buffer *iob;
  221. QETH_CARD_TEXT(card, 5, "issnxrd");
  222. if (card->read.state != CH_STATE_UP)
  223. return -EIO;
  224. iob = qeth_get_buffer(&card->read);
  225. if (!iob) {
  226. dev_warn(&card->gdev->dev, "The qeth device driver "
  227. "failed to recover an error on the device\n");
  228. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  229. "available\n", dev_name(&card->gdev->dev));
  230. return -ENOMEM;
  231. }
  232. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  233. QETH_CARD_TEXT(card, 6, "noirqpnd");
  234. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  235. (addr_t) iob, 0, 0);
  236. if (rc) {
  237. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  238. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  239. atomic_set(&card->read.irq_pending, 0);
  240. card->read_or_write_problem = 1;
  241. qeth_schedule_recovery(card);
  242. wake_up(&card->wait_q);
  243. }
  244. return rc;
  245. }
  246. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  247. {
  248. struct qeth_reply *reply;
  249. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  250. if (reply) {
  251. atomic_set(&reply->refcnt, 1);
  252. atomic_set(&reply->received, 0);
  253. reply->card = card;
  254. };
  255. return reply;
  256. }
  257. static void qeth_get_reply(struct qeth_reply *reply)
  258. {
  259. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  260. atomic_inc(&reply->refcnt);
  261. }
  262. static void qeth_put_reply(struct qeth_reply *reply)
  263. {
  264. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  265. if (atomic_dec_and_test(&reply->refcnt))
  266. kfree(reply);
  267. }
  268. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  269. struct qeth_card *card)
  270. {
  271. char *ipa_name;
  272. int com = cmd->hdr.command;
  273. ipa_name = qeth_get_ipa_cmd_name(com);
  274. if (rc)
  275. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  276. "x%X \"%s\"\n",
  277. ipa_name, com, dev_name(&card->gdev->dev),
  278. QETH_CARD_IFNAME(card), rc,
  279. qeth_get_ipa_msg(rc));
  280. else
  281. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  282. ipa_name, com, dev_name(&card->gdev->dev),
  283. QETH_CARD_IFNAME(card));
  284. }
  285. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  286. struct qeth_cmd_buffer *iob)
  287. {
  288. struct qeth_ipa_cmd *cmd = NULL;
  289. QETH_CARD_TEXT(card, 5, "chkipad");
  290. if (IS_IPA(iob->data)) {
  291. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  292. if (IS_IPA_REPLY(cmd)) {
  293. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  294. cmd->hdr.command != IPA_CMD_DELCCID &&
  295. cmd->hdr.command != IPA_CMD_MODCCID &&
  296. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  297. qeth_issue_ipa_msg(cmd,
  298. cmd->hdr.return_code, card);
  299. return cmd;
  300. } else {
  301. switch (cmd->hdr.command) {
  302. case IPA_CMD_STOPLAN:
  303. dev_warn(&card->gdev->dev,
  304. "The link for interface %s on CHPID"
  305. " 0x%X failed\n",
  306. QETH_CARD_IFNAME(card),
  307. card->info.chpid);
  308. card->lan_online = 0;
  309. if (card->dev && netif_carrier_ok(card->dev))
  310. netif_carrier_off(card->dev);
  311. return NULL;
  312. case IPA_CMD_STARTLAN:
  313. dev_info(&card->gdev->dev,
  314. "The link for %s on CHPID 0x%X has"
  315. " been restored\n",
  316. QETH_CARD_IFNAME(card),
  317. card->info.chpid);
  318. netif_carrier_on(card->dev);
  319. card->lan_online = 1;
  320. qeth_schedule_recovery(card);
  321. return NULL;
  322. case IPA_CMD_MODCCID:
  323. return cmd;
  324. case IPA_CMD_REGISTER_LOCAL_ADDR:
  325. QETH_CARD_TEXT(card, 3, "irla");
  326. break;
  327. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  328. QETH_CARD_TEXT(card, 3, "urla");
  329. break;
  330. default:
  331. QETH_DBF_MESSAGE(2, "Received data is IPA "
  332. "but not a reply!\n");
  333. break;
  334. }
  335. }
  336. }
  337. return cmd;
  338. }
  339. void qeth_clear_ipacmd_list(struct qeth_card *card)
  340. {
  341. struct qeth_reply *reply, *r;
  342. unsigned long flags;
  343. QETH_CARD_TEXT(card, 4, "clipalst");
  344. spin_lock_irqsave(&card->lock, flags);
  345. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  346. qeth_get_reply(reply);
  347. reply->rc = -EIO;
  348. atomic_inc(&reply->received);
  349. list_del_init(&reply->list);
  350. wake_up(&reply->wait_q);
  351. qeth_put_reply(reply);
  352. }
  353. spin_unlock_irqrestore(&card->lock, flags);
  354. atomic_set(&card->write.irq_pending, 0);
  355. }
  356. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  357. static int qeth_check_idx_response(struct qeth_card *card,
  358. unsigned char *buffer)
  359. {
  360. if (!buffer)
  361. return 0;
  362. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  363. if ((buffer[2] & 0xc0) == 0xc0) {
  364. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  365. "with cause code 0x%02x%s\n",
  366. buffer[4],
  367. ((buffer[4] == 0x22) ?
  368. " -- try another portname" : ""));
  369. QETH_CARD_TEXT(card, 2, "ckidxres");
  370. QETH_CARD_TEXT(card, 2, " idxterm");
  371. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  372. if (buffer[4] == 0xf6) {
  373. dev_err(&card->gdev->dev,
  374. "The qeth device is not configured "
  375. "for the OSI layer required by z/VM\n");
  376. return -EPERM;
  377. }
  378. return -EIO;
  379. }
  380. return 0;
  381. }
  382. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  383. __u32 len)
  384. {
  385. struct qeth_card *card;
  386. card = CARD_FROM_CDEV(channel->ccwdev);
  387. QETH_CARD_TEXT(card, 4, "setupccw");
  388. if (channel == &card->read)
  389. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  390. else
  391. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  392. channel->ccw.count = len;
  393. channel->ccw.cda = (__u32) __pa(iob);
  394. }
  395. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  396. {
  397. __u8 index;
  398. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  399. index = channel->io_buf_no;
  400. do {
  401. if (channel->iob[index].state == BUF_STATE_FREE) {
  402. channel->iob[index].state = BUF_STATE_LOCKED;
  403. channel->io_buf_no = (channel->io_buf_no + 1) %
  404. QETH_CMD_BUFFER_NO;
  405. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  406. return channel->iob + index;
  407. }
  408. index = (index + 1) % QETH_CMD_BUFFER_NO;
  409. } while (index != channel->io_buf_no);
  410. return NULL;
  411. }
  412. void qeth_release_buffer(struct qeth_channel *channel,
  413. struct qeth_cmd_buffer *iob)
  414. {
  415. unsigned long flags;
  416. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  417. spin_lock_irqsave(&channel->iob_lock, flags);
  418. memset(iob->data, 0, QETH_BUFSIZE);
  419. iob->state = BUF_STATE_FREE;
  420. iob->callback = qeth_send_control_data_cb;
  421. iob->rc = 0;
  422. spin_unlock_irqrestore(&channel->iob_lock, flags);
  423. }
  424. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  425. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  426. {
  427. struct qeth_cmd_buffer *buffer = NULL;
  428. unsigned long flags;
  429. spin_lock_irqsave(&channel->iob_lock, flags);
  430. buffer = __qeth_get_buffer(channel);
  431. spin_unlock_irqrestore(&channel->iob_lock, flags);
  432. return buffer;
  433. }
  434. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  435. {
  436. struct qeth_cmd_buffer *buffer;
  437. wait_event(channel->wait_q,
  438. ((buffer = qeth_get_buffer(channel)) != NULL));
  439. return buffer;
  440. }
  441. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  442. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  443. {
  444. int cnt;
  445. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  446. qeth_release_buffer(channel, &channel->iob[cnt]);
  447. channel->buf_no = 0;
  448. channel->io_buf_no = 0;
  449. }
  450. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  451. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  452. struct qeth_cmd_buffer *iob)
  453. {
  454. struct qeth_card *card;
  455. struct qeth_reply *reply, *r;
  456. struct qeth_ipa_cmd *cmd;
  457. unsigned long flags;
  458. int keep_reply;
  459. int rc = 0;
  460. card = CARD_FROM_CDEV(channel->ccwdev);
  461. QETH_CARD_TEXT(card, 4, "sndctlcb");
  462. rc = qeth_check_idx_response(card, iob->data);
  463. switch (rc) {
  464. case 0:
  465. break;
  466. case -EIO:
  467. qeth_clear_ipacmd_list(card);
  468. qeth_schedule_recovery(card);
  469. /* fall through */
  470. default:
  471. goto out;
  472. }
  473. cmd = qeth_check_ipa_data(card, iob);
  474. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  475. goto out;
  476. /*in case of OSN : check if cmd is set */
  477. if (card->info.type == QETH_CARD_TYPE_OSN &&
  478. cmd &&
  479. cmd->hdr.command != IPA_CMD_STARTLAN &&
  480. card->osn_info.assist_cb != NULL) {
  481. card->osn_info.assist_cb(card->dev, cmd);
  482. goto out;
  483. }
  484. spin_lock_irqsave(&card->lock, flags);
  485. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  486. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  487. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  488. qeth_get_reply(reply);
  489. list_del_init(&reply->list);
  490. spin_unlock_irqrestore(&card->lock, flags);
  491. keep_reply = 0;
  492. if (reply->callback != NULL) {
  493. if (cmd) {
  494. reply->offset = (__u16)((char *)cmd -
  495. (char *)iob->data);
  496. keep_reply = reply->callback(card,
  497. reply,
  498. (unsigned long)cmd);
  499. } else
  500. keep_reply = reply->callback(card,
  501. reply,
  502. (unsigned long)iob);
  503. }
  504. if (cmd)
  505. reply->rc = (u16) cmd->hdr.return_code;
  506. else if (iob->rc)
  507. reply->rc = iob->rc;
  508. if (keep_reply) {
  509. spin_lock_irqsave(&card->lock, flags);
  510. list_add_tail(&reply->list,
  511. &card->cmd_waiter_list);
  512. spin_unlock_irqrestore(&card->lock, flags);
  513. } else {
  514. atomic_inc(&reply->received);
  515. wake_up(&reply->wait_q);
  516. }
  517. qeth_put_reply(reply);
  518. goto out;
  519. }
  520. }
  521. spin_unlock_irqrestore(&card->lock, flags);
  522. out:
  523. memcpy(&card->seqno.pdu_hdr_ack,
  524. QETH_PDU_HEADER_SEQ_NO(iob->data),
  525. QETH_SEQ_NO_LENGTH);
  526. qeth_release_buffer(channel, iob);
  527. }
  528. static int qeth_setup_channel(struct qeth_channel *channel)
  529. {
  530. int cnt;
  531. QETH_DBF_TEXT(SETUP, 2, "setupch");
  532. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  533. channel->iob[cnt].data =
  534. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  535. if (channel->iob[cnt].data == NULL)
  536. break;
  537. channel->iob[cnt].state = BUF_STATE_FREE;
  538. channel->iob[cnt].channel = channel;
  539. channel->iob[cnt].callback = qeth_send_control_data_cb;
  540. channel->iob[cnt].rc = 0;
  541. }
  542. if (cnt < QETH_CMD_BUFFER_NO) {
  543. while (cnt-- > 0)
  544. kfree(channel->iob[cnt].data);
  545. return -ENOMEM;
  546. }
  547. channel->buf_no = 0;
  548. channel->io_buf_no = 0;
  549. atomic_set(&channel->irq_pending, 0);
  550. spin_lock_init(&channel->iob_lock);
  551. init_waitqueue_head(&channel->wait_q);
  552. return 0;
  553. }
  554. static int qeth_set_thread_start_bit(struct qeth_card *card,
  555. unsigned long thread)
  556. {
  557. unsigned long flags;
  558. spin_lock_irqsave(&card->thread_mask_lock, flags);
  559. if (!(card->thread_allowed_mask & thread) ||
  560. (card->thread_start_mask & thread)) {
  561. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  562. return -EPERM;
  563. }
  564. card->thread_start_mask |= thread;
  565. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  566. return 0;
  567. }
  568. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  569. {
  570. unsigned long flags;
  571. spin_lock_irqsave(&card->thread_mask_lock, flags);
  572. card->thread_start_mask &= ~thread;
  573. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  574. wake_up(&card->wait_q);
  575. }
  576. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  577. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  578. {
  579. unsigned long flags;
  580. spin_lock_irqsave(&card->thread_mask_lock, flags);
  581. card->thread_running_mask &= ~thread;
  582. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  583. wake_up(&card->wait_q);
  584. }
  585. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  586. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  587. {
  588. unsigned long flags;
  589. int rc = 0;
  590. spin_lock_irqsave(&card->thread_mask_lock, flags);
  591. if (card->thread_start_mask & thread) {
  592. if ((card->thread_allowed_mask & thread) &&
  593. !(card->thread_running_mask & thread)) {
  594. rc = 1;
  595. card->thread_start_mask &= ~thread;
  596. card->thread_running_mask |= thread;
  597. } else
  598. rc = -EPERM;
  599. }
  600. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  601. return rc;
  602. }
  603. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  604. {
  605. int rc = 0;
  606. wait_event(card->wait_q,
  607. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  608. return rc;
  609. }
  610. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  611. void qeth_schedule_recovery(struct qeth_card *card)
  612. {
  613. QETH_CARD_TEXT(card, 2, "startrec");
  614. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  615. schedule_work(&card->kernel_thread_starter);
  616. }
  617. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  618. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  619. {
  620. int dstat, cstat;
  621. char *sense;
  622. struct qeth_card *card;
  623. sense = (char *) irb->ecw;
  624. cstat = irb->scsw.cmd.cstat;
  625. dstat = irb->scsw.cmd.dstat;
  626. card = CARD_FROM_CDEV(cdev);
  627. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  628. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  629. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  630. QETH_CARD_TEXT(card, 2, "CGENCHK");
  631. dev_warn(&cdev->dev, "The qeth device driver "
  632. "failed to recover an error on the device\n");
  633. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  634. dev_name(&cdev->dev), dstat, cstat);
  635. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  636. 16, 1, irb, 64, 1);
  637. return 1;
  638. }
  639. if (dstat & DEV_STAT_UNIT_CHECK) {
  640. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  641. SENSE_RESETTING_EVENT_FLAG) {
  642. QETH_CARD_TEXT(card, 2, "REVIND");
  643. return 1;
  644. }
  645. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  646. SENSE_COMMAND_REJECT_FLAG) {
  647. QETH_CARD_TEXT(card, 2, "CMDREJi");
  648. return 1;
  649. }
  650. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  651. QETH_CARD_TEXT(card, 2, "AFFE");
  652. return 1;
  653. }
  654. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  655. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  656. return 0;
  657. }
  658. QETH_CARD_TEXT(card, 2, "DGENCHK");
  659. return 1;
  660. }
  661. return 0;
  662. }
  663. static long __qeth_check_irb_error(struct ccw_device *cdev,
  664. unsigned long intparm, struct irb *irb)
  665. {
  666. struct qeth_card *card;
  667. card = CARD_FROM_CDEV(cdev);
  668. if (!IS_ERR(irb))
  669. return 0;
  670. switch (PTR_ERR(irb)) {
  671. case -EIO:
  672. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  673. dev_name(&cdev->dev));
  674. QETH_CARD_TEXT(card, 2, "ckirberr");
  675. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  676. break;
  677. case -ETIMEDOUT:
  678. dev_warn(&cdev->dev, "A hardware operation timed out"
  679. " on the device\n");
  680. QETH_CARD_TEXT(card, 2, "ckirberr");
  681. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  682. if (intparm == QETH_RCD_PARM) {
  683. if (card && (card->data.ccwdev == cdev)) {
  684. card->data.state = CH_STATE_DOWN;
  685. wake_up(&card->wait_q);
  686. }
  687. }
  688. break;
  689. default:
  690. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  691. dev_name(&cdev->dev), PTR_ERR(irb));
  692. QETH_CARD_TEXT(card, 2, "ckirberr");
  693. QETH_CARD_TEXT(card, 2, " rc???");
  694. }
  695. return PTR_ERR(irb);
  696. }
  697. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  698. struct irb *irb)
  699. {
  700. int rc;
  701. int cstat, dstat;
  702. struct qeth_cmd_buffer *buffer;
  703. struct qeth_channel *channel;
  704. struct qeth_card *card;
  705. struct qeth_cmd_buffer *iob;
  706. __u8 index;
  707. if (__qeth_check_irb_error(cdev, intparm, irb))
  708. return;
  709. cstat = irb->scsw.cmd.cstat;
  710. dstat = irb->scsw.cmd.dstat;
  711. card = CARD_FROM_CDEV(cdev);
  712. if (!card)
  713. return;
  714. QETH_CARD_TEXT(card, 5, "irq");
  715. if (card->read.ccwdev == cdev) {
  716. channel = &card->read;
  717. QETH_CARD_TEXT(card, 5, "read");
  718. } else if (card->write.ccwdev == cdev) {
  719. channel = &card->write;
  720. QETH_CARD_TEXT(card, 5, "write");
  721. } else {
  722. channel = &card->data;
  723. QETH_CARD_TEXT(card, 5, "data");
  724. }
  725. atomic_set(&channel->irq_pending, 0);
  726. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  727. channel->state = CH_STATE_STOPPED;
  728. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  729. channel->state = CH_STATE_HALTED;
  730. /*let's wake up immediately on data channel*/
  731. if ((channel == &card->data) && (intparm != 0) &&
  732. (intparm != QETH_RCD_PARM))
  733. goto out;
  734. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  735. QETH_CARD_TEXT(card, 6, "clrchpar");
  736. /* we don't have to handle this further */
  737. intparm = 0;
  738. }
  739. if (intparm == QETH_HALT_CHANNEL_PARM) {
  740. QETH_CARD_TEXT(card, 6, "hltchpar");
  741. /* we don't have to handle this further */
  742. intparm = 0;
  743. }
  744. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  745. (dstat & DEV_STAT_UNIT_CHECK) ||
  746. (cstat)) {
  747. if (irb->esw.esw0.erw.cons) {
  748. dev_warn(&channel->ccwdev->dev,
  749. "The qeth device driver failed to recover "
  750. "an error on the device\n");
  751. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  752. "0x%X dstat 0x%X\n",
  753. dev_name(&channel->ccwdev->dev), cstat, dstat);
  754. print_hex_dump(KERN_WARNING, "qeth: irb ",
  755. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  756. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  757. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  758. }
  759. if (intparm == QETH_RCD_PARM) {
  760. channel->state = CH_STATE_DOWN;
  761. goto out;
  762. }
  763. rc = qeth_get_problem(cdev, irb);
  764. if (rc) {
  765. qeth_clear_ipacmd_list(card);
  766. qeth_schedule_recovery(card);
  767. goto out;
  768. }
  769. }
  770. if (intparm == QETH_RCD_PARM) {
  771. channel->state = CH_STATE_RCD_DONE;
  772. goto out;
  773. }
  774. if (intparm) {
  775. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  776. buffer->state = BUF_STATE_PROCESSED;
  777. }
  778. if (channel == &card->data)
  779. return;
  780. if (channel == &card->read &&
  781. channel->state == CH_STATE_UP)
  782. qeth_issue_next_read(card);
  783. iob = channel->iob;
  784. index = channel->buf_no;
  785. while (iob[index].state == BUF_STATE_PROCESSED) {
  786. if (iob[index].callback != NULL)
  787. iob[index].callback(channel, iob + index);
  788. index = (index + 1) % QETH_CMD_BUFFER_NO;
  789. }
  790. channel->buf_no = index;
  791. out:
  792. wake_up(&card->wait_q);
  793. return;
  794. }
  795. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  796. struct qeth_qdio_out_buffer *buf)
  797. {
  798. int i;
  799. struct sk_buff *skb;
  800. /* is PCI flag set on buffer? */
  801. if (buf->buffer->element[0].flags & 0x40)
  802. atomic_dec(&queue->set_pci_flags_count);
  803. skb = skb_dequeue(&buf->skb_list);
  804. while (skb) {
  805. atomic_dec(&skb->users);
  806. dev_kfree_skb_any(skb);
  807. skb = skb_dequeue(&buf->skb_list);
  808. }
  809. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  810. if (buf->buffer->element[i].addr && buf->is_header[i])
  811. kmem_cache_free(qeth_core_header_cache,
  812. buf->buffer->element[i].addr);
  813. buf->is_header[i] = 0;
  814. buf->buffer->element[i].length = 0;
  815. buf->buffer->element[i].addr = NULL;
  816. buf->buffer->element[i].flags = 0;
  817. }
  818. buf->buffer->element[15].flags = 0;
  819. buf->next_element_to_fill = 0;
  820. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  821. }
  822. void qeth_clear_qdio_buffers(struct qeth_card *card)
  823. {
  824. int i, j;
  825. QETH_CARD_TEXT(card, 2, "clearqdbf");
  826. /* clear outbound buffers to free skbs */
  827. for (i = 0; i < card->qdio.no_out_queues; ++i)
  828. if (card->qdio.out_qs[i]) {
  829. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  830. qeth_clear_output_buffer(card->qdio.out_qs[i],
  831. &card->qdio.out_qs[i]->bufs[j]);
  832. }
  833. }
  834. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  835. static void qeth_free_buffer_pool(struct qeth_card *card)
  836. {
  837. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  838. int i = 0;
  839. list_for_each_entry_safe(pool_entry, tmp,
  840. &card->qdio.init_pool.entry_list, init_list){
  841. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  842. free_page((unsigned long)pool_entry->elements[i]);
  843. list_del(&pool_entry->init_list);
  844. kfree(pool_entry);
  845. }
  846. }
  847. static void qeth_free_qdio_buffers(struct qeth_card *card)
  848. {
  849. int i, j;
  850. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  851. QETH_QDIO_UNINITIALIZED)
  852. return;
  853. kfree(card->qdio.in_q);
  854. card->qdio.in_q = NULL;
  855. /* inbound buffer pool */
  856. qeth_free_buffer_pool(card);
  857. /* free outbound qdio_qs */
  858. if (card->qdio.out_qs) {
  859. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  860. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  861. qeth_clear_output_buffer(card->qdio.out_qs[i],
  862. &card->qdio.out_qs[i]->bufs[j]);
  863. kfree(card->qdio.out_qs[i]);
  864. }
  865. kfree(card->qdio.out_qs);
  866. card->qdio.out_qs = NULL;
  867. }
  868. }
  869. static void qeth_clean_channel(struct qeth_channel *channel)
  870. {
  871. int cnt;
  872. QETH_DBF_TEXT(SETUP, 2, "freech");
  873. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  874. kfree(channel->iob[cnt].data);
  875. }
  876. static void qeth_get_channel_path_desc(struct qeth_card *card)
  877. {
  878. struct ccw_device *ccwdev;
  879. struct channelPath_dsc {
  880. u8 flags;
  881. u8 lsn;
  882. u8 desc;
  883. u8 chpid;
  884. u8 swla;
  885. u8 zeroes;
  886. u8 chla;
  887. u8 chpp;
  888. } *chp_dsc;
  889. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  890. ccwdev = card->data.ccwdev;
  891. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  892. if (chp_dsc != NULL) {
  893. /* CHPP field bit 6 == 1 -> single queue */
  894. if ((chp_dsc->chpp & 0x02) == 0x02) {
  895. if ((atomic_read(&card->qdio.state) !=
  896. QETH_QDIO_UNINITIALIZED) &&
  897. (card->qdio.no_out_queues == 4))
  898. /* change from 4 to 1 outbound queues */
  899. qeth_free_qdio_buffers(card);
  900. card->qdio.no_out_queues = 1;
  901. if (card->qdio.default_out_queue != 0)
  902. dev_info(&card->gdev->dev,
  903. "Priority Queueing not supported\n");
  904. card->qdio.default_out_queue = 0;
  905. } else {
  906. if ((atomic_read(&card->qdio.state) !=
  907. QETH_QDIO_UNINITIALIZED) &&
  908. (card->qdio.no_out_queues == 1)) {
  909. /* change from 1 to 4 outbound queues */
  910. qeth_free_qdio_buffers(card);
  911. card->qdio.default_out_queue = 2;
  912. }
  913. card->qdio.no_out_queues = 4;
  914. }
  915. card->info.func_level = 0x4100 + chp_dsc->desc;
  916. kfree(chp_dsc);
  917. }
  918. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  919. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  920. return;
  921. }
  922. static void qeth_init_qdio_info(struct qeth_card *card)
  923. {
  924. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  925. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  926. /* inbound */
  927. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  928. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  929. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  930. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  931. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  932. }
  933. static void qeth_set_intial_options(struct qeth_card *card)
  934. {
  935. card->options.route4.type = NO_ROUTER;
  936. card->options.route6.type = NO_ROUTER;
  937. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  938. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  939. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  940. card->options.fake_broadcast = 0;
  941. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  942. card->options.performance_stats = 0;
  943. card->options.rx_sg_cb = QETH_RX_SG_CB;
  944. card->options.isolation = ISOLATION_MODE_NONE;
  945. }
  946. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  947. {
  948. unsigned long flags;
  949. int rc = 0;
  950. spin_lock_irqsave(&card->thread_mask_lock, flags);
  951. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  952. (u8) card->thread_start_mask,
  953. (u8) card->thread_allowed_mask,
  954. (u8) card->thread_running_mask);
  955. rc = (card->thread_start_mask & thread);
  956. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  957. return rc;
  958. }
  959. static void qeth_start_kernel_thread(struct work_struct *work)
  960. {
  961. struct qeth_card *card = container_of(work, struct qeth_card,
  962. kernel_thread_starter);
  963. QETH_CARD_TEXT(card , 2, "strthrd");
  964. if (card->read.state != CH_STATE_UP &&
  965. card->write.state != CH_STATE_UP)
  966. return;
  967. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  968. kthread_run(card->discipline.recover, (void *) card,
  969. "qeth_recover");
  970. }
  971. static int qeth_setup_card(struct qeth_card *card)
  972. {
  973. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  974. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  975. card->read.state = CH_STATE_DOWN;
  976. card->write.state = CH_STATE_DOWN;
  977. card->data.state = CH_STATE_DOWN;
  978. card->state = CARD_STATE_DOWN;
  979. card->lan_online = 0;
  980. card->read_or_write_problem = 0;
  981. card->dev = NULL;
  982. spin_lock_init(&card->vlanlock);
  983. spin_lock_init(&card->mclock);
  984. card->vlangrp = NULL;
  985. spin_lock_init(&card->lock);
  986. spin_lock_init(&card->ip_lock);
  987. spin_lock_init(&card->thread_mask_lock);
  988. mutex_init(&card->conf_mutex);
  989. mutex_init(&card->discipline_mutex);
  990. card->thread_start_mask = 0;
  991. card->thread_allowed_mask = 0;
  992. card->thread_running_mask = 0;
  993. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  994. INIT_LIST_HEAD(&card->ip_list);
  995. INIT_LIST_HEAD(card->ip_tbd_list);
  996. INIT_LIST_HEAD(&card->cmd_waiter_list);
  997. init_waitqueue_head(&card->wait_q);
  998. /* intial options */
  999. qeth_set_intial_options(card);
  1000. /* IP address takeover */
  1001. INIT_LIST_HEAD(&card->ipato.entries);
  1002. card->ipato.enabled = 0;
  1003. card->ipato.invert4 = 0;
  1004. card->ipato.invert6 = 0;
  1005. /* init QDIO stuff */
  1006. qeth_init_qdio_info(card);
  1007. return 0;
  1008. }
  1009. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1010. {
  1011. struct qeth_card *card = container_of(slr, struct qeth_card,
  1012. qeth_service_level);
  1013. if (card->info.mcl_level[0])
  1014. seq_printf(m, "qeth: %s firmware level %s\n",
  1015. CARD_BUS_ID(card), card->info.mcl_level);
  1016. }
  1017. static struct qeth_card *qeth_alloc_card(void)
  1018. {
  1019. struct qeth_card *card;
  1020. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1021. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1022. if (!card)
  1023. goto out;
  1024. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1025. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1026. if (!card->ip_tbd_list) {
  1027. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1028. goto out_card;
  1029. }
  1030. if (qeth_setup_channel(&card->read))
  1031. goto out_ip;
  1032. if (qeth_setup_channel(&card->write))
  1033. goto out_channel;
  1034. card->options.layer2 = -1;
  1035. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1036. register_service_level(&card->qeth_service_level);
  1037. return card;
  1038. out_channel:
  1039. qeth_clean_channel(&card->read);
  1040. out_ip:
  1041. kfree(card->ip_tbd_list);
  1042. out_card:
  1043. kfree(card);
  1044. out:
  1045. return NULL;
  1046. }
  1047. static int qeth_determine_card_type(struct qeth_card *card)
  1048. {
  1049. int i = 0;
  1050. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1051. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1052. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1053. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1054. if ((CARD_RDEV(card)->id.dev_type ==
  1055. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1056. (CARD_RDEV(card)->id.dev_model ==
  1057. known_devices[i][QETH_DEV_MODEL_IND])) {
  1058. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1059. card->qdio.no_out_queues =
  1060. known_devices[i][QETH_QUEUE_NO_IND];
  1061. card->info.is_multicast_different =
  1062. known_devices[i][QETH_MULTICAST_IND];
  1063. qeth_get_channel_path_desc(card);
  1064. return 0;
  1065. }
  1066. i++;
  1067. }
  1068. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1069. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1070. "unknown type\n");
  1071. return -ENOENT;
  1072. }
  1073. static int qeth_clear_channel(struct qeth_channel *channel)
  1074. {
  1075. unsigned long flags;
  1076. struct qeth_card *card;
  1077. int rc;
  1078. card = CARD_FROM_CDEV(channel->ccwdev);
  1079. QETH_CARD_TEXT(card, 3, "clearch");
  1080. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1081. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1082. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1083. if (rc)
  1084. return rc;
  1085. rc = wait_event_interruptible_timeout(card->wait_q,
  1086. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1087. if (rc == -ERESTARTSYS)
  1088. return rc;
  1089. if (channel->state != CH_STATE_STOPPED)
  1090. return -ETIME;
  1091. channel->state = CH_STATE_DOWN;
  1092. return 0;
  1093. }
  1094. static int qeth_halt_channel(struct qeth_channel *channel)
  1095. {
  1096. unsigned long flags;
  1097. struct qeth_card *card;
  1098. int rc;
  1099. card = CARD_FROM_CDEV(channel->ccwdev);
  1100. QETH_CARD_TEXT(card, 3, "haltch");
  1101. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1102. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1103. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1104. if (rc)
  1105. return rc;
  1106. rc = wait_event_interruptible_timeout(card->wait_q,
  1107. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1108. if (rc == -ERESTARTSYS)
  1109. return rc;
  1110. if (channel->state != CH_STATE_HALTED)
  1111. return -ETIME;
  1112. return 0;
  1113. }
  1114. static int qeth_halt_channels(struct qeth_card *card)
  1115. {
  1116. int rc1 = 0, rc2 = 0, rc3 = 0;
  1117. QETH_CARD_TEXT(card, 3, "haltchs");
  1118. rc1 = qeth_halt_channel(&card->read);
  1119. rc2 = qeth_halt_channel(&card->write);
  1120. rc3 = qeth_halt_channel(&card->data);
  1121. if (rc1)
  1122. return rc1;
  1123. if (rc2)
  1124. return rc2;
  1125. return rc3;
  1126. }
  1127. static int qeth_clear_channels(struct qeth_card *card)
  1128. {
  1129. int rc1 = 0, rc2 = 0, rc3 = 0;
  1130. QETH_CARD_TEXT(card, 3, "clearchs");
  1131. rc1 = qeth_clear_channel(&card->read);
  1132. rc2 = qeth_clear_channel(&card->write);
  1133. rc3 = qeth_clear_channel(&card->data);
  1134. if (rc1)
  1135. return rc1;
  1136. if (rc2)
  1137. return rc2;
  1138. return rc3;
  1139. }
  1140. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1141. {
  1142. int rc = 0;
  1143. QETH_CARD_TEXT(card, 3, "clhacrd");
  1144. if (halt)
  1145. rc = qeth_halt_channels(card);
  1146. if (rc)
  1147. return rc;
  1148. return qeth_clear_channels(card);
  1149. }
  1150. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1151. {
  1152. int rc = 0;
  1153. QETH_CARD_TEXT(card, 3, "qdioclr");
  1154. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1155. QETH_QDIO_CLEANING)) {
  1156. case QETH_QDIO_ESTABLISHED:
  1157. if (card->info.type == QETH_CARD_TYPE_IQD)
  1158. rc = qdio_shutdown(CARD_DDEV(card),
  1159. QDIO_FLAG_CLEANUP_USING_HALT);
  1160. else
  1161. rc = qdio_shutdown(CARD_DDEV(card),
  1162. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1163. if (rc)
  1164. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1165. qdio_free(CARD_DDEV(card));
  1166. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1167. break;
  1168. case QETH_QDIO_CLEANING:
  1169. return rc;
  1170. default:
  1171. break;
  1172. }
  1173. rc = qeth_clear_halt_card(card, use_halt);
  1174. if (rc)
  1175. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1176. card->state = CARD_STATE_DOWN;
  1177. return rc;
  1178. }
  1179. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1180. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1181. int *length)
  1182. {
  1183. struct ciw *ciw;
  1184. char *rcd_buf;
  1185. int ret;
  1186. struct qeth_channel *channel = &card->data;
  1187. unsigned long flags;
  1188. /*
  1189. * scan for RCD command in extended SenseID data
  1190. */
  1191. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1192. if (!ciw || ciw->cmd == 0)
  1193. return -EOPNOTSUPP;
  1194. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1195. if (!rcd_buf)
  1196. return -ENOMEM;
  1197. channel->ccw.cmd_code = ciw->cmd;
  1198. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1199. channel->ccw.count = ciw->count;
  1200. channel->ccw.flags = CCW_FLAG_SLI;
  1201. channel->state = CH_STATE_RCD;
  1202. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1203. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1204. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1205. QETH_RCD_TIMEOUT);
  1206. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1207. if (!ret)
  1208. wait_event(card->wait_q,
  1209. (channel->state == CH_STATE_RCD_DONE ||
  1210. channel->state == CH_STATE_DOWN));
  1211. if (channel->state == CH_STATE_DOWN)
  1212. ret = -EIO;
  1213. else
  1214. channel->state = CH_STATE_DOWN;
  1215. if (ret) {
  1216. kfree(rcd_buf);
  1217. *buffer = NULL;
  1218. *length = 0;
  1219. } else {
  1220. *length = ciw->count;
  1221. *buffer = rcd_buf;
  1222. }
  1223. return ret;
  1224. }
  1225. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1226. {
  1227. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1228. card->info.chpid = prcd[30];
  1229. card->info.unit_addr2 = prcd[31];
  1230. card->info.cula = prcd[63];
  1231. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1232. (prcd[0x11] == _ascebc['M']));
  1233. }
  1234. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1235. {
  1236. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1237. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1238. card->info.blkt.time_total = 250;
  1239. card->info.blkt.inter_packet = 5;
  1240. card->info.blkt.inter_packet_jumbo = 15;
  1241. } else {
  1242. card->info.blkt.time_total = 0;
  1243. card->info.blkt.inter_packet = 0;
  1244. card->info.blkt.inter_packet_jumbo = 0;
  1245. }
  1246. }
  1247. static void qeth_init_tokens(struct qeth_card *card)
  1248. {
  1249. card->token.issuer_rm_w = 0x00010103UL;
  1250. card->token.cm_filter_w = 0x00010108UL;
  1251. card->token.cm_connection_w = 0x0001010aUL;
  1252. card->token.ulp_filter_w = 0x0001010bUL;
  1253. card->token.ulp_connection_w = 0x0001010dUL;
  1254. }
  1255. static void qeth_init_func_level(struct qeth_card *card)
  1256. {
  1257. switch (card->info.type) {
  1258. case QETH_CARD_TYPE_IQD:
  1259. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1260. break;
  1261. case QETH_CARD_TYPE_OSD:
  1262. case QETH_CARD_TYPE_OSN:
  1263. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1264. break;
  1265. default:
  1266. break;
  1267. }
  1268. }
  1269. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1270. void (*idx_reply_cb)(struct qeth_channel *,
  1271. struct qeth_cmd_buffer *))
  1272. {
  1273. struct qeth_cmd_buffer *iob;
  1274. unsigned long flags;
  1275. int rc;
  1276. struct qeth_card *card;
  1277. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1278. card = CARD_FROM_CDEV(channel->ccwdev);
  1279. iob = qeth_get_buffer(channel);
  1280. iob->callback = idx_reply_cb;
  1281. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1282. channel->ccw.count = QETH_BUFSIZE;
  1283. channel->ccw.cda = (__u32) __pa(iob->data);
  1284. wait_event(card->wait_q,
  1285. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1286. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1287. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1288. rc = ccw_device_start(channel->ccwdev,
  1289. &channel->ccw, (addr_t) iob, 0, 0);
  1290. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1291. if (rc) {
  1292. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1293. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1294. atomic_set(&channel->irq_pending, 0);
  1295. wake_up(&card->wait_q);
  1296. return rc;
  1297. }
  1298. rc = wait_event_interruptible_timeout(card->wait_q,
  1299. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1300. if (rc == -ERESTARTSYS)
  1301. return rc;
  1302. if (channel->state != CH_STATE_UP) {
  1303. rc = -ETIME;
  1304. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1305. qeth_clear_cmd_buffers(channel);
  1306. } else
  1307. rc = 0;
  1308. return rc;
  1309. }
  1310. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1311. void (*idx_reply_cb)(struct qeth_channel *,
  1312. struct qeth_cmd_buffer *))
  1313. {
  1314. struct qeth_card *card;
  1315. struct qeth_cmd_buffer *iob;
  1316. unsigned long flags;
  1317. __u16 temp;
  1318. __u8 tmp;
  1319. int rc;
  1320. struct ccw_dev_id temp_devid;
  1321. card = CARD_FROM_CDEV(channel->ccwdev);
  1322. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1323. iob = qeth_get_buffer(channel);
  1324. iob->callback = idx_reply_cb;
  1325. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1326. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1327. channel->ccw.cda = (__u32) __pa(iob->data);
  1328. if (channel == &card->write) {
  1329. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1330. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1331. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1332. card->seqno.trans_hdr++;
  1333. } else {
  1334. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1335. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1336. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1337. }
  1338. tmp = ((__u8)card->info.portno) | 0x80;
  1339. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1340. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1341. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1342. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1343. &card->info.func_level, sizeof(__u16));
  1344. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1345. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1346. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1347. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1348. wait_event(card->wait_q,
  1349. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1350. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1351. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1352. rc = ccw_device_start(channel->ccwdev,
  1353. &channel->ccw, (addr_t) iob, 0, 0);
  1354. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1355. if (rc) {
  1356. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1357. rc);
  1358. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1359. atomic_set(&channel->irq_pending, 0);
  1360. wake_up(&card->wait_q);
  1361. return rc;
  1362. }
  1363. rc = wait_event_interruptible_timeout(card->wait_q,
  1364. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1365. if (rc == -ERESTARTSYS)
  1366. return rc;
  1367. if (channel->state != CH_STATE_ACTIVATING) {
  1368. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1369. " failed to recover an error on the device\n");
  1370. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1371. dev_name(&channel->ccwdev->dev));
  1372. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1373. qeth_clear_cmd_buffers(channel);
  1374. return -ETIME;
  1375. }
  1376. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1377. }
  1378. static int qeth_peer_func_level(int level)
  1379. {
  1380. if ((level & 0xff) == 8)
  1381. return (level & 0xff) + 0x400;
  1382. if (((level >> 8) & 3) == 1)
  1383. return (level & 0xff) + 0x200;
  1384. return level;
  1385. }
  1386. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1387. struct qeth_cmd_buffer *iob)
  1388. {
  1389. struct qeth_card *card;
  1390. __u16 temp;
  1391. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1392. if (channel->state == CH_STATE_DOWN) {
  1393. channel->state = CH_STATE_ACTIVATING;
  1394. goto out;
  1395. }
  1396. card = CARD_FROM_CDEV(channel->ccwdev);
  1397. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1398. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1399. dev_err(&card->write.ccwdev->dev,
  1400. "The adapter is used exclusively by another "
  1401. "host\n");
  1402. else
  1403. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1404. " negative reply\n",
  1405. dev_name(&card->write.ccwdev->dev));
  1406. goto out;
  1407. }
  1408. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1409. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1410. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1411. "function level mismatch (sent: 0x%x, received: "
  1412. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1413. card->info.func_level, temp);
  1414. goto out;
  1415. }
  1416. channel->state = CH_STATE_UP;
  1417. out:
  1418. qeth_release_buffer(channel, iob);
  1419. }
  1420. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1421. struct qeth_cmd_buffer *iob)
  1422. {
  1423. struct qeth_card *card;
  1424. __u16 temp;
  1425. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1426. if (channel->state == CH_STATE_DOWN) {
  1427. channel->state = CH_STATE_ACTIVATING;
  1428. goto out;
  1429. }
  1430. card = CARD_FROM_CDEV(channel->ccwdev);
  1431. if (qeth_check_idx_response(card, iob->data))
  1432. goto out;
  1433. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1434. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1435. case QETH_IDX_ACT_ERR_EXCL:
  1436. dev_err(&card->write.ccwdev->dev,
  1437. "The adapter is used exclusively by another "
  1438. "host\n");
  1439. break;
  1440. case QETH_IDX_ACT_ERR_AUTH:
  1441. case QETH_IDX_ACT_ERR_AUTH_USER:
  1442. dev_err(&card->read.ccwdev->dev,
  1443. "Setting the device online failed because of "
  1444. "insufficient authorization\n");
  1445. break;
  1446. default:
  1447. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1448. " negative reply\n",
  1449. dev_name(&card->read.ccwdev->dev));
  1450. }
  1451. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1452. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1453. goto out;
  1454. }
  1455. /**
  1456. * * temporary fix for microcode bug
  1457. * * to revert it,replace OR by AND
  1458. * */
  1459. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1460. (card->info.type == QETH_CARD_TYPE_OSD))
  1461. card->info.portname_required = 1;
  1462. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1463. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1464. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1465. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1466. dev_name(&card->read.ccwdev->dev),
  1467. card->info.func_level, temp);
  1468. goto out;
  1469. }
  1470. memcpy(&card->token.issuer_rm_r,
  1471. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1472. QETH_MPC_TOKEN_LENGTH);
  1473. memcpy(&card->info.mcl_level[0],
  1474. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1475. channel->state = CH_STATE_UP;
  1476. out:
  1477. qeth_release_buffer(channel, iob);
  1478. }
  1479. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1480. struct qeth_cmd_buffer *iob)
  1481. {
  1482. qeth_setup_ccw(&card->write, iob->data, len);
  1483. iob->callback = qeth_release_buffer;
  1484. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1485. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1486. card->seqno.trans_hdr++;
  1487. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1488. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1489. card->seqno.pdu_hdr++;
  1490. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1491. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1492. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1493. }
  1494. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1495. int qeth_send_control_data(struct qeth_card *card, int len,
  1496. struct qeth_cmd_buffer *iob,
  1497. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1498. unsigned long),
  1499. void *reply_param)
  1500. {
  1501. int rc;
  1502. unsigned long flags;
  1503. struct qeth_reply *reply = NULL;
  1504. unsigned long timeout, event_timeout;
  1505. struct qeth_ipa_cmd *cmd;
  1506. QETH_CARD_TEXT(card, 2, "sendctl");
  1507. if (card->read_or_write_problem) {
  1508. qeth_release_buffer(iob->channel, iob);
  1509. return -EIO;
  1510. }
  1511. reply = qeth_alloc_reply(card);
  1512. if (!reply) {
  1513. return -ENOMEM;
  1514. }
  1515. reply->callback = reply_cb;
  1516. reply->param = reply_param;
  1517. if (card->state == CARD_STATE_DOWN)
  1518. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1519. else
  1520. reply->seqno = card->seqno.ipa++;
  1521. init_waitqueue_head(&reply->wait_q);
  1522. spin_lock_irqsave(&card->lock, flags);
  1523. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1524. spin_unlock_irqrestore(&card->lock, flags);
  1525. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1526. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1527. qeth_prepare_control_data(card, len, iob);
  1528. if (IS_IPA(iob->data))
  1529. event_timeout = QETH_IPA_TIMEOUT;
  1530. else
  1531. event_timeout = QETH_TIMEOUT;
  1532. timeout = jiffies + event_timeout;
  1533. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1534. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1535. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1536. (addr_t) iob, 0, 0);
  1537. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1538. if (rc) {
  1539. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1540. "ccw_device_start rc = %i\n",
  1541. dev_name(&card->write.ccwdev->dev), rc);
  1542. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1543. spin_lock_irqsave(&card->lock, flags);
  1544. list_del_init(&reply->list);
  1545. qeth_put_reply(reply);
  1546. spin_unlock_irqrestore(&card->lock, flags);
  1547. qeth_release_buffer(iob->channel, iob);
  1548. atomic_set(&card->write.irq_pending, 0);
  1549. wake_up(&card->wait_q);
  1550. return rc;
  1551. }
  1552. /* we have only one long running ipassist, since we can ensure
  1553. process context of this command we can sleep */
  1554. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1555. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1556. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1557. if (!wait_event_timeout(reply->wait_q,
  1558. atomic_read(&reply->received), event_timeout))
  1559. goto time_err;
  1560. } else {
  1561. while (!atomic_read(&reply->received)) {
  1562. if (time_after(jiffies, timeout))
  1563. goto time_err;
  1564. cpu_relax();
  1565. };
  1566. }
  1567. if (reply->rc == -EIO)
  1568. goto error;
  1569. rc = reply->rc;
  1570. qeth_put_reply(reply);
  1571. return rc;
  1572. time_err:
  1573. reply->rc = -ETIME;
  1574. spin_lock_irqsave(&reply->card->lock, flags);
  1575. list_del_init(&reply->list);
  1576. spin_unlock_irqrestore(&reply->card->lock, flags);
  1577. atomic_inc(&reply->received);
  1578. error:
  1579. atomic_set(&card->write.irq_pending, 0);
  1580. qeth_release_buffer(iob->channel, iob);
  1581. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1582. rc = reply->rc;
  1583. qeth_put_reply(reply);
  1584. return rc;
  1585. }
  1586. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1587. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1588. unsigned long data)
  1589. {
  1590. struct qeth_cmd_buffer *iob;
  1591. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1592. iob = (struct qeth_cmd_buffer *) data;
  1593. memcpy(&card->token.cm_filter_r,
  1594. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1595. QETH_MPC_TOKEN_LENGTH);
  1596. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1597. return 0;
  1598. }
  1599. static int qeth_cm_enable(struct qeth_card *card)
  1600. {
  1601. int rc;
  1602. struct qeth_cmd_buffer *iob;
  1603. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1604. iob = qeth_wait_for_buffer(&card->write);
  1605. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1606. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1607. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1608. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1609. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1610. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1611. qeth_cm_enable_cb, NULL);
  1612. return rc;
  1613. }
  1614. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1615. unsigned long data)
  1616. {
  1617. struct qeth_cmd_buffer *iob;
  1618. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1619. iob = (struct qeth_cmd_buffer *) data;
  1620. memcpy(&card->token.cm_connection_r,
  1621. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1622. QETH_MPC_TOKEN_LENGTH);
  1623. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1624. return 0;
  1625. }
  1626. static int qeth_cm_setup(struct qeth_card *card)
  1627. {
  1628. int rc;
  1629. struct qeth_cmd_buffer *iob;
  1630. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1631. iob = qeth_wait_for_buffer(&card->write);
  1632. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1633. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1634. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1635. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1636. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1637. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1638. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1639. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1640. qeth_cm_setup_cb, NULL);
  1641. return rc;
  1642. }
  1643. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1644. {
  1645. switch (card->info.type) {
  1646. case QETH_CARD_TYPE_UNKNOWN:
  1647. return 1500;
  1648. case QETH_CARD_TYPE_IQD:
  1649. return card->info.max_mtu;
  1650. case QETH_CARD_TYPE_OSD:
  1651. switch (card->info.link_type) {
  1652. case QETH_LINK_TYPE_HSTR:
  1653. case QETH_LINK_TYPE_LANE_TR:
  1654. return 2000;
  1655. default:
  1656. return 1492;
  1657. }
  1658. case QETH_CARD_TYPE_OSM:
  1659. case QETH_CARD_TYPE_OSX:
  1660. return 1492;
  1661. default:
  1662. return 1500;
  1663. }
  1664. }
  1665. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1666. {
  1667. switch (framesize) {
  1668. case 0x4000:
  1669. return 8192;
  1670. case 0x6000:
  1671. return 16384;
  1672. case 0xa000:
  1673. return 32768;
  1674. case 0xffff:
  1675. return 57344;
  1676. default:
  1677. return 0;
  1678. }
  1679. }
  1680. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1681. {
  1682. switch (card->info.type) {
  1683. case QETH_CARD_TYPE_OSD:
  1684. case QETH_CARD_TYPE_OSM:
  1685. case QETH_CARD_TYPE_OSX:
  1686. case QETH_CARD_TYPE_IQD:
  1687. return ((mtu >= 576) &&
  1688. (mtu <= card->info.max_mtu));
  1689. case QETH_CARD_TYPE_OSN:
  1690. case QETH_CARD_TYPE_UNKNOWN:
  1691. default:
  1692. return 1;
  1693. }
  1694. }
  1695. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1696. unsigned long data)
  1697. {
  1698. __u16 mtu, framesize;
  1699. __u16 len;
  1700. __u8 link_type;
  1701. struct qeth_cmd_buffer *iob;
  1702. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1703. iob = (struct qeth_cmd_buffer *) data;
  1704. memcpy(&card->token.ulp_filter_r,
  1705. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1706. QETH_MPC_TOKEN_LENGTH);
  1707. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1708. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1709. mtu = qeth_get_mtu_outof_framesize(framesize);
  1710. if (!mtu) {
  1711. iob->rc = -EINVAL;
  1712. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1713. return 0;
  1714. }
  1715. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1716. /* frame size has changed */
  1717. if (card->dev &&
  1718. ((card->dev->mtu == card->info.initial_mtu) ||
  1719. (card->dev->mtu > mtu)))
  1720. card->dev->mtu = mtu;
  1721. qeth_free_qdio_buffers(card);
  1722. }
  1723. card->info.initial_mtu = mtu;
  1724. card->info.max_mtu = mtu;
  1725. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1726. } else {
  1727. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1728. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1729. iob->data);
  1730. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1731. }
  1732. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1733. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1734. memcpy(&link_type,
  1735. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1736. card->info.link_type = link_type;
  1737. } else
  1738. card->info.link_type = 0;
  1739. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  1740. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1741. return 0;
  1742. }
  1743. static int qeth_ulp_enable(struct qeth_card *card)
  1744. {
  1745. int rc;
  1746. char prot_type;
  1747. struct qeth_cmd_buffer *iob;
  1748. /*FIXME: trace view callbacks*/
  1749. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1750. iob = qeth_wait_for_buffer(&card->write);
  1751. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1752. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1753. (__u8) card->info.portno;
  1754. if (card->options.layer2)
  1755. if (card->info.type == QETH_CARD_TYPE_OSN)
  1756. prot_type = QETH_PROT_OSN2;
  1757. else
  1758. prot_type = QETH_PROT_LAYER2;
  1759. else
  1760. prot_type = QETH_PROT_TCPIP;
  1761. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1762. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1763. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1764. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1765. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1766. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1767. card->info.portname, 9);
  1768. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1769. qeth_ulp_enable_cb, NULL);
  1770. return rc;
  1771. }
  1772. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1773. unsigned long data)
  1774. {
  1775. struct qeth_cmd_buffer *iob;
  1776. int rc = 0;
  1777. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1778. iob = (struct qeth_cmd_buffer *) data;
  1779. memcpy(&card->token.ulp_connection_r,
  1780. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1781. QETH_MPC_TOKEN_LENGTH);
  1782. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1783. 3)) {
  1784. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1785. dev_err(&card->gdev->dev, "A connection could not be "
  1786. "established because of an OLM limit\n");
  1787. iob->rc = -EMLINK;
  1788. }
  1789. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1790. return rc;
  1791. }
  1792. static int qeth_ulp_setup(struct qeth_card *card)
  1793. {
  1794. int rc;
  1795. __u16 temp;
  1796. struct qeth_cmd_buffer *iob;
  1797. struct ccw_dev_id dev_id;
  1798. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1799. iob = qeth_wait_for_buffer(&card->write);
  1800. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1801. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1802. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1803. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1804. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1805. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1806. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1807. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1808. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1809. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1810. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1811. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1812. qeth_ulp_setup_cb, NULL);
  1813. return rc;
  1814. }
  1815. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1816. {
  1817. int i, j;
  1818. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1819. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1820. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1821. return 0;
  1822. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1823. GFP_KERNEL);
  1824. if (!card->qdio.in_q)
  1825. goto out_nomem;
  1826. QETH_DBF_TEXT(SETUP, 2, "inq");
  1827. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1828. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1829. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1830. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1831. card->qdio.in_q->bufs[i].buffer =
  1832. &card->qdio.in_q->qdio_bufs[i];
  1833. /* inbound buffer pool */
  1834. if (qeth_alloc_buffer_pool(card))
  1835. goto out_freeinq;
  1836. /* outbound */
  1837. card->qdio.out_qs =
  1838. kmalloc(card->qdio.no_out_queues *
  1839. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1840. if (!card->qdio.out_qs)
  1841. goto out_freepool;
  1842. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1843. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1844. GFP_KERNEL);
  1845. if (!card->qdio.out_qs[i])
  1846. goto out_freeoutq;
  1847. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1848. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1849. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1850. card->qdio.out_qs[i]->queue_no = i;
  1851. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1852. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1853. card->qdio.out_qs[i]->bufs[j].buffer =
  1854. &card->qdio.out_qs[i]->qdio_bufs[j];
  1855. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1856. skb_list);
  1857. lockdep_set_class(
  1858. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1859. &qdio_out_skb_queue_key);
  1860. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1861. }
  1862. }
  1863. return 0;
  1864. out_freeoutq:
  1865. while (i > 0)
  1866. kfree(card->qdio.out_qs[--i]);
  1867. kfree(card->qdio.out_qs);
  1868. card->qdio.out_qs = NULL;
  1869. out_freepool:
  1870. qeth_free_buffer_pool(card);
  1871. out_freeinq:
  1872. kfree(card->qdio.in_q);
  1873. card->qdio.in_q = NULL;
  1874. out_nomem:
  1875. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1876. return -ENOMEM;
  1877. }
  1878. static void qeth_create_qib_param_field(struct qeth_card *card,
  1879. char *param_field)
  1880. {
  1881. param_field[0] = _ascebc['P'];
  1882. param_field[1] = _ascebc['C'];
  1883. param_field[2] = _ascebc['I'];
  1884. param_field[3] = _ascebc['T'];
  1885. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1886. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1887. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1888. }
  1889. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1890. char *param_field)
  1891. {
  1892. param_field[16] = _ascebc['B'];
  1893. param_field[17] = _ascebc['L'];
  1894. param_field[18] = _ascebc['K'];
  1895. param_field[19] = _ascebc['T'];
  1896. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1897. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1898. *((unsigned int *) (&param_field[28])) =
  1899. card->info.blkt.inter_packet_jumbo;
  1900. }
  1901. static int qeth_qdio_activate(struct qeth_card *card)
  1902. {
  1903. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1904. return qdio_activate(CARD_DDEV(card));
  1905. }
  1906. static int qeth_dm_act(struct qeth_card *card)
  1907. {
  1908. int rc;
  1909. struct qeth_cmd_buffer *iob;
  1910. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1911. iob = qeth_wait_for_buffer(&card->write);
  1912. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1913. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1914. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1915. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1916. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1917. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1918. return rc;
  1919. }
  1920. static int qeth_mpc_initialize(struct qeth_card *card)
  1921. {
  1922. int rc;
  1923. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1924. rc = qeth_issue_next_read(card);
  1925. if (rc) {
  1926. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1927. return rc;
  1928. }
  1929. rc = qeth_cm_enable(card);
  1930. if (rc) {
  1931. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1932. goto out_qdio;
  1933. }
  1934. rc = qeth_cm_setup(card);
  1935. if (rc) {
  1936. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1937. goto out_qdio;
  1938. }
  1939. rc = qeth_ulp_enable(card);
  1940. if (rc) {
  1941. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1942. goto out_qdio;
  1943. }
  1944. rc = qeth_ulp_setup(card);
  1945. if (rc) {
  1946. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1947. goto out_qdio;
  1948. }
  1949. rc = qeth_alloc_qdio_buffers(card);
  1950. if (rc) {
  1951. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1952. goto out_qdio;
  1953. }
  1954. rc = qeth_qdio_establish(card);
  1955. if (rc) {
  1956. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1957. qeth_free_qdio_buffers(card);
  1958. goto out_qdio;
  1959. }
  1960. rc = qeth_qdio_activate(card);
  1961. if (rc) {
  1962. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1963. goto out_qdio;
  1964. }
  1965. rc = qeth_dm_act(card);
  1966. if (rc) {
  1967. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1968. goto out_qdio;
  1969. }
  1970. return 0;
  1971. out_qdio:
  1972. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1973. return rc;
  1974. }
  1975. static void qeth_print_status_with_portname(struct qeth_card *card)
  1976. {
  1977. char dbf_text[15];
  1978. int i;
  1979. sprintf(dbf_text, "%s", card->info.portname + 1);
  1980. for (i = 0; i < 8; i++)
  1981. dbf_text[i] =
  1982. (char) _ebcasc[(__u8) dbf_text[i]];
  1983. dbf_text[8] = 0;
  1984. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1985. "with link type %s (portname: %s)\n",
  1986. qeth_get_cardname(card),
  1987. (card->info.mcl_level[0]) ? " (level: " : "",
  1988. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1989. (card->info.mcl_level[0]) ? ")" : "",
  1990. qeth_get_cardname_short(card),
  1991. dbf_text);
  1992. }
  1993. static void qeth_print_status_no_portname(struct qeth_card *card)
  1994. {
  1995. if (card->info.portname[0])
  1996. dev_info(&card->gdev->dev, "Device is a%s "
  1997. "card%s%s%s\nwith link type %s "
  1998. "(no portname needed by interface).\n",
  1999. qeth_get_cardname(card),
  2000. (card->info.mcl_level[0]) ? " (level: " : "",
  2001. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2002. (card->info.mcl_level[0]) ? ")" : "",
  2003. qeth_get_cardname_short(card));
  2004. else
  2005. dev_info(&card->gdev->dev, "Device is a%s "
  2006. "card%s%s%s\nwith link type %s.\n",
  2007. qeth_get_cardname(card),
  2008. (card->info.mcl_level[0]) ? " (level: " : "",
  2009. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2010. (card->info.mcl_level[0]) ? ")" : "",
  2011. qeth_get_cardname_short(card));
  2012. }
  2013. void qeth_print_status_message(struct qeth_card *card)
  2014. {
  2015. switch (card->info.type) {
  2016. case QETH_CARD_TYPE_OSD:
  2017. case QETH_CARD_TYPE_OSM:
  2018. case QETH_CARD_TYPE_OSX:
  2019. /* VM will use a non-zero first character
  2020. * to indicate a HiperSockets like reporting
  2021. * of the level OSA sets the first character to zero
  2022. * */
  2023. if (!card->info.mcl_level[0]) {
  2024. sprintf(card->info.mcl_level, "%02x%02x",
  2025. card->info.mcl_level[2],
  2026. card->info.mcl_level[3]);
  2027. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2028. break;
  2029. }
  2030. /* fallthrough */
  2031. case QETH_CARD_TYPE_IQD:
  2032. if ((card->info.guestlan) ||
  2033. (card->info.mcl_level[0] & 0x80)) {
  2034. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2035. card->info.mcl_level[0]];
  2036. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2037. card->info.mcl_level[1]];
  2038. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2039. card->info.mcl_level[2]];
  2040. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2041. card->info.mcl_level[3]];
  2042. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2043. }
  2044. break;
  2045. default:
  2046. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2047. }
  2048. if (card->info.portname_required)
  2049. qeth_print_status_with_portname(card);
  2050. else
  2051. qeth_print_status_no_portname(card);
  2052. }
  2053. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2054. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2055. {
  2056. struct qeth_buffer_pool_entry *entry;
  2057. QETH_CARD_TEXT(card, 5, "inwrklst");
  2058. list_for_each_entry(entry,
  2059. &card->qdio.init_pool.entry_list, init_list) {
  2060. qeth_put_buffer_pool_entry(card, entry);
  2061. }
  2062. }
  2063. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2064. struct qeth_card *card)
  2065. {
  2066. struct list_head *plh;
  2067. struct qeth_buffer_pool_entry *entry;
  2068. int i, free;
  2069. struct page *page;
  2070. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2071. return NULL;
  2072. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2073. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2074. free = 1;
  2075. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2076. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2077. free = 0;
  2078. break;
  2079. }
  2080. }
  2081. if (free) {
  2082. list_del_init(&entry->list);
  2083. return entry;
  2084. }
  2085. }
  2086. /* no free buffer in pool so take first one and swap pages */
  2087. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2088. struct qeth_buffer_pool_entry, list);
  2089. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2090. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2091. page = alloc_page(GFP_ATOMIC);
  2092. if (!page) {
  2093. return NULL;
  2094. } else {
  2095. free_page((unsigned long)entry->elements[i]);
  2096. entry->elements[i] = page_address(page);
  2097. if (card->options.performance_stats)
  2098. card->perf_stats.sg_alloc_page_rx++;
  2099. }
  2100. }
  2101. }
  2102. list_del_init(&entry->list);
  2103. return entry;
  2104. }
  2105. static int qeth_init_input_buffer(struct qeth_card *card,
  2106. struct qeth_qdio_buffer *buf)
  2107. {
  2108. struct qeth_buffer_pool_entry *pool_entry;
  2109. int i;
  2110. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2111. if (!pool_entry)
  2112. return 1;
  2113. /*
  2114. * since the buffer is accessed only from the input_tasklet
  2115. * there shouldn't be a need to synchronize; also, since we use
  2116. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2117. * buffers
  2118. */
  2119. buf->pool_entry = pool_entry;
  2120. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2121. buf->buffer->element[i].length = PAGE_SIZE;
  2122. buf->buffer->element[i].addr = pool_entry->elements[i];
  2123. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2124. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2125. else
  2126. buf->buffer->element[i].flags = 0;
  2127. }
  2128. return 0;
  2129. }
  2130. int qeth_init_qdio_queues(struct qeth_card *card)
  2131. {
  2132. int i, j;
  2133. int rc;
  2134. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2135. /* inbound queue */
  2136. memset(card->qdio.in_q->qdio_bufs, 0,
  2137. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2138. qeth_initialize_working_pool_list(card);
  2139. /*give only as many buffers to hardware as we have buffer pool entries*/
  2140. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2141. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2142. card->qdio.in_q->next_buf_to_init =
  2143. card->qdio.in_buf_pool.buf_count - 1;
  2144. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2145. card->qdio.in_buf_pool.buf_count - 1);
  2146. if (rc) {
  2147. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2148. return rc;
  2149. }
  2150. /* outbound queue */
  2151. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2152. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2153. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2154. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2155. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2156. &card->qdio.out_qs[i]->bufs[j]);
  2157. }
  2158. card->qdio.out_qs[i]->card = card;
  2159. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2160. card->qdio.out_qs[i]->do_pack = 0;
  2161. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2162. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2163. atomic_set(&card->qdio.out_qs[i]->state,
  2164. QETH_OUT_Q_UNLOCKED);
  2165. }
  2166. return 0;
  2167. }
  2168. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2169. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2170. {
  2171. switch (link_type) {
  2172. case QETH_LINK_TYPE_HSTR:
  2173. return 2;
  2174. default:
  2175. return 1;
  2176. }
  2177. }
  2178. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2179. struct qeth_ipa_cmd *cmd, __u8 command,
  2180. enum qeth_prot_versions prot)
  2181. {
  2182. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2183. cmd->hdr.command = command;
  2184. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2185. cmd->hdr.seqno = card->seqno.ipa;
  2186. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2187. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2188. if (card->options.layer2)
  2189. cmd->hdr.prim_version_no = 2;
  2190. else
  2191. cmd->hdr.prim_version_no = 1;
  2192. cmd->hdr.param_count = 1;
  2193. cmd->hdr.prot_version = prot;
  2194. cmd->hdr.ipa_supported = 0;
  2195. cmd->hdr.ipa_enabled = 0;
  2196. }
  2197. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2198. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2199. {
  2200. struct qeth_cmd_buffer *iob;
  2201. struct qeth_ipa_cmd *cmd;
  2202. iob = qeth_wait_for_buffer(&card->write);
  2203. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2204. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2205. return iob;
  2206. }
  2207. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2208. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2209. char prot_type)
  2210. {
  2211. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2212. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2213. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2214. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2215. }
  2216. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2217. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2218. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2219. unsigned long),
  2220. void *reply_param)
  2221. {
  2222. int rc;
  2223. char prot_type;
  2224. QETH_CARD_TEXT(card, 4, "sendipa");
  2225. if (card->options.layer2)
  2226. if (card->info.type == QETH_CARD_TYPE_OSN)
  2227. prot_type = QETH_PROT_OSN2;
  2228. else
  2229. prot_type = QETH_PROT_LAYER2;
  2230. else
  2231. prot_type = QETH_PROT_TCPIP;
  2232. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2233. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2234. iob, reply_cb, reply_param);
  2235. if (rc == -ETIME) {
  2236. qeth_clear_ipacmd_list(card);
  2237. qeth_schedule_recovery(card);
  2238. }
  2239. return rc;
  2240. }
  2241. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2242. int qeth_send_startlan(struct qeth_card *card)
  2243. {
  2244. int rc;
  2245. struct qeth_cmd_buffer *iob;
  2246. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2247. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2248. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2249. return rc;
  2250. }
  2251. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2252. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2253. struct qeth_reply *reply, unsigned long data)
  2254. {
  2255. struct qeth_ipa_cmd *cmd;
  2256. QETH_CARD_TEXT(card, 4, "defadpcb");
  2257. cmd = (struct qeth_ipa_cmd *) data;
  2258. if (cmd->hdr.return_code == 0)
  2259. cmd->hdr.return_code =
  2260. cmd->data.setadapterparms.hdr.return_code;
  2261. return 0;
  2262. }
  2263. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2264. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2265. struct qeth_reply *reply, unsigned long data)
  2266. {
  2267. struct qeth_ipa_cmd *cmd;
  2268. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2269. cmd = (struct qeth_ipa_cmd *) data;
  2270. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2271. card->info.link_type =
  2272. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2273. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2274. }
  2275. card->options.adp.supported_funcs =
  2276. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2277. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2278. }
  2279. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2280. __u32 command, __u32 cmdlen)
  2281. {
  2282. struct qeth_cmd_buffer *iob;
  2283. struct qeth_ipa_cmd *cmd;
  2284. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2285. QETH_PROT_IPV4);
  2286. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2287. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2288. cmd->data.setadapterparms.hdr.command_code = command;
  2289. cmd->data.setadapterparms.hdr.used_total = 1;
  2290. cmd->data.setadapterparms.hdr.seq_no = 1;
  2291. return iob;
  2292. }
  2293. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2294. int qeth_query_setadapterparms(struct qeth_card *card)
  2295. {
  2296. int rc;
  2297. struct qeth_cmd_buffer *iob;
  2298. QETH_CARD_TEXT(card, 3, "queryadp");
  2299. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2300. sizeof(struct qeth_ipacmd_setadpparms));
  2301. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2302. return rc;
  2303. }
  2304. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2305. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2306. unsigned int qdio_error, const char *dbftext)
  2307. {
  2308. if (qdio_error) {
  2309. QETH_CARD_TEXT(card, 2, dbftext);
  2310. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2311. buf->element[15].flags & 0xff);
  2312. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2313. buf->element[14].flags & 0xff);
  2314. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2315. if ((buf->element[15].flags & 0xff) == 0x12) {
  2316. card->stats.rx_dropped++;
  2317. return 0;
  2318. } else
  2319. return 1;
  2320. }
  2321. return 0;
  2322. }
  2323. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2324. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2325. {
  2326. struct qeth_qdio_q *queue = card->qdio.in_q;
  2327. int count;
  2328. int i;
  2329. int rc;
  2330. int newcount = 0;
  2331. count = (index < queue->next_buf_to_init)?
  2332. card->qdio.in_buf_pool.buf_count -
  2333. (queue->next_buf_to_init - index) :
  2334. card->qdio.in_buf_pool.buf_count -
  2335. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2336. /* only requeue at a certain threshold to avoid SIGAs */
  2337. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2338. for (i = queue->next_buf_to_init;
  2339. i < queue->next_buf_to_init + count; ++i) {
  2340. if (qeth_init_input_buffer(card,
  2341. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2342. break;
  2343. } else {
  2344. newcount++;
  2345. }
  2346. }
  2347. if (newcount < count) {
  2348. /* we are in memory shortage so we switch back to
  2349. traditional skb allocation and drop packages */
  2350. atomic_set(&card->force_alloc_skb, 3);
  2351. count = newcount;
  2352. } else {
  2353. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2354. }
  2355. /*
  2356. * according to old code it should be avoided to requeue all
  2357. * 128 buffers in order to benefit from PCI avoidance.
  2358. * this function keeps at least one buffer (the buffer at
  2359. * 'index') un-requeued -> this buffer is the first buffer that
  2360. * will be requeued the next time
  2361. */
  2362. if (card->options.performance_stats) {
  2363. card->perf_stats.inbound_do_qdio_cnt++;
  2364. card->perf_stats.inbound_do_qdio_start_time =
  2365. qeth_get_micros();
  2366. }
  2367. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2368. queue->next_buf_to_init, count);
  2369. if (card->options.performance_stats)
  2370. card->perf_stats.inbound_do_qdio_time +=
  2371. qeth_get_micros() -
  2372. card->perf_stats.inbound_do_qdio_start_time;
  2373. if (rc) {
  2374. dev_warn(&card->gdev->dev,
  2375. "QDIO reported an error, rc=%i\n", rc);
  2376. QETH_CARD_TEXT(card, 2, "qinberr");
  2377. }
  2378. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2379. QDIO_MAX_BUFFERS_PER_Q;
  2380. }
  2381. }
  2382. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2383. static int qeth_handle_send_error(struct qeth_card *card,
  2384. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2385. {
  2386. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2387. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2388. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2389. if (sbalf15 == 0) {
  2390. qdio_err = 0;
  2391. } else {
  2392. qdio_err = 1;
  2393. }
  2394. }
  2395. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2396. if (!qdio_err)
  2397. return QETH_SEND_ERROR_NONE;
  2398. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2399. return QETH_SEND_ERROR_RETRY;
  2400. QETH_CARD_TEXT(card, 1, "lnkfail");
  2401. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2402. (u16)qdio_err, (u8)sbalf15);
  2403. return QETH_SEND_ERROR_LINK_FAILURE;
  2404. }
  2405. /*
  2406. * Switched to packing state if the number of used buffers on a queue
  2407. * reaches a certain limit.
  2408. */
  2409. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2410. {
  2411. if (!queue->do_pack) {
  2412. if (atomic_read(&queue->used_buffers)
  2413. >= QETH_HIGH_WATERMARK_PACK){
  2414. /* switch non-PACKING -> PACKING */
  2415. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2416. if (queue->card->options.performance_stats)
  2417. queue->card->perf_stats.sc_dp_p++;
  2418. queue->do_pack = 1;
  2419. }
  2420. }
  2421. }
  2422. /*
  2423. * Switches from packing to non-packing mode. If there is a packing
  2424. * buffer on the queue this buffer will be prepared to be flushed.
  2425. * In that case 1 is returned to inform the caller. If no buffer
  2426. * has to be flushed, zero is returned.
  2427. */
  2428. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2429. {
  2430. struct qeth_qdio_out_buffer *buffer;
  2431. int flush_count = 0;
  2432. if (queue->do_pack) {
  2433. if (atomic_read(&queue->used_buffers)
  2434. <= QETH_LOW_WATERMARK_PACK) {
  2435. /* switch PACKING -> non-PACKING */
  2436. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2437. if (queue->card->options.performance_stats)
  2438. queue->card->perf_stats.sc_p_dp++;
  2439. queue->do_pack = 0;
  2440. /* flush packing buffers */
  2441. buffer = &queue->bufs[queue->next_buf_to_fill];
  2442. if ((atomic_read(&buffer->state) ==
  2443. QETH_QDIO_BUF_EMPTY) &&
  2444. (buffer->next_element_to_fill > 0)) {
  2445. atomic_set(&buffer->state,
  2446. QETH_QDIO_BUF_PRIMED);
  2447. flush_count++;
  2448. queue->next_buf_to_fill =
  2449. (queue->next_buf_to_fill + 1) %
  2450. QDIO_MAX_BUFFERS_PER_Q;
  2451. }
  2452. }
  2453. }
  2454. return flush_count;
  2455. }
  2456. /*
  2457. * Called to flush a packing buffer if no more pci flags are on the queue.
  2458. * Checks if there is a packing buffer and prepares it to be flushed.
  2459. * In that case returns 1, otherwise zero.
  2460. */
  2461. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2462. {
  2463. struct qeth_qdio_out_buffer *buffer;
  2464. buffer = &queue->bufs[queue->next_buf_to_fill];
  2465. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2466. (buffer->next_element_to_fill > 0)) {
  2467. /* it's a packing buffer */
  2468. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2469. queue->next_buf_to_fill =
  2470. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2471. return 1;
  2472. }
  2473. return 0;
  2474. }
  2475. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2476. int count)
  2477. {
  2478. struct qeth_qdio_out_buffer *buf;
  2479. int rc;
  2480. int i;
  2481. unsigned int qdio_flags;
  2482. for (i = index; i < index + count; ++i) {
  2483. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2484. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2485. SBAL_FLAGS_LAST_ENTRY;
  2486. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2487. continue;
  2488. if (!queue->do_pack) {
  2489. if ((atomic_read(&queue->used_buffers) >=
  2490. (QETH_HIGH_WATERMARK_PACK -
  2491. QETH_WATERMARK_PACK_FUZZ)) &&
  2492. !atomic_read(&queue->set_pci_flags_count)) {
  2493. /* it's likely that we'll go to packing
  2494. * mode soon */
  2495. atomic_inc(&queue->set_pci_flags_count);
  2496. buf->buffer->element[0].flags |= 0x40;
  2497. }
  2498. } else {
  2499. if (!atomic_read(&queue->set_pci_flags_count)) {
  2500. /*
  2501. * there's no outstanding PCI any more, so we
  2502. * have to request a PCI to be sure the the PCI
  2503. * will wake at some time in the future then we
  2504. * can flush packed buffers that might still be
  2505. * hanging around, which can happen if no
  2506. * further send was requested by the stack
  2507. */
  2508. atomic_inc(&queue->set_pci_flags_count);
  2509. buf->buffer->element[0].flags |= 0x40;
  2510. }
  2511. }
  2512. }
  2513. queue->card->dev->trans_start = jiffies;
  2514. if (queue->card->options.performance_stats) {
  2515. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2516. queue->card->perf_stats.outbound_do_qdio_start_time =
  2517. qeth_get_micros();
  2518. }
  2519. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2520. if (atomic_read(&queue->set_pci_flags_count))
  2521. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2522. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2523. queue->queue_no, index, count);
  2524. if (queue->card->options.performance_stats)
  2525. queue->card->perf_stats.outbound_do_qdio_time +=
  2526. qeth_get_micros() -
  2527. queue->card->perf_stats.outbound_do_qdio_start_time;
  2528. atomic_add(count, &queue->used_buffers);
  2529. if (rc) {
  2530. queue->card->stats.tx_errors += count;
  2531. /* ignore temporary SIGA errors without busy condition */
  2532. if (rc == QDIO_ERROR_SIGA_TARGET)
  2533. return;
  2534. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2535. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2536. /* this must not happen under normal circumstances. if it
  2537. * happens something is really wrong -> recover */
  2538. qeth_schedule_recovery(queue->card);
  2539. return;
  2540. }
  2541. if (queue->card->options.performance_stats)
  2542. queue->card->perf_stats.bufs_sent += count;
  2543. }
  2544. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2545. {
  2546. int index;
  2547. int flush_cnt = 0;
  2548. int q_was_packing = 0;
  2549. /*
  2550. * check if weed have to switch to non-packing mode or if
  2551. * we have to get a pci flag out on the queue
  2552. */
  2553. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2554. !atomic_read(&queue->set_pci_flags_count)) {
  2555. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2556. QETH_OUT_Q_UNLOCKED) {
  2557. /*
  2558. * If we get in here, there was no action in
  2559. * do_send_packet. So, we check if there is a
  2560. * packing buffer to be flushed here.
  2561. */
  2562. netif_stop_queue(queue->card->dev);
  2563. index = queue->next_buf_to_fill;
  2564. q_was_packing = queue->do_pack;
  2565. /* queue->do_pack may change */
  2566. barrier();
  2567. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2568. if (!flush_cnt &&
  2569. !atomic_read(&queue->set_pci_flags_count))
  2570. flush_cnt +=
  2571. qeth_flush_buffers_on_no_pci(queue);
  2572. if (queue->card->options.performance_stats &&
  2573. q_was_packing)
  2574. queue->card->perf_stats.bufs_sent_pack +=
  2575. flush_cnt;
  2576. if (flush_cnt)
  2577. qeth_flush_buffers(queue, index, flush_cnt);
  2578. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2579. }
  2580. }
  2581. }
  2582. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  2583. unsigned long card_ptr)
  2584. {
  2585. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2586. if (card->dev && (card->dev->flags & IFF_UP))
  2587. napi_schedule(&card->napi);
  2588. }
  2589. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  2590. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  2591. unsigned int queue, int first_element, int count,
  2592. unsigned long card_ptr)
  2593. {
  2594. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2595. if (qdio_err)
  2596. qeth_schedule_recovery(card);
  2597. }
  2598. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  2599. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2600. unsigned int qdio_error, int __queue, int first_element,
  2601. int count, unsigned long card_ptr)
  2602. {
  2603. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2604. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2605. struct qeth_qdio_out_buffer *buffer;
  2606. int i;
  2607. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2608. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2609. QETH_CARD_TEXT(card, 2, "achkcond");
  2610. netif_stop_queue(card->dev);
  2611. qeth_schedule_recovery(card);
  2612. return;
  2613. }
  2614. if (card->options.performance_stats) {
  2615. card->perf_stats.outbound_handler_cnt++;
  2616. card->perf_stats.outbound_handler_start_time =
  2617. qeth_get_micros();
  2618. }
  2619. for (i = first_element; i < (first_element + count); ++i) {
  2620. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2621. qeth_handle_send_error(card, buffer, qdio_error);
  2622. qeth_clear_output_buffer(queue, buffer);
  2623. }
  2624. atomic_sub(count, &queue->used_buffers);
  2625. /* check if we need to do something on this outbound queue */
  2626. if (card->info.type != QETH_CARD_TYPE_IQD)
  2627. qeth_check_outbound_queue(queue);
  2628. netif_wake_queue(queue->card->dev);
  2629. if (card->options.performance_stats)
  2630. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2631. card->perf_stats.outbound_handler_start_time;
  2632. }
  2633. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2634. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2635. int ipv, int cast_type)
  2636. {
  2637. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2638. card->info.type == QETH_CARD_TYPE_OSX))
  2639. return card->qdio.default_out_queue;
  2640. switch (card->qdio.no_out_queues) {
  2641. case 4:
  2642. if (cast_type && card->info.is_multicast_different)
  2643. return card->info.is_multicast_different &
  2644. (card->qdio.no_out_queues - 1);
  2645. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2646. const u8 tos = ip_hdr(skb)->tos;
  2647. if (card->qdio.do_prio_queueing ==
  2648. QETH_PRIO_Q_ING_TOS) {
  2649. if (tos & IP_TOS_NOTIMPORTANT)
  2650. return 3;
  2651. if (tos & IP_TOS_HIGHRELIABILITY)
  2652. return 2;
  2653. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2654. return 1;
  2655. if (tos & IP_TOS_LOWDELAY)
  2656. return 0;
  2657. }
  2658. if (card->qdio.do_prio_queueing ==
  2659. QETH_PRIO_Q_ING_PREC)
  2660. return 3 - (tos >> 6);
  2661. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2662. /* TODO: IPv6!!! */
  2663. }
  2664. return card->qdio.default_out_queue;
  2665. case 1: /* fallthrough for single-out-queue 1920-device */
  2666. default:
  2667. return card->qdio.default_out_queue;
  2668. }
  2669. }
  2670. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2671. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2672. struct sk_buff *skb, int elems)
  2673. {
  2674. int dlen = skb->len - skb->data_len;
  2675. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  2676. PFN_DOWN((unsigned long)skb->data);
  2677. elements_needed += skb_shinfo(skb)->nr_frags;
  2678. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2679. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2680. "(Number=%d / Length=%d). Discarded.\n",
  2681. (elements_needed+elems), skb->len);
  2682. return 0;
  2683. }
  2684. return elements_needed;
  2685. }
  2686. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2687. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  2688. {
  2689. int hroom, inpage, rest;
  2690. if (((unsigned long)skb->data & PAGE_MASK) !=
  2691. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  2692. hroom = skb_headroom(skb);
  2693. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  2694. rest = len - inpage;
  2695. if (rest > hroom)
  2696. return 1;
  2697. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  2698. skb->data -= rest;
  2699. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  2700. }
  2701. return 0;
  2702. }
  2703. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  2704. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2705. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2706. int offset)
  2707. {
  2708. int length = skb->len - skb->data_len;
  2709. int length_here;
  2710. int element;
  2711. char *data;
  2712. int first_lap, cnt;
  2713. struct skb_frag_struct *frag;
  2714. element = *next_element_to_fill;
  2715. data = skb->data;
  2716. first_lap = (is_tso == 0 ? 1 : 0);
  2717. if (offset >= 0) {
  2718. data = skb->data + offset;
  2719. length -= offset;
  2720. first_lap = 0;
  2721. }
  2722. while (length > 0) {
  2723. /* length_here is the remaining amount of data in this page */
  2724. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2725. if (length < length_here)
  2726. length_here = length;
  2727. buffer->element[element].addr = data;
  2728. buffer->element[element].length = length_here;
  2729. length -= length_here;
  2730. if (!length) {
  2731. if (first_lap)
  2732. if (skb_shinfo(skb)->nr_frags)
  2733. buffer->element[element].flags =
  2734. SBAL_FLAGS_FIRST_FRAG;
  2735. else
  2736. buffer->element[element].flags = 0;
  2737. else
  2738. buffer->element[element].flags =
  2739. SBAL_FLAGS_MIDDLE_FRAG;
  2740. } else {
  2741. if (first_lap)
  2742. buffer->element[element].flags =
  2743. SBAL_FLAGS_FIRST_FRAG;
  2744. else
  2745. buffer->element[element].flags =
  2746. SBAL_FLAGS_MIDDLE_FRAG;
  2747. }
  2748. data += length_here;
  2749. element++;
  2750. first_lap = 0;
  2751. }
  2752. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  2753. frag = &skb_shinfo(skb)->frags[cnt];
  2754. buffer->element[element].addr = (char *)page_to_phys(frag->page)
  2755. + frag->page_offset;
  2756. buffer->element[element].length = frag->size;
  2757. buffer->element[element].flags = SBAL_FLAGS_MIDDLE_FRAG;
  2758. element++;
  2759. }
  2760. if (buffer->element[element - 1].flags)
  2761. buffer->element[element - 1].flags = SBAL_FLAGS_LAST_FRAG;
  2762. *next_element_to_fill = element;
  2763. }
  2764. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2765. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2766. struct qeth_hdr *hdr, int offset, int hd_len)
  2767. {
  2768. struct qdio_buffer *buffer;
  2769. int flush_cnt = 0, hdr_len, large_send = 0;
  2770. buffer = buf->buffer;
  2771. atomic_inc(&skb->users);
  2772. skb_queue_tail(&buf->skb_list, skb);
  2773. /*check first on TSO ....*/
  2774. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2775. int element = buf->next_element_to_fill;
  2776. hdr_len = sizeof(struct qeth_hdr_tso) +
  2777. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2778. /*fill first buffer entry only with header information */
  2779. buffer->element[element].addr = skb->data;
  2780. buffer->element[element].length = hdr_len;
  2781. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2782. buf->next_element_to_fill++;
  2783. skb->data += hdr_len;
  2784. skb->len -= hdr_len;
  2785. large_send = 1;
  2786. }
  2787. if (offset >= 0) {
  2788. int element = buf->next_element_to_fill;
  2789. buffer->element[element].addr = hdr;
  2790. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2791. hd_len;
  2792. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2793. buf->is_header[element] = 1;
  2794. buf->next_element_to_fill++;
  2795. }
  2796. __qeth_fill_buffer(skb, buffer, large_send,
  2797. (int *)&buf->next_element_to_fill, offset);
  2798. if (!queue->do_pack) {
  2799. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2800. /* set state to PRIMED -> will be flushed */
  2801. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2802. flush_cnt = 1;
  2803. } else {
  2804. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2805. if (queue->card->options.performance_stats)
  2806. queue->card->perf_stats.skbs_sent_pack++;
  2807. if (buf->next_element_to_fill >=
  2808. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2809. /*
  2810. * packed buffer if full -> set state PRIMED
  2811. * -> will be flushed
  2812. */
  2813. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2814. flush_cnt = 1;
  2815. }
  2816. }
  2817. return flush_cnt;
  2818. }
  2819. int qeth_do_send_packet_fast(struct qeth_card *card,
  2820. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2821. struct qeth_hdr *hdr, int elements_needed,
  2822. int offset, int hd_len)
  2823. {
  2824. struct qeth_qdio_out_buffer *buffer;
  2825. int index;
  2826. /* spin until we get the queue ... */
  2827. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2828. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2829. /* ... now we've got the queue */
  2830. index = queue->next_buf_to_fill;
  2831. buffer = &queue->bufs[queue->next_buf_to_fill];
  2832. /*
  2833. * check if buffer is empty to make sure that we do not 'overtake'
  2834. * ourselves and try to fill a buffer that is already primed
  2835. */
  2836. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2837. goto out;
  2838. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2839. QDIO_MAX_BUFFERS_PER_Q;
  2840. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2841. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2842. qeth_flush_buffers(queue, index, 1);
  2843. return 0;
  2844. out:
  2845. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2846. return -EBUSY;
  2847. }
  2848. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2849. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2850. struct sk_buff *skb, struct qeth_hdr *hdr,
  2851. int elements_needed)
  2852. {
  2853. struct qeth_qdio_out_buffer *buffer;
  2854. int start_index;
  2855. int flush_count = 0;
  2856. int do_pack = 0;
  2857. int tmp;
  2858. int rc = 0;
  2859. /* spin until we get the queue ... */
  2860. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2861. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2862. start_index = queue->next_buf_to_fill;
  2863. buffer = &queue->bufs[queue->next_buf_to_fill];
  2864. /*
  2865. * check if buffer is empty to make sure that we do not 'overtake'
  2866. * ourselves and try to fill a buffer that is already primed
  2867. */
  2868. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2869. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2870. return -EBUSY;
  2871. }
  2872. /* check if we need to switch packing state of this queue */
  2873. qeth_switch_to_packing_if_needed(queue);
  2874. if (queue->do_pack) {
  2875. do_pack = 1;
  2876. /* does packet fit in current buffer? */
  2877. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2878. buffer->next_element_to_fill) < elements_needed) {
  2879. /* ... no -> set state PRIMED */
  2880. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2881. flush_count++;
  2882. queue->next_buf_to_fill =
  2883. (queue->next_buf_to_fill + 1) %
  2884. QDIO_MAX_BUFFERS_PER_Q;
  2885. buffer = &queue->bufs[queue->next_buf_to_fill];
  2886. /* we did a step forward, so check buffer state
  2887. * again */
  2888. if (atomic_read(&buffer->state) !=
  2889. QETH_QDIO_BUF_EMPTY) {
  2890. qeth_flush_buffers(queue, start_index,
  2891. flush_count);
  2892. atomic_set(&queue->state,
  2893. QETH_OUT_Q_UNLOCKED);
  2894. return -EBUSY;
  2895. }
  2896. }
  2897. }
  2898. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2899. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2900. QDIO_MAX_BUFFERS_PER_Q;
  2901. flush_count += tmp;
  2902. if (flush_count)
  2903. qeth_flush_buffers(queue, start_index, flush_count);
  2904. else if (!atomic_read(&queue->set_pci_flags_count))
  2905. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2906. /*
  2907. * queue->state will go from LOCKED -> UNLOCKED or from
  2908. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2909. * (switch packing state or flush buffer to get another pci flag out).
  2910. * In that case we will enter this loop
  2911. */
  2912. while (atomic_dec_return(&queue->state)) {
  2913. flush_count = 0;
  2914. start_index = queue->next_buf_to_fill;
  2915. /* check if we can go back to non-packing state */
  2916. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2917. /*
  2918. * check if we need to flush a packing buffer to get a pci
  2919. * flag out on the queue
  2920. */
  2921. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2922. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2923. if (flush_count)
  2924. qeth_flush_buffers(queue, start_index, flush_count);
  2925. }
  2926. /* at this point the queue is UNLOCKED again */
  2927. if (queue->card->options.performance_stats && do_pack)
  2928. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2929. return rc;
  2930. }
  2931. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2932. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2933. struct qeth_reply *reply, unsigned long data)
  2934. {
  2935. struct qeth_ipa_cmd *cmd;
  2936. struct qeth_ipacmd_setadpparms *setparms;
  2937. QETH_CARD_TEXT(card, 4, "prmadpcb");
  2938. cmd = (struct qeth_ipa_cmd *) data;
  2939. setparms = &(cmd->data.setadapterparms);
  2940. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2941. if (cmd->hdr.return_code) {
  2942. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2943. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2944. }
  2945. card->info.promisc_mode = setparms->data.mode;
  2946. return 0;
  2947. }
  2948. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2949. {
  2950. enum qeth_ipa_promisc_modes mode;
  2951. struct net_device *dev = card->dev;
  2952. struct qeth_cmd_buffer *iob;
  2953. struct qeth_ipa_cmd *cmd;
  2954. QETH_CARD_TEXT(card, 4, "setprom");
  2955. if (((dev->flags & IFF_PROMISC) &&
  2956. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2957. (!(dev->flags & IFF_PROMISC) &&
  2958. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2959. return;
  2960. mode = SET_PROMISC_MODE_OFF;
  2961. if (dev->flags & IFF_PROMISC)
  2962. mode = SET_PROMISC_MODE_ON;
  2963. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  2964. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2965. sizeof(struct qeth_ipacmd_setadpparms));
  2966. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2967. cmd->data.setadapterparms.data.mode = mode;
  2968. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2969. }
  2970. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2971. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2972. {
  2973. struct qeth_card *card;
  2974. char dbf_text[15];
  2975. card = dev->ml_priv;
  2976. QETH_CARD_TEXT(card, 4, "chgmtu");
  2977. sprintf(dbf_text, "%8x", new_mtu);
  2978. QETH_CARD_TEXT(card, 4, dbf_text);
  2979. if (new_mtu < 64)
  2980. return -EINVAL;
  2981. if (new_mtu > 65535)
  2982. return -EINVAL;
  2983. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2984. (!qeth_mtu_is_valid(card, new_mtu)))
  2985. return -EINVAL;
  2986. dev->mtu = new_mtu;
  2987. return 0;
  2988. }
  2989. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  2990. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  2991. {
  2992. struct qeth_card *card;
  2993. card = dev->ml_priv;
  2994. QETH_CARD_TEXT(card, 5, "getstat");
  2995. return &card->stats;
  2996. }
  2997. EXPORT_SYMBOL_GPL(qeth_get_stats);
  2998. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  2999. struct qeth_reply *reply, unsigned long data)
  3000. {
  3001. struct qeth_ipa_cmd *cmd;
  3002. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3003. cmd = (struct qeth_ipa_cmd *) data;
  3004. if (!card->options.layer2 ||
  3005. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3006. memcpy(card->dev->dev_addr,
  3007. &cmd->data.setadapterparms.data.change_addr.addr,
  3008. OSA_ADDR_LEN);
  3009. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3010. }
  3011. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3012. return 0;
  3013. }
  3014. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3015. {
  3016. int rc;
  3017. struct qeth_cmd_buffer *iob;
  3018. struct qeth_ipa_cmd *cmd;
  3019. QETH_CARD_TEXT(card, 4, "chgmac");
  3020. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3021. sizeof(struct qeth_ipacmd_setadpparms));
  3022. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3023. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3024. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3025. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3026. card->dev->dev_addr, OSA_ADDR_LEN);
  3027. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3028. NULL);
  3029. return rc;
  3030. }
  3031. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3032. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3033. struct qeth_reply *reply, unsigned long data)
  3034. {
  3035. struct qeth_ipa_cmd *cmd;
  3036. struct qeth_set_access_ctrl *access_ctrl_req;
  3037. QETH_CARD_TEXT(card, 4, "setaccb");
  3038. cmd = (struct qeth_ipa_cmd *) data;
  3039. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3040. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3041. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3042. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3043. cmd->data.setadapterparms.hdr.return_code);
  3044. switch (cmd->data.setadapterparms.hdr.return_code) {
  3045. case SET_ACCESS_CTRL_RC_SUCCESS:
  3046. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3047. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3048. {
  3049. card->options.isolation = access_ctrl_req->subcmd_code;
  3050. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3051. dev_info(&card->gdev->dev,
  3052. "QDIO data connection isolation is deactivated\n");
  3053. } else {
  3054. dev_info(&card->gdev->dev,
  3055. "QDIO data connection isolation is activated\n");
  3056. }
  3057. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3058. card->gdev->dev.kobj.name,
  3059. access_ctrl_req->subcmd_code,
  3060. cmd->data.setadapterparms.hdr.return_code);
  3061. break;
  3062. }
  3063. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3064. {
  3065. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3066. card->gdev->dev.kobj.name,
  3067. access_ctrl_req->subcmd_code,
  3068. cmd->data.setadapterparms.hdr.return_code);
  3069. dev_err(&card->gdev->dev, "Adapter does not "
  3070. "support QDIO data connection isolation\n");
  3071. /* ensure isolation mode is "none" */
  3072. card->options.isolation = ISOLATION_MODE_NONE;
  3073. break;
  3074. }
  3075. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3076. {
  3077. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3078. card->gdev->dev.kobj.name,
  3079. access_ctrl_req->subcmd_code,
  3080. cmd->data.setadapterparms.hdr.return_code);
  3081. dev_err(&card->gdev->dev,
  3082. "Adapter is dedicated. "
  3083. "QDIO data connection isolation not supported\n");
  3084. /* ensure isolation mode is "none" */
  3085. card->options.isolation = ISOLATION_MODE_NONE;
  3086. break;
  3087. }
  3088. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3089. {
  3090. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3091. card->gdev->dev.kobj.name,
  3092. access_ctrl_req->subcmd_code,
  3093. cmd->data.setadapterparms.hdr.return_code);
  3094. dev_err(&card->gdev->dev,
  3095. "TSO does not permit QDIO data connection isolation\n");
  3096. /* ensure isolation mode is "none" */
  3097. card->options.isolation = ISOLATION_MODE_NONE;
  3098. break;
  3099. }
  3100. default:
  3101. {
  3102. /* this should never happen */
  3103. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3104. "==UNKNOWN\n",
  3105. card->gdev->dev.kobj.name,
  3106. access_ctrl_req->subcmd_code,
  3107. cmd->data.setadapterparms.hdr.return_code);
  3108. /* ensure isolation mode is "none" */
  3109. card->options.isolation = ISOLATION_MODE_NONE;
  3110. break;
  3111. }
  3112. }
  3113. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3114. return 0;
  3115. }
  3116. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3117. enum qeth_ipa_isolation_modes isolation)
  3118. {
  3119. int rc;
  3120. struct qeth_cmd_buffer *iob;
  3121. struct qeth_ipa_cmd *cmd;
  3122. struct qeth_set_access_ctrl *access_ctrl_req;
  3123. QETH_CARD_TEXT(card, 4, "setacctl");
  3124. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3125. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3126. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3127. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3128. sizeof(struct qeth_set_access_ctrl));
  3129. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3130. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3131. access_ctrl_req->subcmd_code = isolation;
  3132. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3133. NULL);
  3134. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3135. return rc;
  3136. }
  3137. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3138. {
  3139. int rc = 0;
  3140. QETH_CARD_TEXT(card, 4, "setactlo");
  3141. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3142. card->info.type == QETH_CARD_TYPE_OSX) &&
  3143. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3144. rc = qeth_setadpparms_set_access_ctrl(card,
  3145. card->options.isolation);
  3146. if (rc) {
  3147. QETH_DBF_MESSAGE(3,
  3148. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3149. card->gdev->dev.kobj.name,
  3150. rc);
  3151. }
  3152. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3153. card->options.isolation = ISOLATION_MODE_NONE;
  3154. dev_err(&card->gdev->dev, "Adapter does not "
  3155. "support QDIO data connection isolation\n");
  3156. rc = -EOPNOTSUPP;
  3157. }
  3158. return rc;
  3159. }
  3160. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3161. void qeth_tx_timeout(struct net_device *dev)
  3162. {
  3163. struct qeth_card *card;
  3164. card = dev->ml_priv;
  3165. QETH_CARD_TEXT(card, 4, "txtimeo");
  3166. card->stats.tx_errors++;
  3167. qeth_schedule_recovery(card);
  3168. }
  3169. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3170. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3171. {
  3172. struct qeth_card *card = dev->ml_priv;
  3173. int rc = 0;
  3174. switch (regnum) {
  3175. case MII_BMCR: /* Basic mode control register */
  3176. rc = BMCR_FULLDPLX;
  3177. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3178. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3179. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3180. rc |= BMCR_SPEED100;
  3181. break;
  3182. case MII_BMSR: /* Basic mode status register */
  3183. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3184. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3185. BMSR_100BASE4;
  3186. break;
  3187. case MII_PHYSID1: /* PHYS ID 1 */
  3188. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3189. dev->dev_addr[2];
  3190. rc = (rc >> 5) & 0xFFFF;
  3191. break;
  3192. case MII_PHYSID2: /* PHYS ID 2 */
  3193. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3194. break;
  3195. case MII_ADVERTISE: /* Advertisement control reg */
  3196. rc = ADVERTISE_ALL;
  3197. break;
  3198. case MII_LPA: /* Link partner ability reg */
  3199. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3200. LPA_100BASE4 | LPA_LPACK;
  3201. break;
  3202. case MII_EXPANSION: /* Expansion register */
  3203. break;
  3204. case MII_DCOUNTER: /* disconnect counter */
  3205. break;
  3206. case MII_FCSCOUNTER: /* false carrier counter */
  3207. break;
  3208. case MII_NWAYTEST: /* N-way auto-neg test register */
  3209. break;
  3210. case MII_RERRCOUNTER: /* rx error counter */
  3211. rc = card->stats.rx_errors;
  3212. break;
  3213. case MII_SREVISION: /* silicon revision */
  3214. break;
  3215. case MII_RESV1: /* reserved 1 */
  3216. break;
  3217. case MII_LBRERROR: /* loopback, rx, bypass error */
  3218. break;
  3219. case MII_PHYADDR: /* physical address */
  3220. break;
  3221. case MII_RESV2: /* reserved 2 */
  3222. break;
  3223. case MII_TPISTATUS: /* TPI status for 10mbps */
  3224. break;
  3225. case MII_NCONFIG: /* network interface config */
  3226. break;
  3227. default:
  3228. break;
  3229. }
  3230. return rc;
  3231. }
  3232. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3233. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3234. struct qeth_cmd_buffer *iob, int len,
  3235. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3236. unsigned long),
  3237. void *reply_param)
  3238. {
  3239. u16 s1, s2;
  3240. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3241. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3242. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3243. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3244. /* adjust PDU length fields in IPA_PDU_HEADER */
  3245. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3246. s2 = (u32) len;
  3247. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3248. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3249. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3250. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3251. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3252. reply_cb, reply_param);
  3253. }
  3254. static int qeth_snmp_command_cb(struct qeth_card *card,
  3255. struct qeth_reply *reply, unsigned long sdata)
  3256. {
  3257. struct qeth_ipa_cmd *cmd;
  3258. struct qeth_arp_query_info *qinfo;
  3259. struct qeth_snmp_cmd *snmp;
  3260. unsigned char *data;
  3261. __u16 data_len;
  3262. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3263. cmd = (struct qeth_ipa_cmd *) sdata;
  3264. data = (unsigned char *)((char *)cmd - reply->offset);
  3265. qinfo = (struct qeth_arp_query_info *) reply->param;
  3266. snmp = &cmd->data.setadapterparms.data.snmp;
  3267. if (cmd->hdr.return_code) {
  3268. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3269. return 0;
  3270. }
  3271. if (cmd->data.setadapterparms.hdr.return_code) {
  3272. cmd->hdr.return_code =
  3273. cmd->data.setadapterparms.hdr.return_code;
  3274. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3275. return 0;
  3276. }
  3277. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3278. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3279. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3280. else
  3281. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3282. /* check if there is enough room in userspace */
  3283. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3284. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3285. cmd->hdr.return_code = -ENOMEM;
  3286. return 0;
  3287. }
  3288. QETH_CARD_TEXT_(card, 4, "snore%i",
  3289. cmd->data.setadapterparms.hdr.used_total);
  3290. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3291. cmd->data.setadapterparms.hdr.seq_no);
  3292. /*copy entries to user buffer*/
  3293. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3294. memcpy(qinfo->udata + qinfo->udata_offset,
  3295. (char *)snmp,
  3296. data_len + offsetof(struct qeth_snmp_cmd, data));
  3297. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3298. } else {
  3299. memcpy(qinfo->udata + qinfo->udata_offset,
  3300. (char *)&snmp->request, data_len);
  3301. }
  3302. qinfo->udata_offset += data_len;
  3303. /* check if all replies received ... */
  3304. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3305. cmd->data.setadapterparms.hdr.used_total);
  3306. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3307. cmd->data.setadapterparms.hdr.seq_no);
  3308. if (cmd->data.setadapterparms.hdr.seq_no <
  3309. cmd->data.setadapterparms.hdr.used_total)
  3310. return 1;
  3311. return 0;
  3312. }
  3313. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3314. {
  3315. struct qeth_cmd_buffer *iob;
  3316. struct qeth_ipa_cmd *cmd;
  3317. struct qeth_snmp_ureq *ureq;
  3318. int req_len;
  3319. struct qeth_arp_query_info qinfo = {0, };
  3320. int rc = 0;
  3321. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3322. if (card->info.guestlan)
  3323. return -EOPNOTSUPP;
  3324. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3325. (!card->options.layer2)) {
  3326. return -EOPNOTSUPP;
  3327. }
  3328. /* skip 4 bytes (data_len struct member) to get req_len */
  3329. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3330. return -EFAULT;
  3331. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3332. if (IS_ERR(ureq)) {
  3333. QETH_CARD_TEXT(card, 2, "snmpnome");
  3334. return PTR_ERR(ureq);
  3335. }
  3336. qinfo.udata_len = ureq->hdr.data_len;
  3337. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3338. if (!qinfo.udata) {
  3339. kfree(ureq);
  3340. return -ENOMEM;
  3341. }
  3342. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3343. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3344. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3345. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3346. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3347. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3348. qeth_snmp_command_cb, (void *)&qinfo);
  3349. if (rc)
  3350. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3351. QETH_CARD_IFNAME(card), rc);
  3352. else {
  3353. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3354. rc = -EFAULT;
  3355. }
  3356. kfree(ureq);
  3357. kfree(qinfo.udata);
  3358. return rc;
  3359. }
  3360. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3361. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3362. {
  3363. switch (card->info.type) {
  3364. case QETH_CARD_TYPE_IQD:
  3365. return 2;
  3366. default:
  3367. return 0;
  3368. }
  3369. }
  3370. static void qeth_determine_capabilities(struct qeth_card *card)
  3371. {
  3372. int rc;
  3373. int length;
  3374. char *prcd;
  3375. struct ccw_device *ddev;
  3376. int ddev_offline = 0;
  3377. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3378. ddev = CARD_DDEV(card);
  3379. if (!ddev->online) {
  3380. ddev_offline = 1;
  3381. rc = ccw_device_set_online(ddev);
  3382. if (rc) {
  3383. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3384. goto out;
  3385. }
  3386. }
  3387. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3388. if (rc) {
  3389. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3390. dev_name(&card->gdev->dev), rc);
  3391. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3392. goto out_offline;
  3393. }
  3394. qeth_configure_unitaddr(card, prcd);
  3395. qeth_configure_blkt_default(card, prcd);
  3396. kfree(prcd);
  3397. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  3398. if (rc)
  3399. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3400. out_offline:
  3401. if (ddev_offline == 1)
  3402. ccw_device_set_offline(ddev);
  3403. out:
  3404. return;
  3405. }
  3406. static int qeth_qdio_establish(struct qeth_card *card)
  3407. {
  3408. struct qdio_initialize init_data;
  3409. char *qib_param_field;
  3410. struct qdio_buffer **in_sbal_ptrs;
  3411. struct qdio_buffer **out_sbal_ptrs;
  3412. int i, j, k;
  3413. int rc = 0;
  3414. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3415. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3416. GFP_KERNEL);
  3417. if (!qib_param_field)
  3418. return -ENOMEM;
  3419. qeth_create_qib_param_field(card, qib_param_field);
  3420. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3421. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3422. GFP_KERNEL);
  3423. if (!in_sbal_ptrs) {
  3424. kfree(qib_param_field);
  3425. return -ENOMEM;
  3426. }
  3427. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3428. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3429. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3430. out_sbal_ptrs =
  3431. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3432. sizeof(void *), GFP_KERNEL);
  3433. if (!out_sbal_ptrs) {
  3434. kfree(in_sbal_ptrs);
  3435. kfree(qib_param_field);
  3436. return -ENOMEM;
  3437. }
  3438. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3439. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3440. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3441. card->qdio.out_qs[i]->bufs[j].buffer);
  3442. }
  3443. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3444. init_data.cdev = CARD_DDEV(card);
  3445. init_data.q_format = qeth_get_qdio_q_format(card);
  3446. init_data.qib_param_field_format = 0;
  3447. init_data.qib_param_field = qib_param_field;
  3448. init_data.no_input_qs = 1;
  3449. init_data.no_output_qs = card->qdio.no_out_queues;
  3450. init_data.input_handler = card->discipline.input_handler;
  3451. init_data.output_handler = card->discipline.output_handler;
  3452. init_data.queue_start_poll = card->discipline.start_poll;
  3453. init_data.int_parm = (unsigned long) card;
  3454. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3455. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3456. init_data.scan_threshold =
  3457. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  3458. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3459. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3460. rc = qdio_allocate(&init_data);
  3461. if (rc) {
  3462. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3463. goto out;
  3464. }
  3465. rc = qdio_establish(&init_data);
  3466. if (rc) {
  3467. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3468. qdio_free(CARD_DDEV(card));
  3469. }
  3470. }
  3471. out:
  3472. kfree(out_sbal_ptrs);
  3473. kfree(in_sbal_ptrs);
  3474. kfree(qib_param_field);
  3475. return rc;
  3476. }
  3477. static void qeth_core_free_card(struct qeth_card *card)
  3478. {
  3479. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3480. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3481. qeth_clean_channel(&card->read);
  3482. qeth_clean_channel(&card->write);
  3483. if (card->dev)
  3484. free_netdev(card->dev);
  3485. kfree(card->ip_tbd_list);
  3486. qeth_free_qdio_buffers(card);
  3487. unregister_service_level(&card->qeth_service_level);
  3488. kfree(card);
  3489. }
  3490. static struct ccw_device_id qeth_ids[] = {
  3491. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3492. .driver_info = QETH_CARD_TYPE_OSD},
  3493. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3494. .driver_info = QETH_CARD_TYPE_IQD},
  3495. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3496. .driver_info = QETH_CARD_TYPE_OSN},
  3497. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3498. .driver_info = QETH_CARD_TYPE_OSM},
  3499. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3500. .driver_info = QETH_CARD_TYPE_OSX},
  3501. {},
  3502. };
  3503. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3504. static struct ccw_driver qeth_ccw_driver = {
  3505. .name = "qeth",
  3506. .ids = qeth_ids,
  3507. .probe = ccwgroup_probe_ccwdev,
  3508. .remove = ccwgroup_remove_ccwdev,
  3509. };
  3510. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3511. unsigned long driver_id)
  3512. {
  3513. return ccwgroup_create_from_string(root_dev, driver_id,
  3514. &qeth_ccw_driver, 3, buf);
  3515. }
  3516. int qeth_core_hardsetup_card(struct qeth_card *card)
  3517. {
  3518. int retries = 0;
  3519. int rc;
  3520. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3521. atomic_set(&card->force_alloc_skb, 0);
  3522. qeth_get_channel_path_desc(card);
  3523. retry:
  3524. if (retries)
  3525. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3526. dev_name(&card->gdev->dev));
  3527. ccw_device_set_offline(CARD_DDEV(card));
  3528. ccw_device_set_offline(CARD_WDEV(card));
  3529. ccw_device_set_offline(CARD_RDEV(card));
  3530. rc = ccw_device_set_online(CARD_RDEV(card));
  3531. if (rc)
  3532. goto retriable;
  3533. rc = ccw_device_set_online(CARD_WDEV(card));
  3534. if (rc)
  3535. goto retriable;
  3536. rc = ccw_device_set_online(CARD_DDEV(card));
  3537. if (rc)
  3538. goto retriable;
  3539. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3540. retriable:
  3541. if (rc == -ERESTARTSYS) {
  3542. QETH_DBF_TEXT(SETUP, 2, "break1");
  3543. return rc;
  3544. } else if (rc) {
  3545. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3546. if (++retries > 3)
  3547. goto out;
  3548. else
  3549. goto retry;
  3550. }
  3551. qeth_determine_capabilities(card);
  3552. qeth_init_tokens(card);
  3553. qeth_init_func_level(card);
  3554. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3555. if (rc == -ERESTARTSYS) {
  3556. QETH_DBF_TEXT(SETUP, 2, "break2");
  3557. return rc;
  3558. } else if (rc) {
  3559. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3560. if (--retries < 0)
  3561. goto out;
  3562. else
  3563. goto retry;
  3564. }
  3565. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3566. if (rc == -ERESTARTSYS) {
  3567. QETH_DBF_TEXT(SETUP, 2, "break3");
  3568. return rc;
  3569. } else if (rc) {
  3570. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3571. if (--retries < 0)
  3572. goto out;
  3573. else
  3574. goto retry;
  3575. }
  3576. card->read_or_write_problem = 0;
  3577. rc = qeth_mpc_initialize(card);
  3578. if (rc) {
  3579. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3580. goto out;
  3581. }
  3582. return 0;
  3583. out:
  3584. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3585. "an error on the device\n");
  3586. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3587. dev_name(&card->gdev->dev), rc);
  3588. return rc;
  3589. }
  3590. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3591. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3592. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3593. {
  3594. struct page *page = virt_to_page(element->addr);
  3595. if (*pskb == NULL) {
  3596. /* the upper protocol layers assume that there is data in the
  3597. * skb itself. Copy a small amount (64 bytes) to make them
  3598. * happy. */
  3599. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3600. if (!(*pskb))
  3601. return -ENOMEM;
  3602. skb_reserve(*pskb, ETH_HLEN);
  3603. if (data_len <= 64) {
  3604. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3605. data_len);
  3606. } else {
  3607. get_page(page);
  3608. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3609. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3610. data_len - 64);
  3611. (*pskb)->data_len += data_len - 64;
  3612. (*pskb)->len += data_len - 64;
  3613. (*pskb)->truesize += data_len - 64;
  3614. (*pfrag)++;
  3615. }
  3616. } else {
  3617. get_page(page);
  3618. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3619. (*pskb)->data_len += data_len;
  3620. (*pskb)->len += data_len;
  3621. (*pskb)->truesize += data_len;
  3622. (*pfrag)++;
  3623. }
  3624. return 0;
  3625. }
  3626. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3627. struct qdio_buffer *buffer,
  3628. struct qdio_buffer_element **__element, int *__offset,
  3629. struct qeth_hdr **hdr)
  3630. {
  3631. struct qdio_buffer_element *element = *__element;
  3632. int offset = *__offset;
  3633. struct sk_buff *skb = NULL;
  3634. int skb_len = 0;
  3635. void *data_ptr;
  3636. int data_len;
  3637. int headroom = 0;
  3638. int use_rx_sg = 0;
  3639. int frag = 0;
  3640. /* qeth_hdr must not cross element boundaries */
  3641. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3642. if (qeth_is_last_sbale(element))
  3643. return NULL;
  3644. element++;
  3645. offset = 0;
  3646. if (element->length < sizeof(struct qeth_hdr))
  3647. return NULL;
  3648. }
  3649. *hdr = element->addr + offset;
  3650. offset += sizeof(struct qeth_hdr);
  3651. switch ((*hdr)->hdr.l2.id) {
  3652. case QETH_HEADER_TYPE_LAYER2:
  3653. skb_len = (*hdr)->hdr.l2.pkt_length;
  3654. break;
  3655. case QETH_HEADER_TYPE_LAYER3:
  3656. skb_len = (*hdr)->hdr.l3.length;
  3657. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3658. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3659. headroom = TR_HLEN;
  3660. else
  3661. headroom = ETH_HLEN;
  3662. break;
  3663. case QETH_HEADER_TYPE_OSN:
  3664. skb_len = (*hdr)->hdr.osn.pdu_length;
  3665. headroom = sizeof(struct qeth_hdr);
  3666. break;
  3667. default:
  3668. break;
  3669. }
  3670. if (!skb_len)
  3671. return NULL;
  3672. if ((skb_len >= card->options.rx_sg_cb) &&
  3673. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3674. (!atomic_read(&card->force_alloc_skb))) {
  3675. use_rx_sg = 1;
  3676. } else {
  3677. skb = dev_alloc_skb(skb_len + headroom);
  3678. if (!skb)
  3679. goto no_mem;
  3680. if (headroom)
  3681. skb_reserve(skb, headroom);
  3682. }
  3683. data_ptr = element->addr + offset;
  3684. while (skb_len) {
  3685. data_len = min(skb_len, (int)(element->length - offset));
  3686. if (data_len) {
  3687. if (use_rx_sg) {
  3688. if (qeth_create_skb_frag(element, &skb, offset,
  3689. &frag, data_len))
  3690. goto no_mem;
  3691. } else {
  3692. memcpy(skb_put(skb, data_len), data_ptr,
  3693. data_len);
  3694. }
  3695. }
  3696. skb_len -= data_len;
  3697. if (skb_len) {
  3698. if (qeth_is_last_sbale(element)) {
  3699. QETH_CARD_TEXT(card, 4, "unexeob");
  3700. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  3701. dev_kfree_skb_any(skb);
  3702. card->stats.rx_errors++;
  3703. return NULL;
  3704. }
  3705. element++;
  3706. offset = 0;
  3707. data_ptr = element->addr;
  3708. } else {
  3709. offset += data_len;
  3710. }
  3711. }
  3712. *__element = element;
  3713. *__offset = offset;
  3714. if (use_rx_sg && card->options.performance_stats) {
  3715. card->perf_stats.sg_skbs_rx++;
  3716. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3717. }
  3718. return skb;
  3719. no_mem:
  3720. if (net_ratelimit()) {
  3721. QETH_CARD_TEXT(card, 2, "noskbmem");
  3722. }
  3723. card->stats.rx_dropped++;
  3724. return NULL;
  3725. }
  3726. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3727. static void qeth_unregister_dbf_views(void)
  3728. {
  3729. int x;
  3730. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3731. debug_unregister(qeth_dbf[x].id);
  3732. qeth_dbf[x].id = NULL;
  3733. }
  3734. }
  3735. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3736. {
  3737. char dbf_txt_buf[32];
  3738. va_list args;
  3739. if (level > id->level)
  3740. return;
  3741. va_start(args, fmt);
  3742. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3743. va_end(args);
  3744. debug_text_event(id, level, dbf_txt_buf);
  3745. }
  3746. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3747. static int qeth_register_dbf_views(void)
  3748. {
  3749. int ret;
  3750. int x;
  3751. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3752. /* register the areas */
  3753. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3754. qeth_dbf[x].pages,
  3755. qeth_dbf[x].areas,
  3756. qeth_dbf[x].len);
  3757. if (qeth_dbf[x].id == NULL) {
  3758. qeth_unregister_dbf_views();
  3759. return -ENOMEM;
  3760. }
  3761. /* register a view */
  3762. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3763. if (ret) {
  3764. qeth_unregister_dbf_views();
  3765. return ret;
  3766. }
  3767. /* set a passing level */
  3768. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3769. }
  3770. return 0;
  3771. }
  3772. int qeth_core_load_discipline(struct qeth_card *card,
  3773. enum qeth_discipline_id discipline)
  3774. {
  3775. int rc = 0;
  3776. switch (discipline) {
  3777. case QETH_DISCIPLINE_LAYER3:
  3778. card->discipline.ccwgdriver = try_then_request_module(
  3779. symbol_get(qeth_l3_ccwgroup_driver),
  3780. "qeth_l3");
  3781. break;
  3782. case QETH_DISCIPLINE_LAYER2:
  3783. card->discipline.ccwgdriver = try_then_request_module(
  3784. symbol_get(qeth_l2_ccwgroup_driver),
  3785. "qeth_l2");
  3786. break;
  3787. }
  3788. if (!card->discipline.ccwgdriver) {
  3789. dev_err(&card->gdev->dev, "There is no kernel module to "
  3790. "support discipline %d\n", discipline);
  3791. rc = -EINVAL;
  3792. }
  3793. return rc;
  3794. }
  3795. void qeth_core_free_discipline(struct qeth_card *card)
  3796. {
  3797. if (card->options.layer2)
  3798. symbol_put(qeth_l2_ccwgroup_driver);
  3799. else
  3800. symbol_put(qeth_l3_ccwgroup_driver);
  3801. card->discipline.ccwgdriver = NULL;
  3802. }
  3803. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3804. {
  3805. struct qeth_card *card;
  3806. struct device *dev;
  3807. int rc;
  3808. unsigned long flags;
  3809. char dbf_name[20];
  3810. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3811. dev = &gdev->dev;
  3812. if (!get_device(dev))
  3813. return -ENODEV;
  3814. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3815. card = qeth_alloc_card();
  3816. if (!card) {
  3817. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3818. rc = -ENOMEM;
  3819. goto err_dev;
  3820. }
  3821. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3822. dev_name(&gdev->dev));
  3823. card->debug = debug_register(dbf_name, 2, 1, 8);
  3824. if (!card->debug) {
  3825. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3826. rc = -ENOMEM;
  3827. goto err_card;
  3828. }
  3829. debug_register_view(card->debug, &debug_hex_ascii_view);
  3830. card->read.ccwdev = gdev->cdev[0];
  3831. card->write.ccwdev = gdev->cdev[1];
  3832. card->data.ccwdev = gdev->cdev[2];
  3833. dev_set_drvdata(&gdev->dev, card);
  3834. card->gdev = gdev;
  3835. gdev->cdev[0]->handler = qeth_irq;
  3836. gdev->cdev[1]->handler = qeth_irq;
  3837. gdev->cdev[2]->handler = qeth_irq;
  3838. rc = qeth_determine_card_type(card);
  3839. if (rc) {
  3840. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3841. goto err_dbf;
  3842. }
  3843. rc = qeth_setup_card(card);
  3844. if (rc) {
  3845. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3846. goto err_dbf;
  3847. }
  3848. if (card->info.type == QETH_CARD_TYPE_OSN)
  3849. rc = qeth_core_create_osn_attributes(dev);
  3850. else
  3851. rc = qeth_core_create_device_attributes(dev);
  3852. if (rc)
  3853. goto err_dbf;
  3854. switch (card->info.type) {
  3855. case QETH_CARD_TYPE_OSN:
  3856. case QETH_CARD_TYPE_OSM:
  3857. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3858. if (rc)
  3859. goto err_attr;
  3860. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3861. if (rc)
  3862. goto err_disc;
  3863. case QETH_CARD_TYPE_OSD:
  3864. case QETH_CARD_TYPE_OSX:
  3865. default:
  3866. break;
  3867. }
  3868. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3869. list_add_tail(&card->list, &qeth_core_card_list.list);
  3870. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3871. qeth_determine_capabilities(card);
  3872. return 0;
  3873. err_disc:
  3874. qeth_core_free_discipline(card);
  3875. err_attr:
  3876. if (card->info.type == QETH_CARD_TYPE_OSN)
  3877. qeth_core_remove_osn_attributes(dev);
  3878. else
  3879. qeth_core_remove_device_attributes(dev);
  3880. err_dbf:
  3881. debug_unregister(card->debug);
  3882. err_card:
  3883. qeth_core_free_card(card);
  3884. err_dev:
  3885. put_device(dev);
  3886. return rc;
  3887. }
  3888. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3889. {
  3890. unsigned long flags;
  3891. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3892. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3893. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3894. qeth_core_remove_osn_attributes(&gdev->dev);
  3895. } else {
  3896. qeth_core_remove_device_attributes(&gdev->dev);
  3897. }
  3898. if (card->discipline.ccwgdriver) {
  3899. card->discipline.ccwgdriver->remove(gdev);
  3900. qeth_core_free_discipline(card);
  3901. }
  3902. debug_unregister(card->debug);
  3903. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3904. list_del(&card->list);
  3905. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3906. qeth_core_free_card(card);
  3907. dev_set_drvdata(&gdev->dev, NULL);
  3908. put_device(&gdev->dev);
  3909. return;
  3910. }
  3911. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3912. {
  3913. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3914. int rc = 0;
  3915. int def_discipline;
  3916. if (!card->discipline.ccwgdriver) {
  3917. if (card->info.type == QETH_CARD_TYPE_IQD)
  3918. def_discipline = QETH_DISCIPLINE_LAYER3;
  3919. else
  3920. def_discipline = QETH_DISCIPLINE_LAYER2;
  3921. rc = qeth_core_load_discipline(card, def_discipline);
  3922. if (rc)
  3923. goto err;
  3924. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3925. if (rc)
  3926. goto err;
  3927. }
  3928. rc = card->discipline.ccwgdriver->set_online(gdev);
  3929. err:
  3930. return rc;
  3931. }
  3932. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3933. {
  3934. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3935. return card->discipline.ccwgdriver->set_offline(gdev);
  3936. }
  3937. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3938. {
  3939. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3940. if (card->discipline.ccwgdriver &&
  3941. card->discipline.ccwgdriver->shutdown)
  3942. card->discipline.ccwgdriver->shutdown(gdev);
  3943. }
  3944. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3945. {
  3946. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3947. if (card->discipline.ccwgdriver &&
  3948. card->discipline.ccwgdriver->prepare)
  3949. return card->discipline.ccwgdriver->prepare(gdev);
  3950. return 0;
  3951. }
  3952. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3953. {
  3954. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3955. if (card->discipline.ccwgdriver &&
  3956. card->discipline.ccwgdriver->complete)
  3957. card->discipline.ccwgdriver->complete(gdev);
  3958. }
  3959. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3960. {
  3961. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3962. if (card->discipline.ccwgdriver &&
  3963. card->discipline.ccwgdriver->freeze)
  3964. return card->discipline.ccwgdriver->freeze(gdev);
  3965. return 0;
  3966. }
  3967. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3968. {
  3969. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3970. if (card->discipline.ccwgdriver &&
  3971. card->discipline.ccwgdriver->thaw)
  3972. return card->discipline.ccwgdriver->thaw(gdev);
  3973. return 0;
  3974. }
  3975. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3976. {
  3977. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3978. if (card->discipline.ccwgdriver &&
  3979. card->discipline.ccwgdriver->restore)
  3980. return card->discipline.ccwgdriver->restore(gdev);
  3981. return 0;
  3982. }
  3983. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3984. .owner = THIS_MODULE,
  3985. .name = "qeth",
  3986. .driver_id = 0xD8C5E3C8,
  3987. .probe = qeth_core_probe_device,
  3988. .remove = qeth_core_remove_device,
  3989. .set_online = qeth_core_set_online,
  3990. .set_offline = qeth_core_set_offline,
  3991. .shutdown = qeth_core_shutdown,
  3992. .prepare = qeth_core_prepare,
  3993. .complete = qeth_core_complete,
  3994. .freeze = qeth_core_freeze,
  3995. .thaw = qeth_core_thaw,
  3996. .restore = qeth_core_restore,
  3997. };
  3998. static ssize_t
  3999. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4000. size_t count)
  4001. {
  4002. int err;
  4003. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4004. qeth_core_ccwgroup_driver.driver_id);
  4005. if (err)
  4006. return err;
  4007. else
  4008. return count;
  4009. }
  4010. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4011. static struct {
  4012. const char str[ETH_GSTRING_LEN];
  4013. } qeth_ethtool_stats_keys[] = {
  4014. /* 0 */{"rx skbs"},
  4015. {"rx buffers"},
  4016. {"tx skbs"},
  4017. {"tx buffers"},
  4018. {"tx skbs no packing"},
  4019. {"tx buffers no packing"},
  4020. {"tx skbs packing"},
  4021. {"tx buffers packing"},
  4022. {"tx sg skbs"},
  4023. {"tx sg frags"},
  4024. /* 10 */{"rx sg skbs"},
  4025. {"rx sg frags"},
  4026. {"rx sg page allocs"},
  4027. {"tx large kbytes"},
  4028. {"tx large count"},
  4029. {"tx pk state ch n->p"},
  4030. {"tx pk state ch p->n"},
  4031. {"tx pk watermark low"},
  4032. {"tx pk watermark high"},
  4033. {"queue 0 buffer usage"},
  4034. /* 20 */{"queue 1 buffer usage"},
  4035. {"queue 2 buffer usage"},
  4036. {"queue 3 buffer usage"},
  4037. {"rx poll time"},
  4038. {"rx poll count"},
  4039. {"rx do_QDIO time"},
  4040. {"rx do_QDIO count"},
  4041. {"tx handler time"},
  4042. {"tx handler count"},
  4043. {"tx time"},
  4044. /* 30 */{"tx count"},
  4045. {"tx do_QDIO time"},
  4046. {"tx do_QDIO count"},
  4047. {"tx csum"},
  4048. {"tx lin"},
  4049. };
  4050. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4051. {
  4052. switch (stringset) {
  4053. case ETH_SS_STATS:
  4054. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4055. default:
  4056. return -EINVAL;
  4057. }
  4058. }
  4059. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4060. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4061. struct ethtool_stats *stats, u64 *data)
  4062. {
  4063. struct qeth_card *card = dev->ml_priv;
  4064. data[0] = card->stats.rx_packets -
  4065. card->perf_stats.initial_rx_packets;
  4066. data[1] = card->perf_stats.bufs_rec;
  4067. data[2] = card->stats.tx_packets -
  4068. card->perf_stats.initial_tx_packets;
  4069. data[3] = card->perf_stats.bufs_sent;
  4070. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4071. - card->perf_stats.skbs_sent_pack;
  4072. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4073. data[6] = card->perf_stats.skbs_sent_pack;
  4074. data[7] = card->perf_stats.bufs_sent_pack;
  4075. data[8] = card->perf_stats.sg_skbs_sent;
  4076. data[9] = card->perf_stats.sg_frags_sent;
  4077. data[10] = card->perf_stats.sg_skbs_rx;
  4078. data[11] = card->perf_stats.sg_frags_rx;
  4079. data[12] = card->perf_stats.sg_alloc_page_rx;
  4080. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4081. data[14] = card->perf_stats.large_send_cnt;
  4082. data[15] = card->perf_stats.sc_dp_p;
  4083. data[16] = card->perf_stats.sc_p_dp;
  4084. data[17] = QETH_LOW_WATERMARK_PACK;
  4085. data[18] = QETH_HIGH_WATERMARK_PACK;
  4086. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4087. data[20] = (card->qdio.no_out_queues > 1) ?
  4088. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4089. data[21] = (card->qdio.no_out_queues > 2) ?
  4090. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4091. data[22] = (card->qdio.no_out_queues > 3) ?
  4092. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4093. data[23] = card->perf_stats.inbound_time;
  4094. data[24] = card->perf_stats.inbound_cnt;
  4095. data[25] = card->perf_stats.inbound_do_qdio_time;
  4096. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4097. data[27] = card->perf_stats.outbound_handler_time;
  4098. data[28] = card->perf_stats.outbound_handler_cnt;
  4099. data[29] = card->perf_stats.outbound_time;
  4100. data[30] = card->perf_stats.outbound_cnt;
  4101. data[31] = card->perf_stats.outbound_do_qdio_time;
  4102. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4103. data[33] = card->perf_stats.tx_csum;
  4104. data[34] = card->perf_stats.tx_lin;
  4105. }
  4106. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4107. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4108. {
  4109. switch (stringset) {
  4110. case ETH_SS_STATS:
  4111. memcpy(data, &qeth_ethtool_stats_keys,
  4112. sizeof(qeth_ethtool_stats_keys));
  4113. break;
  4114. default:
  4115. WARN_ON(1);
  4116. break;
  4117. }
  4118. }
  4119. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4120. void qeth_core_get_drvinfo(struct net_device *dev,
  4121. struct ethtool_drvinfo *info)
  4122. {
  4123. struct qeth_card *card = dev->ml_priv;
  4124. if (card->options.layer2)
  4125. strcpy(info->driver, "qeth_l2");
  4126. else
  4127. strcpy(info->driver, "qeth_l3");
  4128. strcpy(info->version, "1.0");
  4129. strcpy(info->fw_version, card->info.mcl_level);
  4130. sprintf(info->bus_info, "%s/%s/%s",
  4131. CARD_RDEV_ID(card),
  4132. CARD_WDEV_ID(card),
  4133. CARD_DDEV_ID(card));
  4134. }
  4135. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4136. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4137. struct ethtool_cmd *ecmd)
  4138. {
  4139. struct qeth_card *card = netdev->ml_priv;
  4140. enum qeth_link_types link_type;
  4141. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4142. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4143. else
  4144. link_type = card->info.link_type;
  4145. ecmd->transceiver = XCVR_INTERNAL;
  4146. ecmd->supported = SUPPORTED_Autoneg;
  4147. ecmd->advertising = ADVERTISED_Autoneg;
  4148. ecmd->duplex = DUPLEX_FULL;
  4149. ecmd->autoneg = AUTONEG_ENABLE;
  4150. switch (link_type) {
  4151. case QETH_LINK_TYPE_FAST_ETH:
  4152. case QETH_LINK_TYPE_LANE_ETH100:
  4153. ecmd->supported |= SUPPORTED_10baseT_Half |
  4154. SUPPORTED_10baseT_Full |
  4155. SUPPORTED_100baseT_Half |
  4156. SUPPORTED_100baseT_Full |
  4157. SUPPORTED_TP;
  4158. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4159. ADVERTISED_10baseT_Full |
  4160. ADVERTISED_100baseT_Half |
  4161. ADVERTISED_100baseT_Full |
  4162. ADVERTISED_TP;
  4163. ecmd->speed = SPEED_100;
  4164. ecmd->port = PORT_TP;
  4165. break;
  4166. case QETH_LINK_TYPE_GBIT_ETH:
  4167. case QETH_LINK_TYPE_LANE_ETH1000:
  4168. ecmd->supported |= SUPPORTED_10baseT_Half |
  4169. SUPPORTED_10baseT_Full |
  4170. SUPPORTED_100baseT_Half |
  4171. SUPPORTED_100baseT_Full |
  4172. SUPPORTED_1000baseT_Half |
  4173. SUPPORTED_1000baseT_Full |
  4174. SUPPORTED_FIBRE;
  4175. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4176. ADVERTISED_10baseT_Full |
  4177. ADVERTISED_100baseT_Half |
  4178. ADVERTISED_100baseT_Full |
  4179. ADVERTISED_1000baseT_Half |
  4180. ADVERTISED_1000baseT_Full |
  4181. ADVERTISED_FIBRE;
  4182. ecmd->speed = SPEED_1000;
  4183. ecmd->port = PORT_FIBRE;
  4184. break;
  4185. case QETH_LINK_TYPE_10GBIT_ETH:
  4186. ecmd->supported |= SUPPORTED_10baseT_Half |
  4187. SUPPORTED_10baseT_Full |
  4188. SUPPORTED_100baseT_Half |
  4189. SUPPORTED_100baseT_Full |
  4190. SUPPORTED_1000baseT_Half |
  4191. SUPPORTED_1000baseT_Full |
  4192. SUPPORTED_10000baseT_Full |
  4193. SUPPORTED_FIBRE;
  4194. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4195. ADVERTISED_10baseT_Full |
  4196. ADVERTISED_100baseT_Half |
  4197. ADVERTISED_100baseT_Full |
  4198. ADVERTISED_1000baseT_Half |
  4199. ADVERTISED_1000baseT_Full |
  4200. ADVERTISED_10000baseT_Full |
  4201. ADVERTISED_FIBRE;
  4202. ecmd->speed = SPEED_10000;
  4203. ecmd->port = PORT_FIBRE;
  4204. break;
  4205. default:
  4206. ecmd->supported |= SUPPORTED_10baseT_Half |
  4207. SUPPORTED_10baseT_Full |
  4208. SUPPORTED_TP;
  4209. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4210. ADVERTISED_10baseT_Full |
  4211. ADVERTISED_TP;
  4212. ecmd->speed = SPEED_10;
  4213. ecmd->port = PORT_TP;
  4214. }
  4215. return 0;
  4216. }
  4217. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4218. static int __init qeth_core_init(void)
  4219. {
  4220. int rc;
  4221. pr_info("loading core functions\n");
  4222. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4223. rwlock_init(&qeth_core_card_list.rwlock);
  4224. rc = qeth_register_dbf_views();
  4225. if (rc)
  4226. goto out_err;
  4227. rc = ccw_driver_register(&qeth_ccw_driver);
  4228. if (rc)
  4229. goto ccw_err;
  4230. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4231. if (rc)
  4232. goto ccwgroup_err;
  4233. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4234. &driver_attr_group);
  4235. if (rc)
  4236. goto driver_err;
  4237. qeth_core_root_dev = root_device_register("qeth");
  4238. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4239. if (rc)
  4240. goto register_err;
  4241. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4242. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4243. if (!qeth_core_header_cache) {
  4244. rc = -ENOMEM;
  4245. goto slab_err;
  4246. }
  4247. return 0;
  4248. slab_err:
  4249. root_device_unregister(qeth_core_root_dev);
  4250. register_err:
  4251. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4252. &driver_attr_group);
  4253. driver_err:
  4254. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4255. ccwgroup_err:
  4256. ccw_driver_unregister(&qeth_ccw_driver);
  4257. ccw_err:
  4258. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4259. qeth_unregister_dbf_views();
  4260. out_err:
  4261. pr_err("Initializing the qeth device driver failed\n");
  4262. return rc;
  4263. }
  4264. static void __exit qeth_core_exit(void)
  4265. {
  4266. root_device_unregister(qeth_core_root_dev);
  4267. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4268. &driver_attr_group);
  4269. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4270. ccw_driver_unregister(&qeth_ccw_driver);
  4271. kmem_cache_destroy(qeth_core_header_cache);
  4272. qeth_unregister_dbf_views();
  4273. pr_info("core functions removed\n");
  4274. }
  4275. module_init(qeth_core_init);
  4276. module_exit(qeth_core_exit);
  4277. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4278. MODULE_DESCRIPTION("qeth core functions");
  4279. MODULE_LICENSE("GPL");