mcdi.c 31 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200
  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2009 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. /* Software-defined structure to the shared-memory */
  23. #define CMD_NOTIFY_PORT0 0
  24. #define CMD_NOTIFY_PORT1 4
  25. #define CMD_PDU_PORT0 0x008
  26. #define CMD_PDU_PORT1 0x108
  27. #define REBOOT_FLAG_PORT0 0x3f8
  28. #define REBOOT_FLAG_PORT1 0x3fc
  29. #define MCDI_RPC_TIMEOUT 10 /*seconds */
  30. #define MCDI_PDU(efx) \
  31. (efx_port_num(efx) ? CMD_PDU_PORT1 : CMD_PDU_PORT0)
  32. #define MCDI_DOORBELL(efx) \
  33. (efx_port_num(efx) ? CMD_NOTIFY_PORT1 : CMD_NOTIFY_PORT0)
  34. #define MCDI_REBOOT_FLAG(efx) \
  35. (efx_port_num(efx) ? REBOOT_FLAG_PORT1 : REBOOT_FLAG_PORT0)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. void efx_mcdi_init(struct efx_nic *efx)
  46. {
  47. struct efx_mcdi_iface *mcdi;
  48. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  49. return;
  50. mcdi = efx_mcdi(efx);
  51. init_waitqueue_head(&mcdi->wq);
  52. spin_lock_init(&mcdi->iface_lock);
  53. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  54. mcdi->mode = MCDI_MODE_POLL;
  55. (void) efx_mcdi_poll_reboot(efx);
  56. }
  57. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  58. const u8 *inbuf, size_t inlen)
  59. {
  60. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  61. unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  62. unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
  63. unsigned int i;
  64. efx_dword_t hdr;
  65. u32 xflags, seqno;
  66. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  67. BUG_ON(inlen & 3 || inlen >= 0x100);
  68. seqno = mcdi->seqno & SEQ_MASK;
  69. xflags = 0;
  70. if (mcdi->mode == MCDI_MODE_EVENTS)
  71. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  72. EFX_POPULATE_DWORD_6(hdr,
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. efx_writed(efx, &hdr, pdu);
  80. for (i = 0; i < inlen; i += 4)
  81. _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
  82. /* Ensure the payload is written out before the header */
  83. wmb();
  84. /* ring the doorbell with a distinctive value */
  85. _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
  86. }
  87. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  88. {
  89. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  90. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  91. int i;
  92. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  93. BUG_ON(outlen & 3 || outlen >= 0x100);
  94. for (i = 0; i < outlen; i += 4)
  95. *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
  96. }
  97. static int efx_mcdi_poll(struct efx_nic *efx)
  98. {
  99. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  100. unsigned int time, finish;
  101. unsigned int respseq, respcmd, error;
  102. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  103. unsigned int rc, spins;
  104. efx_dword_t reg;
  105. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  106. rc = -efx_mcdi_poll_reboot(efx);
  107. if (rc)
  108. goto out;
  109. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  110. * because generally mcdi responses are fast. After that, back off
  111. * and poll once a jiffy (approximately)
  112. */
  113. spins = TICK_USEC;
  114. finish = get_seconds() + MCDI_RPC_TIMEOUT;
  115. while (1) {
  116. if (spins != 0) {
  117. --spins;
  118. udelay(1);
  119. } else {
  120. schedule_timeout_uninterruptible(1);
  121. }
  122. time = get_seconds();
  123. rmb();
  124. efx_readd(efx, &reg, pdu);
  125. /* All 1's indicates that shared memory is in reset (and is
  126. * not a valid header). Wait for it to come out reset before
  127. * completing the command */
  128. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  129. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  130. break;
  131. if (time >= finish)
  132. return -ETIMEDOUT;
  133. }
  134. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  135. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  136. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  137. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  138. if (error && mcdi->resplen == 0) {
  139. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  140. rc = EIO;
  141. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  142. netif_err(efx, hw, efx->net_dev,
  143. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  144. respseq, mcdi->seqno);
  145. rc = EIO;
  146. } else if (error) {
  147. efx_readd(efx, &reg, pdu + 4);
  148. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  149. #define TRANSLATE_ERROR(name) \
  150. case MC_CMD_ERR_ ## name: \
  151. rc = name; \
  152. break
  153. TRANSLATE_ERROR(ENOENT);
  154. TRANSLATE_ERROR(EINTR);
  155. TRANSLATE_ERROR(EACCES);
  156. TRANSLATE_ERROR(EBUSY);
  157. TRANSLATE_ERROR(EINVAL);
  158. TRANSLATE_ERROR(EDEADLK);
  159. TRANSLATE_ERROR(ENOSYS);
  160. TRANSLATE_ERROR(ETIME);
  161. #undef TRANSLATE_ERROR
  162. default:
  163. rc = EIO;
  164. break;
  165. }
  166. } else
  167. rc = 0;
  168. out:
  169. mcdi->resprc = rc;
  170. if (rc)
  171. mcdi->resplen = 0;
  172. /* Return rc=0 like wait_event_timeout() */
  173. return 0;
  174. }
  175. /* Test and clear MC-rebooted flag for this port/function */
  176. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  177. {
  178. unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx);
  179. efx_dword_t reg;
  180. uint32_t value;
  181. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  182. return false;
  183. efx_readd(efx, &reg, addr);
  184. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  185. if (value == 0)
  186. return 0;
  187. EFX_ZERO_DWORD(reg);
  188. efx_writed(efx, &reg, addr);
  189. if (value == MC_STATUS_DWORD_ASSERT)
  190. return -EINTR;
  191. else
  192. return -EIO;
  193. }
  194. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  195. {
  196. /* Wait until the interface becomes QUIESCENT and we win the race
  197. * to mark it RUNNING. */
  198. wait_event(mcdi->wq,
  199. atomic_cmpxchg(&mcdi->state,
  200. MCDI_STATE_QUIESCENT,
  201. MCDI_STATE_RUNNING)
  202. == MCDI_STATE_QUIESCENT);
  203. }
  204. static int efx_mcdi_await_completion(struct efx_nic *efx)
  205. {
  206. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  207. if (wait_event_timeout(
  208. mcdi->wq,
  209. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  210. msecs_to_jiffies(MCDI_RPC_TIMEOUT * 1000)) == 0)
  211. return -ETIMEDOUT;
  212. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  213. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  214. * completed the request first, then we'll just end up completing the
  215. * request again, which is safe.
  216. *
  217. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  218. * wait_event_timeout() implicitly provides.
  219. */
  220. if (mcdi->mode == MCDI_MODE_POLL)
  221. return efx_mcdi_poll(efx);
  222. return 0;
  223. }
  224. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  225. {
  226. /* If the interface is RUNNING, then move to COMPLETED and wake any
  227. * waiters. If the interface isn't in RUNNING then we've received a
  228. * duplicate completion after we've already transitioned back to
  229. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  230. * have failed the seqno check].
  231. */
  232. if (atomic_cmpxchg(&mcdi->state,
  233. MCDI_STATE_RUNNING,
  234. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  235. wake_up(&mcdi->wq);
  236. return true;
  237. }
  238. return false;
  239. }
  240. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  241. {
  242. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  243. wake_up(&mcdi->wq);
  244. }
  245. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  246. unsigned int datalen, unsigned int errno)
  247. {
  248. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  249. bool wake = false;
  250. spin_lock(&mcdi->iface_lock);
  251. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  252. if (mcdi->credits)
  253. /* The request has been cancelled */
  254. --mcdi->credits;
  255. else
  256. netif_err(efx, hw, efx->net_dev,
  257. "MC response mismatch tx seq 0x%x rx "
  258. "seq 0x%x\n", seqno, mcdi->seqno);
  259. } else {
  260. mcdi->resprc = errno;
  261. mcdi->resplen = datalen;
  262. wake = true;
  263. }
  264. spin_unlock(&mcdi->iface_lock);
  265. if (wake)
  266. efx_mcdi_complete(mcdi);
  267. }
  268. /* Issue the given command by writing the data into the shared memory PDU,
  269. * ring the doorbell and wait for completion. Copyout the result. */
  270. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  271. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  272. size_t *outlen_actual)
  273. {
  274. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  275. int rc;
  276. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  277. efx_mcdi_acquire(mcdi);
  278. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  279. spin_lock_bh(&mcdi->iface_lock);
  280. ++mcdi->seqno;
  281. spin_unlock_bh(&mcdi->iface_lock);
  282. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  283. if (mcdi->mode == MCDI_MODE_POLL)
  284. rc = efx_mcdi_poll(efx);
  285. else
  286. rc = efx_mcdi_await_completion(efx);
  287. if (rc != 0) {
  288. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  289. * and completing a request we've just cancelled, by ensuring
  290. * that the seqno check therein fails.
  291. */
  292. spin_lock_bh(&mcdi->iface_lock);
  293. ++mcdi->seqno;
  294. ++mcdi->credits;
  295. spin_unlock_bh(&mcdi->iface_lock);
  296. netif_err(efx, hw, efx->net_dev,
  297. "MC command 0x%x inlen %d mode %d timed out\n",
  298. cmd, (int)inlen, mcdi->mode);
  299. } else {
  300. size_t resplen;
  301. /* At the very least we need a memory barrier here to ensure
  302. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  303. * a spurious efx_mcdi_ev_cpl() running concurrently by
  304. * acquiring the iface_lock. */
  305. spin_lock_bh(&mcdi->iface_lock);
  306. rc = -mcdi->resprc;
  307. resplen = mcdi->resplen;
  308. spin_unlock_bh(&mcdi->iface_lock);
  309. if (rc == 0) {
  310. efx_mcdi_copyout(efx, outbuf,
  311. min(outlen, mcdi->resplen + 3) & ~0x3);
  312. if (outlen_actual != NULL)
  313. *outlen_actual = resplen;
  314. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  315. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  316. else if (rc == -EIO || rc == -EINTR) {
  317. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  318. -rc);
  319. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  320. } else
  321. netif_dbg(efx, hw, efx->net_dev,
  322. "MC command 0x%x inlen %d failed rc=%d\n",
  323. cmd, (int)inlen, -rc);
  324. }
  325. efx_mcdi_release(mcdi);
  326. return rc;
  327. }
  328. void efx_mcdi_mode_poll(struct efx_nic *efx)
  329. {
  330. struct efx_mcdi_iface *mcdi;
  331. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  332. return;
  333. mcdi = efx_mcdi(efx);
  334. if (mcdi->mode == MCDI_MODE_POLL)
  335. return;
  336. /* We can switch from event completion to polled completion, because
  337. * mcdi requests are always completed in shared memory. We do this by
  338. * switching the mode to POLL'd then completing the request.
  339. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  340. *
  341. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  342. * which efx_mcdi_complete() provides for us.
  343. */
  344. mcdi->mode = MCDI_MODE_POLL;
  345. efx_mcdi_complete(mcdi);
  346. }
  347. void efx_mcdi_mode_event(struct efx_nic *efx)
  348. {
  349. struct efx_mcdi_iface *mcdi;
  350. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  351. return;
  352. mcdi = efx_mcdi(efx);
  353. if (mcdi->mode == MCDI_MODE_EVENTS)
  354. return;
  355. /* We can't switch from polled to event completion in the middle of a
  356. * request, because the completion method is specified in the request.
  357. * So acquire the interface to serialise the requestors. We don't need
  358. * to acquire the iface_lock to change the mode here, but we do need a
  359. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  360. * efx_mcdi_acquire() provides.
  361. */
  362. efx_mcdi_acquire(mcdi);
  363. mcdi->mode = MCDI_MODE_EVENTS;
  364. efx_mcdi_release(mcdi);
  365. }
  366. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  367. {
  368. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  369. /* If there is an outstanding MCDI request, it has been terminated
  370. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  371. * in polled mode, then do nothing because the MC reboot handler will
  372. * set the header correctly. However, if the mcdi interface is waiting
  373. * for a CMDDONE event it won't receive it [and since all MCDI events
  374. * are sent to the same queue, we can't be racing with
  375. * efx_mcdi_ev_cpl()]
  376. *
  377. * There's a race here with efx_mcdi_rpc(), because we might receive
  378. * a REBOOT event *before* the request has been copied out. In polled
  379. * mode (during startup) this is irrelevent, because efx_mcdi_complete()
  380. * is ignored. In event mode, this condition is just an edge-case of
  381. * receiving a REBOOT event after posting the MCDI request. Did the mc
  382. * reboot before or after the copyout? The best we can do always is
  383. * just return failure.
  384. */
  385. spin_lock(&mcdi->iface_lock);
  386. if (efx_mcdi_complete(mcdi)) {
  387. if (mcdi->mode == MCDI_MODE_EVENTS) {
  388. mcdi->resprc = rc;
  389. mcdi->resplen = 0;
  390. ++mcdi->credits;
  391. }
  392. } else
  393. /* Nobody was waiting for an MCDI request, so trigger a reset */
  394. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  395. spin_unlock(&mcdi->iface_lock);
  396. }
  397. static unsigned int efx_mcdi_event_link_speed[] = {
  398. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  399. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  400. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  401. };
  402. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  403. {
  404. u32 flags, fcntl, speed, lpa;
  405. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  406. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  407. speed = efx_mcdi_event_link_speed[speed];
  408. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  409. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  410. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  411. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  412. * which is only run after flushing the event queues. Therefore, it
  413. * is safe to modify the link state outside of the mac_lock here.
  414. */
  415. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  416. efx_mcdi_phy_check_fcntl(efx, lpa);
  417. efx_link_status_changed(efx);
  418. }
  419. static const char *sensor_names[] = {
  420. [MC_CMD_SENSOR_CONTROLLER_TEMP] = "Controller temp. sensor",
  421. [MC_CMD_SENSOR_PHY_COMMON_TEMP] = "PHY shared temp. sensor",
  422. [MC_CMD_SENSOR_CONTROLLER_COOLING] = "Controller cooling",
  423. [MC_CMD_SENSOR_PHY0_TEMP] = "PHY 0 temp. sensor",
  424. [MC_CMD_SENSOR_PHY0_COOLING] = "PHY 0 cooling",
  425. [MC_CMD_SENSOR_PHY1_TEMP] = "PHY 1 temp. sensor",
  426. [MC_CMD_SENSOR_PHY1_COOLING] = "PHY 1 cooling",
  427. [MC_CMD_SENSOR_IN_1V0] = "1.0V supply sensor",
  428. [MC_CMD_SENSOR_IN_1V2] = "1.2V supply sensor",
  429. [MC_CMD_SENSOR_IN_1V8] = "1.8V supply sensor",
  430. [MC_CMD_SENSOR_IN_2V5] = "2.5V supply sensor",
  431. [MC_CMD_SENSOR_IN_3V3] = "3.3V supply sensor",
  432. [MC_CMD_SENSOR_IN_12V0] = "12V supply sensor"
  433. };
  434. static const char *sensor_status_names[] = {
  435. [MC_CMD_SENSOR_STATE_OK] = "OK",
  436. [MC_CMD_SENSOR_STATE_WARNING] = "Warning",
  437. [MC_CMD_SENSOR_STATE_FATAL] = "Fatal",
  438. [MC_CMD_SENSOR_STATE_BROKEN] = "Device failure",
  439. };
  440. static void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
  441. {
  442. unsigned int monitor, state, value;
  443. const char *name, *state_txt;
  444. monitor = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_MONITOR);
  445. state = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_STATE);
  446. value = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_VALUE);
  447. /* Deal gracefully with the board having more drivers than we
  448. * know about, but do not expect new sensor states. */
  449. name = (monitor >= ARRAY_SIZE(sensor_names))
  450. ? "No sensor name available" :
  451. sensor_names[monitor];
  452. EFX_BUG_ON_PARANOID(state >= ARRAY_SIZE(sensor_status_names));
  453. state_txt = sensor_status_names[state];
  454. netif_err(efx, hw, efx->net_dev,
  455. "Sensor %d (%s) reports condition '%s' for raw value %d\n",
  456. monitor, name, state_txt, value);
  457. }
  458. /* Called from falcon_process_eventq for MCDI events */
  459. void efx_mcdi_process_event(struct efx_channel *channel,
  460. efx_qword_t *event)
  461. {
  462. struct efx_nic *efx = channel->efx;
  463. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  464. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  465. switch (code) {
  466. case MCDI_EVENT_CODE_BADSSERT:
  467. netif_err(efx, hw, efx->net_dev,
  468. "MC watchdog or assertion failure at 0x%x\n", data);
  469. efx_mcdi_ev_death(efx, EINTR);
  470. break;
  471. case MCDI_EVENT_CODE_PMNOTICE:
  472. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  473. break;
  474. case MCDI_EVENT_CODE_CMDDONE:
  475. efx_mcdi_ev_cpl(efx,
  476. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  477. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  478. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  479. break;
  480. case MCDI_EVENT_CODE_LINKCHANGE:
  481. efx_mcdi_process_link_change(efx, event);
  482. break;
  483. case MCDI_EVENT_CODE_SENSOREVT:
  484. efx_mcdi_sensor_event(efx, event);
  485. break;
  486. case MCDI_EVENT_CODE_SCHEDERR:
  487. netif_info(efx, hw, efx->net_dev,
  488. "MC Scheduler error address=0x%x\n", data);
  489. break;
  490. case MCDI_EVENT_CODE_REBOOT:
  491. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  492. efx_mcdi_ev_death(efx, EIO);
  493. break;
  494. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  495. /* MAC stats are gather lazily. We can ignore this. */
  496. break;
  497. default:
  498. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  499. code);
  500. }
  501. }
  502. /**************************************************************************
  503. *
  504. * Specific request functions
  505. *
  506. **************************************************************************
  507. */
  508. int efx_mcdi_fwver(struct efx_nic *efx, u64 *version, u32 *build)
  509. {
  510. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_V1_OUT_LEN, 4)];
  511. size_t outlength;
  512. const __le16 *ver_words;
  513. int rc;
  514. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  515. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  516. outbuf, sizeof(outbuf), &outlength);
  517. if (rc)
  518. goto fail;
  519. if (outlength == MC_CMD_GET_VERSION_V0_OUT_LEN) {
  520. *version = 0;
  521. *build = MCDI_DWORD(outbuf, GET_VERSION_OUT_FIRMWARE);
  522. return 0;
  523. }
  524. if (outlength < MC_CMD_GET_VERSION_V1_OUT_LEN) {
  525. rc = -EIO;
  526. goto fail;
  527. }
  528. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  529. *version = (((u64)le16_to_cpu(ver_words[0]) << 48) |
  530. ((u64)le16_to_cpu(ver_words[1]) << 32) |
  531. ((u64)le16_to_cpu(ver_words[2]) << 16) |
  532. le16_to_cpu(ver_words[3]));
  533. *build = MCDI_DWORD(outbuf, GET_VERSION_OUT_FIRMWARE);
  534. return 0;
  535. fail:
  536. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  537. return rc;
  538. }
  539. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  540. bool *was_attached)
  541. {
  542. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  543. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  544. size_t outlen;
  545. int rc;
  546. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  547. driver_operating ? 1 : 0);
  548. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  549. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  550. outbuf, sizeof(outbuf), &outlen);
  551. if (rc)
  552. goto fail;
  553. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  554. rc = -EIO;
  555. goto fail;
  556. }
  557. if (was_attached != NULL)
  558. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  559. return 0;
  560. fail:
  561. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  562. return rc;
  563. }
  564. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  565. u16 *fw_subtype_list)
  566. {
  567. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LEN];
  568. size_t outlen;
  569. int port_num = efx_port_num(efx);
  570. int offset;
  571. int rc;
  572. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  573. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  574. outbuf, sizeof(outbuf), &outlen);
  575. if (rc)
  576. goto fail;
  577. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LEN) {
  578. rc = -EIO;
  579. goto fail;
  580. }
  581. offset = (port_num)
  582. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  583. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  584. if (mac_address)
  585. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  586. if (fw_subtype_list)
  587. memcpy(fw_subtype_list,
  588. outbuf + MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST,
  589. MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN);
  590. return 0;
  591. fail:
  592. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  593. __func__, rc, (int)outlen);
  594. return rc;
  595. }
  596. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  597. {
  598. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  599. u32 dest = 0;
  600. int rc;
  601. if (uart)
  602. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  603. if (evq)
  604. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  605. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  606. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  607. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  608. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  609. NULL, 0, NULL);
  610. if (rc)
  611. goto fail;
  612. return 0;
  613. fail:
  614. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  615. return rc;
  616. }
  617. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  618. {
  619. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  620. size_t outlen;
  621. int rc;
  622. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  623. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  624. outbuf, sizeof(outbuf), &outlen);
  625. if (rc)
  626. goto fail;
  627. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  628. rc = -EIO;
  629. goto fail;
  630. }
  631. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  632. return 0;
  633. fail:
  634. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  635. __func__, rc);
  636. return rc;
  637. }
  638. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  639. size_t *size_out, size_t *erase_size_out,
  640. bool *protected_out)
  641. {
  642. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  643. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  644. size_t outlen;
  645. int rc;
  646. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  647. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  648. outbuf, sizeof(outbuf), &outlen);
  649. if (rc)
  650. goto fail;
  651. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  652. rc = -EIO;
  653. goto fail;
  654. }
  655. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  656. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  657. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  658. (1 << MC_CMD_NVRAM_PROTECTED_LBN));
  659. return 0;
  660. fail:
  661. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  662. return rc;
  663. }
  664. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  665. {
  666. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  667. int rc;
  668. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  669. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  670. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  671. NULL, 0, NULL);
  672. if (rc)
  673. goto fail;
  674. return 0;
  675. fail:
  676. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  677. return rc;
  678. }
  679. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  680. loff_t offset, u8 *buffer, size_t length)
  681. {
  682. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  683. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  684. size_t outlen;
  685. int rc;
  686. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  687. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  688. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  689. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  690. outbuf, sizeof(outbuf), &outlen);
  691. if (rc)
  692. goto fail;
  693. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  694. return 0;
  695. fail:
  696. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  697. return rc;
  698. }
  699. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  700. loff_t offset, const u8 *buffer, size_t length)
  701. {
  702. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  703. int rc;
  704. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  705. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  706. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  707. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  708. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  709. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  710. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  711. NULL, 0, NULL);
  712. if (rc)
  713. goto fail;
  714. return 0;
  715. fail:
  716. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  717. return rc;
  718. }
  719. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  720. loff_t offset, size_t length)
  721. {
  722. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  723. int rc;
  724. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  725. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  726. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  727. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  728. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  729. NULL, 0, NULL);
  730. if (rc)
  731. goto fail;
  732. return 0;
  733. fail:
  734. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  735. return rc;
  736. }
  737. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  738. {
  739. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  740. int rc;
  741. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  742. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  743. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  744. NULL, 0, NULL);
  745. if (rc)
  746. goto fail;
  747. return 0;
  748. fail:
  749. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  750. return rc;
  751. }
  752. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  753. {
  754. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  755. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  756. int rc;
  757. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  758. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  759. outbuf, sizeof(outbuf), NULL);
  760. if (rc)
  761. return rc;
  762. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  763. case MC_CMD_NVRAM_TEST_PASS:
  764. case MC_CMD_NVRAM_TEST_NOTSUPP:
  765. return 0;
  766. default:
  767. return -EIO;
  768. }
  769. }
  770. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  771. {
  772. u32 nvram_types;
  773. unsigned int type;
  774. int rc;
  775. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  776. if (rc)
  777. goto fail1;
  778. type = 0;
  779. while (nvram_types != 0) {
  780. if (nvram_types & 1) {
  781. rc = efx_mcdi_nvram_test(efx, type);
  782. if (rc)
  783. goto fail2;
  784. }
  785. type++;
  786. nvram_types >>= 1;
  787. }
  788. return 0;
  789. fail2:
  790. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  791. __func__, type);
  792. fail1:
  793. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  794. return rc;
  795. }
  796. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  797. {
  798. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  799. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  800. unsigned int flags, index, ofst;
  801. const char *reason;
  802. size_t outlen;
  803. int retry;
  804. int rc;
  805. /* Attempt to read any stored assertion state before we reboot
  806. * the mcfw out of the assertion handler. Retry twice, once
  807. * because a boot-time assertion might cause this command to fail
  808. * with EINTR. And once again because GET_ASSERTS can race with
  809. * MC_CMD_REBOOT running on the other port. */
  810. retry = 2;
  811. do {
  812. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  813. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  814. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  815. outbuf, sizeof(outbuf), &outlen);
  816. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  817. if (rc)
  818. return rc;
  819. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  820. return -EIO;
  821. /* Print out any recorded assertion state */
  822. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  823. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  824. return 0;
  825. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  826. ? "system-level assertion"
  827. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  828. ? "thread-level assertion"
  829. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  830. ? "watchdog reset"
  831. : "unknown assertion";
  832. netif_err(efx, hw, efx->net_dev,
  833. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  834. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  835. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  836. /* Print out the registers */
  837. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  838. for (index = 1; index < 32; index++) {
  839. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
  840. MCDI_DWORD2(outbuf, ofst));
  841. ofst += sizeof(efx_dword_t);
  842. }
  843. return 0;
  844. }
  845. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  846. {
  847. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  848. /* Atomically reboot the mcfw out of the assertion handler */
  849. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  850. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  851. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  852. efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  853. NULL, 0, NULL);
  854. }
  855. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  856. {
  857. int rc;
  858. rc = efx_mcdi_read_assertion(efx);
  859. if (rc)
  860. return rc;
  861. efx_mcdi_exit_assertion(efx);
  862. return 0;
  863. }
  864. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  865. {
  866. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  867. int rc;
  868. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  869. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  870. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  871. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  872. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  873. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  874. NULL, 0, NULL);
  875. if (rc)
  876. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  877. __func__, rc);
  878. }
  879. int efx_mcdi_reset_port(struct efx_nic *efx)
  880. {
  881. int rc = efx_mcdi_rpc(efx, MC_CMD_PORT_RESET, NULL, 0, NULL, 0, NULL);
  882. if (rc)
  883. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  884. __func__, rc);
  885. return rc;
  886. }
  887. int efx_mcdi_reset_mc(struct efx_nic *efx)
  888. {
  889. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  890. int rc;
  891. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  892. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  893. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  894. NULL, 0, NULL);
  895. /* White is black, and up is down */
  896. if (rc == -EIO)
  897. return 0;
  898. if (rc == 0)
  899. rc = -EIO;
  900. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  901. return rc;
  902. }
  903. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  904. const u8 *mac, int *id_out)
  905. {
  906. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  907. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  908. size_t outlen;
  909. int rc;
  910. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  911. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  912. MC_CMD_FILTER_MODE_SIMPLE);
  913. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  914. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  915. outbuf, sizeof(outbuf), &outlen);
  916. if (rc)
  917. goto fail;
  918. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  919. rc = -EIO;
  920. goto fail;
  921. }
  922. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  923. return 0;
  924. fail:
  925. *id_out = -1;
  926. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  927. return rc;
  928. }
  929. int
  930. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  931. {
  932. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  933. }
  934. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  935. {
  936. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  937. size_t outlen;
  938. int rc;
  939. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  940. outbuf, sizeof(outbuf), &outlen);
  941. if (rc)
  942. goto fail;
  943. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  944. rc = -EIO;
  945. goto fail;
  946. }
  947. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  948. return 0;
  949. fail:
  950. *id_out = -1;
  951. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  952. return rc;
  953. }
  954. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  955. {
  956. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  957. int rc;
  958. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  959. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  960. NULL, 0, NULL);
  961. if (rc)
  962. goto fail;
  963. return 0;
  964. fail:
  965. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  966. return rc;
  967. }
  968. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  969. {
  970. int rc;
  971. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  972. if (rc)
  973. goto fail;
  974. return 0;
  975. fail:
  976. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  977. return rc;
  978. }