ixgbe_82598.c 35 KB

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  1. /*******************************************************************************
  2. Intel 10 Gigabit PCI Express Linux driver
  3. Copyright(c) 1999 - 2010 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  18. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  19. *******************************************************************************/
  20. #include <linux/pci.h>
  21. #include <linux/delay.h>
  22. #include <linux/sched.h>
  23. #include "ixgbe.h"
  24. #include "ixgbe_phy.h"
  25. #define IXGBE_82598_MAX_TX_QUEUES 32
  26. #define IXGBE_82598_MAX_RX_QUEUES 64
  27. #define IXGBE_82598_RAR_ENTRIES 16
  28. #define IXGBE_82598_MC_TBL_SIZE 128
  29. #define IXGBE_82598_VFT_TBL_SIZE 128
  30. static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
  31. ixgbe_link_speed speed,
  32. bool autoneg,
  33. bool autoneg_wait_to_complete);
  34. static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  35. u8 *eeprom_data);
  36. /**
  37. * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
  38. * @hw: pointer to the HW structure
  39. *
  40. * The defaults for 82598 should be in the range of 50us to 50ms,
  41. * however the hardware default for these parts is 500us to 1ms which is less
  42. * than the 10ms recommended by the pci-e spec. To address this we need to
  43. * increase the value to either 10ms to 250ms for capability version 1 config,
  44. * or 16ms to 55ms for version 2.
  45. **/
  46. static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
  47. {
  48. struct ixgbe_adapter *adapter = hw->back;
  49. u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
  50. u16 pcie_devctl2;
  51. /* only take action if timeout value is defaulted to 0 */
  52. if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
  53. goto out;
  54. /*
  55. * if capababilities version is type 1 we can write the
  56. * timeout of 10ms to 250ms through the GCR register
  57. */
  58. if (!(gcr & IXGBE_GCR_CAP_VER2)) {
  59. gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
  60. goto out;
  61. }
  62. /*
  63. * for version 2 capabilities we need to write the config space
  64. * directly in order to set the completion timeout value for
  65. * 16ms to 55ms
  66. */
  67. pci_read_config_word(adapter->pdev,
  68. IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2);
  69. pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
  70. pci_write_config_word(adapter->pdev,
  71. IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
  72. out:
  73. /* disable completion timeout resend */
  74. gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
  75. IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
  76. }
  77. /**
  78. * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  79. * @hw: pointer to hardware structure
  80. *
  81. * Read PCIe configuration space, and get the MSI-X vector count from
  82. * the capabilities table.
  83. **/
  84. static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  85. {
  86. struct ixgbe_adapter *adapter = hw->back;
  87. u16 msix_count;
  88. pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  89. &msix_count);
  90. msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  91. /* MSI-X count is zero-based in HW, so increment to give proper value */
  92. msix_count++;
  93. return msix_count;
  94. }
  95. /**
  96. */
  97. static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  98. {
  99. struct ixgbe_mac_info *mac = &hw->mac;
  100. /* Call PHY identify routine to get the phy type */
  101. ixgbe_identify_phy_generic(hw);
  102. mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
  103. mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
  104. mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
  105. mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
  106. mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
  107. mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
  108. return 0;
  109. }
  110. /**
  111. * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
  112. * @hw: pointer to hardware structure
  113. *
  114. * Initialize any function pointers that were not able to be
  115. * set during get_invariants because the PHY/SFP type was
  116. * not known. Perform the SFP init if necessary.
  117. *
  118. **/
  119. static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
  120. {
  121. struct ixgbe_mac_info *mac = &hw->mac;
  122. struct ixgbe_phy_info *phy = &hw->phy;
  123. s32 ret_val = 0;
  124. u16 list_offset, data_offset;
  125. /* Identify the PHY */
  126. phy->ops.identify(hw);
  127. /* Overwrite the link function pointers if copper PHY */
  128. if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
  129. mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
  130. mac->ops.get_link_capabilities =
  131. &ixgbe_get_copper_link_capabilities_generic;
  132. }
  133. switch (hw->phy.type) {
  134. case ixgbe_phy_tn:
  135. phy->ops.check_link = &ixgbe_check_phy_link_tnx;
  136. phy->ops.get_firmware_version =
  137. &ixgbe_get_phy_firmware_version_tnx;
  138. break;
  139. case ixgbe_phy_nl:
  140. phy->ops.reset = &ixgbe_reset_phy_nl;
  141. /* Call SFP+ identify routine to get the SFP+ module type */
  142. ret_val = phy->ops.identify_sfp(hw);
  143. if (ret_val != 0)
  144. goto out;
  145. else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
  146. ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
  147. goto out;
  148. }
  149. /* Check to see if SFP+ module is supported */
  150. ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
  151. &list_offset,
  152. &data_offset);
  153. if (ret_val != 0) {
  154. ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
  155. goto out;
  156. }
  157. break;
  158. default:
  159. break;
  160. }
  161. out:
  162. return ret_val;
  163. }
  164. /**
  165. * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
  166. * @hw: pointer to hardware structure
  167. *
  168. * Starts the hardware using the generic start_hw function.
  169. * Then set pcie completion timeout
  170. **/
  171. static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
  172. {
  173. s32 ret_val = 0;
  174. ret_val = ixgbe_start_hw_generic(hw);
  175. /* set the completion timeout for interface */
  176. if (ret_val == 0)
  177. ixgbe_set_pcie_completion_timeout(hw);
  178. return ret_val;
  179. }
  180. /**
  181. * ixgbe_get_link_capabilities_82598 - Determines link capabilities
  182. * @hw: pointer to hardware structure
  183. * @speed: pointer to link speed
  184. * @autoneg: boolean auto-negotiation value
  185. *
  186. * Determines the link capabilities by reading the AUTOC register.
  187. **/
  188. static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
  189. ixgbe_link_speed *speed,
  190. bool *autoneg)
  191. {
  192. s32 status = 0;
  193. u32 autoc = 0;
  194. /*
  195. * Determine link capabilities based on the stored value of AUTOC,
  196. * which represents EEPROM defaults. If AUTOC value has not been
  197. * stored, use the current register value.
  198. */
  199. if (hw->mac.orig_link_settings_stored)
  200. autoc = hw->mac.orig_autoc;
  201. else
  202. autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
  203. switch (autoc & IXGBE_AUTOC_LMS_MASK) {
  204. case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
  205. *speed = IXGBE_LINK_SPEED_1GB_FULL;
  206. *autoneg = false;
  207. break;
  208. case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
  209. *speed = IXGBE_LINK_SPEED_10GB_FULL;
  210. *autoneg = false;
  211. break;
  212. case IXGBE_AUTOC_LMS_1G_AN:
  213. *speed = IXGBE_LINK_SPEED_1GB_FULL;
  214. *autoneg = true;
  215. break;
  216. case IXGBE_AUTOC_LMS_KX4_AN:
  217. case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
  218. *speed = IXGBE_LINK_SPEED_UNKNOWN;
  219. if (autoc & IXGBE_AUTOC_KX4_SUPP)
  220. *speed |= IXGBE_LINK_SPEED_10GB_FULL;
  221. if (autoc & IXGBE_AUTOC_KX_SUPP)
  222. *speed |= IXGBE_LINK_SPEED_1GB_FULL;
  223. *autoneg = true;
  224. break;
  225. default:
  226. status = IXGBE_ERR_LINK_SETUP;
  227. break;
  228. }
  229. return status;
  230. }
  231. /**
  232. * ixgbe_get_media_type_82598 - Determines media type
  233. * @hw: pointer to hardware structure
  234. *
  235. * Returns the media type (fiber, copper, backplane)
  236. **/
  237. static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
  238. {
  239. enum ixgbe_media_type media_type;
  240. /* Media type for I82598 is based on device ID */
  241. switch (hw->device_id) {
  242. case IXGBE_DEV_ID_82598:
  243. case IXGBE_DEV_ID_82598_BX:
  244. media_type = ixgbe_media_type_backplane;
  245. break;
  246. case IXGBE_DEV_ID_82598AF_DUAL_PORT:
  247. case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
  248. case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
  249. case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
  250. case IXGBE_DEV_ID_82598EB_XF_LR:
  251. case IXGBE_DEV_ID_82598EB_SFP_LOM:
  252. media_type = ixgbe_media_type_fiber;
  253. break;
  254. case IXGBE_DEV_ID_82598EB_CX4:
  255. case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
  256. media_type = ixgbe_media_type_cx4;
  257. break;
  258. case IXGBE_DEV_ID_82598AT:
  259. case IXGBE_DEV_ID_82598AT2:
  260. media_type = ixgbe_media_type_copper;
  261. break;
  262. default:
  263. media_type = ixgbe_media_type_unknown;
  264. break;
  265. }
  266. return media_type;
  267. }
  268. /**
  269. * ixgbe_fc_enable_82598 - Enable flow control
  270. * @hw: pointer to hardware structure
  271. * @packetbuf_num: packet buffer number (0-7)
  272. *
  273. * Enable flow control according to the current settings.
  274. **/
  275. static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
  276. {
  277. s32 ret_val = 0;
  278. u32 fctrl_reg;
  279. u32 rmcs_reg;
  280. u32 reg;
  281. u32 rx_pba_size;
  282. u32 link_speed = 0;
  283. bool link_up;
  284. #ifdef CONFIG_DCB
  285. if (hw->fc.requested_mode == ixgbe_fc_pfc)
  286. goto out;
  287. #endif /* CONFIG_DCB */
  288. /*
  289. * On 82598 having Rx FC on causes resets while doing 1G
  290. * so if it's on turn it off once we know link_speed. For
  291. * more details see 82598 Specification update.
  292. */
  293. hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
  294. if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
  295. switch (hw->fc.requested_mode) {
  296. case ixgbe_fc_full:
  297. hw->fc.requested_mode = ixgbe_fc_tx_pause;
  298. break;
  299. case ixgbe_fc_rx_pause:
  300. hw->fc.requested_mode = ixgbe_fc_none;
  301. break;
  302. default:
  303. /* no change */
  304. break;
  305. }
  306. }
  307. /* Negotiate the fc mode to use */
  308. ret_val = ixgbe_fc_autoneg(hw);
  309. if (ret_val)
  310. goto out;
  311. /* Disable any previous flow control settings */
  312. fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
  313. fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
  314. rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
  315. rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
  316. /*
  317. * The possible values of fc.current_mode are:
  318. * 0: Flow control is completely disabled
  319. * 1: Rx flow control is enabled (we can receive pause frames,
  320. * but not send pause frames).
  321. * 2: Tx flow control is enabled (we can send pause frames but
  322. * we do not support receiving pause frames).
  323. * 3: Both Rx and Tx flow control (symmetric) are enabled.
  324. * other: Invalid.
  325. #ifdef CONFIG_DCB
  326. * 4: Priority Flow Control is enabled.
  327. #endif
  328. */
  329. switch (hw->fc.current_mode) {
  330. case ixgbe_fc_none:
  331. /*
  332. * Flow control is disabled by software override or autoneg.
  333. * The code below will actually disable it in the HW.
  334. */
  335. break;
  336. case ixgbe_fc_rx_pause:
  337. /*
  338. * Rx Flow control is enabled and Tx Flow control is
  339. * disabled by software override. Since there really
  340. * isn't a way to advertise that we are capable of RX
  341. * Pause ONLY, we will advertise that we support both
  342. * symmetric and asymmetric Rx PAUSE. Later, we will
  343. * disable the adapter's ability to send PAUSE frames.
  344. */
  345. fctrl_reg |= IXGBE_FCTRL_RFCE;
  346. break;
  347. case ixgbe_fc_tx_pause:
  348. /*
  349. * Tx Flow control is enabled, and Rx Flow control is
  350. * disabled by software override.
  351. */
  352. rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
  353. break;
  354. case ixgbe_fc_full:
  355. /* Flow control (both Rx and Tx) is enabled by SW override. */
  356. fctrl_reg |= IXGBE_FCTRL_RFCE;
  357. rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
  358. break;
  359. #ifdef CONFIG_DCB
  360. case ixgbe_fc_pfc:
  361. goto out;
  362. break;
  363. #endif /* CONFIG_DCB */
  364. default:
  365. hw_dbg(hw, "Flow control param set incorrectly\n");
  366. ret_val = IXGBE_ERR_CONFIG;
  367. goto out;
  368. break;
  369. }
  370. /* Set 802.3x based flow control settings. */
  371. fctrl_reg |= IXGBE_FCTRL_DPF;
  372. IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
  373. IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
  374. /* Set up and enable Rx high/low water mark thresholds, enable XON. */
  375. if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
  376. rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
  377. rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
  378. reg = (rx_pba_size - hw->fc.low_water) << 6;
  379. if (hw->fc.send_xon)
  380. reg |= IXGBE_FCRTL_XONE;
  381. IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
  382. reg = (rx_pba_size - hw->fc.high_water) << 10;
  383. reg |= IXGBE_FCRTH_FCEN;
  384. IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
  385. }
  386. /* Configure pause time (2 TCs per register) */
  387. reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
  388. if ((packetbuf_num & 1) == 0)
  389. reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
  390. else
  391. reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
  392. IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
  393. IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
  394. out:
  395. return ret_val;
  396. }
  397. /**
  398. * ixgbe_start_mac_link_82598 - Configures MAC link settings
  399. * @hw: pointer to hardware structure
  400. *
  401. * Configures link settings based on values in the ixgbe_hw struct.
  402. * Restarts the link. Performs autonegotiation if needed.
  403. **/
  404. static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
  405. bool autoneg_wait_to_complete)
  406. {
  407. u32 autoc_reg;
  408. u32 links_reg;
  409. u32 i;
  410. s32 status = 0;
  411. /* Restart link */
  412. autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
  413. autoc_reg |= IXGBE_AUTOC_AN_RESTART;
  414. IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
  415. /* Only poll for autoneg to complete if specified to do so */
  416. if (autoneg_wait_to_complete) {
  417. if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
  418. IXGBE_AUTOC_LMS_KX4_AN ||
  419. (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
  420. IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
  421. links_reg = 0; /* Just in case Autoneg time = 0 */
  422. for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
  423. links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
  424. if (links_reg & IXGBE_LINKS_KX_AN_COMP)
  425. break;
  426. msleep(100);
  427. }
  428. if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
  429. status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
  430. hw_dbg(hw, "Autonegotiation did not complete.\n");
  431. }
  432. }
  433. }
  434. /* Add delay to filter out noises during initial link setup */
  435. msleep(50);
  436. return status;
  437. }
  438. /**
  439. * ixgbe_validate_link_ready - Function looks for phy link
  440. * @hw: pointer to hardware structure
  441. *
  442. * Function indicates success when phy link is available. If phy is not ready
  443. * within 5 seconds of MAC indicating link, the function returns error.
  444. **/
  445. static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
  446. {
  447. u32 timeout;
  448. u16 an_reg;
  449. if (hw->device_id != IXGBE_DEV_ID_82598AT2)
  450. return 0;
  451. for (timeout = 0;
  452. timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
  453. hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
  454. if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
  455. (an_reg & MDIO_STAT1_LSTATUS))
  456. break;
  457. msleep(100);
  458. }
  459. if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
  460. hw_dbg(hw, "Link was indicated but link is down\n");
  461. return IXGBE_ERR_LINK_SETUP;
  462. }
  463. return 0;
  464. }
  465. /**
  466. * ixgbe_check_mac_link_82598 - Get link/speed status
  467. * @hw: pointer to hardware structure
  468. * @speed: pointer to link speed
  469. * @link_up: true is link is up, false otherwise
  470. * @link_up_wait_to_complete: bool used to wait for link up or not
  471. *
  472. * Reads the links register to determine if link is up and the current speed
  473. **/
  474. static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
  475. ixgbe_link_speed *speed, bool *link_up,
  476. bool link_up_wait_to_complete)
  477. {
  478. u32 links_reg;
  479. u32 i;
  480. u16 link_reg, adapt_comp_reg;
  481. /*
  482. * SERDES PHY requires us to read link status from register 0xC79F.
  483. * Bit 0 set indicates link is up/ready; clear indicates link down.
  484. * 0xC00C is read to check that the XAUI lanes are active. Bit 0
  485. * clear indicates active; set indicates inactive.
  486. */
  487. if (hw->phy.type == ixgbe_phy_nl) {
  488. hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
  489. hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
  490. hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
  491. &adapt_comp_reg);
  492. if (link_up_wait_to_complete) {
  493. for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
  494. if ((link_reg & 1) &&
  495. ((adapt_comp_reg & 1) == 0)) {
  496. *link_up = true;
  497. break;
  498. } else {
  499. *link_up = false;
  500. }
  501. msleep(100);
  502. hw->phy.ops.read_reg(hw, 0xC79F,
  503. MDIO_MMD_PMAPMD,
  504. &link_reg);
  505. hw->phy.ops.read_reg(hw, 0xC00C,
  506. MDIO_MMD_PMAPMD,
  507. &adapt_comp_reg);
  508. }
  509. } else {
  510. if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
  511. *link_up = true;
  512. else
  513. *link_up = false;
  514. }
  515. if (*link_up == false)
  516. goto out;
  517. }
  518. links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
  519. if (link_up_wait_to_complete) {
  520. for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
  521. if (links_reg & IXGBE_LINKS_UP) {
  522. *link_up = true;
  523. break;
  524. } else {
  525. *link_up = false;
  526. }
  527. msleep(100);
  528. links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
  529. }
  530. } else {
  531. if (links_reg & IXGBE_LINKS_UP)
  532. *link_up = true;
  533. else
  534. *link_up = false;
  535. }
  536. if (links_reg & IXGBE_LINKS_SPEED)
  537. *speed = IXGBE_LINK_SPEED_10GB_FULL;
  538. else
  539. *speed = IXGBE_LINK_SPEED_1GB_FULL;
  540. if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
  541. (ixgbe_validate_link_ready(hw) != 0))
  542. *link_up = false;
  543. /* if link is down, zero out the current_mode */
  544. if (*link_up == false) {
  545. hw->fc.current_mode = ixgbe_fc_none;
  546. hw->fc.fc_was_autonegged = false;
  547. }
  548. out:
  549. return 0;
  550. }
  551. /**
  552. * ixgbe_setup_mac_link_82598 - Set MAC link speed
  553. * @hw: pointer to hardware structure
  554. * @speed: new link speed
  555. * @autoneg: true if auto-negotiation enabled
  556. * @autoneg_wait_to_complete: true if waiting is needed to complete
  557. *
  558. * Set the link speed in the AUTOC register and restarts link.
  559. **/
  560. static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
  561. ixgbe_link_speed speed, bool autoneg,
  562. bool autoneg_wait_to_complete)
  563. {
  564. s32 status = 0;
  565. ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
  566. u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
  567. u32 autoc = curr_autoc;
  568. u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
  569. /* Check to see if speed passed in is supported. */
  570. ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
  571. speed &= link_capabilities;
  572. if (speed == IXGBE_LINK_SPEED_UNKNOWN)
  573. status = IXGBE_ERR_LINK_SETUP;
  574. /* Set KX4/KX support according to speed requested */
  575. else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
  576. link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
  577. autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
  578. if (speed & IXGBE_LINK_SPEED_10GB_FULL)
  579. autoc |= IXGBE_AUTOC_KX4_SUPP;
  580. if (speed & IXGBE_LINK_SPEED_1GB_FULL)
  581. autoc |= IXGBE_AUTOC_KX_SUPP;
  582. if (autoc != curr_autoc)
  583. IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
  584. }
  585. if (status == 0) {
  586. /*
  587. * Setup and restart the link based on the new values in
  588. * ixgbe_hw This will write the AUTOC register based on the new
  589. * stored values
  590. */
  591. status = ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
  592. }
  593. return status;
  594. }
  595. /**
  596. * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
  597. * @hw: pointer to hardware structure
  598. * @speed: new link speed
  599. * @autoneg: true if autonegotiation enabled
  600. * @autoneg_wait_to_complete: true if waiting is needed to complete
  601. *
  602. * Sets the link speed in the AUTOC register in the MAC and restarts link.
  603. **/
  604. static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
  605. ixgbe_link_speed speed,
  606. bool autoneg,
  607. bool autoneg_wait_to_complete)
  608. {
  609. s32 status;
  610. /* Setup the PHY according to input speed */
  611. status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
  612. autoneg_wait_to_complete);
  613. /* Set up MAC */
  614. ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
  615. return status;
  616. }
  617. /**
  618. * ixgbe_reset_hw_82598 - Performs hardware reset
  619. * @hw: pointer to hardware structure
  620. *
  621. * Resets the hardware by resetting the transmit and receive units, masks and
  622. * clears all interrupts, performing a PHY reset, and performing a link (MAC)
  623. * reset.
  624. **/
  625. static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
  626. {
  627. s32 status = 0;
  628. s32 phy_status = 0;
  629. u32 ctrl;
  630. u32 gheccr;
  631. u32 i;
  632. u32 autoc;
  633. u8 analog_val;
  634. /* Call adapter stop to disable tx/rx and clear interrupts */
  635. hw->mac.ops.stop_adapter(hw);
  636. /*
  637. * Power up the Atlas Tx lanes if they are currently powered down.
  638. * Atlas Tx lanes are powered down for MAC loopback tests, but
  639. * they are not automatically restored on reset.
  640. */
  641. hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
  642. if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
  643. /* Enable Tx Atlas so packets can be transmitted again */
  644. hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
  645. &analog_val);
  646. analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
  647. hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
  648. analog_val);
  649. hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
  650. &analog_val);
  651. analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
  652. hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
  653. analog_val);
  654. hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
  655. &analog_val);
  656. analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
  657. hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
  658. analog_val);
  659. hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
  660. &analog_val);
  661. analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
  662. hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
  663. analog_val);
  664. }
  665. /* Reset PHY */
  666. if (hw->phy.reset_disable == false) {
  667. /* PHY ops must be identified and initialized prior to reset */
  668. /* Init PHY and function pointers, perform SFP setup */
  669. phy_status = hw->phy.ops.init(hw);
  670. if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
  671. goto reset_hw_out;
  672. else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
  673. goto no_phy_reset;
  674. hw->phy.ops.reset(hw);
  675. }
  676. no_phy_reset:
  677. /*
  678. * Prevent the PCI-E bus from from hanging by disabling PCI-E master
  679. * access and verify no pending requests before reset
  680. */
  681. status = ixgbe_disable_pcie_master(hw);
  682. if (status != 0) {
  683. status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
  684. hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
  685. }
  686. /*
  687. * Issue global reset to the MAC. This needs to be a SW reset.
  688. * If link reset is used, it might reset the MAC when mng is using it
  689. */
  690. ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
  691. IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
  692. IXGBE_WRITE_FLUSH(hw);
  693. /* Poll for reset bit to self-clear indicating reset is complete */
  694. for (i = 0; i < 10; i++) {
  695. udelay(1);
  696. ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
  697. if (!(ctrl & IXGBE_CTRL_RST))
  698. break;
  699. }
  700. if (ctrl & IXGBE_CTRL_RST) {
  701. status = IXGBE_ERR_RESET_FAILED;
  702. hw_dbg(hw, "Reset polling failed to complete.\n");
  703. }
  704. msleep(50);
  705. gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
  706. gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
  707. IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
  708. /*
  709. * Store the original AUTOC value if it has not been
  710. * stored off yet. Otherwise restore the stored original
  711. * AUTOC value since the reset operation sets back to deaults.
  712. */
  713. autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
  714. if (hw->mac.orig_link_settings_stored == false) {
  715. hw->mac.orig_autoc = autoc;
  716. hw->mac.orig_link_settings_stored = true;
  717. } else if (autoc != hw->mac.orig_autoc) {
  718. IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
  719. }
  720. /*
  721. * Store MAC address from RAR0, clear receive address registers, and
  722. * clear the multicast table
  723. */
  724. hw->mac.ops.init_rx_addrs(hw);
  725. /* Store the permanent mac address */
  726. hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
  727. reset_hw_out:
  728. if (phy_status)
  729. status = phy_status;
  730. return status;
  731. }
  732. /**
  733. * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
  734. * @hw: pointer to hardware struct
  735. * @rar: receive address register index to associate with a VMDq index
  736. * @vmdq: VMDq set index
  737. **/
  738. static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
  739. {
  740. u32 rar_high;
  741. rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
  742. rar_high &= ~IXGBE_RAH_VIND_MASK;
  743. rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
  744. IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
  745. return 0;
  746. }
  747. /**
  748. * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
  749. * @hw: pointer to hardware struct
  750. * @rar: receive address register index to associate with a VMDq index
  751. * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
  752. **/
  753. static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
  754. {
  755. u32 rar_high;
  756. u32 rar_entries = hw->mac.num_rar_entries;
  757. if (rar < rar_entries) {
  758. rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
  759. if (rar_high & IXGBE_RAH_VIND_MASK) {
  760. rar_high &= ~IXGBE_RAH_VIND_MASK;
  761. IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
  762. }
  763. } else {
  764. hw_dbg(hw, "RAR index %d is out of range.\n", rar);
  765. }
  766. return 0;
  767. }
  768. /**
  769. * ixgbe_set_vfta_82598 - Set VLAN filter table
  770. * @hw: pointer to hardware structure
  771. * @vlan: VLAN id to write to VLAN filter
  772. * @vind: VMDq output index that maps queue to VLAN id in VFTA
  773. * @vlan_on: boolean flag to turn on/off VLAN in VFTA
  774. *
  775. * Turn on/off specified VLAN in the VLAN filter table.
  776. **/
  777. static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
  778. bool vlan_on)
  779. {
  780. u32 regindex;
  781. u32 bitindex;
  782. u32 bits;
  783. u32 vftabyte;
  784. if (vlan > 4095)
  785. return IXGBE_ERR_PARAM;
  786. /* Determine 32-bit word position in array */
  787. regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
  788. /* Determine the location of the (VMD) queue index */
  789. vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
  790. bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
  791. /* Set the nibble for VMD queue index */
  792. bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
  793. bits &= (~(0x0F << bitindex));
  794. bits |= (vind << bitindex);
  795. IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
  796. /* Determine the location of the bit for this VLAN id */
  797. bitindex = vlan & 0x1F; /* lower five bits */
  798. bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
  799. if (vlan_on)
  800. /* Turn on this VLAN id */
  801. bits |= (1 << bitindex);
  802. else
  803. /* Turn off this VLAN id */
  804. bits &= ~(1 << bitindex);
  805. IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
  806. return 0;
  807. }
  808. /**
  809. * ixgbe_clear_vfta_82598 - Clear VLAN filter table
  810. * @hw: pointer to hardware structure
  811. *
  812. * Clears the VLAN filer table, and the VMDq index associated with the filter
  813. **/
  814. static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
  815. {
  816. u32 offset;
  817. u32 vlanbyte;
  818. for (offset = 0; offset < hw->mac.vft_size; offset++)
  819. IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
  820. for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
  821. for (offset = 0; offset < hw->mac.vft_size; offset++)
  822. IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
  823. 0);
  824. return 0;
  825. }
  826. /**
  827. * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
  828. * @hw: pointer to hardware structure
  829. * @reg: analog register to read
  830. * @val: read value
  831. *
  832. * Performs read operation to Atlas analog register specified.
  833. **/
  834. static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
  835. {
  836. u32 atlas_ctl;
  837. IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
  838. IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
  839. IXGBE_WRITE_FLUSH(hw);
  840. udelay(10);
  841. atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
  842. *val = (u8)atlas_ctl;
  843. return 0;
  844. }
  845. /**
  846. * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
  847. * @hw: pointer to hardware structure
  848. * @reg: atlas register to write
  849. * @val: value to write
  850. *
  851. * Performs write operation to Atlas analog register specified.
  852. **/
  853. static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
  854. {
  855. u32 atlas_ctl;
  856. atlas_ctl = (reg << 8) | val;
  857. IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
  858. IXGBE_WRITE_FLUSH(hw);
  859. udelay(10);
  860. return 0;
  861. }
  862. /**
  863. * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
  864. * over I2C interface through an intermediate phy.
  865. * @hw: pointer to hardware structure
  866. * @byte_offset: EEPROM byte offset to read
  867. * @eeprom_data: value read
  868. *
  869. * Performs byte read operation to SFP module's EEPROM over I2C interface.
  870. **/
  871. static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  872. u8 *eeprom_data)
  873. {
  874. s32 status = 0;
  875. u16 sfp_addr = 0;
  876. u16 sfp_data = 0;
  877. u16 sfp_stat = 0;
  878. u32 i;
  879. if (hw->phy.type == ixgbe_phy_nl) {
  880. /*
  881. * phy SDA/SCL registers are at addresses 0xC30A to
  882. * 0xC30D. These registers are used to talk to the SFP+
  883. * module's EEPROM through the SDA/SCL (I2C) interface.
  884. */
  885. sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
  886. sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
  887. hw->phy.ops.write_reg(hw,
  888. IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
  889. MDIO_MMD_PMAPMD,
  890. sfp_addr);
  891. /* Poll status */
  892. for (i = 0; i < 100; i++) {
  893. hw->phy.ops.read_reg(hw,
  894. IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
  895. MDIO_MMD_PMAPMD,
  896. &sfp_stat);
  897. sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
  898. if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
  899. break;
  900. msleep(10);
  901. }
  902. if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
  903. hw_dbg(hw, "EEPROM read did not pass.\n");
  904. status = IXGBE_ERR_SFP_NOT_PRESENT;
  905. goto out;
  906. }
  907. /* Read data */
  908. hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
  909. MDIO_MMD_PMAPMD, &sfp_data);
  910. *eeprom_data = (u8)(sfp_data >> 8);
  911. } else {
  912. status = IXGBE_ERR_PHY;
  913. goto out;
  914. }
  915. out:
  916. return status;
  917. }
  918. /**
  919. * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
  920. * @hw: pointer to hardware structure
  921. *
  922. * Determines physical layer capabilities of the current configuration.
  923. **/
  924. static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
  925. {
  926. u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
  927. u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
  928. u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
  929. u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
  930. u16 ext_ability = 0;
  931. hw->phy.ops.identify(hw);
  932. /* Copper PHY must be checked before AUTOC LMS to determine correct
  933. * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
  934. if (hw->phy.type == ixgbe_phy_tn ||
  935. hw->phy.type == ixgbe_phy_cu_unknown) {
  936. hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
  937. &ext_ability);
  938. if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
  939. physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
  940. if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
  941. physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
  942. if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
  943. physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
  944. goto out;
  945. }
  946. switch (autoc & IXGBE_AUTOC_LMS_MASK) {
  947. case IXGBE_AUTOC_LMS_1G_AN:
  948. case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
  949. if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
  950. physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
  951. else
  952. physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
  953. break;
  954. case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
  955. if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
  956. physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
  957. else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
  958. physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
  959. else /* XAUI */
  960. physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
  961. break;
  962. case IXGBE_AUTOC_LMS_KX4_AN:
  963. case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
  964. if (autoc & IXGBE_AUTOC_KX_SUPP)
  965. physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
  966. if (autoc & IXGBE_AUTOC_KX4_SUPP)
  967. physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
  968. break;
  969. default:
  970. break;
  971. }
  972. if (hw->phy.type == ixgbe_phy_nl) {
  973. hw->phy.ops.identify_sfp(hw);
  974. switch (hw->phy.sfp_type) {
  975. case ixgbe_sfp_type_da_cu:
  976. physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
  977. break;
  978. case ixgbe_sfp_type_sr:
  979. physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
  980. break;
  981. case ixgbe_sfp_type_lr:
  982. physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
  983. break;
  984. default:
  985. physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
  986. break;
  987. }
  988. }
  989. switch (hw->device_id) {
  990. case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
  991. physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
  992. break;
  993. case IXGBE_DEV_ID_82598AF_DUAL_PORT:
  994. case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
  995. case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
  996. physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
  997. break;
  998. case IXGBE_DEV_ID_82598EB_XF_LR:
  999. physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
  1000. break;
  1001. default:
  1002. break;
  1003. }
  1004. out:
  1005. return physical_layer;
  1006. }
  1007. static struct ixgbe_mac_operations mac_ops_82598 = {
  1008. .init_hw = &ixgbe_init_hw_generic,
  1009. .reset_hw = &ixgbe_reset_hw_82598,
  1010. .start_hw = &ixgbe_start_hw_82598,
  1011. .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
  1012. .get_media_type = &ixgbe_get_media_type_82598,
  1013. .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
  1014. .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
  1015. .get_mac_addr = &ixgbe_get_mac_addr_generic,
  1016. .stop_adapter = &ixgbe_stop_adapter_generic,
  1017. .get_bus_info = &ixgbe_get_bus_info_generic,
  1018. .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
  1019. .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
  1020. .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
  1021. .setup_link = &ixgbe_setup_mac_link_82598,
  1022. .check_link = &ixgbe_check_mac_link_82598,
  1023. .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
  1024. .led_on = &ixgbe_led_on_generic,
  1025. .led_off = &ixgbe_led_off_generic,
  1026. .blink_led_start = &ixgbe_blink_led_start_generic,
  1027. .blink_led_stop = &ixgbe_blink_led_stop_generic,
  1028. .set_rar = &ixgbe_set_rar_generic,
  1029. .clear_rar = &ixgbe_clear_rar_generic,
  1030. .set_vmdq = &ixgbe_set_vmdq_82598,
  1031. .clear_vmdq = &ixgbe_clear_vmdq_82598,
  1032. .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
  1033. .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
  1034. .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
  1035. .enable_mc = &ixgbe_enable_mc_generic,
  1036. .disable_mc = &ixgbe_disable_mc_generic,
  1037. .clear_vfta = &ixgbe_clear_vfta_82598,
  1038. .set_vfta = &ixgbe_set_vfta_82598,
  1039. .fc_enable = &ixgbe_fc_enable_82598,
  1040. };
  1041. static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
  1042. .init_params = &ixgbe_init_eeprom_params_generic,
  1043. .read = &ixgbe_read_eerd_generic,
  1044. .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
  1045. .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
  1046. .update_checksum = &ixgbe_update_eeprom_checksum_generic,
  1047. };
  1048. static struct ixgbe_phy_operations phy_ops_82598 = {
  1049. .identify = &ixgbe_identify_phy_generic,
  1050. .identify_sfp = &ixgbe_identify_sfp_module_generic,
  1051. .init = &ixgbe_init_phy_ops_82598,
  1052. .reset = &ixgbe_reset_phy_generic,
  1053. .read_reg = &ixgbe_read_phy_reg_generic,
  1054. .write_reg = &ixgbe_write_phy_reg_generic,
  1055. .setup_link = &ixgbe_setup_phy_link_generic,
  1056. .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
  1057. .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
  1058. .check_overtemp = &ixgbe_tn_check_overtemp,
  1059. };
  1060. struct ixgbe_info ixgbe_82598_info = {
  1061. .mac = ixgbe_mac_82598EB,
  1062. .get_invariants = &ixgbe_get_invariants_82598,
  1063. .mac_ops = &mac_ops_82598,
  1064. .eeprom_ops = &eeprom_ops_82598,
  1065. .phy_ops = &phy_ops_82598,
  1066. };