core.c 20 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/core.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * Some code and ideas taken from drivers/video/omap/ driver
  8. * by Imre Deak.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published by
  12. * the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #define DSS_SUBSYS_NAME "CORE"
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/clk.h>
  26. #include <linux/err.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/io.h>
  31. #include <linux/device.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <plat/display.h>
  34. #include <plat/clock.h>
  35. #include "dss.h"
  36. static struct {
  37. struct platform_device *pdev;
  38. int ctx_id;
  39. struct clk *dss_ick;
  40. struct clk *dss1_fck;
  41. struct clk *dss2_fck;
  42. struct clk *dss_54m_fck;
  43. struct clk *dss_96m_fck;
  44. unsigned num_clks_enabled;
  45. struct regulator *vdds_dsi_reg;
  46. struct regulator *vdds_sdi_reg;
  47. struct regulator *vdda_dac_reg;
  48. } core;
  49. static void dss_clk_enable_all_no_ctx(void);
  50. static void dss_clk_disable_all_no_ctx(void);
  51. static void dss_clk_enable_no_ctx(enum dss_clock clks);
  52. static void dss_clk_disable_no_ctx(enum dss_clock clks);
  53. static char *def_disp_name;
  54. module_param_named(def_disp, def_disp_name, charp, 0);
  55. MODULE_PARM_DESC(def_disp_name, "default display name");
  56. #ifdef DEBUG
  57. unsigned int dss_debug;
  58. module_param_named(debug, dss_debug, bool, 0644);
  59. #endif
  60. /* CONTEXT */
  61. static int dss_get_ctx_id(void)
  62. {
  63. struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
  64. int r;
  65. if (!pdata->get_last_off_on_transaction_id)
  66. return 0;
  67. r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
  68. if (r < 0) {
  69. dev_err(&core.pdev->dev, "getting transaction ID failed, "
  70. "will force context restore\n");
  71. r = -1;
  72. }
  73. return r;
  74. }
  75. int dss_need_ctx_restore(void)
  76. {
  77. int id = dss_get_ctx_id();
  78. if (id < 0 || id != core.ctx_id) {
  79. DSSDBG("ctx id %d -> id %d\n",
  80. core.ctx_id, id);
  81. core.ctx_id = id;
  82. return 1;
  83. } else {
  84. return 0;
  85. }
  86. }
  87. static void save_all_ctx(void)
  88. {
  89. DSSDBG("save context\n");
  90. dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
  91. dss_save_context();
  92. dispc_save_context();
  93. #ifdef CONFIG_OMAP2_DSS_DSI
  94. dsi_save_context();
  95. #endif
  96. dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
  97. }
  98. static void restore_all_ctx(void)
  99. {
  100. DSSDBG("restore context\n");
  101. dss_clk_enable_all_no_ctx();
  102. dss_restore_context();
  103. dispc_restore_context();
  104. #ifdef CONFIG_OMAP2_DSS_DSI
  105. dsi_restore_context();
  106. #endif
  107. dss_clk_disable_all_no_ctx();
  108. }
  109. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  110. /* CLOCKS */
  111. static void core_dump_clocks(struct seq_file *s)
  112. {
  113. int i;
  114. struct clk *clocks[5] = {
  115. core.dss_ick,
  116. core.dss1_fck,
  117. core.dss2_fck,
  118. core.dss_54m_fck,
  119. core.dss_96m_fck
  120. };
  121. seq_printf(s, "- CORE -\n");
  122. seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
  123. for (i = 0; i < 5; i++) {
  124. if (!clocks[i])
  125. continue;
  126. seq_printf(s, "%-15s\t%lu\t%d\n",
  127. clocks[i]->name,
  128. clk_get_rate(clocks[i]),
  129. clocks[i]->usecount);
  130. }
  131. }
  132. #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
  133. static int dss_get_clock(struct clk **clock, const char *clk_name)
  134. {
  135. struct clk *clk;
  136. clk = clk_get(&core.pdev->dev, clk_name);
  137. if (IS_ERR(clk)) {
  138. DSSERR("can't get clock %s", clk_name);
  139. return PTR_ERR(clk);
  140. }
  141. *clock = clk;
  142. DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
  143. return 0;
  144. }
  145. static int dss_get_clocks(void)
  146. {
  147. int r;
  148. core.dss_ick = NULL;
  149. core.dss1_fck = NULL;
  150. core.dss2_fck = NULL;
  151. core.dss_54m_fck = NULL;
  152. core.dss_96m_fck = NULL;
  153. r = dss_get_clock(&core.dss_ick, "ick");
  154. if (r)
  155. goto err;
  156. r = dss_get_clock(&core.dss1_fck, "dss1_fck");
  157. if (r)
  158. goto err;
  159. r = dss_get_clock(&core.dss2_fck, "dss2_fck");
  160. if (r)
  161. goto err;
  162. r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
  163. if (r)
  164. goto err;
  165. r = dss_get_clock(&core.dss_96m_fck, "video_fck");
  166. if (r)
  167. goto err;
  168. return 0;
  169. err:
  170. if (core.dss_ick)
  171. clk_put(core.dss_ick);
  172. if (core.dss1_fck)
  173. clk_put(core.dss1_fck);
  174. if (core.dss2_fck)
  175. clk_put(core.dss2_fck);
  176. if (core.dss_54m_fck)
  177. clk_put(core.dss_54m_fck);
  178. if (core.dss_96m_fck)
  179. clk_put(core.dss_96m_fck);
  180. return r;
  181. }
  182. static void dss_put_clocks(void)
  183. {
  184. if (core.dss_96m_fck)
  185. clk_put(core.dss_96m_fck);
  186. clk_put(core.dss_54m_fck);
  187. clk_put(core.dss1_fck);
  188. clk_put(core.dss2_fck);
  189. clk_put(core.dss_ick);
  190. }
  191. unsigned long dss_clk_get_rate(enum dss_clock clk)
  192. {
  193. switch (clk) {
  194. case DSS_CLK_ICK:
  195. return clk_get_rate(core.dss_ick);
  196. case DSS_CLK_FCK1:
  197. return clk_get_rate(core.dss1_fck);
  198. case DSS_CLK_FCK2:
  199. return clk_get_rate(core.dss2_fck);
  200. case DSS_CLK_54M:
  201. return clk_get_rate(core.dss_54m_fck);
  202. case DSS_CLK_96M:
  203. return clk_get_rate(core.dss_96m_fck);
  204. }
  205. BUG();
  206. return 0;
  207. }
  208. static unsigned count_clk_bits(enum dss_clock clks)
  209. {
  210. unsigned num_clks = 0;
  211. if (clks & DSS_CLK_ICK)
  212. ++num_clks;
  213. if (clks & DSS_CLK_FCK1)
  214. ++num_clks;
  215. if (clks & DSS_CLK_FCK2)
  216. ++num_clks;
  217. if (clks & DSS_CLK_54M)
  218. ++num_clks;
  219. if (clks & DSS_CLK_96M)
  220. ++num_clks;
  221. return num_clks;
  222. }
  223. static void dss_clk_enable_no_ctx(enum dss_clock clks)
  224. {
  225. unsigned num_clks = count_clk_bits(clks);
  226. if (clks & DSS_CLK_ICK)
  227. clk_enable(core.dss_ick);
  228. if (clks & DSS_CLK_FCK1)
  229. clk_enable(core.dss1_fck);
  230. if (clks & DSS_CLK_FCK2)
  231. clk_enable(core.dss2_fck);
  232. if (clks & DSS_CLK_54M)
  233. clk_enable(core.dss_54m_fck);
  234. if (clks & DSS_CLK_96M)
  235. clk_enable(core.dss_96m_fck);
  236. core.num_clks_enabled += num_clks;
  237. }
  238. void dss_clk_enable(enum dss_clock clks)
  239. {
  240. dss_clk_enable_no_ctx(clks);
  241. if (cpu_is_omap34xx() && dss_need_ctx_restore())
  242. restore_all_ctx();
  243. }
  244. static void dss_clk_disable_no_ctx(enum dss_clock clks)
  245. {
  246. unsigned num_clks = count_clk_bits(clks);
  247. if (clks & DSS_CLK_ICK)
  248. clk_disable(core.dss_ick);
  249. if (clks & DSS_CLK_FCK1)
  250. clk_disable(core.dss1_fck);
  251. if (clks & DSS_CLK_FCK2)
  252. clk_disable(core.dss2_fck);
  253. if (clks & DSS_CLK_54M)
  254. clk_disable(core.dss_54m_fck);
  255. if (clks & DSS_CLK_96M)
  256. clk_disable(core.dss_96m_fck);
  257. core.num_clks_enabled -= num_clks;
  258. }
  259. void dss_clk_disable(enum dss_clock clks)
  260. {
  261. if (cpu_is_omap34xx()) {
  262. unsigned num_clks = count_clk_bits(clks);
  263. BUG_ON(core.num_clks_enabled < num_clks);
  264. if (core.num_clks_enabled == num_clks)
  265. save_all_ctx();
  266. }
  267. dss_clk_disable_no_ctx(clks);
  268. }
  269. static void dss_clk_enable_all_no_ctx(void)
  270. {
  271. enum dss_clock clks;
  272. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  273. if (cpu_is_omap34xx())
  274. clks |= DSS_CLK_96M;
  275. dss_clk_enable_no_ctx(clks);
  276. }
  277. static void dss_clk_disable_all_no_ctx(void)
  278. {
  279. enum dss_clock clks;
  280. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  281. if (cpu_is_omap34xx())
  282. clks |= DSS_CLK_96M;
  283. dss_clk_disable_no_ctx(clks);
  284. }
  285. static void dss_clk_disable_all(void)
  286. {
  287. enum dss_clock clks;
  288. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  289. if (cpu_is_omap34xx())
  290. clks |= DSS_CLK_96M;
  291. dss_clk_disable(clks);
  292. }
  293. /* REGULATORS */
  294. struct regulator *dss_get_vdds_dsi(void)
  295. {
  296. struct regulator *reg;
  297. if (core.vdds_dsi_reg != NULL)
  298. return core.vdds_dsi_reg;
  299. reg = regulator_get(&core.pdev->dev, "vdds_dsi");
  300. if (!IS_ERR(reg))
  301. core.vdds_dsi_reg = reg;
  302. return reg;
  303. }
  304. struct regulator *dss_get_vdds_sdi(void)
  305. {
  306. struct regulator *reg;
  307. if (core.vdds_sdi_reg != NULL)
  308. return core.vdds_sdi_reg;
  309. reg = regulator_get(&core.pdev->dev, "vdds_sdi");
  310. if (!IS_ERR(reg))
  311. core.vdds_sdi_reg = reg;
  312. return reg;
  313. }
  314. struct regulator *dss_get_vdda_dac(void)
  315. {
  316. struct regulator *reg;
  317. if (core.vdda_dac_reg != NULL)
  318. return core.vdda_dac_reg;
  319. reg = regulator_get(&core.pdev->dev, "vdda_dac");
  320. if (!IS_ERR(reg))
  321. core.vdda_dac_reg = reg;
  322. return reg;
  323. }
  324. /* DEBUGFS */
  325. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  326. static void dss_debug_dump_clocks(struct seq_file *s)
  327. {
  328. core_dump_clocks(s);
  329. dss_dump_clocks(s);
  330. dispc_dump_clocks(s);
  331. #ifdef CONFIG_OMAP2_DSS_DSI
  332. dsi_dump_clocks(s);
  333. #endif
  334. }
  335. static int dss_debug_show(struct seq_file *s, void *unused)
  336. {
  337. void (*func)(struct seq_file *) = s->private;
  338. func(s);
  339. return 0;
  340. }
  341. static int dss_debug_open(struct inode *inode, struct file *file)
  342. {
  343. return single_open(file, dss_debug_show, inode->i_private);
  344. }
  345. static const struct file_operations dss_debug_fops = {
  346. .open = dss_debug_open,
  347. .read = seq_read,
  348. .llseek = seq_lseek,
  349. .release = single_release,
  350. };
  351. static struct dentry *dss_debugfs_dir;
  352. static int dss_initialize_debugfs(void)
  353. {
  354. dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
  355. if (IS_ERR(dss_debugfs_dir)) {
  356. int err = PTR_ERR(dss_debugfs_dir);
  357. dss_debugfs_dir = NULL;
  358. return err;
  359. }
  360. debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
  361. &dss_debug_dump_clocks, &dss_debug_fops);
  362. #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
  363. debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir,
  364. &dispc_dump_irqs, &dss_debug_fops);
  365. #endif
  366. #if defined(CONFIG_OMAP2_DSS_DSI) && defined(CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS)
  367. debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir,
  368. &dsi_dump_irqs, &dss_debug_fops);
  369. #endif
  370. debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
  371. &dss_dump_regs, &dss_debug_fops);
  372. debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
  373. &dispc_dump_regs, &dss_debug_fops);
  374. #ifdef CONFIG_OMAP2_DSS_RFBI
  375. debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
  376. &rfbi_dump_regs, &dss_debug_fops);
  377. #endif
  378. #ifdef CONFIG_OMAP2_DSS_DSI
  379. debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
  380. &dsi_dump_regs, &dss_debug_fops);
  381. #endif
  382. #ifdef CONFIG_OMAP2_DSS_VENC
  383. debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
  384. &venc_dump_regs, &dss_debug_fops);
  385. #endif
  386. return 0;
  387. }
  388. static void dss_uninitialize_debugfs(void)
  389. {
  390. if (dss_debugfs_dir)
  391. debugfs_remove_recursive(dss_debugfs_dir);
  392. }
  393. #endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
  394. /* PLATFORM DEVICE */
  395. static int omap_dss_probe(struct platform_device *pdev)
  396. {
  397. struct omap_dss_board_info *pdata = pdev->dev.platform_data;
  398. int skip_init = 0;
  399. int r;
  400. int i;
  401. core.pdev = pdev;
  402. dss_init_overlay_managers(pdev);
  403. dss_init_overlays(pdev);
  404. r = dss_get_clocks();
  405. if (r)
  406. goto fail0;
  407. dss_clk_enable_all_no_ctx();
  408. core.ctx_id = dss_get_ctx_id();
  409. DSSDBG("initial ctx id %u\n", core.ctx_id);
  410. #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
  411. /* DISPC_CONTROL */
  412. if (omap_readl(0x48050440) & 1) /* LCD enabled? */
  413. skip_init = 1;
  414. #endif
  415. r = dss_init(skip_init);
  416. if (r) {
  417. DSSERR("Failed to initialize DSS\n");
  418. goto fail0;
  419. }
  420. #ifdef CONFIG_OMAP2_DSS_RFBI
  421. r = rfbi_init();
  422. if (r) {
  423. DSSERR("Failed to initialize rfbi\n");
  424. goto fail0;
  425. }
  426. #endif
  427. r = dpi_init(pdev);
  428. if (r) {
  429. DSSERR("Failed to initialize dpi\n");
  430. goto fail0;
  431. }
  432. r = dispc_init();
  433. if (r) {
  434. DSSERR("Failed to initialize dispc\n");
  435. goto fail0;
  436. }
  437. #ifdef CONFIG_OMAP2_DSS_VENC
  438. r = venc_init(pdev);
  439. if (r) {
  440. DSSERR("Failed to initialize venc\n");
  441. goto fail0;
  442. }
  443. #endif
  444. if (cpu_is_omap34xx()) {
  445. #ifdef CONFIG_OMAP2_DSS_SDI
  446. r = sdi_init(skip_init);
  447. if (r) {
  448. DSSERR("Failed to initialize SDI\n");
  449. goto fail0;
  450. }
  451. #endif
  452. #ifdef CONFIG_OMAP2_DSS_DSI
  453. r = dsi_init(pdev);
  454. if (r) {
  455. DSSERR("Failed to initialize DSI\n");
  456. goto fail0;
  457. }
  458. #endif
  459. }
  460. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  461. r = dss_initialize_debugfs();
  462. if (r)
  463. goto fail0;
  464. #endif
  465. for (i = 0; i < pdata->num_devices; ++i) {
  466. struct omap_dss_device *dssdev = pdata->devices[i];
  467. r = omap_dss_register_device(dssdev);
  468. if (r)
  469. DSSERR("device reg failed %d\n", i);
  470. if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0)
  471. pdata->default_device = dssdev;
  472. }
  473. dss_clk_disable_all();
  474. return 0;
  475. /* XXX fail correctly */
  476. fail0:
  477. return r;
  478. }
  479. static int omap_dss_remove(struct platform_device *pdev)
  480. {
  481. struct omap_dss_board_info *pdata = pdev->dev.platform_data;
  482. int i;
  483. int c;
  484. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  485. dss_uninitialize_debugfs();
  486. #endif
  487. #ifdef CONFIG_OMAP2_DSS_VENC
  488. venc_exit();
  489. #endif
  490. dispc_exit();
  491. dpi_exit();
  492. #ifdef CONFIG_OMAP2_DSS_RFBI
  493. rfbi_exit();
  494. #endif
  495. if (cpu_is_omap34xx()) {
  496. #ifdef CONFIG_OMAP2_DSS_DSI
  497. dsi_exit();
  498. #endif
  499. #ifdef CONFIG_OMAP2_DSS_SDI
  500. sdi_exit();
  501. #endif
  502. }
  503. dss_exit();
  504. /* these should be removed at some point */
  505. c = core.dss_ick->usecount;
  506. if (c > 0) {
  507. DSSERR("warning: dss_ick usecount %d, disabling\n", c);
  508. while (c-- > 0)
  509. clk_disable(core.dss_ick);
  510. }
  511. c = core.dss1_fck->usecount;
  512. if (c > 0) {
  513. DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
  514. while (c-- > 0)
  515. clk_disable(core.dss1_fck);
  516. }
  517. c = core.dss2_fck->usecount;
  518. if (c > 0) {
  519. DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
  520. while (c-- > 0)
  521. clk_disable(core.dss2_fck);
  522. }
  523. c = core.dss_54m_fck->usecount;
  524. if (c > 0) {
  525. DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
  526. while (c-- > 0)
  527. clk_disable(core.dss_54m_fck);
  528. }
  529. if (core.dss_96m_fck) {
  530. c = core.dss_96m_fck->usecount;
  531. if (c > 0) {
  532. DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
  533. c);
  534. while (c-- > 0)
  535. clk_disable(core.dss_96m_fck);
  536. }
  537. }
  538. dss_put_clocks();
  539. dss_uninit_overlays(pdev);
  540. dss_uninit_overlay_managers(pdev);
  541. for (i = 0; i < pdata->num_devices; ++i)
  542. omap_dss_unregister_device(pdata->devices[i]);
  543. return 0;
  544. }
  545. static void omap_dss_shutdown(struct platform_device *pdev)
  546. {
  547. DSSDBG("shutdown\n");
  548. dss_disable_all_devices();
  549. }
  550. static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
  551. {
  552. DSSDBG("suspend %d\n", state.event);
  553. return dss_suspend_all_devices();
  554. }
  555. static int omap_dss_resume(struct platform_device *pdev)
  556. {
  557. DSSDBG("resume\n");
  558. return dss_resume_all_devices();
  559. }
  560. static struct platform_driver omap_dss_driver = {
  561. .probe = omap_dss_probe,
  562. .remove = omap_dss_remove,
  563. .shutdown = omap_dss_shutdown,
  564. .suspend = omap_dss_suspend,
  565. .resume = omap_dss_resume,
  566. .driver = {
  567. .name = "omapdss",
  568. .owner = THIS_MODULE,
  569. },
  570. };
  571. /* BUS */
  572. static int dss_bus_match(struct device *dev, struct device_driver *driver)
  573. {
  574. struct omap_dss_device *dssdev = to_dss_device(dev);
  575. DSSDBG("bus_match. dev %s/%s, drv %s\n",
  576. dev_name(dev), dssdev->driver_name, driver->name);
  577. return strcmp(dssdev->driver_name, driver->name) == 0;
  578. }
  579. static ssize_t device_name_show(struct device *dev,
  580. struct device_attribute *attr, char *buf)
  581. {
  582. struct omap_dss_device *dssdev = to_dss_device(dev);
  583. return snprintf(buf, PAGE_SIZE, "%s\n",
  584. dssdev->name ?
  585. dssdev->name : "");
  586. }
  587. static struct device_attribute default_dev_attrs[] = {
  588. __ATTR(name, S_IRUGO, device_name_show, NULL),
  589. __ATTR_NULL,
  590. };
  591. static ssize_t driver_name_show(struct device_driver *drv, char *buf)
  592. {
  593. struct omap_dss_driver *dssdrv = to_dss_driver(drv);
  594. return snprintf(buf, PAGE_SIZE, "%s\n",
  595. dssdrv->driver.name ?
  596. dssdrv->driver.name : "");
  597. }
  598. static struct driver_attribute default_drv_attrs[] = {
  599. __ATTR(name, S_IRUGO, driver_name_show, NULL),
  600. __ATTR_NULL,
  601. };
  602. static struct bus_type dss_bus_type = {
  603. .name = "omapdss",
  604. .match = dss_bus_match,
  605. .dev_attrs = default_dev_attrs,
  606. .drv_attrs = default_drv_attrs,
  607. };
  608. static void dss_bus_release(struct device *dev)
  609. {
  610. DSSDBG("bus_release\n");
  611. }
  612. static struct device dss_bus = {
  613. .release = dss_bus_release,
  614. };
  615. struct bus_type *dss_get_bus(void)
  616. {
  617. return &dss_bus_type;
  618. }
  619. /* DRIVER */
  620. static int dss_driver_probe(struct device *dev)
  621. {
  622. int r;
  623. struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
  624. struct omap_dss_device *dssdev = to_dss_device(dev);
  625. struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
  626. bool force;
  627. DSSDBG("driver_probe: dev %s/%s, drv %s\n",
  628. dev_name(dev), dssdev->driver_name,
  629. dssdrv->driver.name);
  630. dss_init_device(core.pdev, dssdev);
  631. /* skip this if the device is behind a ctrl */
  632. if (!dssdev->panel.ctrl) {
  633. force = pdata->default_device == dssdev;
  634. dss_recheck_connections(dssdev, force);
  635. }
  636. r = dssdrv->probe(dssdev);
  637. if (r) {
  638. DSSERR("driver probe failed: %d\n", r);
  639. return r;
  640. }
  641. DSSDBG("probe done for device %s\n", dev_name(dev));
  642. dssdev->driver = dssdrv;
  643. return 0;
  644. }
  645. static int dss_driver_remove(struct device *dev)
  646. {
  647. struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
  648. struct omap_dss_device *dssdev = to_dss_device(dev);
  649. DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev),
  650. dssdev->driver_name);
  651. dssdrv->remove(dssdev);
  652. dss_uninit_device(core.pdev, dssdev);
  653. dssdev->driver = NULL;
  654. return 0;
  655. }
  656. int omap_dss_register_driver(struct omap_dss_driver *dssdriver)
  657. {
  658. dssdriver->driver.bus = &dss_bus_type;
  659. dssdriver->driver.probe = dss_driver_probe;
  660. dssdriver->driver.remove = dss_driver_remove;
  661. return driver_register(&dssdriver->driver);
  662. }
  663. EXPORT_SYMBOL(omap_dss_register_driver);
  664. void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver)
  665. {
  666. driver_unregister(&dssdriver->driver);
  667. }
  668. EXPORT_SYMBOL(omap_dss_unregister_driver);
  669. /* DEVICE */
  670. static void reset_device(struct device *dev, int check)
  671. {
  672. u8 *dev_p = (u8 *)dev;
  673. u8 *dev_end = dev_p + sizeof(*dev);
  674. void *saved_pdata;
  675. saved_pdata = dev->platform_data;
  676. if (check) {
  677. /*
  678. * Check if there is any other setting than platform_data
  679. * in struct device; warn that these will be reset by our
  680. * init.
  681. */
  682. dev->platform_data = NULL;
  683. while (dev_p < dev_end) {
  684. if (*dev_p) {
  685. WARN("%s: struct device fields will be "
  686. "discarded\n",
  687. __func__);
  688. break;
  689. }
  690. dev_p++;
  691. }
  692. }
  693. memset(dev, 0, sizeof(*dev));
  694. dev->platform_data = saved_pdata;
  695. }
  696. static void omap_dss_dev_release(struct device *dev)
  697. {
  698. reset_device(dev, 0);
  699. }
  700. int omap_dss_register_device(struct omap_dss_device *dssdev)
  701. {
  702. static int dev_num;
  703. static int panel_num;
  704. int r;
  705. WARN_ON(!dssdev->driver_name);
  706. reset_device(&dssdev->dev, 1);
  707. dssdev->dev.bus = &dss_bus_type;
  708. dssdev->dev.parent = &dss_bus;
  709. dssdev->dev.release = omap_dss_dev_release;
  710. dev_set_name(&dssdev->dev, "display%d", dev_num++);
  711. r = device_register(&dssdev->dev);
  712. if (r)
  713. return r;
  714. if (dssdev->ctrl.panel) {
  715. struct omap_dss_device *panel = dssdev->ctrl.panel;
  716. panel->panel.ctrl = dssdev;
  717. reset_device(&panel->dev, 1);
  718. panel->dev.bus = &dss_bus_type;
  719. panel->dev.parent = &dssdev->dev;
  720. panel->dev.release = omap_dss_dev_release;
  721. dev_set_name(&panel->dev, "panel%d", panel_num++);
  722. r = device_register(&panel->dev);
  723. if (r)
  724. return r;
  725. }
  726. return 0;
  727. }
  728. void omap_dss_unregister_device(struct omap_dss_device *dssdev)
  729. {
  730. device_unregister(&dssdev->dev);
  731. if (dssdev->ctrl.panel) {
  732. struct omap_dss_device *panel = dssdev->ctrl.panel;
  733. device_unregister(&panel->dev);
  734. }
  735. }
  736. /* BUS */
  737. static int omap_dss_bus_register(void)
  738. {
  739. int r;
  740. r = bus_register(&dss_bus_type);
  741. if (r) {
  742. DSSERR("bus register failed\n");
  743. return r;
  744. }
  745. dev_set_name(&dss_bus, "omapdss");
  746. r = device_register(&dss_bus);
  747. if (r) {
  748. DSSERR("bus driver register failed\n");
  749. bus_unregister(&dss_bus_type);
  750. return r;
  751. }
  752. return 0;
  753. }
  754. /* INIT */
  755. #ifdef CONFIG_OMAP2_DSS_MODULE
  756. static void omap_dss_bus_unregister(void)
  757. {
  758. device_unregister(&dss_bus);
  759. bus_unregister(&dss_bus_type);
  760. }
  761. static int __init omap_dss_init(void)
  762. {
  763. int r;
  764. r = omap_dss_bus_register();
  765. if (r)
  766. return r;
  767. r = platform_driver_register(&omap_dss_driver);
  768. if (r) {
  769. omap_dss_bus_unregister();
  770. return r;
  771. }
  772. return 0;
  773. }
  774. static void __exit omap_dss_exit(void)
  775. {
  776. if (core.vdds_dsi_reg != NULL) {
  777. regulator_put(core.vdds_dsi_reg);
  778. core.vdds_dsi_reg = NULL;
  779. }
  780. if (core.vdds_sdi_reg != NULL) {
  781. regulator_put(core.vdds_sdi_reg);
  782. core.vdds_sdi_reg = NULL;
  783. }
  784. if (core.vdda_dac_reg != NULL) {
  785. regulator_put(core.vdda_dac_reg);
  786. core.vdda_dac_reg = NULL;
  787. }
  788. platform_driver_unregister(&omap_dss_driver);
  789. omap_dss_bus_unregister();
  790. }
  791. module_init(omap_dss_init);
  792. module_exit(omap_dss_exit);
  793. #else
  794. static int __init omap_dss_init(void)
  795. {
  796. return omap_dss_bus_register();
  797. }
  798. static int __init omap_dss_init2(void)
  799. {
  800. return platform_driver_register(&omap_dss_driver);
  801. }
  802. core_initcall(omap_dss_init);
  803. device_initcall(omap_dss_init2);
  804. #endif
  805. MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
  806. MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
  807. MODULE_LICENSE("GPL v2");