ar9003_phy.c 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147
  1. /*
  2. * Copyright (c) 2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. /**
  18. * ar9003_hw_set_channel - set channel on single-chip device
  19. * @ah: atheros hardware structure
  20. * @chan:
  21. *
  22. * This is the function to change channel on single-chip devices, that is
  23. * all devices after ar9280.
  24. *
  25. * This function takes the channel value in MHz and sets
  26. * hardware channel value. Assumes writes have been enabled to analog bus.
  27. *
  28. * Actual Expression,
  29. *
  30. * For 2GHz channel,
  31. * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  32. * (freq_ref = 40MHz)
  33. *
  34. * For 5GHz channel,
  35. * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  36. * (freq_ref = 40MHz/(24>>amodeRefSel))
  37. *
  38. * For 5GHz channels which are 5MHz spaced,
  39. * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  40. * (freq_ref = 40MHz)
  41. */
  42. static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  43. {
  44. /* TODO */
  45. return 0;
  46. }
  47. /**
  48. * ar9003_hw_spur_mitigate - convert baseband spur frequency
  49. * @ah: atheros hardware structure
  50. * @chan:
  51. *
  52. * For single-chip solutions. Converts to baseband spur frequency given the
  53. * input channel frequency and compute register settings below.
  54. *
  55. * Spur mitigation for MRC CCK
  56. */
  57. static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
  58. struct ath9k_channel *chan)
  59. {
  60. /* TODO */
  61. }
  62. static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
  63. struct ath9k_channel *chan)
  64. {
  65. /* TODO */
  66. return 0;
  67. }
  68. static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
  69. struct ath9k_channel *chan)
  70. {
  71. /* TODO */
  72. }
  73. static void ar9003_hw_init_bb(struct ath_hw *ah,
  74. struct ath9k_channel *chan)
  75. {
  76. /* TODO */
  77. }
  78. static int ar9003_hw_process_ini(struct ath_hw *ah,
  79. struct ath9k_channel *chan)
  80. {
  81. /* TODO */
  82. return -1;
  83. }
  84. static void ar9003_hw_set_rfmode(struct ath_hw *ah,
  85. struct ath9k_channel *chan)
  86. {
  87. /* TODO */
  88. }
  89. static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
  90. {
  91. /* TODO */
  92. }
  93. static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
  94. struct ath9k_channel *chan)
  95. {
  96. /* TODO */
  97. }
  98. static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
  99. {
  100. /* TODO */
  101. return false;
  102. }
  103. static void ar9003_hw_rfbus_done(struct ath_hw *ah)
  104. {
  105. /* TODO */
  106. }
  107. static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
  108. {
  109. /* TODO */
  110. }
  111. static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
  112. {
  113. /* TODO */
  114. }
  115. void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
  116. {
  117. struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  118. priv_ops->rf_set_freq = ar9003_hw_set_channel;
  119. priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
  120. priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
  121. priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
  122. priv_ops->init_bb = ar9003_hw_init_bb;
  123. priv_ops->process_ini = ar9003_hw_process_ini;
  124. priv_ops->set_rfmode = ar9003_hw_set_rfmode;
  125. priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
  126. priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
  127. priv_ops->rfbus_req = ar9003_hw_rfbus_req;
  128. priv_ops->rfbus_done = ar9003_hw_rfbus_done;
  129. priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
  130. priv_ops->set_diversity = ar9003_hw_set_diversity;
  131. }